4-Channel, 200 kSPS 12-Bit ADC
with Sequencer in 16-Lead TSSOP
AD7923
Rev. A
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Fast throughput rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
3.6 mW max at 200 kSPS with 3 V supply
7.5 mW max at 200 kSPS with 5 V supply
4 (single-ended) inputs with sequencer
Wide input bandwidth
70 dB Min SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface SPI®-/QSPITM-/
MICROWIRETM-/DSP-compatible
Shutdown mode: 0.5 μA max
16-lead TSSOP package
GENERAL DESCRIPTION
The AD7923 is a 12-bit, high speed, low power, 4-channel, suc-
cessive approximation (SAR) ADC. It operates from a single
2.7 V to 5.25 V power supply and features throughput rates up to
200 kSPS. It contains a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled by
CS and the serial clock, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS; the conversion is also initiated at this
point.
The AD7923 uses advanced design techniques to achieve very
low power dissipation at maximum throughput rates. At
maximum throughput rates, it consumes 1.2 mA maximum
with 3 V supplies and 1.5 mA maximum with 5 V supplies.
Through the configuration of the control register, the analog
input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN,
with either straight binary or twos complement output coding.
The AD7923 features four single-ended analog inputs with a
channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
The conversion time for the AD7923 is determined by the serial
clock, SCLK, frequency, since this is used as the master clock to
control the conversion. The conversion time can be as short as
800 ns with a 20 MHz SCLK.
FUNCTIONAL BLOCK DIAGRAM
•
•
•
•
•
•
•
•
•
•
•
•
•
V
IN
3
T/H
I/P
MUX
SEQUENCER CONTROL LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
GND
SCLK
DOUT
DIN
CS
V
DRIVE
AV
DD
AD7923
REF
IN
V
IN
0
03086-001
Figure 1.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7923 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7923
dissipates just 3.6 mW of power.
2. Four Single-Ended Inputs with a Channel Sequencer.
3. Single-Supply Operation with VDRIVE Function.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
of AVDD.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Current consumption is 0.5 µA
maximum when in full shutdown.
5. No Pipeline Delay.
The part features a SAR ADC with accurate control of the
sampling instant via a CS input and once off conversion
control.
AD7923
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Typical Performance Characteristics ............................................. 8
Ter mi no log y .................................................................................... 10
Control Register Descriptions ...................................................... 12
Sequencer Operation ................................................................. 13
Theory of Operation ...................................................................... 14
Circuit Information.................................................................... 14
Converter Operation.................................................................. 14
ADC Transfer Function............................................................. 15
Typical Connection Diagram ................................................... 16
Modes of Operation ................................................................... 17
Powering Up the AD7923 ......................................................... 18
Power vs. Throughput Rate....................................................... 19
Serial Interface............................................................................ 20
Microprocessor Interfacing....................................................... 21
Application Hints ........................................................................... 23
Grounding and Layout .............................................................. 23
Evaluating the AD7923 Performance ...................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
8/05—Rev. 0 to Rev. A
Update Format ................................................................Universal
Change to Table 1 ......................................................................... 3
Change to Table 3 ......................................................................... 6
Change to Reference Section .................................................... 16
Changes to Ordering Guide ...................................................... 24
11/02—Revision 0: Initial Version
AD7923
Rev. A | Page 3 of 24
SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter B Version1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz
Signal-to-(Noise + Distortion) (SINAD)270 dB min @ 5 V, –40°C to +85°C
69 dB min @ 5 V, 85°C to 125°C, typ 70 dB
69 dB min @ 3 V typ 70 dB, –40°C to +125°C
Signal-to-Noise (SNR)270 dB min
Total Harmonic Distortion (THD)2−77 dB max @ 5 V typ, −84 dB
−73 dB max @ 3 V typ,−77 dB
Peak Harmonic or Spurious Noise −78 dB max @ 5 V typ, −86 dB
(SFDR)2 −76 dB max @ 3 V typ, −80 dB
Intermodulation Distortion (IMD)2 f
A = 40.1 kHz, fB = 41.5 kHz B
Second Order Terms −90 dB typ
Third Order Terms −90 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 50 ps typ
Channel-to-Channel Isolation −85 dB typ fIN = 400 kHz
Full Power Bandwidth 8.2 MHz typ @ 3 dB
1.6 MHz typ @ 0.1 dB
DC ACCURACY2
Resolution 12 Bits
Integral Nonlinearity ±1 LSB max
Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits
0 V to REFIN Input Range Straight binary output coding
Offset Error ±8 LSB max Typ ±0.5 LSB
Offset Error Match ±0.5 LSB max
Gain Error ±1.5 LSB max
Gain Error Match ±0.5 LSB max
0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos
complement output coding
Positive Gain Error ±1.5 LSB max
Positive Gain Error Match ±0.5 LSB max
Zero-Code Error ±8 LSB max Typ ±0.8 LSB
Zero-Code Error Match ±0.5 LSB max
Negative Gain Error ±1 LSB max
Negative Gain Error Match ±0.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to REFIN V Range bit set to 1
0 to 2 × REFIN V Range bit set to 0, AVDD = 4.75 V to 5.25 V
DC Leakage Current ±1 μA max
Input Capacitance 20 pF typ
REFERENCE INPUT
REFIN Input Voltage 2.5 V ±1% specified performance
DC Leakage Current ±1 μA max
REFIN Input Impedance 36 kΩ typ fSAMPLE = 200 kSPS
LOGIC INPUTS
Input High Voltage, VINH 0.7 × VDRIVE V min
Input Low Voltage, VINL 0.3 × VDRIVE V max
Input Current, IIN ±1 μA max Typ 10 nA, VIN = 0 V or VDRIVE
Input Capacitance, CIN3 10 pF max
AD7923
Rev. A | Page 4 of 24
Parameter B Version1Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH VDRIVE – 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V
Output Low Voltage, VOL 0.4 V max ISINK = 200 μA
Floating-State Leakage Current ±1 μA max
Floating-State Output Capacitance 10 pF max
Output Coding Twos Complement Coding bit set to 0
Straight (Natural)
Binary
Coding bit set to 1
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz
300 ns max Sinewave input
300 ns max Full-scale step Input
Throughput Rate 200 kSPS max See Serial Interface section
POWER REQUIREMENTS
AVDD 2.7/5.25 V min/max
VDRIVE 2.7/5.25 V min/max
IDD4 Digital I/Ps = 0 V or VDRIVE
During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
2.0 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
Normal Mode (Static) 600 μA typ AVDD = 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) fSAMPLE = 200 kSPS 1.5 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
1.2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
Using Auto Shutdown Mode fSAMPLE = 200 kSPS 900 μA typ AVDD = 4.75 V to 5.25 V, fSAMPLE = 200 kSPS
650 μA typ AVDD = 2.7 V to 3.6 V, fSAMPLE = 200 kSPS
Auto Shutdown (Static) 0.5 μA max SCLK on or off (20 nA typ)
Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ)
Power Dissipation4
Normal Mode (Operational) fSAMPLE = 200 kSPS 7.5 mW max AVDD = 5 V, fSCLK = 20 MHz
3.6 mW max AVDD = 3 V, fSCLK = 20 MHz
Auto Shutdown (Static) 2.5 μW max AVDD = 5 V
1.5 μW max AVDD = 3 V
Full Shutdown Mode 2.5 μW max AVDD = 5 V
1.5 μW max AVDD = 3 V
1 Temperature range: B Version: −40°C to +125°C.
2 See Terminology section.
3 Sample tested @ 25°C to ensure compliance.
4 See Power vs. Throughput Rate section.
AD7923
Rev. A | Page 5 of 24
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Limit at TMIN, TMAX
Parameter AVDD = 3 V AVDD = 5 V Unit Description
fSCLK2 10 10 kHz min
20 20 MHz max
tCONVERT 16 × tSCLK 16 × tSCLK
tQUIET 50 50 ns min Minimum quiet time required between CS rising edge and start of next
conversion
t210 10 ns min
CS to SCLK set-up time
t3335 30 ns max
Delay from CS until DOUT three-state disabled
t43 40 40 ns max Data access time after SCLK falling edge
t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width
t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width
t7 10 10 ns min SCLK to DOUT valid hold time
t8 4 15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance
t9 10 10 ns min DIN set-up time prior to SCLK falling edge
t10 5 5 ns min DIN hold time after SCLK falling edge
t11 20 20 ns min Sixteenth SCLK falling edge to CS high
t12 1 1 μs max Power-Up time from full power-down/auto shutdown mode
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 The mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish
time of the part and is independent of the bus loading.
200μAI
OL
200μAI
OH
1.6V
TO OUTPUT
PIN C
L
50pF
03086-002
Figure 2. Load Circuit for Digital Output Timing Specification
AD7923
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND −0.3 V to +7 V
VDRIVE to AGND −0.3 V to AVDD + 0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND −0.3 V to +7 V
Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V
REFIN to AGND −0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except
Supplies1
±10 mA
Operating Temperature Range
Commercial (B Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance 150.4°C/W (TSSOP)
θJC Thermal Impedance 27.6°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Pb-free Temperature, Soldering
Reflow 260(+0)°C
ESD 2 kV
1 Transient currents of up to 100 mA do not cause SCR latchup.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7923
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIN
CS
A
GND
REF
IN
AV
DD
AV
DD
SCLK
V
DRIVE
DOUT
AGND
V
IN
2
A
GND V
IN
3
V
IN
1
V
IN
0
AGND
AD7923
TOP VIEW
(Not to Scale)
03086-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Function
1 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the part. This clock input is also used
as the clock source for the AD7923 conversion process.
2 DIN Data In. Logic Input. Data to be written to the control register is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Control Register Descriptions section).
3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923
and framing the serial data transfer.
4, 8,
13, 16
AGND Analog Ground. Ground reference point for all analog circuitry on the AD7923. All analog input signals and any
external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
5, 6 AVDD Analog Power Supply Input. The AVDD range for the AD7923 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range,
AVDD should be from 4.75 V to 5.25 V.
7 REFIN Reference Input for the AD7923. An external reference must be applied to this input. The voltage range for the
external reference is 2.5 V ± 1% for specified performance.
12 to 9 VIN0 to VIN3 Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on-
chip track-and-hold. The analog input channel to be converted is selected by using the Address Bits ADD1 and
ADD0 of the control register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to
be programmed. The input range for all input channels can extend from 0 V to REFIN or from 0 V to 2 × REFIN as
selected via the range bit in the control register. Any unused input channels must be connected to AGND to avoid
noise pickup.
14 DOUT Data Out. Logic Output. The conversion result from the AD7923 is provided on this output pin as a serial data
stream. The AD7923 serial data stream consists of two leading 0s, and two address bits indicating which channel
the conversion result corresponds to, followed by 12 bits of conversion data, MSB first. The output coding can be
selected as straight binary or twos complement via the coding bit in the control register. The data bits are clocked
out of the AD7923 on the SCLK falling edge.
15 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface
operates.
AD7923
Rev. A | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (kHz)
SNR (dB)
–10
–50
–30
–70
–90
–110 0 10203040 6070809050 100
03096-004
4096 POINT FFT
AVDD = 4.75V
fSAMPLE = 200kSPS
fIN = 50 kHz
SINAD = 70.714dB
THD = –82.853dB
SFDR = –84.815dB
Figure 4. Dynamic Performance at 200 kSPS
INPUT FREQUENCY (kHz)
SINAD (dB)
75
70
65
60 0 100
03086-005
f
SAMPLE
= 200kSPS
T
A
= 25°C
RANGE = 0V TO REF
IN
AV
DD
= V
DRIVE
= 5.25V
AV
DD
= V
DRIVE
= 4.75V
AV
DD
= V
DRIVE
= 3.6V
AV
DD
= V
DRIVE
= 2.7V
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages at
200 kSPS
SUPPLY RIPPLE FREQUENCY (kHz)
PSRR (dB)
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 20 40 60 80 100 120 140 160 180 200
03086-006
AV
DD
= 5V
200mV p-p SINE WAVE ON AV
DD
REF
IN
= 2.5V, 1μF CAPACITOR
T
A
= 25°C
Figure 6. PSRR vs. Supply Ripple Frequency
INPUT FREQUENCY (kHz)
THD (dB)
–50
–90
–85
–80
–75
–70
–65
–60
–55
10 100
03086-007
f
SAMPLE
= 200kSPS
T
A
= 25°C
RANGE = 0V TO REF
IN
AV
DD
= V
DRIVE
= 5.25V
AV
DD
= V
DRIVE
= 4.75V
AV
DD
= V
DRIVE
= 2.7V
AV
DD
= V
DRIVE
= 3.6V
Figure 7. THD vs. Analog Input Frequency
for Various Supply Voltages at 200 kSPS
INPUT FREQUENCY (kHz)
THD (dB)
–55
–95
–90
–85
–80
–75
–70
–65
–60
10 100
03086-008
f
SAMPLE
= 200kSPS
T
A
= 25°C
AV
DD
= 5.25V
RANGE = 0V TO REF
IN
R
IN
= 100Ω
R
IN
= 1000Ω
R
IN
= 10Ω
R
IN
= 50Ω
Figure 8. THD vs. Analog Input Frequency for Various Source Impedances
CODE
INL ERROR (LSB)
1.0
0.6
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 0 512 1024 1536 2048 2560 3072 3584 4096
03096-009
AV
DD
= V
DRIVE
= 5V
TEMP = 25°C
Figure 9. Typical INL
AD7923
Rev. A | Page 9 of 24
CODE
DNL ERROR (LSB)
1.0
0.6
0.8
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 0 512 1024 1536 2048 2560 3072 3584 4096
03096-010
AV
DD
= V
DRIVE
= 5V
TEMP = 25°C
Figure 10. Typical DNL
AD7923
Rev. A | Page 10 of 24
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 ... 000) to
(00 ... 001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 ... 110) to
(111 ... 111) from the ideal (that is, REFIN – 1 LSB) after the
offset error has been adjusted.
Gain Error Match
This is the difference in gain error between any two channels.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
−REFIN to +REFIN is biased around the REFIN point. It defined
as the deviation of the midscale transition (all 0s to all 1s) from
the ideal VIN voltage, that is, REFIN – 1 LSB.
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
−REFIN to +REFIN is biased around the REFIN point. It is the
deviation of the last code transition (011 ... 110) to (011 ... 111)
from the ideal (that is, +REFIN – 1 LSB) after the zero-code
error has been adjusted.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
−REFIN to +REFIN is biased around the REFIN point. It is the
deviation of the first code transition (100 ... 000) to (100 ... 001)
from the ideal (that is, −REFIN + 1 LSB) after the zero-code
error has been adjusted.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of cross-
talk between channels. It is measured by applying a full-scale
400 kHz sine wave signal to all three nonselected input channels
and determining how much that signal is attenuated in the
selected channel with a 50 kHz signal. The figure is given in the
worst-case across all four channels for the AD7923.
Power Supply Rejection (PSR)
Variations in power supply affect the full-scale transition, but
not the converter’s linearity. Power supply rejection is the maxi-
mum change in the full-scale transition point from a change in
power supply voltage from the nominal value.
Figure 6 shows the power supply rejection ratio vs. supply ripple
frequency for the AD7923 with no decoupling. The power sup-
ply rejection ratio is defined as the ratio of the power in the
ADC output at full-scale frequency, f, to the power of a 200 mV
p-p sine wave applied to the ADC AVDD supply of frequency fS:
PSSR (dB) = 10log(Pf/PfS)
Pf is equal to the power at frequency f in the ADC output; PfS is
equal to the power at frequency fS coupled onto the ADC AVDD
supply.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.
AD7923
Rev. A | Page 11 of 24
Signal-to-(Noise + Distortion) (SINAD) Ratio
This is the measured ratio of SINAD at the output of the ADC.
The signal is the rms amplitude of the fundamental. Noise is the
sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process, the
more levels, the smaller the quantization noise. The theoretical
SINAD ratio for an ideal N-bit converter with a sine wave input
is given by
SINAD = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7923, it is defined as
1
2
6
2
5
2
4
2
3
2
2
log20)( V
VVVVV
dBTHD ++++
=
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
AD7923
Rev. A | Page 12 of 24
CONTROL REGISTER DESCRIPTIONS
The control register on the AD7923 is a 12-bit, write-only
register. Data is loaded from the DIN pin of the AD7923 on the
falling edge of SCLK. The data is transferred on the DIN line at
the same time that the conversion result is read from the part.
The data transferred on the DIN line corresponds to the
AD7923 configuration for the next conversion. This requires
16 serial clocks for every data transfer. Only the information
provided on the first 12 falling clock edges (after CS falling
edge) is loaded to the control register. MSB denotes the first bit
in the data stream. The bit functions are outlined in Table 5.
Table 5. Control Register Bit Functions
MSB LSB
WRITE SEQ1 DONTC DONTC ADD1 ADD0 PM1 PM0 SEQ0 DONTC RANGE CODING
Table 6.
Bit Name Description
11 WRITE The value written to this bit of the control register determines whether the following 11 bits are loaded to the
control register. If this bit is a 1, the following 11 bits are written to the control register. If it is a 0, the remaining
11 bits are not loaded to the control register and it remains unchanged.
10 SEQ1 The SEQ1 bit in the control register is used with the SEQ0 bit to control the use of the sequencer function (see
Table 9).
7–6 ADD1
ADD0
These two address bits are loaded at the end of the present conversion and select which analog input channel is
converted in the next serial transfer, or they can also be used to select the final channel in a consecutive sequence,
as described in Table 9. The selected input channel is decoded, as shown in Table 7. The next channel to be
converted on is selected by the mux on the 14th SCLK falling edge. Channel address bits corresponding to the
conversion result are also output on the DOUT serial data stream prior to the 12 bits of data (see the Serial Interface
section).
5, 4 PM1
PM0
Power management bits. These two bits decode the mode of operation of the AD7923, as shown in Table 8.
3 SEQ0 The SEQ0 bit in the control register is used with the SEQ1 bit to control the use of the sequencer function.
(see Table 9).
2, 9–8 DONTC Don’t care.
1 RANGE This bit selects the analog input range to be used on the AD7923. If it is set to 0, the analog input range extends from
0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For the 0 V
to 2 × REFIN range, AVDD = 4.75 V to 5.25 V.
0 CODING This bit selects the type of output coding the AD7923 uses for the conversion result. If this bit is set to 0, the output
coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for
the next conversion).
Table 7. Channel Selection
ADD1 ADD0 Analog Input Channel
0 0 VIN0
0 1 VIN1
1 0 VIN2
1 1 VIN3
AD7923
Rev. A | Page 13 of 24
Table 8. Power Mode Selection
PM1 PM0 Mode
1 1 Normal operation. In this mode, the AD7923 remains in full power mode, regardless of the status of any of the logic inputs.
This mode allows the fastest possible throughput rate from the AD7923.
1 0 Full shutdown. In this mode, the AD7923 is in full shutdown mode with all circuitry on the AD7923 powering down. The
AD7923 retains the information in the control register while in full shutdown. The part remains in full shutdown until these
bits are changed.
0 1 Auto shutdown. In this mode, the AD7923 automatically enters full shutdown mode at the end of each conversion when the
control register is updated. Wake-up time from full shutdown is 1 μs, and the user should ensure that 1 μs has elapsed
before attempting to perform a valid conversion on the part in this mode.
0 0 Invalid selection. This configuration is not allowed.
SEQUENCER OPERATION
The configuration of the SEQ1 and SEQ0 bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 9 outlines the three modes of operation of the sequencer.
Table 9. Sequence Selection
SEQ1 SEQ0 Sequence Type
0 X This configuration means that the sequence function is not used. The analog input channel selected for each individual
conversion is determined by the contents of Channel Address Bits ADD1 and ADD0 in each prior write operation. This
mode of operation reflects the traditional operation of a multichannel ADC without the sequencer function being used,
where each write to the AD7923 selects the next channel for conversion (see Figure 11).
1 0 If the SEQ1 and SEQ0 bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
1 1 This configuration is used in conjunction with Channel Address Bits ADD1 and ADD0 to program continuous conversions
on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address
bits in the control register (see Figure 12).
Figure 11 reflects the traditional operation of a multichannel
ADC, where each serial transfer selects the next channel for
conversion. In this mode of operation the sequencer function is
not used.
Figure 12 shows how to program the AD7923 to continuously
convert on a sequence of consecutive channels from Channel 0
to a selected final channel. To exit this mode of operation and
revert back to the traditional mode of operation of a multi-
channel ADC (as outlined in Figure 11), ensure that the write
bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer.
POWER-ON
DUMMY CONVERSION
WRITE BIT = 1,
SEQ1 = 0,
SEQ0 = x
CS
CS
03086-011
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A1, A0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A1, A0 FOR CONVERSION.
SEQ1 = 0, SEQ0 = x
DOUT: CONVERSION RESULT FROM
PREVIOUSLY SELECTED CHANNEL A1, A0
Figure 11. SEQ1 Bit = 0, SEQ0 Bit = X Flowchart
POWER-ON
DUMMY CONVERSION
CS
CS
CS
03086-012
WRITE BIT = 1,
SEQ1 = 1,
SEQ0 = 0
WRITE BIT = 0
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A1, A0 FOR CONVERSION.
SEQ1 = 1, SEQ0 = 1
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A1, A0 IN THE CONTROL REGISGER
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT WILL ALLOW
RANGE, CODING, ETC., TO CHANGE IN THE CON-
TROL REGISTER WITHOUT INTERRUPTING THE
SEQUENCY, PROVIDED SEQ =1, SEQ0 = 0
DOUT: CONVERSION RESULT FROM CHANNEL 0
Figure 12. SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart
AD7923
Rev. A | Page 14 of 24
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7923 is a high speed, 4-channel, 12-bit single-supply
ADC. The part can be operated from a 2.7 V to 5.25 V supply.
When operated from either a 5 V or 3 V supply, the AD7923 is
capable of throughput rates of 200 kSPS. The conversion time
can be as short as 800 ns when provided with a 20 MHz clock.
The AD7923 provides the user with an on-chip track-and-hold
ADC and with a serial interface housed in a 16-lead TSSOP
package. The AD7923 has four, single-ended input channels
with a channel sequencer, allowing the user to select a channel
sequence through which the ADC can cycle with each conse-
utive CS falling edge. The serial clock input accesses data from
the part, controls the transfer of data written to the ADC, and
provides the clock source for the successive approximation
ADC. The analog input range is 0 V to REFIN or 0 V to 2 ×
REFIN, depending on the status of the RANGE bit in the control
register. For the 0 to 2 × REFIN range, the part must be operated
from a 4.75 V to 5.25 V AVDD supply.
The AD7923 provides flexible power management options to
allow the user to achieve the best power performance for a
given throughput rate. These options are selected by program-
ming the power management bits, PM1 and PM0, in the control
register.
CONVERTER OPERATION
The AD7923 is a 12-bit successive approximation ADC based
around a capacitive DAC. It can convert analog input signals in
the range 0 V to REFIN or 0 V to 2 × REFIN. Figure 13 and
Figure 14 show simplified schematics of the ADC. The ADC is
comprised of a control logic, SAR, and capacitive DAC, which
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. Figure 13 shows the ADC during its acquisition phase.
SW2 is closed and SW1 is in Position A. The comparator is held
in a balanced condition and the sampling capacitor acquires the
signal on the selected VIN channel.
V
IN
0
V
IN
3
AGND
A
B
SW1 SW2
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
4kΩ
03086-013
Figure 13. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 14), SW2 opens
and SW1 moves to Position B, causing the comparator to
become unbalanced. The control logic and the capacitive DAC
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into balance.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code. Figure 16 and
Figure 17 show the ADC transfer functions.
V
IN
0
V
IN
3
AGND
A
B
SW1 SW2
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
4kΩ
03086-014
Figure 14. ADC Conversion Phase
Analog Input
Figure 15 shows an equivalent circuit of the analog input
structure of the AD7923. The two diodes D1 and D2 provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 200 mV; otherwise these diodes become
forward-biased and start conducting current into the substrate.
10 mA is the maximum current these diodes can conduct
without causing irreversible damage to the part. Capacitor C1,
shown in Figure 15, is typically around 4 pF and can primarily
be attributed to pin capacitance. The resistor R1 is a lumped
component made up of the on resistance of the track-and-hold
switch and includes the on resistance of the input multiplexer.
The total resistance is typically about 400 Ω. Capacitor C2 is the
ADC sampling capacitor and has a capacitance of 30 pF typi-
cally. For ac applications, removing high frequency components
from the analog input signal is recommended by using an RC
low-pass filter on the relevant analog input pin. In applications
where harmonic distortion and the signal-to-noise ratio are
critical, the analog input should be driven from a low impe-
dance source. Large source impedances significantly affect the
ac performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades (see Figure 8).
V
IN
C1
4pF
C2
30pF
R1
D1
D2
AV
DD
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
03086-015
Figure 15. Equivalent Analog Input Circuit
AD7923
Rev. A | Page 15 of 24
ADC TRANSFER FUNCTION
The output coding of the AD7923 is either straight binary or
twos complement, depending on the status of the LSB in the
control register. The designed code transitions occur at succes-
sive LSB values (for example, 1 LSB, 2 LSBs). The LSB size is
REFIN /4096 for the AD7923. The ideal transfer characteristic
for the AD7923 when straight binary coding is selected is
shown in Figure 16 and the ideal transfer characteristic for the
AD7923 when twos complement coding is selected is shown in
Figure 17.
+VREF –1LSB
000...000
0V ANALOG INPUT
111...111
000...001
000...010
111...110
•
•
111...000
•
011...111
•
•
1LSB
1LSB = VREF/4096
NOTES
1.VREF ISEITHERREFINOR2×REFIN
ADC CODE
03086-016
Figure 16. Straight Binary Transfer Characteristic
–V
REF
+1LSB
ADC CODE
ANALOG INPUT
+V
REF
–1LSB
1LSB = 2 × V
REF
/4096
V
REF
–1LSB
100...000
011...111
100...001
100...010
011...110
•
•
000...001
111...111
•
•
000...000
03086-017
Figure 17. Twos Complement Transfer Characteristic
with REFIN ± REFIN Input Range
Handling Bipolar Input Signals
Figure 18 shows how useful the combination of the 2 × REFIN
input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal is
biased around REFIN and twos complement output coding is
selected, then REFIN becomes the zero-code point, −REFIN is
negative full scale, and + REFIN becomes positive full scale with
a dynamic range of 2 × REFIN.
R3
R2
R4
REF
IN
V
IN
0
V
IN
3
AD7923
DSP/μP
V
DD
0.1μF
V
AV
DD
V
DRIVE
DOUT
TWOS
COMPLEMENT
+REF
IN
REF
IN
–REF
IN
011...111
000...000
100...000
(= 0V)
(= 2 × REF
IN
)
0
V
V
R1
R1 = R2 = R3 = R4
V
DD
V
REF
•
•
03086-018
Figure 18. Handling Bipolar Signals
AD7923
Rev. A | Page 16 of 24
TYPICAL CONNECTION DIAGRAM
Figure 19 shows a typical connection diagram for the AD7923.
In this setup the AGND pin is connected to the analog ground
plane of the system. In Figure 19, REFIN is connected to a
decoupled 2.5 V supply from a reference source, the AD780, to
provide an analog input range of 0 V to 2.5 V (if the range bit is
1) or 0 V to 5 V (if the range bit is 0). Although the AD7923 is
connected to AVDD of 5 V, the serial interface is connected to a
3 V microprocessor. The VDRIVE pin of the AD7923 is connected
to the same 3 V supply of the microprocessor to allow a 3 V
logic interface (see the Digital Inputs section). The conversion
result is output in a 16-bit word. This 16-bit data stream
consists of two leading 0s, two address bits indicating which
channel the conversion result corresponds to, followed by the
12 bits of conversion data. For applications where power
consumption is a concern, the power-down modes should be
used between conversions or bursts of several conversions to
improve power performance. See the Modes of Operation
section.
SERIAL
INTERFACE
AD780
2.5V
AD7923
0.1μF
μC/μP
0.1μF10μF3V
SUPPLY
5V
SUPPLY
0.1μF10μF
AGND
AV
DD
•
•
0VTOREF
IN
SCLK
DOUT
CS
DIN
V
DRIVE
REF
IN
NOTES
1. ALL UNUSED INPUT CHANNELS MUST BE CONNECTED TO AGND.
V
IN
0
V
IN
3
03086-019
Figure 19. Typical Connection Diagram
Analog Input Selection
Any one of four analog input channels can be selected for
conversion by programming the multiplexer with Address Bits
ADD1 and ADD0 in the control register. The channel
configurations are shown in Tabl e 7.
The AD7923 can also be configured to automatically cycle
through selected channels. The sequencer feature is accessed via
the SEQ1 and SEQ0 bits in the control register (see Table 9).
The AD7923 can be programmed to continuously convert on a
number of consecutive channels in ascending order from
Channel 0 to a selected final channel as determined by Channel
Address Bits ADD1 and ADD0. This is possible if the SEQ1 and
SEQ0 bits are set to 1, 1. The next serial transfer then acts on
the sequence programmed by executing a conversion on
Channel 0. The next serial transfer results in a conversion on
Channel 1, and so on, until the channel selected via Address
Bits ADD1 and ADD0 is reached. It is not necessary to write to
the control register again once a sequencer operation has been
initiated. The write bit must be set to 0 or the DIN line must be
set low to ensure that the control register is not accidentally
overwritten or the sequence operation is interrupted. If the
control register is written to at any time during the sequence,
the user must ensure that the SEQ1 and SEQ0 bits are set to 1, 0
to avoid interrupting the automatic conversion sequence. This
pattern continues until the AD7923 is written to and the SEQ1
and SEQ0 bits are configured with any bit combination except
1, 0, resulting in the termination of the sequence. If uninter-
rupted, however (write bit = 0, or write bit = 1 and SEQ1 and
SEQ0 bits are set to 1, 0), then upon completion of the
sequence, the AD7923 sequencer returns to Channel 0 and
commences the sequence again.
Regardless of which channel selection method is used, the
16-bit word output from the AD7923 during each conversion
always contains two leading 0s, and two channel address bits
that the conversion result corresponds to, followed by the 12-bit
conversion result. (see the Serial Interface section).
Digital Inputs
The digital inputs applied to the AD7923 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
AVDD + 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and CS not being restricted
by the AVDD + 0.3 V limit is that possible power supply
sequencing issues are avoided. If CS, DIN, or SCLK are applied
before AVDD, there is no risk of latchup as there would be on the
analog inputs if a signal greater than 0.3 V were applied prior to
AVDD.
VDRIVE
The AD7923 also has the VDRIVE feature. VDRIVE controls the
voltage at which the serial interface operates. VDRIVE allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7923 were operated with an AVDD of 5 V, the
VDRIVE pin could be powered from a 3 V supply. The AD7923
has a larger dynamic range with an AVDD of 5 V while still being
able to interface to 3 V processors. Care should be taken to
ensure that VDRIVE does not exceed AVDD by more than 0.3 V
(see the Absolute Maximum Ratings section).
Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7923. Errors in the reference source result in
gain errors in the AD7923 transfer function and add to the
specified full-scale errors of the part. A capacitor of at least
0.1 µF should be placed on the REFIN pin. Suitable reference
sources for the AD7923 include the AD780, REF 192, and the
AD1582.
AD7923
Rev. A | Page 17 of 24
If 2.5 V is applied to the REFIN pin, the analog input range can
be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the range bit in the control register.
MODES OF OPERATION
The AD7923 has a number of different modes of operation,
which are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for differing application
requirements. The mode of operation of the AD7923 is
controlled by the power management bits, PM1 and PM0, in
the control register, as detailed in Table 8. When power supplies
are first applied to the AD7923, care should be taken to ensure
that the part is placed in the required mode of operation (see
the Powering Up the AD7923 section).
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perfor-
mance where the user does not have to worry about power-up
time since the AD7923 remains fully powered at all times.
Figure 20 shows the general diagram of the operation of the
AD7923 in this mode.
The conversion is initiated on the falling edge of CS and the
track-and-hold enters hold mode, as described in the Serial
Interface section. The data presented to the AD7923 on the
DIN line during the first 12 clock cycles of the data transfer is
loaded into the control register (provided the write bit is set to
1). The part remains fully powered up in normal mode at the
end of the conversion as long as PM1 and PM0 are set to 1 in
the write transfer during that same conversion. To ensure
continued operation in normal mode, PM1 and PM0 must both
be loaded with 1 on every data transfer, assuming a write
operation is taking place. If the write bit is set to 0, the power
management bits are left unchanged and the part remains in
normal mode.
Sixteen serial clock cycles are required to complete the conver-
sion and access the conversion result. The track-and-hold go
back into track on the 14th SCLK falling edge. CS may then idle
high until the next conversion or may idle low until sometime
prior to the next conversion (effectively idling CS low).
For specified performance, the throughput rate should not
exceed 200 kSPS, which means there should be no less than 5 µs
between consecutive falling edges of CS when converting. The
actual frequency of the SCLK used determines the duration of
the conversion within this 5 µs cycle; however, once a conver-
sion is complete, and CS has returned high, a minimum of the
quiet time, tQUIET, must elapse before bringing CS low again to
initiate another conversion.
112
CS
SCLK
DOUT
DIN
16
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DATA INTO CONTROL REGISTER
CONTROL REGISTER DATA IS LOADED
ON THE FIRST 12 SCLK CYCLES.
03086-020
Figure 20. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7923 is powered
down. The part retains information in the control register
during full shutdown. The AD7923 remains in full shutdown
until the power management bits in the control register, PM1
and PM0, are changed.
If a write to the control register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
PM1 = 1, normal mode, the part begins to power up on the CS
rising edge. The track-and-hold that was in hold while the part
was in full shutdown returns to tracking on the 14th SCLK
falling edge. A full 16-SCLK transfer must occur to ensure that
the control register contents are updated; however, the DOUT
line is not driven during this wake-up transfer.
To ensure that the part is fully powered up, tPOWER UP (t12) should
have elapsed before the next CS falling edge; otherwise invalid
data is read if a conversion is initiated before this time.
Figure 21 shows the general diagram for this sequence.
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7923 automatically enters shutdown at the
end of each conversion when the control register is updated.
When the part is in shutdown, the track-and-hold is in hold
mode. Figure 22 shows the general diagram of the operation of
the AD7923 in this mode. In shutdown mode all internal
circuitry on the AD7923 is powered down. The part retains
information in the control register during shutdown. The
AD7923 remains in shutdown until the next CS falling edge it
receives. On this CS falling edge, the track-and-hold that was in
hold while the part was in shutdown returns to tracking. Wake-
up time from auto shutdown is 1 µs maximum, and the user
should ensure that 1 µs has elapsed before attempting a valid
conversion. When running the AD7923 with a 20 MHz clock,
one dummy 16 SCLK transfer should be sufficient to ensure
that the part is fully powered up. During this dummy transfer,
the contents of the control register should remain unchanged,
therefore the write bit should be 0 on the DIN line. Depending
on the SCLK frequency used, this dummy transfer may affect
the achievable throughput rate of the part, with every other data
transfer being a valid conversion result. If, for example, the
maximum SCLK frequency of 20 MHz is used, the auto shut-
down mode could be used at the full throughout rate of
AD7923
Rev. A | Page 18 of 24
200 kSPS without affecting the throughput rate at all. Only a
portion of the cycle time is taken up by the conversion time and
the dummy transfer for wakeup. In this mode, the power con-
sumption of the part is greatly reduced because the part enters
shutdown at the end of each conversion. When the control
register is programmed to move into auto shutdown, it does so
at the end of the conversion. The user can move the ADC in
and out of the low power state by controlling the CS signal.
POWERING UP THE AD7923
When supplies are first applied to the AD7923, the ADC can
power up in any of the operating modes of the part. To ensure
that the part is placed into the required operating mode, the
user should perform a dummy cycle operation, as outlined in
Figure 23 through Figure 25.
The dummy conversion operation must be performed to place
the part into the desired mode of operation. To ensure that the
part is in normal mode, this dummy cycle operation can be
performed with the DIN line tied high, that is, PM1, PM0 = 1, 1
(depending on other required settings in the control register),
but the minimum power-up time of 1 µs must be allowed from
the rising edge of CS, where the control register is updated,
before attempting the first valid conversion. This is to allow for
the possibility that the part initially powered up in shutdown.
If the desired mode of operation is full shutdown, then again
only one dummy cycle is required after supplies are applied. In
this dummy cycle, the user simply sets the power management
bits, PM1, PM0 = 1, 0, and upon the rising edge of CS at the
end of that serial transfer, the part enters full shutdown. If the
desired mode of operation is auto shutdown after supplies are
applied, two dummy cycles are required, the first with DIN tied
high and the second dummy cycle to set the power manage-
ment bits PM1 and PM0 = 0,1. On the second CS rising edge
after the supplies are applied, the control register contains the
correct information and the part enters auto shutdown mode as
programmed. If power consumption is of critical concern, then
in the first dummy cycle the user may set PM1, PM0 = 1, 0, that
is, full shutdown, and then place the part into auto shutdown in
the second dummy cycle. For illustration purposes, Figure 25 is
shown with DIN tied high on the first dummy cycle in this case.
Figure 23, Figure 24, and Figure 25 each show the required
dummy cycle(s) after supplies are applied in the case of normal
mode, full shutdown mode, and auto shutdown mode, respect-
ively, being the desired mode of operation.
CS
SCLK
DOUT
DIN
1 14 16 1 14 16
PART IS IN FULL
SHUTDOWN PART BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 =1 THE PART IS FULLY POWERED UP
ONCE
t
POWER UP
HAS ELAPSED
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1 TO KEEPTHE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER
t
12
03086-021
Figure 21. Full Shutdown Mode Operation
1
CS
SCLK
DOUT
DIN
16 116116
DUMMY CONVERSION
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 0, PM0 = 1 CONTROL REGISTER CONTENTS SHOULD
NOT CHANGE, WRITE BIT = 0 TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1
IN CONTROL REGISTER OR SET WRITE BIT = 0
PART IS FULLY
POWERED UP
PART BEGINS
TO POWER
UP ON CS
FALLING EDGE
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 = 0, PM0 =1
1212
12
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 = 0, PM0 =1
DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER DATA INTO CONTROL REGISTER
03086-022
Figure 22. Auto Shutdown Mode Operation
AD7923
Rev. A | Page 19 of 24
INVALID DATA CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DATA INTO CONTROL REGISTER
TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
1 14 16 1 14 16
ALLOW
t
POWER TO ELAPSE
IF IN SHUTDOWN AT POWER-ON
PART BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
CS
SCLK
DOUT
DIN
03086-023
t
12
Figure 23. Placing the AD7923 into Normal Mode after Supplies are First Applied
INVALID DATA
114
PART ENTERS SHUTDOWN ON
CS RISING EDGE AS PM1 = PM0 = 0
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
CS
SCLK
DOUT
DIN
16
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON
THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0
03086-024
Figure 24. Placing the AD7923 into Full Shutdown Mode after Supplies are First Applied
INVALID DATA INVALID DATA
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 0, PM0 = 1
1 14 16 1 14 16
PART IS IN
UNKNOWN MODE
AFTER POWER-ON
CS
SCLK
DOUT
DIN
03086-025
PART ENTERS AUTO SHUTDOWN ON
CS RISING EDGE AS PM1 = 0, PM0 = 1
Figure 25. Placing the AD7923 into Auto Shutdown Mode after Supplies are First Applied
POWER vs. THROUGHPUT RATE
In auto shutdown mode, the average power consumption of the
ADC can be reduced at any given throughput rate. The power
saving depends on the SCLK frequency used, that is, conversion
time. In some cases where the conversion time is a large propor-
tion of the cycle time, the throughput rate needs to be reduced
to take advantage of the power-down modes. Assuming a
20 MHz SCLK is used, the conversion time is 800 ns, but the
cycle time is 5 s when the sampling rate is at a maximum of
200 kSPS. If the AD7923 is placed into shutdown for the
remainder of the cycle time, then on average far less power is
consumed in every cycle compared to leaving the device in
normal mode. Furthermore, Figure 26 shows how, as the
throughput rate is reduced, the part remains in its shutdown
longer and the average power consumption drops accordingly
over time.
AD7923
Rev. A | Page 20 of 24
For example, if the AD7923 is operated in a continuous samp-
ling mode, with a throughput rate of 200 kSPS and an SCLK of
20 MHz (AVDD = 5 V), and the device is placed in auto shut-
down mode, that is, if PM1 = 0 and PM0 = 1, then the power
consumption is calculated as follows:
The maximum power dissipation during conversion is 13.5 mW
(IDD = 2.7 mA max, AVDD = 5 V). If the power-up time from auto
shutdown is one dummy cycle, that is 1 µs, and the remaining
conversion time is another cycle, that is, 800 ns, then the
AD7923 can be said to dissipate 13.5 mW for 1.8 µs during each
conversion cycle. For the remainder of the conversion cycle,
3.2 µs, the part remains in shutdown. The AD7923 can be said
to dissipate 2.5 µW for the remaining 3.2 µs of the conver-sion
cycle. If the throughput rate is 200 kSPS, the cycle time is
5 µs and the average power dissipated during each cycle is
(1.8/5) × (13.5 mW) + (3.2/5) × (2.5 µW) = 4.8616 mW.
Figure 26 shows the maximum power vs. throughput rate when
using the auto shutdown mode with 5 V and 3 V supplies.
THROUGHPUT (kSPS)
POWER (mW)
10
1
0.1
0.01 0604020 10080 180160140120 100
03086-026
AV
DD
= 5V AV
DD
= 3V
Figure 26. Power vs. Throughput Rate
SERIAL INTERFACE
Figure 27 shows the detailed timing diagrams for serial inter-
facing to the AD7923. The serial clock provides the conversion
clock and controls the transfer of information to and from the
AD7923 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold
returns to track mode at Point B on the 14th SCLK falling edge,
as shown in Figure 27. On the 16th SCLK falling edge the
DOUT line returns to three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion is terminated, the
DOUT line returns to three-state, and the control register is not
updated; otherwise DOUT returns to three-state on the 16th
SCLK falling edge, as shown in Figure 27.
Sixteen serial clock cycles are required to perform the conver-
sion process and to access data from the AD7923. For the
AD7923, the 12 bits of data are preceded by two leading 0s and
Channel Address Bits ADD1 and ADD0, identifying which
channel the result corresponds to. CS going low clocks out the
first leading 0 to be read by the microcontroller or DSP on the
first falling edge of SCLK. The first falling edge of SCLK also
clocks out the second leading 0 to be read by the microcon-
troller or DSP on the second SCLK falling edge, and so on. The
remaining two address bits and 12 data bits are then clocked out
by subsequent SCLK falling edges, beginning with the first
Address Bit ADD1, thus the second falling clock edge on the
serial clock has the second leading 0 and also clocks out
Address Bit ADD1. The final bit in the data transfer is valid on
the 16th falling edge, having been clocked out on the previous
(15th) falling edge.
Writing information to the control register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the
MSB, that is, the write bit, has been set to 1.
The 16-bit word read from the AD7923 always contain two
leading 0s, two channel address bits that the conversion result
corresponds to, followed by the 12-bit conversion result.
Writing Between Conversions
As outlined in the operating modes section, not less than 5 µs
should be left between consecutive valid conversions. There is
one exception, however: consider the case when writing to the
AD7923 to power it up from shutdown prior to a valid conver-
sion. The user must write to the part to tell it to power up before
it can convert successfully. Once the serial write to power up
has finished, the user might want to perform the conversion as
soon as possible without waiting an additional 5 µs before
bringing CS low for the conversion. In this case, as long as there
is a minimum of 5 µs between each valid conversion, only the
quiet time between the CS rising edge at the end of the write to
power up and the next CS falling edge needs to be met.
Figure 28 illustrates this point. Note that when writing to the
AD7923 between these valid conversions, the DOUT line is not
driven during the extra write operation.
It is critical that an extra write operation as outlined above is
never issued between valid conversions when the AD7923 is
executing a sequence function, because the falling edge of CS in
the extra write moves the mux to the next channel in the
sequence. This means that when the next valid conversion takes
place a channel result would be missed.
AD7923
Rev. A | Page 21 of 24
CS
SCLK
DOUT
DIN
t5t11
t8tQUIET
tCONVERT
1 2 3 4 5 6 11 12 13 14 15 16
THREE-
STATE
ZERO ADD1 ADD0 DB11 DB10 DB4 DB3 DB2 DB1 DB0 THREE-
STATE
2 IDENTIFICATION
BITS
ZERO
B
WRITE SEQ1 DONTC DONTC ADD1 ADD0 CODING DONTC DONTC DONTC DONTC
t9
t2
t3
t10
t6
t7
t4
03086-027
Figure 27. Serial Interface Timing Diagram
CS
116 116 116
SCLK
VALID DATA VALID DATA
DOUT
POWER-UP
DIN
t
CYCLE
5μs MIN
t
QUIET
MIN
03086-028
Figure 28. General Timing Diagram
MICROPROCESSOR INTERFACING
The serial interface on the AD7923 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7923 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7923-to-TMS320C541
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7923. The CS input allows easy interfacing between the
TMS320C541 and the AD7923 without any glue logic required.
The serial port of the TMS320C541 is set up to operate in burst
mode with internal CLKX0 (Tx serial clock on Serial Port 0)
and FSX0 (Tx frame sync from Serial Port 0). The serial port
control register (SPC) must have the following setup: FO = 0,
FSM = 1, MCM = 1, and TXM = 1. The connection diagram is
shown in Figure 29. It should be noted that for signal processing
applications, it is imperative that the frame synchronization
signal from the TMS320C541 provides equidistant sampling.
The VDRIVE pin of the AD7923 takes the same supply voltage as
the TMS320C541. This allows the ADC to operate at a higher
voltage than the serial interface, that is, the TMS320C541, if
necessary.
TMS320C541
1
AD7923
1
CLKX
CLKR
DR
DT
FSX
FSR
V
DD
SCLK
DOUT
DIN
CS
1
ADDITIONAL PINS REMOVED FOR CLARITY.
03086-029
V
DRIVE
Figure 29. Interfacing to the TMS320C541
AD792-to-ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the
AD7923 without any glue logic required. The VDRIVE pin of the
AD7923 takes the same supply voltage as the ADSP-218x,
which allows the ADC to operate at a higher voltage than the
serial interface, that is, ADSP-218x, if necessary.
The SPORT0 control register should be set up as follows:
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right justify data
SLEN = 1111, 16-bit data-words
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0
ITFS = 1
AD7923
Rev. A | Page 22 of 24
The connection diagram is shown in Figure 30. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS and, as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this
example, the timer interrupt is used to control the sampling rate
of the ADC, and under certain conditions equidistant sampling
might not be achieved.
V
DRIVE
AD79231
ADSP-218x
1
SCLK
DR
RFS
TFS
DT
SCLK
DOUT
CS
DIN
1
ADDITIONAL PINS REMOVED FOR CLARITY. V
DD
03086-030
Figure 30. Interfacing to the ADSP-218x
The timer register, for instance, is loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given (that is, AX0 = TX0), the state of the SCLK is
checked. The DSP waits until the SCLK has gone high, low, and
high before the transmission starts. If the timer and SCLK
values are chosen such that the instruction to transmit occurs
on or near the rising edge of SCLK, the data can be transmitted,
or it can wait until the next clock edge.
For example, if the ADSP-2189 has a 20 MHz crystal such that it
has a master clock frequency of 40 MHz, then the master cycle
time is 25 ns. If the SCLKDIV register is loaded with the value
3, then a SCLK of 5 MHz is obtained, and eight master clock
periods elapse for every SCLK period. Depending on the
throughput rate selected, if the timer registers are loaded with
the value 803, 100.5 SCLKs occur between interrupts and
subsequently between transmit instructions. This situation
results in nonequidistant sampling since the transmit
instruction occurs on a SCLK edge. If the number of SCLKs
between interrupts is an integer of N, equidistant sampling is
implemented by the DSP.
AD7923-to-DSP563xx
The connection diagram in Figure 31 shows how the AD7923
can be connected to the synchronous serial interface (ESSI) of
the DSP563xx family of DSPs from Motorola. Each ESSI (two
on board) is operated in synchronous mode (SYN bit in CRB =
1), with an internally generated word length frame sync for
both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal
operation of the ESSI is selected by making MOD = 0 in the
CRB. Set the word length to 16 by setting bits WL1 = 1 and
WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so
the frame sync is negative. It should be noted that for signal
processing applications, it is imperative that the frame synchro-
nization signal from the DSP563xx provides equidistant
sampling.
In the example shown in Figure 31, the serial clock is taken
from the ESSI, therefore the SCK0 pin must be set as an output,
SCKD = 1. The VDRIVE pin of the AD7923 takes the same supply
voltage as the DSP563xx, which allows the ADC to operate at a
higher voltage than the serial interface, that is, DSP563xx, if
necessary.
AD7923
1
DSP563xx
1
SCK
SRD
STD
SC2
SCLK
DOUT
CS
DIN
V
DRIVE
1
ADDITIONAL PINS REMOVED FOR CLARITY. V
DD
03086-031
Figure 31. Interfacing to the DSP563xx
AD7923
Rev. A | Page 23 of 24
APPLICATION HINTS
GROUNDING AND LAYOUT
The AD7923 has very good immunity to noise on the power
supplies as can be seen by the PSRR vs. supply ripple frequency
plot, Figure 6. However, care should still be taken in grounding
and layout.
The printed circuit board that houses the AD7923 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. All three AGND pins of the AD7923 should
be sunk into the AGND plane. Digital and analog ground
planes should be joined at only one place. If the AD7923 is in a
system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point
only, a star ground point that should be established as close as
possible to the AD7923.
Avoid running digital lines under the device since they couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7923 to avoid noise coupling. The power
supply lines to the AD7923 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, like
clocks, should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by far
the best technique, but is not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, while signals are placed on the
solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum in parallel with 0.1 µF capa-
citors to AGND. To achieve the best results from these
decoupling components, they must be placed as close as pos-
sible to the device, ideally right up against the device. The 0.1
µF capacitors should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types or surface mount types, which provide a low
impedance path to ground at high frequencies to handle
transient currents from internal logic switching.
EVALUATING THE AD7923 PERFORMANCE
The recommended layout for the AD7923 is outlined in the
evaluation board for the AD7923. The evaluation board pack-
age includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the EVAL-CONTROL BRD2. The EVAL-CONTROL
BRD2 can be used with the AD7923 evaluation board and many
other Analog Devices evaluation boards ending in the CB
designator to demonstrate and evaluate the ac and dc
performance of the AD7923.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7923.
The software and documentation are on a CD shipped with the
evaluation board.
AD7923
Rev. A | Page 24 of 24
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Linearity Error (LSB)1 Package Option Package Description
AD7923BRU −40°C to +125°C ±1 RU-16 16-Lead TSSOP
AD7923BRU-REEL −40°C to +125°C ±1 RU-16 16-Lead TSSOP
AD7923BRU-REEL7 −40°C to +125°C ±1 RU-16 16-Lead TSSOP
AD7923BRUZ2−40°C to +125°C ±1 RU-16 16-Lead TSSOP
AD7923BRUZ-REEL2−40°C to +125°C ±1 RU-16 16-Lead TSSOP
AD7923BRUZ-REEL72−40°C to +125°C ±1 RU-16 16-Lead TSSOP
EVAL-AD7923CB3 Evaluation Board
EVAL-CONTROL BRD24 Controller Board
1 Linearity error refers to integral linearity error.
2 Z = Pb-free part.
3 This can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/demonstration purposes.
4 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, order the particular ADC evaluation board, for example, the EVAL-AD7923CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant
evaluation board application note for more information.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03086-0-8/05(A)
