ADP3205AJCPZ-REEL - ON Semiconductor

April, 2010 − Rev. 3

1Publication Order Number:

ADP3419/D

ADP3419

Dual Bootstrapped, High

Voltage MOSFET Driver

with Output Disable

The ADP3419 is a dual MOSFET driver optimized for driving two

N-channel switching MOSFETs in nonisolated synchronous buck

power converters used to power CPUs in portable computers. The

driver impedances have been chosen to provide optimum performance

in multiphase regulators at up to 25 A per phase. The high-side driver

can be bootstrapped relative to the switch node of the buck converter

and is designed to accommodate the high voltage slew rate associated

with floating high-side gate drivers.

The ADP3419 includes an anticross-conduction protection circuit,

undervoltage lockout to hold the switches off until the driver has

sufficient voltage for proper operation, a crowbar input that turns on

the low-side MOSFET independently of the input signal state, and a

low-side MOSFET disable pin to provide higher efficiency at light

loads. The SD pin shuts off both the high-side and the low-side

MOSFETs to prevent rapid output capacitor discharge during system

shutdown.

The ADP3419 is specified over the extended commercial

temperature range of 0°C to 100°C and is available in a 10-lead MSOP

package.

FEATURES

•All-In-One Synchronous Buck Driver

•One PWM Signal Generates Both Drives

•Anticross-Conduction Protection Circuitry

•Output Disable Function

•Crowbar Control

•Synchronous Override Control

•Undervoltage Lockout

•Pb−Free Package is Available

APPLICATIONS

•Mobile Computing CPU Core Power Converters

•Multiphase Desk-Note CPU Supplies

•Single-Supply Synchronous Buck Converters

•Non-Synchronous-to-Synchronous Drive Conversion

http://onsemi.com

PIN ASSIGNMENT

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

ADP3419

DRVLSD

CROWBAR

VCC

BST

5 6

(Top View)

MARKING DIAGRAM

MSOP−10

CASE 846AC

P9x

RYWG

P9x = Device Code

x = A or B

R = Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

(Note: Microdot may be in either location)

DRVH

GND

DRVL

ADP3419

http://onsemi.com

Figure 1. Simplified Block Diagram Figure 2. General Application Circuit

CROWBAR

UVLO,

OVERLAP

PROTECTION,

SHUTDOWN

AND

CROWBAR

CIRCUITS

BSTVCC

DRVH

DRVL

GND

ADP3419

105

DRVLSD 3

SD 2

VCC

BST

DRVH

DRVLSD

CROWBAR

GND

DRVL

ADP3419

VDC

VOUT

FROM SYSTEM

ENABLE CONTROL

FROM CONTROLLER

PWM OUTPUT

FROM

CONTROLLER

FROM CONTROLLER

CLAMP OUTPUT

ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

VCC −0.3 to +7.0 V

BST −0.3 to +30 V

BST to SW −0.3 to +7.0 V

SW −3.0 to +25 V

DRVH SW −0.3 to BST +0.3 V

DRVL −0.3 to VCC +0.3 V

All Other Inputs and Outputs −0.3 to VCC +0.3 V

qJA 2-Layer Board

4-Layer Board

340

220

°C/W

Operating Ambient Temperature Range 0 to 100 °C

Junction Temperature Range 0 to 150 °C

Storage Temperature Range −65 to +150 °C

Lead Temperature Range

Soldering (10 s)

Vapor Phase (60 s)

Infrared (15 s)

300

215

220

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

ADP3419

http://onsemi.com

PIN ASSIGNMENT

Pin No. Mnemonic Description

1 IN Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling

this pin low turns on the low-side driver; pulling it high turns on the high-side driver.

2 SD Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low.

3 DRVLSD Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled

and controlled by IN and by the adaptive overlap protection control circuitry.

4 CROWBAR Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition.

5 VCC Input Supply. This pin should be bypassed to GND with a 4.7 mF or larger ceramic capacitor.

6 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

7 GND Ground. This pin should be closely connected to the source of the lower MOSFET.

8 SW Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s

source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the

switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.

9 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

10 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins

holds this bootstrapped voltage for the high-side MOSFET as it is switched.

ELECTRICAL CHARACTERISTICS VCC = SD = 5.0 V, BST = 4.0 V to 26 V. TA = 0°C to 100°C, unless otherwise noted All limits at

temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.

Parameter Symbol Conditions Min Typ Max Unit

LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR)

Input Voltage High VIH 2.0 V

Input Voltage Low VIL 0.8 V

Input Current IIN Inputs = 0 V or 5.0 V −1.0 +1.0 mA

DRVLSD Propagation Delay Time tpdl DRVLSD,

tpdh DRVLSD

CLOAD = 3 nF, Figure 3 20 ns

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current BST − SW = 4.6 V 1.7 3.3 W

Output Resistance, Sinking Current BST − SW = 4.6 V 0.8 2.3 W

Transition Times trDRVH

tfDRVH

BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4

Propagation Delay Times (Note 1) tpdhDRVH

tpdlDRVH

BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4

15 32

LOW-SIDE DRIVER

Output Resistance, Sourcing Current 1.7 3.3 W

Output Resistance, Sinking Current 0.8 2.3 W

Transition Times trDRVL

tfDRVL

CLOAD = 3 nF, Figure 4

Propagation Delay Times (Note 2) tpdhDRVL

tpdlDRVL

CLOAD = 3 nF, Figure 4

SW Transition Timeout (Note 1 and 2) tSWTO BST − SW = 4.6 V 150 350 600 ns

Zero-Crossing Threshold VZC 1.0 V

SUPPLY

Supply Voltage Range VCC 4.6 6.0 V

Supply Current

Normal Mode

Shutdown Mode

ISYS(NM)

ISYS(SD)

ICC + IBST

, IN = 0 V or 5.0 V

ICC + IBST

, SD = 0 V

0.8

325

1.5

600

Undervoltage Lockout Threshold VCC rising 3.8 4.25 4.5 V

Undervoltage Lockout Hysteresis

(Note 3)

VCC falling 50 120 mV

1. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%.

2. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO.

3. Guaranteed by characterization, not production tested.

ADP3419

http://onsemi.com

Figure 3. Output Disable Timing Diagram

(Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted)

Figure 4. Non−Overlap Timing Diagram

(Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted)

DRVLSD

DRVL

tpdlDRVLSD

0.8V

2.0V

tpdhDRVLSD

DRVL

DRVH−SW

tpdhDRVH

tpdlDRVH

trDRVH

tpdlDRVL tfDRVL

tfDRVH

tpdhDRVL

trDRVL

VTH

tSWTO

VTH

ADP3419

http://onsemi.com

TYPICAL CHARACTERISTICS

Figure 5. DRVH Rise and DRVL Fall Times

CH1 = IN, CH2 = DRVH, CH3 = DRVL Figure 6. DRVH Fall and DRVL Rise Times

CH1 = IN, CH2 = DRVH, CH3 = DRVL

Figure 7. DRVH Rise and Fall Times vs.

Temperature

Figure 8. DRVL Rise and Fall Times vs.

Temperature

Figure 9. DRVH and DRVL Rise Times vs. Load

acitance

Figure 10. DRVH and DRVL Fall Times vs. Load

acitance

TIME (ns)

JUNCTION TEMPERATURE (°C)

0 25 50 75 100 125

VCC = 5V

CLOAD = 3nF

RISE TIME

FALLTIME

RISE TIME (ns)

LOAD CAPACITANCE (nF)

DRVH

DRVL

108642

VCC = 5V

TA = 25°C

FALL TIME (ns)

LOAD CAPACITANCE (nF)

DRVH

DRVL

010864

VCC = 5V

TA = 25°C

TIME (ns)

JUNCTION TEMPERATURE (°C)

0 25 50 75 100 125

VCC = 5V

CLOAD = 3nF

RISE TIME

FALLTIME

ADP3419

http://onsemi.com

TYPICAL CHARACTERISTICS

Figure 11. DRVH and DRVL tpdh vs. Temperature Figure 12. DRVH and DRVL tpdl vs. Temperature

Figure 13. IN Pin Input Current vs. Input Voltage Figure 14. Supply Current vs. Frequency

Figure 15. Supply Current vs. Temperature

TIME (ns)

JUNCTION TEMPERATURE (°C)

0 25 50 75 100 125

VCC = 5V

CLOAD = 3nF tpdlDRVH

tpdlDRVL

100

PEAK INPUT CURRENT (μA)

INPUT VOLTAGE (V)

01 2 3 4 5

VCC = 5V

CLOAD

A = 25°C

= 3nF

0 200 400 600 800 1000 1200

ISYS CURRENT (mA)

IN FREQUENCY (kHz)

VCC = BST = 5V

CLOAD

A = 25°C

= 3nF

1.5

1.0

0.5

ISYS CURRENT (mA)

JUNCTION TEMPERATURE (°C)

0 25 50 75 100 125

VCC = 5V

CLOAD = 3nF

TIME (ns)

JUNCTION TEMPERATURE (°C)

0 25 50 75 100 125

VCC = 5V

CLOAD = 3nF tpdhDRVH

tpdhDRVL

ADP3419

http://onsemi.com

Theory of Operation

The ADP3419 is a dual MOSFET driver optimized for

driving two N-channel MOSFETs in a synchronous buck

converter topology. A single PWM input signal is all that is

required to properly drive the high-side and the low-side

MOSFETs. Each driver is capable of driving a 3 nF load at

speeds up to 1 MHz. A more detailed description of the

ADP3419 and its features follows. Refer to the detailed

block diagram in Figure 16.

Figure 16. Detailed Block Diagram of the ADP3419

ADP3419

VCC

CROWBAR

VCC

BST

DRVH

GND

DRVL

UVLO

AND BIAS

OVERLAP

PROTECTION

AND

TIME−OUT

CIRCUIT

RBST CBST

VDCIN

DRVLSD

Undervoltage Lockout

The undervoltage lockout (UVLO) circuit holds both

MOSFET driver outputs low during VCC supply ramp-up.

The UVLO logic becomes active and in control of the driver

outputs at a supply voltage of no greater than 1.5 V. The

UVLO circuit waits until the VCC supply has reached a

voltage high enough to bias logic level MOSFETs fully on

before releasing control of the drivers to the control pins.

Driver Control Input

The driver control input (IN) is connected to the duty ratio

modulation signal of a switch-mode controller. IN can be

driven by 2.5 V to 5.0 V logic. The output MOSFETs are

driven so that the SW node follows the polarity of IN.

Low-Side Driver

The low-side driver is designed to drive a

ground-referenced low RDS(ON) N-channel synchronous

rectifier MOSFET. The bias to the low-side driver is

internally connected to the VCC supply and GND. Once the

supply voltage ramps up and exceeds the UVLO threshold,

the driver is enabled. When the driver is enabled, the driver’s

output is 180° out of phase with the IN pin. Table 2 shows

the relationship between DRVL and the different control

inputs of the ADP3419.

High-Side Driver

The high-side driver is designed to drive a floating low

RDS(ON) N-channel MOSFET. The bias voltage for the

high-side driver is developed by an external bootstrap supply

circuit, which is connected between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

capacitor, CBST. When the ADP3419 is starting up, the SW

pin is at ground, so the bootstrap capacitor charges up to

VCC through D1. Once the supply voltage ramps up and

exceeds the UVLO threshold, the driver is enabled. When IN

goes high, the high-side driver begins to turn on the

high-side MOSFET (Q1) by transferring charge from CBST.

As Q1 turns on, the SW pin rises up to VDCIN, forcing the

BST pin to VDCIN + VC(BST), which is enough

gate-to-source voltage to hold Q1 on. To complete the cycle,

Q1 is switched off by pulling the gate down to the voltage at

the SW pin. When the low-side MOSFET (Q2) turns on, the

SW pin is pulled to ground. This allows the bootstrap

capacitor to charge up to VCC again.

When the driver is enabled, the driver’s output is in phase

with the IN pin. Table 2 shows the relationship between

DRVH and the different control inputs of the ADP3419.

Overlap Protection Circuit

The overlap protection circuit prevents both main power

switches, Q1 and Q2, from being on at the same time. This

is done to prevent shoot-through currents from flowing

through both power switches and the associated losses that

can occur during their on-off transitions. The overlap

protection circuit accomplishes this by adaptively

controlling the delay from Q1’s turn-off to Q2’s turn-on, and

the delay from Q2’s turn-off to Q1’s turn-on.

To prevent the overlap of the gate drives during Q1’s

turn-off and Q2’s turn-on, the overlap circuit monitors the

voltage at the SW pin and DRVH pin. When IN goes low, Q1

begins to turn off. The overlap protection circuit waits for

the voltage at the SW and DRVH pins to both fall below

1.6 V. Once both of these conditions are met, Q2 begins to

turn on. Using this method, the overlap protection circuit

ensures that Q1 is off before Q2 turns on, regardless of

variations in temperature, supply voltage, gate charge, and

drive current. There is, however, a timeout circuit that

overrides the waiting period for the SW and DRVH pins to

reach 1.6 V. After the timeout period has expired, DRVL is

asserted high regardless of the SW and DRVH voltages. In

the opposite case, when IN goes high, Q2 begins to turn off

after a propagation delay. The overlap protection circuit

waits for the voltage at DRVL to fall below 1.6 V, after which

DRVH is asserted high and Q1 turns on.

Low-Side Driver Shutdown

The low-side driver shutdown DRVLSD allows a control

signal to shut down the synchronous rectifier. Under light

load conditions, DRVLSD should be pulled low before the

polarity reversal of the inductor current to maximize light

load conversion efficiency. DRVLSD can also be pulled low

for reverse voltage protection purposes.

ADP3419

http://onsemi.com

When DRVLSD is low, the low-side driver stays low.

When DRVLSD is high, the low-side driver is enabled and

controlled by the driver signals, as previously described.

Low-Side Driver Timeout

In normal operation, the DRVH signal tracks the IN signal

and turns off the Q1 high-side switch with a few 10 ns delay

(tpdlDRVH) following the falling edge of the input signal.

When Q1 is turned off, DRVL is allowed to go high, Q2 turns

on, and the SW node voltage collapses to zero. But in a fault

condition such as a high-side Q1 switch drain-source short

circuit, the SW node cannot fall to zero, even when DRVH

goes low. The ADP3419 has a timer circuit to address this

scenario. Every time the IN goes low, a DRVL on-time delay

timer is triggered. If the SW node voltage does not trigger a

low-side turn-on, the DRVL on-time delay circuit does it

instead, when it times out with tSW(TO) delay. If Q1 is still

turned on, that is, its drain is shorted to the source, Q2 turns

on and creates a direct short circuit across the VDCIN voltage

rail. The crowbar action causes the fuse in the VDCIN current

path to open. The opening of the fuse saves the load (CPU)

from potential damage that the high-side switch short circuit

could have caused.

Crowbar Function

In addition to the internal low-side drive time-out circuit,

the ADP3419 includes a CROWBAR input pin to provide a

means for additional overvoltage protection. When

CROWBAR goes high, the ADP3419 turns off DRVH and

turns on DRVL. The crowbar logic overrides the overlap

protection circuit, the shutdown logic, the DRVLSD logic,

and the UVLO protection on DRVL. Thus, the crowbar

function maximizes the overvoltage protection coverage in

the application. The CROWBAR can be either driven by the

CLAMP pin of buck controllers, such as the ADP3422,

ADP3203, ADP3204, or ADP3205, or controlled by an

independent overvoltage monitoring circuit.

Table 1. ADP3419 Truth Table

CROWBAR UVLO SD DRVLSD IN DRVH DRVL

L L H H H H L

L L H H L L H

L L H L H H L

L L H L L L L

L L L * * L L

L H * * * L L

H L * * * L H

H H * * * L H

* = Don’t Care.

Application Information

Supply Capacitor Selection

For the supply input (VCC) of the ADP3419, a local

bypass capacitor is recommended to reduce the noise and to

supply some of the peak currents drawn. Use a 10 mF or

4.7 mF multilayer ceramic (MLC) capacitor. MLC

capacitors provide the best combination of low ESR and

small size, and can be obtained from the following vendors.

Table 2.

Vendor Part Number Web Address

Murata GRM235Y5V106Z16 www.murata.com

Taiyo-Yuden EMK325F106ZF www.t-yuden.com

Tokin C23Y5V1C106ZP www.tokin.com

Keep the ceramic capacitor as close as possible to the ADP3419.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

(CBST) and a Schottky diode (D1), as shown in Figure 16.

Selection of these components can be done after the

high-side MOSFET has been chosen. The bootstrap

capacitor must have a voltage rating that is able to handle at

least 5.0 V more than the maximum supply voltage. The

capacitance is determined by:

CBST +QHSGATE

DVBST

(eq. 1)

where:

QHSGATE is the total gate charge of the high-side MOSFET.

DVBST is the voltage droop allowed on the high-side

MOSFET drive.

For example, two IRF7811 MOSFETs in parallel have a

total gate charge of about 36 nC. For an allowed droop of

100 mV, the required bootstrap capacitance is 360 nF. A

good quality ceramic capacitor should be used, and derating

for the significant capacitance drop of MLCs at high

temperature must be applied. In this example, selection of

470 nF or even 1 mF would be recommended.

A Schottky diode is recommended for the bootstrap diode

due to its low forward drop, which maximizes the drive

available for the high-side MOSFET. The bootstrap diode

must also be able to handle at least 5.0 V more than the

maximum battery voltage. The average forward current can

be estimated by:

IF(AVG) +QHSGATE fMAX (eq. 2)

where fMAX is the maximum switching frequency of the

controller.

Power and Thermal Considerations

The major power consumption of the ADP3419-based

driver circuit is from the dissipation of MOSFET gate

charge. It can be estimated as:

PMAX [VCC (QHSGATE )QLSGATE) fMAX (eq. 3)

where:

VCC is the supply voltage 5.0 V.

fMAX is the highest switching frequency.

QHSGATE and QLSGATE are the total gate charge of high-side

and low-side MOSFETs, respectively.

For example, the ADP3419 drives two IRF7821 high-side

MOSFETs and two IRF7832 low-side MOSFETs. According

ADP3419

http://onsemi.com

to the MOSFET data sheets, QHSGATE = 18.6 nC and

QLSGATE = 68 nC. Given that fMAX is 300 kHz, PMAX would

be about 130 mW.

Part of this power consumption generates heat inside the

ADP3419. The temperature rise of the ADP3419 against its

environment is estimated as:

DT[qJA PMAX h(eq. 4)

where θJA is ADP3419’s thermal resistance from junction

to air, given in the absolute maximum ratings as 220°C/W

for a 4−layer board.

The total MOSFET drive power dissipates in the output

resistance of ADP3419 and in the MOSFET gate resistance

as well. η represents the ratio of power dissipation inside the

ADP3419 over the total MOSFET gate driving power. For

normal applications, a rough estimation for η is 0.7. A more

accurate estimation can be calculated using:

h[QHSGATE

QHSGATE )QLSGATE ǒ0.5 R1

R1 )RHSGATE )R)0.5 R2

R2 )RHSGATEǓ

(eq. 5)

)QLSGATE

QHSGATE )QLSGATE ǒ0.5 R3

R3 )RLSGATE )0.5 R4

R4 )RLSGATEǓ

where:

R1 and R2 are the output resistances of the high-side driver:

R1 = 1.7 (DRVH − BST), R2 = 0.8 (DRVH − SW).

R3 and R4 are the output resistances of the low-side driver:

R3 = 1.7 (DRVL − VCC), R4 = 0.8 (DRVL − GND).

R is the external resistor between the BST pin and the BST

capacitor.

RHSGATE and RLSGATE are gate resistances of high-side and

low-side MOSFETs, respectively.

Assuming that R = 0 and that RHSGATE = RLSGATE = 0.5,

Equation 5 gives a value of η = 0.71. Based on Equation 4,

the estimated temperature rise in this example is about 22°C.

PC Board Layout Considerations

Use the following general guidelines when designing

printed circuit boards. Figure 17 gives an example of the

typical land patterns based on the guidelines given here.

•The VCC bypass capacitor should be located as close as

possible to the VCC and GND pins. Place the

ADP3419 and bypass capacitor on the same layer of the

board, so that the PCB trace between the ADP3419

VCC pin and the MLC capacitor does not contain any

via. An ideal location for the bypass MLC capacitor is

near Pin 5 and Pin 6 of the ADP3419.

•High frequency switching noise can be coupled into the

VCC pin of the ADP3419 via the BST diode.

Therefore, do not connect the anode of the BST diode

to the VCC pin with a short trace. Use a separate via or

trace to connect the anode of the BST diode directly to

the VCC 5.0 V power rail.

•It is best to have the low-side MOSFET gate close to

the DRVL pin; otherwise, use a short and very thick

PCB trace between the DRVL pin and the low-side

MOSFET gate.

•Fast switching of the high-side MOSFET can reduce

switching loss. However, EMI problems can arise due

to the severe ringing of the switch node voltage.

Depending on the character of the low-side MOSFET, a

very fast turn-on of the high-side MOSFET may falsely

turn on the low-side MOSFET through the dv/dt

coupling of its Miller capacitance. Therefore, when fast

turn-on of the high-side MOSFET is not required by the

application, a resistor of about 1 W to 2 W can be placed

between the BST pin and the BST capacitor to limit the

turn-on speed of the high-side MOSFET.

Figure 17. External Component Placement Example

CVCC

CBST

RBST

SHORT, THICK TRACE

TO THE GATES OF

LOW-SIDE MOSFETS

TO SWITCH

NODE

ORDERING INFORMATION

Device Number Branding Package Type Shipping†

ADP3419JRM−REEL P9A 10−Lead MSOP 3000 Tape & Reel

ADP3419JRMZ−REEL P9B 10−Lead MSOP 3000 Tape & Reel

ADP34190091RMZR P9B 10−Lead MSOP 3000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*The “Z’’ suffix indicates Pb−Free part.

ADP3419

http://onsemi.com

PACKAGE DIMENSIONS

MSOP10

CASE 846AC−01

ISSUE O

0.08 (0.003) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.95 1.10 0.037 0.043

D0.20 0.30 0.008 0.012

G0.50 BSC 0.020 BSC

H0.05 0.15 0.002 0.006

J0.10 0.21 0.004 0.008

K4.75 5.05 0.187 0.199

L0.40 0.70 0.016 0.028

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION “A” DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE

BURRS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

4. DIMENSION “B” DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. 846B−01 OBSOLETE. NEW STANDARD

846B−02

−B−

−A−

PIN 1 ID 8 PL

0.038 (0.0015)

−T−SEATING

PLANE

HJL

ǒmm

inchesǓ

SCALE 8:1

10X 10X

1.04

0.041

0.32

0.0126

5.28

0.208

4.24

0.167

3.20

0.126

0.50

0.0196

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

ADP3419/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative