CY2291/CY2291F/CY22911 = a Te 2 CY2292/CY2292F/CY22921 SS. ss CY2295/CY2295l = = F CYPRESS Three-PLL General Purpose EPROM Programmable Clock Generator Features Benefits + Three integrated phase-locked loops Provides all necessary system clocks in a single package * EPROM programmability Easy customization and fast turnaround time * Low skew, low jitter, high accuracy outputs Meets critical timing requirements in complex system designs + Power management options (Shutdown, OE, Suspend) Supports low power applications + Frequency select option Enables design flexibility and margin testing * Smooth slewing on CPUCLK Allows downstream PLLs to stay locked on CPUCLK output 3.3V or 5V operation Enables application compatibility 1 MHz-30 MHz (reference clock) Part Number | Outputs Input Frequency Range Output Frequency Range Specifics CY2291 & 10 MHz-25 MHz (external crystal) | 76.923 kHz100 MHz (5V) Factory Programmable 1 MHz-30 MHz (reference clock) | 76.923 kKHz-80 MHz (3.3V} Commercial Temperature CY2291| 8 10 MHz-25 MHz (external crystal) | 76.923 kKHz-90 MHz (5V) Factory Programmable 1 MHz-30 MHz (reference clock) | 76.923 kKHz66.6 MHz (3.3V) Industrial Temperature CY2291F 8 10 MHz-25 MHz (external crystal) | 76.923 kKHz-90 MHz (5V) Field Programmable 1 MHz-30 MHz (reference clock) | 76.923 kHz-66.6 MHz (3.3V} Commercial Temperature CY2292 6 10 MHz-25 MHz (external crystal) | 76.923 kHz100 MHz (5V) Factory Programmable 1 MHz-30 MHz (reference clock) | 76.923 kKHz-80 MHz (3.3V} Commercial Temperature CY2292! 6 10 MHz-25 MHz (external crystal) | 76.923 kKHz-90 MHz (5V) Factory Programmable 1 MHz-30 MHz (reference clock) | 76.923 kKHz66.6 MHz (3.3V) Industrial Temperature CY2292F 6 10 MHz-25 MHz (external crystal) | 76.923 kKHz-90 MHz (5V) Field Programmable 1 MHz-30 MHz (reference clock) | 76.923 kHz-66.6 MHz (3.3V} Commercial Temperature CY2295 & 10 MHz-25 MHz (external crystal) | 76.923 kHz100 MHz (5V) Factory Programmable 1 MHz-30 MHz (reference clock) | 76.923 kKHz-80 MHz (3.3V} Commercial Temperature CY2295| 8 10 MHz-25 MHz (external crystal) | 76.923 kKHz-90 MHz (5V) Factory Programmable 76.923 kHz-68.6 MHz (3.3V) Industrial Temperature Logic Block Diagram I 1 82XIN BET ogc, >] 32k ! 1 32XOUT KH ae Le art eee ee ee eee, I I XTALIN Be I I osc. XBUF | 1 XTALOUT KKH ----t ; I CLKF 1 se oe CPUCLK OUTPUT UTIL MULTIPLEXER GLKA PLL AND CLKE 1 | | DIVIDERS CPU CLKC PLL | CLKD S2/SUSPEND x y Ss , CPU a EPROM| CONFIGURATION SO TABLE || EPROM AND TEST LOGIC SHUTDOWN OE I Cypress Semiconductor Corporation * 3901 North FirstStreet +* SanJose * GA 95134 + 408-943-2600 November 10, 1998CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295| Pin Configurations CY2295 28-pin SSOP Cy2291 32xOUTT] 1 98 | 32XIN cY2292 20-pin SOIC sek F] 2 27 [1 Year 16-pin SOIC TT GND [] 3 26 1] Yoo P sexour [1 20 |] 32xIN cLKoE 4 2s F] SHUTDOWNIOE 1 ie [J SHUTDOWNIOE sax T2 19 veatt vooO 5 24 ] SeSUSPEND 2 15 1] s2SUSPEND cike [3 18 [] SHUTDOWNOE voo He 23 Hl \bo 3 1410) po bo [4 17 1) se/SUSPEND enoH 7 2 FH vbo 4 8D st end 5 "6D Yoo GND] s 21 [GND 5 12) so XTALIN [6 5 si XxTALINE] 9 20 81 6 11 GND xTALOUTEY7 "D1 so xTALOUT[] 10 19 1] so 7 10] cLKA xBUF [Je 87 CLKF XBUFT] 14 18] CLKF 8 9 A cue cLKD E]9 12 [1] CLKA CLED GND epueLk Tio 11 [O cLKe Q tz 70 cvz291-3 cy2201-1 we 13 16 CLA cPucLKL] 14 1s 7] cLKB cY2291-4 Pin Summary PinNumber | PinNumber | Pin Number Name cY2291 CY2292 CY2295 Description 32XOUT 1 1 32.768 kHz crystal feedback 32K 2 _ 2 32.768 kHz output (always active if Vga77 is present) CLKG 3 1 4 Configurable clock output G Vop 4,16 2,14 5, 6, 22,23, 26 | Vollage supply GND 5 3,11 3, 7,8, 17, 21 Ground XTALINU 6 9 Reference crystal input or external reference clock input XTALOUTH. 4] 7 5 10 Reference crystal feedback XBUF 8 6 11 Buffered reference clock output CLKD 9 7 12 Configurable clock output D GPUCLK 10 8 14 GPU frequency clock output CLKB 11 9 15 Configurable clock output B CLKA 12 10 16 Configurable clock output A CLKF 13 18 Configurable clock output F SO 14 12 19 GPU clock select input, bit 0 $1 15 13 20 GPU clock select input, bit 1 S2/SUSPEND 17 15 24 GPU clock select input, bit 2. Optionally enables suspend feature when LOW [4] SHUTDOWN/OE | 18 16 25 Places outputs in three-statel4l condition and shuts down chip when LOW. Optionally, only places outputs in three-state!4l condition and does not shut down chip when LOW Veatr 19 _ 27 Battery supply for 32.768-kHz circuit 32XIN 20 _ 28 32.768-kHz crystal input Notes: 1. For best accuracy, use a parallel-resonant crystal, C, gap = 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock fas opposed to crystal}. 3. Please refer to application note Understanding the CY2291, C2292 and GY2295" for more information. 4. The C2291 has weak pull-downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295| Operation The CY2291 , CY2292 and CY2295 are a third-generation fam- ily of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and |CD2028 and contin- ues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. The CY2292 differs from the CY2291 in that it comes in a 16-pin 150-mil SOIC package, and does not provide either the 32-kHz or CLKF outputs. The CY2295 is available in a space-saving 28-pin SSOP package. All parts provide a highly configurable set of clocks for PG motherboard applications. Each of the four configurable clock outputs (CLKA-GLKD)} can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related!4] frequencies will have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The GY2291, CY2292, and CY2295 can be configured for el ther 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output fre- quencies. The reference oscillator has been designed for 10-MHz to 25-MHz crystals, providing additional flexibility. No external components are required with this crystal. Alterna- tively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Customers using the 32-kHz oscil- later on the CY2291 or CY2295 should connect a 10-MQ re- sistor in parallel with the 32-kHz crystal. Output Configuration The C2291 and CY2295 (and CY2292) have five (four) inde- pendent frequency sources on chip. These are the 32-kHz os- cillator (not available on CY2292}, the reference oscillator, and three Phase Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) drives the CLKF output (not available on C2292) and provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divicer options. The GPU PLL (GPLL) is controlled by the select inputs (SOS2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the applica- tion note Understanding the CY2291, CY2292, and CY2295 for information on configuring the part. Power Saving Features The SHUTDOWN/OE input three-states the outputs when pulled LOW (the 32-kHz clock output is not affected). If system shutdown is enabled (the default), a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the Vpp pins will be less than 50 pA (for Commercial Temp. or 100 WA for Indus- trial Temp.) plus 15 WA max. for the 32-kHz subsystem and is typically 10 pA. After leaving shutdown mede, the PLLs will have to re-lock. All outputs except 32K have a weak pull-down so that the outputs do not float when three-stated [4 The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs except 32K can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, alll outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition I The GPUCLK can slew (transition) smoothly between 8 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V for Industrial Temp. and for field-programmed parts). This feature is extremely useful in Green PC and laptop ap- plications, where reducing the frequency of operation can re- sult in considerable power savings. This feature meets all 486 and Pentium processor slewing requirements. CyClocks Software CyClocks is an easy-to-use application that allows you to con- figure any one of the EPROM programmable clocks offered by Cypress. You may specify the input frequency, PLL & output frequencies, and different functional options. Please note the output frequency ranges in this datasheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific configuration. You can download a copy of CyClocks for free on Cypresss website at www.cypress.com.CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295| Maximum Ratings (Above which the useful life may be impaired. For user guide- Max. Soldering Temperature (10 sec) 0... 260C lines, not tested.) Junction Temperature... ccc ceteceeeieereies 150C Supply Voltage oo... eee 0.5V to +7.0V Package Power Dissipation .........cc...sssssssssesseseeeeeeee 750 mW DG Input Voltage ns -0.5V to +7.0V Static Discharge Voltage oo >2000V Storage Temperature oo... eee 65C to +150C (per MIL-STD-883, Method 3015} Operating Conditions! Parameter Description Part Numbers Min. Max. Unit Vop Supply Voltage, 5.0V (3.3V) operation All 4.5 (3.0) 5.5 (3.6) Vv Veatt Battery Backup Voltage All 2.0 5.5 V Ta Operating Temperature, Ambient CY2291/CY2291F 0 +70 C CY2292/CY2292F CY2295 CY2291| 40 +85 C CY2292| CY2295| CLloap Max. Load Capacitance 5.0V (3.3V) Operation All 25 (15) pF frReF Reference Frequency All 10.0 25.0 MHz fRer Reference Frequency, External Reference All 1 30 MHz Clock! 71 Electrical Characteristics Parameter Description Conditions Min. Typ. Max. | Unit Voy!2 HIGH-Level Output Voltage | loy=4.0 mA 24 Vv Vo! LOW-Level Output Voltage | Io, = 4.0 mA 0.4 Vv VoH-32 32.768-kHz HIGH-Level loo =05mA Veatt V Output Voltage 0.5 VoL_32 32.768-kHz LOW-Level lol = 0.5 mA 04 Vv Output Voltage Vin HIGH-Level Input Voltage! | Except crystal pins 2.0 V Vib LOW-Level Input VoltagelS! | Except crystal pins 0.8 V Wy Input HIGH Current Vin = Vpp0.5V <1 10 pA ie Input LOW Current Vin = +0.5V <4 10 HA loz Output Leakage Current Three-state outputs 250 pA Ipp Vpp Supply Current! Vop = Vpp max., 5V (3.3) operation 75(50) | 100(65) | mA loos Vpp Power Supply Current in | Shutdown active, C2291/C2291F 10 50 HA Shutdown Mode!l excluding Vaatt CY2292/C2292F CY2295 CY2291| 10 100 pA CY2292| CY2295| lBatt Veart Power Supply Current | Vpaq7 = 3.0V 5 15 LA Notes: 5. Electrical parameters are guaranteed with these operating conditions. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at Vpp/2. 7. Please refer to application note Crystal Oscillator Topics for information on AG-coupling the external input reference clock. 8. All outputs swing rail to rail. 9. Xtal inputs have CMOS thresholds. = S formula (multiply by 0.65 for 3V operation): Ipp=10+0.06*(Fep_.+Fyp__+2F gay) +0.27*(F oi katFo_kp+FoLkc+FoLko+Fopucikt+Forkr+Fxaur) Load = Max., Vij. = OV or Vpp, Typical (-104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the followingCY2291/CY2291F/CY22911 CY2292/CY2292F/CY2292I CY2295/CY2295| Switching Characteristics!" Parameter Name Description Min. Typ. Max. Unit ty Output Period Clock output range, CY2291 10 13000 ns 5V operation CY2292 (100 MHz) (76.923 kHz) CY2295 CY2291F/CY2291 | 4 13000 ns CY2292F/CY2291| | (90 MHz} (76.923 kHz) CY2295| ty Output Period Clock output range, 3.3V | CY2291 125 13000 ns operation CY2292 (80 MHz) (76.923 kHz) CY2295 CY2291F/CY2291 | 15 13000 ns CY2292F/CY22911 | (66.6 MHz) (76.923 kHz) CY2295| Output Duty Duty cycle for outputs, defined as tp + t,! "4! 40% 50% 60% Cyclel!4] four = 66 MHZ Duty cycle for outputs, defined as tp + t,!74l 45% 50% 55% tg Rise Time Output clock rise time! 3 3 ns ta Fall Time Output clock fall time!!4] 2.5 4 ns ts Output Disable Time for output to enter three-state mode after 10 15 ns Time SHUTDOWN/OE goes LOW te OCutput Enable Time | Time for output to leave three-state mode after 10 15 ns SHUTDOWN/OE goes HIGH tz Skew Skew delay between any identical or related <0.25 O56 ns outputs!*: 75] tg GPUCLK Slew Frequency transition rate 1.0 20.0 MHz/ ms ton Clock Jitter!'*! Peak-to-peak period jitter (tga max. tga min.}, <0.5 { % % of clock period (fgy7 < 4 MHz) top Clock Jitter!) Peak-to-peak period jitter (tg max. tgg min.) <0.7 1 ns (4 MHz < foyt = 16 MHz} tac Clock Jitter!) Peak-to-peak period jitter <400 500 ps (16 MHz < fgy7 < 50 MHz) tsp Clock Jitter!'*! Peak-to-peak period jitter <250 350 ps (fout > 50 MHz} toa Lock Time for CPLL | Lock Time from Power-up <25 50 ms trop Lock Time for UPLL | Lock Time from Power-up <0.25 1 ms and SPLL Slew Limits GPU PLL Slew Limits CY2291 8 100 (5V} MHz CY2292 80 (3.3V) CY2295 CY2291F/CY2291 | 8 90 (SV) MHz CY2292F/CY2291 | 66.6 (3.34) CY2295| Notes: 11. Guaranteed by design and characterization, not 100% tested in production. 12. XBUF duty cycle depends on XTALIN duty cycle. 13. Measured at 1.4. 14. Measured between 0.4V and 2.4V. 15. Jitter varies with configuration. All standard configurations sample tested at the factory contorm to this limit. For more information on jitter, please refer to the application note: Jitter in PLL-Based Systems.CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295| Switching Waveforms All Outputs, Duty Cycle and Rise/Fall Time OUTPUT tg oYe291-7 Output Three-State Timing!! \ =| ts ALL THREE-STATE OUTPUTS Cv2201-8 CLK Outputs Jitter and Skew tan CLK OUTPUT ty RELATED CLK CY2291-9 CPU Frequency Change SELECT OLD SELECT y4 NEW SELECT STABLE Foig tg & tio ' CPU NG F new CY2291-10CY2291/CY2291F/CY22911 CY2292/CY2292F/CY2292I CY2295/CY2295| 0.1 WF T OUTPUTS T CLoap Yoo 1 0.1 LF | ~ = GND O2201-11 Ordering Information Package Operating Operating Ordering Code Name Package Type ange Voltage CY2291SC-XXX $5 20-Pin SOIG Gommercial 5.0V CY2292SC-XXX S16 16-Pin SOIC Commercial 5.0V CY2295PVC-XXX O28 28-Pin SSOP Commercial 5.0V GY2291SL-XXX S85 20-Pin SOIG Gommercial 3.3V CY2292SL-XXX S16 16-Pin SOIC Commercial 3.3V CY2295PVL-XXX O28 28-Pin SSOP Commercial 3.3V CY2291F $5 20-Pin SOIG Commercial 3.3V or 5.0V CY2292F $16 16-Pin SOIC Commercial 3.3V or 5.0V CY2291S|I-XXX $5 20-Pin SOIG Industrial 3.3V of 5.0V GCY2292S|I-XXX $16 16-Pin SOIG Industrial 3.3V of 5.0V CY2295PVI-XXX O28 28-Pin SSOP Industrial 3.3V of 5.0V Document #: 38-00410-D Custom Configuration Request Procedure The CY229x are EPROM-programmable devices which may be configured in the factory or in the field by a Cypress Field Application Engineer (FAE). The output frequencies requested will be matched as closely as the internal PLL divider and multi- plier options allow. All custom requests must be submmitted to your local Cypress FAE or sales representative. There are two methods to use to request custom configurations: 1. Use CyClocks software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free-of-charge fromthe Cypress website (http:/Avwww.cypress.com} or from your local sales representative. 2. Use the custom configuration form attached. All areas must be filled in with the exception of shaded cells and the form submitted to the appropriate Cypress FAE or sales representative. If requesting samples through the factory: Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., C22925C-128) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders.CY2291/CY2291F/CY2291I CY2292/CY2292F/CY2292I CY2295/CY2295| CY2291/2/5 CUSTOM CONFIGURATION REQUEST FORM Please submit to your local FAE or sales representative Company Engineer FAE/Sales Phone# Fax# Date CIRCLE ONE cY2291 CcY2292 CY2295 The CY2291, CY2295, and C2292 are the industry's most flexible frequency synthesizers, offering a high degree of config- urability due to their unique internal programmable EPROM array. Of the CY2291/2/5's outputs, six (five on the CY2292) may be defined within the scope of the PLL frequencies and divider criteria described in the following. Shaded areas are for Cypress use only. Contact your local Cypress representative for assistance. 1. OPERATING VOLTAGE (Circle one) 3.3V 5.0V 2. INPUT REFERENCE FREQUENCY (Circle one) Crystal External Clock 14.31818 MHz (Default) If a different reference is required, specify the frequency in the box to the right (must be between 10 MHz and 25 MHz for crystal, 1 MHz and 30 MHz for external clock): LT 3. CPU-PLL (CPLL) FREQUENCIES (Off'is a valid selection for any address and will automatically be entered for blanks.) Select Requested Actual $2 $1 So 000 Ifthe Suspend Opticn is specified in #7 below, the Select MSB 004 (S2) serves a dual function as both the MSB CPU address and as the Suspend select pin. The GPU frequencies speci- 010 fied for addresses 000-01 1 will be active unless the CPU-PLL od1i4 is shut down during the suspend mode (CPU-PLL is circled 100 in #7}. Also, any outputs derived from a non-suspended 101 CPU-PLL (assigned in #5 as options 5-8) that are not circled 110 in #7 will remain active during the suspend moce. 1144 Range: 8-100 MHz at 5V; 8-80 MHz at 3.3V (Commercial) 8-90 MHz at 5V, 8-66.6 MHz at 3.3V (Industrial/Field-Prog) Default = Off? for all selections 4. UTILITY-PLL (UPLL) AND SYSTEM-PLL (SPLL) FREQUENCIES (Off is a valid frequency selection for either PLL.} To minimize harmonic effects, avoid setting any PLL to an equal or multiple frequency of another PLL. Requested Actual Requested Actual UPLL | | SPLL_ | | Range: 8-100 MHz at 5V; 8-80 MHz at 3.3V (Commercial) Range: 8-100 MHz at 5V; 8-80 MHz at 3.3V (Commercial) 8-90 MHz at 5V, 8-66.6 MHz at 3.3V (Industrial/Field-Prog) 8-90 MHz at 5V, 8-66.6 MHz at 3.3V (Industrial/Field-Prog) Default = 96 MHz at 5V; 48 MHz at 3.3 Default = 96 MHz at 5V; 48 MHz at 3.3V 5. OUTPUT CONFIGURATION (Off'is a valid selection for any output and will automatically be entered for blanks.) Assign by number from the Output Options Table below and fill in the Frequency column as a double-check. Output Options Table 1.Ref 6. CPLL/2 11.UPLL/4 16. SPLL/4 21.SPLL/12 26. SPLL/40 2. Ref/2 7.CPLL/4 12.UPLL/8 17.SPLLA 22.SPLLA13 27.SPLL/48 3. Ref/4 8.CPLL/8 13.SPLL 18. SPLL/6 23.SPLL/20 28.SPLL/52 4. Ref/a8 9. UPLL 14. SPLL/2 19.5PLL/8 24. SPLL/24 29.SPLL/96 5. CPLL 10. UPLL/2 15. SPLL/3 20.SPLL/10 25. SPLL/26 30. SPLL/104 Option Frequency Option Frequency 32K (Fixed 32 kHz} = 32.768kHz CLKA (Options 130, Off) ( CLKB (Options 1 30, Off) CLKC (Options 1-30, Off) CLKD (Options 1-30, Off} CGLKF (Options 14-16, Off} XBUF (Option 1 only) GPUCLK (Options 5-7, Off} 32K and CLKF are not available on the C2292. For CLKD only: option #4 (Ref/8) is replaced with Re#/3. 6. SHUTDOWN OPTION (Circle Yes or No} Yes No 7. SUSPEND OPTION (Circle Yes or No) Yes No IF SUSPEND = Yes: Circle each resource to be shut GPU-PLL XBUF CLKA down when the Suspend mode is active (S2=0). Note that UTIL-PLL CGPUCLK CLKB suspending a PLL automatically suspends its outputs. SYS-PLL GLKF CLKCG FOR CYPRESS USE ONLY (Shaded Areas above and below) GLKD Customer Configuration Marking Date QuantityCY2291/CY2291F/CY22911 CY2292/CY2292F/CY2292I CY2295/CY2295l Package Diagrams 20-Lead (300-Mil) Molded SOIC $5 PIN 1 ID PAOOnAHnna 7 oJ} | oad | rc DIMENSIONS IN INCHES MIN. tl = x ize 0.497 o5ia elt Te nate oats _ ae 51-85024-A 16-Lead (150-Mil) Molded SOIC S16 PIN 1 ID H H H H H A | DIMENSIONS IN INCHES ~ "| 0356 0.393 yer se" _t aaa 0.0192 0.0098 os 51-85068-A 0.050 _. a BSCCY2291/CY2291F/CY22911 CY2292/CY2292F/CY2292I F CYDRESS CY2295/CY2295| Se CYPRESS 9 9 Package Diagrams (continued) 28-Lead (210-Mil) Shrunk Small Outline Package 028 nar 114 DIA _ 14 1 PIN 1 ID. DUTRTAU UVR AT ATAURUGUGI GT Ad i TF 320 DIMENSIONS IN MILLIMETERS MIN. MAX. UU 15 2g oo = 0.65 BSC. 235 MIN- _ . SEATING Vi | | a GAUGE PLANE O* MIN. f.05 | LL 025 OF 1.25 REF. ote fea 51-85079-B Cypress Semiconductor Corporation, 1998. The information contained herein is subject io change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize Its products for use as critical componenis in life-support systems where a maltunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support sysiems application implies ihat the manulacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.