TOSHIBA MOS MEMORY PRODUCTS TMM24128AP/AF 16,384 WORD x 8 BIT ONE TIME PROGRAMMABLE READ ONLY MEMORY N CHANNEL SILICON STACKED GATE MOS TMM24128AP/AF DESCRIPTION The TMM24128AP/AF is a 16,384 word x 8 bit one time programmable read only memory, and molded in a 28 pin plastic DIP. TMM24128AP/AFs access time is 200ns, and has low power standby mode which reduces the power dissipation without FEATURES @ Single 5 volt power supply e@Fast access time :200ns(Max.) @ Power dissipation: 100mA(active current) Max. 30mA\(standby current) Max. @ Low power standby mode : CE. @ Output buffer control : OE @Full static operation @ High speed programming mode PIN CONNECTION increasing access time. The electrical characteristics and programming method are the same as U.V. EPROM TMM27128ADs. Once programed, the TMM24128AP/AF can not be erased because of using plastic DIP without transparent window. @ Single location programming @ Three state outputs e@Inputs and outputs TTL compatible @ Compatible with TAM27128AD and MASK ROM TMM23128P @28 PIN standard plastic package: TMM24128AP @ 28 PIN flat package > TMM24128AF BLOCK DIAGRAM Vpp GND Veo 00 C1 0203 64 05 06 OF ar Vppdi 28D Vog OE i i q_ TPP ITE f Al2Q2 27] POM cE OE, TB and POW BITPUT BUFFERS a7g3 26413 POM 7 cme t aed4 25) as a0 asqs5 2ap ag alo . LS.} cuumn [a COLUMN [0 AZ0O- DECODER CIRCUIT aade 23} all aso & asd? 22008 MoE | } azqds 2iffalo Aso] alq 20p CE aac & Le} row |s22] wamoxy cue A0Q10 19} 07 ager] & DECODEK 16,384 8 bit oof 18{} 06 A104 < 01912 17) 05 A1l304 02413 16f) 04 Qia 03 onD 15f MODE SELECTION PIN | PGM} CE | OE | Vee | Vcc O.~O, POWER MOD (27) | (20) | (22) | (1) | (28) } (11~13, 16~19) PIN NAMES Read H L L Data Out Output Active Aa~Ars Address Inputs utp * * | H | 5V | 5V | High Impedance O,~0; Outputs (Inputs) Deselect CE Chip Enable Input Standby * H * High impedance _| Standby OE Output Enable Input Program L L * Data In PGM Program Control input Program * H * 12.5v| 6V High Impedance Active Vop Program Supply Voltage Inhibit H L H High Impedance Vec Veco Supply Voltage (+5V) Program H L L Data Out GND Ground Verity _]J *x Hart H7 TMM24128AP/AF MAXIMUM RATINGS |_ SYMBOL TEM ee ee i Vec | Vec Power Supply Voltage | [- Vep Program Supply Voltage Vin : | Input Voltage mi Output Voltage Power Dissipation RATING | ik -0.6~7.0 -0.6~7.0 -0.6~14.0 READ OPERATION D. C. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER ~ MAX. Vin Input High Voltage 7 2.0 - Vect+1.0 Vv Vit Input Low Voltage 0.3 - 0.8 Vv Vec Vcc Power Supply Voltage 4.75 5.00 5.25 Vv Vee Ver Power Supply Voltage 2.0 Vec Vect+0.6 Vv 1 D. C. and OPERATING CHARACTERISTICS (Ta=O~70C, Vec=5V+5%, Unless otherwise noted) SYMBOL PARAMETER TEST CONDITION MIN. | TYP. [MAX.] UNIT | lus Input Current Vin=O~Vec |+10 uA Ica Supply Current (Standby) CE=Vin _ 30 mA Iec2 Supply Current (Active) CE=Vit } 100 mA Vou Output High Voltage lon= 400nA 2.4 _ _ Vv Vow Output Low Voltage lo.=2.1mA _ _ 0.4 Vv lppa Vee Current Vep=O~Vec+0.6V _ | +10 uA lo Output Leakage Current Vout=0.4V~Vec _ _ +10 BA 18 TMM24128AP/AF A. C. CHARACTERISTICS (Ta- O~ 70 C, View BV45%, Vow 2.0V~Veo+0.6V, Unless otherwise noted) | SYMBOL PARAMETER | MIN. MAX. UNIT tacc Address Access Time " 0 _ 200 ns tee CE to Output Valid - 200 ns | toe OE to Output Valid _ ~ 70 ns tech PGM to Output Valid _ 70 ns tor CE to Output in High-Z 0 60 ns tor? OE to Output in High-Z 0 60 ns tors PGM to Output in High-Z 0 60 ns tou Output Data Hold Time 0 - ns 1 A. C. TEST CONDITIONS @ Output Load : 1 TTL Gate and C. = 100pF @ Input Pulse Rise and Fall Times 10ns Max. @ Input Pulse Levels : 0.45V to 2.4V @ Timing Measurement Reference Level - Inputs O.8V and 2.0V, Outputs O.8V and 2.0V CAPACITANCE * (Ta=25C, f=1MHz) SYMBOL PARAMETER TEST CONDITION MIN. | TYP. [MAX.| UNIT Cin Input Capacitance Vin = OV _ 4 6 pF Cout Output Capacitance Vout=OV _ 8 12 pF * This parameter 1s periodically sampled and 1s not 100% tested . TIMING WAVEFORMS AO~A13 PGM o00~07 DATA OUTPUTS H9 TMM24128AP/AF HIGH SPEED PROGRAM OPERATION D. C. RECOMMENDED OPERATING CONDITIONS ~~ SYMBOL PARAMETER PMN. TYP [| MAX, UNIT - Ve oo Input High Voltage : - 2.0 - Veet+1.0 Vv : Va 7 Input Low Voltage _ _ -0.3 _ - 0.8 Vv Vee V.. Power Supply Voltage 5.75 6.0 6.25 | Vv Vep ~~ Ves Power Supply Voltage _ : 120 | 12.5 13.0 | Vv D. C. and OPERATING CHARACTERISTICS = (Ta=25+5C, Vcc=6V+0.25V, Vep=12.5V+0.5V) SYMBOL. PARAMETER TEST CONDITION MIN. | TYP. [MAX.| UNIT |, Input Current _ Vin=0~Vec | = F#10} pA Von Output High Voltage Jon 400nA 24) | Vv V.. Output Low Voltage - lol = 2.1mA ~ | Joa Vv 1, . - . Vv Supply Current _ jr 100 mA lpn Ver Supply Current Vee=13.0V Loo : _ 50 mA A. . PROGRAMMING CHARACTERISTICS (Ta=25+5C, Vec=6V+0.25V, Vep=12.5V+0.5V) SYMBOL | PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT tas Address Setup Time 2 _ _ us tan Address Hold Time _ 2 _ _ us tces CE Setup Time 2 _ us tceH CE Hold Time 2 _ Ss tos Data Setup Time _ 2 _ _ BS tou Data Hold Time _ 2 > _ us tvs Vee Setup Time _ 2 _ _ Ss tpw Program Pulse Width = 0.95 1.0 1.05 ms topw Additional Program Pulse Width Note 1 2.85 3.0 78.75 ms tor OE to Output Valid - 100 ns tore OE to Output in High-Z CE=Va _ _ 90 ne A.C. TEST CONDITIONS @ Output Load @ Input Pulse Rise and Fall Times @ Input Pulse Levels @ Timing Measurement Reference Level Note : 1. : 1 TTL Gate and Ci(1O0pF) - 10ns Max. : 0.45V to 2.4V : Input O.8V and 2.0V, Output O.8V and 2.0V topw depend on the program pulse width which is reguired in the initial program. I-20 TT]TMM24128AP/AF TIMING WAVEFORMS (HIGH SPEED PROGMAM) \| ADDRESSES \ 4 tas tay tors toRu / OE / D ff 00~ 07 UNKNOWN STABLE r-K your bY DIN STABLE > Ba tps tpu tpre| tps tpy ! ee + PGM tpw topw Vpp Wy , tvs PROGRAM PROGRAM VERIFY PROGRAM INITIAL PROGRAM ADDITIONAL PROGRAM Note: 1. Vcc must be applied simultaneously or before Ver and cut off simultaneously or after Ver. 2. Removing the device from socket and setting the device in socket with Vpp=12.5V may cause permanent damage to the device. 3. The Ver supply voltage is permitted up to 14V for program operation, so the voltage over 14V should not be applied to the Ver terminal. When the switching pulse voltage is applied to the Ver terminal, the overshoot voltage of its pulse should not be exceeded 14V. +21 TMM24128AP/AF OPERATION INFORMATION The TMM24128AP AFs six operation modes are listed in the following table. Mode selection can be achieved by applying TTL level signal to all inputs. In the read operation mode, a single 5V power supply 1s required and the levels required for all inputs are TTL. we PIN NAMES(NUMBER) | PGM | CE | O Ver Vec Qo~O, POWER i MODE a (27) | (20) | (22) (1) (28) (11~13, 15~19) a " Read H L L Data Out Active Read Operation (Ta=0~70C) Output Deselect * * H 5V 5V High Impedance Active a=0~ Standby * H * High Impedance Standby Program L L * Data In Active Program * H * High Impedance Active Operation Program Inhibit 12.5V 6V - (Ta=25+5C) H L H High Impedance Active Program Verify H L L Data Out Active Note: H: Vin, Li Vi. * > Vie or Vit READ MODE The TMM24128AP/AF has three control func- tions. The chip enable (CE) controls the operation power and should be used for device selection. The output enable (OE) and the program contro! (PGM} control the output buffers, independent of device selection. Assuming that CE=OE=Vit and PGM=Vin, the output data is valid at the output after address access time from stabilizing of all addresses. OUTPUT DESELECT MODE Assuming that CE=Vin or OF=Vin, the outputs will be in a high tmpedance state. So two or more M24128AP/AF can be connected together on a STANDBY MODE The TMM24128AP/AF has a low power standby mode controlled by the CE signal. By applying TTL high level to the CE input, the TMM24128AP/AF is placed in the standby mode which reduce the oper- PROGRAM VERIFY MODE The verify mode is to check that the desired data is correctly programmed on the programmed bits. PROGRAM INHIBIT MODE Under the condition that the program voltage (+ 12.5V) is applied to Vep terminal, a high leve! CE or PGM input inhibits the TMM24128AP/AF from be- ing programmed. Programming of two or more TMM24128AP/AF in parallel with different data is om 22 The CE to output valid (tce) is equal to the address access time (tacc). | Assuming that CE=Vit, PGM=Vin and all ad- dresses are valid, the output data is valid at the outputs after toe from the falling edge of OE. And assuming that CE=OE=Vn and addresses are valid, the output data is valid at the outputs after teem from the rising edge of PGM. common bus line. When CE ts decoded for device selection, all deselected devices are in low power standby mode. ating current from 100mA to 30mA, and then the outputs are in a high impedance state, independent of the O and the PGM inputs. The verify is accomplished with OE and CE at Vit and PGM at Vio. easily accomplished. That is, all inouts except for CE or PGM may be commonly connected, and a TTL iow level program pulse is applied to the CE and PGM of the desired device only and TTL high level signal is applied to the other devices.HIGH SPEED PROGRAMMING MODE The device is set up in the high speed program- ming mode when the programming voltage (+12. 5V) is applied to the Ver terminal with Vcec=6V and PGM=Vin. The programming is achieved by apply- ing a single TTL low level 1ms pulse the PGM input after addresses and data are stable. Then the pro- grammed data |s verified by using Program Verify Mode. If the programmed data is not correct, another program pulse of Ims is applied and then pro- ELECTRIC SIGNATURE MODE Electric signature mode allows to read out a code from TMM24128AP/AF which identifies its manu- facturer and device type. The programming equipment may read out man- ufacturer code and device code from TMM24128AP/AF by using this mode before pro- gram operation and automatically set program volt- age (Ver) and algorithm. Electric signature mode is set up when 12V is TMM24128AP/AF grammed data is verified. This should be repeated until the program operates correctly (max. 25 times). After correctly programming the selected address, one additional program pulse with pulse width 3 times that needed for programming |S applied. When programming has been completed, the data in all addresses should be verified with Vcc=Vep =B5V. The High Speed Program II Algorithm (shown in figure 2, page I-5) may also be used to reduce the programming time further. applied to address line AQ and the rest of address lines is set to Vit in read operation. Data output in this conditions is manufacturer code. Device code is identified when address AO is set to Vin. These two codes possess an odd parity with the parity bit of MSB (07). The following table shows electric signature of TMM24128AP/AF . amu Ay 0, Os Os 0, o | | Oo QO, | HEX. SIGNATURE ao) | (9) | (ra) | 7) 4) (16) | (18) | (3) | 2) | (11) | DATA Manufacture Code Vit 1 0 0 1 1 [| oO 0 0 98 Device Code Vin 1 1 0 1 o | 0 1 1 D3 Notes: A9=12V+0.5V A1~A8, A10~A13, CE, OFE=Vi PGM=Vin I-23TMM24128AP/AF HIGH SPEED PROGRAM MODE FLOW CHART TT ADDRERR = START ADDRESS ADDRESS = NEXT ADDRESS OVERPROGRAM 3X PULSES OF imsec OR ONE PULSE OF 3Xmsec DURATION cee OK LAST ADDRESS 2? Voo = 5.0V Vpp = 5.0V FAILTMM24128AP/AF OUTLINE DRAWINGS (TMM241 28AP) Note : 1. 28 15 Ciriririrjyricpiriariz:pcariripary _ 7 % Unit in mm ) S RN ? a Ua oaTT 3 1 Me 1924+ 025 xf 380 MAX 1% | = a a oO i 0.5+0.15 2,54+0.25 Al 0-25-0905 144015 o~15 S2MIN_. Eacn lead pitch is 2.54mm. All leads are located within 0.25mm of their true longitudinal position with respect No.1 and No.28 leads. This value is measured at the end of leads. . All dimensions are in millimeters. 1-25 TT SSTMM24128AP/AF OUTLINE DRAWINGS (TMM24128AF) ioonnnnnnononnn Unit in mm a 9.0 MAX YUUUUUUUUUUEUU 118403 .. 1B9MAX, | 0.152005 Note: Lead picth is 1.27 and tolerance is+O.12 against theoretical center of each lead that is obtained on the basis of No.1 and No.28 leads. Note: Toshiba does not assume any responsibility for use of any circuitry described: no i are Hed, and Toshib reserves the right, at any time without notice, to change said circuitry. April, 1987 Toshiba Corporation 126 TT TT