1©2015 Inte grated Device Technology, Inc December 11, 2015
General Description
The 8312 is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer
and a member of the family of High Performance Clock Solutions
from IDT. The 8312 single-ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 8312 ideal for
high performance, single ended applications that also require a
limited output voltage.
Features
•Twelve LVCMOS/LVTTL outputs
•CLK input supports the following input types: LVCMOS, LVTTL
•Maximum output frequency: 250MHz
•Output skew: 150ps (maximum)
•Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
1.8V/1.8V
•0°C to 85°C ambient operating temperature
•Available in lead-free (RoHS 6) package
8312
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
VDD
CLK_EN
CLK
GND
OE
VDD
GND
Q4
VDDO
Q5
GND
Q6
VDDO
Q7
GND
Q11
VDDO
Q10
GND
Q9
VDDO
Q8
GND
VDDO
Q1
GND
Q2
VDDO
Q3
GND
Q0
Pin Assignment
D
LE
Q
Q[0:11]
CLK_EN
OE
CLK
Pullup
Pulldown
Pullup
12
Block Diagram
8312
Datasheet
Low Skew, 1-to-12 LVCMOS/LVTTL
Fanout Buffer
2©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 5, 8, 12, 16,
17, 21, 25, 29 GND Power Power supply ground.
2, 7 VDD Power Positive supply pins.
3 CLK_EN Input Pullup Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
4 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
6 OE Input Pullup Output enable. Controls enabling and disabling of outputs Q[0:11].
LVCMOS / LVTTL interface levels.
9, 11, 13, 15,
18, 20, 22, 24,
26, 28, 30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
10, 14, 19, 23,
27, 31 VDDO Power Output supply pins.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLUP Input Pullup Resistor 51 k
RPULLDOWN Input Pulldown Resistor 51 k
CPD
Power Dissipation Capacitance
(per output)
VDDO = 3.465V 19 pF
VDDO = 2.625V 18 pF
VDDO = 2V 16 pF
ROUT Output Impedance
VDDO = 3.3V ± 5% 7
VDDO = 2.5V ± 5% 7
VDDO = 1.8V ± 0.2V 10
3©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Function Tables
Table 3A. Output Enable and Clock Enable Function Table
Table 3B. Output Enable and Clock Enable Function Table
Inputs Outputs
OE CLK_EN Q [0:11]
0X Hi-Z
10 LOW
1 1 Follows CLK input
Inputs Outputs
OE CLK_EN CLK Q [0:11]
110LOW
111HIGH
4©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 85°C
Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 85°C
Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 85°C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, JA 47.9C/W (0 lfpm)
Storage Temperature, TSTG -65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 10 mA
IDDO Output Supply Current 10 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 2.375 2.5 2.625 V
VDDO Output Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 10 mA
IDDO Output Supply Current 10 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 1.6 1.8 2.0 V
VDDO Output Supply Voltage 1.6 1.8 2.0 V
IDD Power Supply Current 10 mA
IDDO Output Supply Current 10 mA
5©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Table 4D. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 85°C
Table 4E. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 85°C
Table 4F. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 10 mA
IDDO Output Supply Current 10 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 1.6 1.8 2.0 V
IDD Power Supply Current 10 mA
IDDO Output Supply Current 10 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Positive Supply Voltage 2.375 2.5 2.625 V
VDDO Output Supply Voltage 1.6 1.8 2.0 V
IDD Power Supply Current 10 mA
IDDO Output Supply Current 10 mA
6©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 85°C
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage
VDD = 3.465V 2 VDD + 0.3 V
VDD = 2.625V 1.7 VDD + 0.3 V
VDD = 2.0V 0.65*VDD VDD + 0.3 V
VIL Input Low Voltage
VDD = 3.465V -0.3 1.3 V
VDD = 2.625V -0.3 0.7 V
VDD = 2.0V -0.3 0.35*VDD V
IIH
Input
High Current
CLK VDD = VIN = 3.465V or
2.625V or 2.0V 150 µA
OE, CLK_EN VDD = VIN = 3.465V or
2.625V or 2.0V 5µA
IIL
Input
Low Current
CLK VDD = 3.465V or 2.625V or 2.0V,
VIN = 0V -5 µA
OE, CLK_EN VDD = 3.465V or 2.625V or 2.0V,
VIN = 0V -150 µA
VOH Output High Voltage; NOTE 1
VDDO = 3.3V ± 5% 2.6 V
VDDO = 2.5V ± 5%; 1.8 V
VDDO = 2.5V ± 5%; IOH = -1mA 2 V
VDDO = 1.8V ± 0.2V VDD – 0.3 V
VDDO = 1.8V ± 0.2V; IOH = -100µA VDD – 0.2 V
VOL Output Low Voltage; NOTE 1
VDDO = 3.3V ± 5% 0.5 V
VDDO = 2.5V ± 5%; 0.45 V
VDDO = 2.5V ± 5%; IOL = 1mA 0.4 V
VDDO = 1.8V ± 0.2V 0.35 V
VDDO = 1.8V ± 0.2V; IOL = 100µA 0.2 V
7©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 250 MHz
tpLH Propagation Delay, Low to High; NOTE 1 ƒ 250MHz 1.2 1.9 2.5 ns
tjit Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz 0.037 ps
tsk(o) Output Skew; NOTE 2, 5 125 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 800 ps
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps
odc Output Duty Cycle ƒ 200MHz 45 55 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 250 MHz
tpLH Propagation Delay, Low to High; NOTE 1 ƒ 250MHz 1.4 2.3 3.2 ns
tjit Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz 0.022 ps
tsk(o) Output Skew; NOTE 2, 5 150 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.1 ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps
odc Output Duty Cycle ƒ 150MHz 45 55 %
8©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Table 5C. AC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 200 MHz
tpLH Propagation Delay, Low to High; NOTE 1 ƒ 200MHz 1.6 3.3 4.8 ns
tjit Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz 0.172 ps
tsk(o) Output Skew; NOTE 2, 5 140 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 2.3 ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps
odc Output Duty Cycle ƒ 100MHz 45 55 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 250 MHz
tpLH Propagation Delay, Low to High; NOTE 1 ƒ 250MHz 1.4 2.1 2.7 ns
tjit Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz 0.045 ps
tsk(o) Output Skew; NOTE 2, 5 135 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 900 ps
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps
odc Output Duty Cycle ƒ 150MHz 45 55 %
9©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Table 5E. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Table 5F. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 85°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 200 MHz
tpLH Propagation Delay, Low to High; NOTE 1 ƒ 200MHz 1.4 2.4 3.4 ns
tjit Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz 0.136 ps
tsk(o) Output Skew; NOTE 2, 5 145 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.3 ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps
odc Output Duty Cycle ƒ 100MHz 45 55 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 200 MHz
tpLH Propagation Delay, Low to High; NOTE 1 ƒ 200MHz 1.5 2.6 3.7 ns
tjit Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
100MHz, Integration Range:
12kHz – 20MHz 0.114 ps
tsk(o) Output Skew; NOTE 2, 5 150 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.5 ns
tR / tFOutput Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps
odc Output Duty Cycle ƒ 100MHz 45 55 %
10©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependant on the input source and measurement equipment.
Additive Phase Jitter, 3.3V @ 100MHz
12kHz to 20MHz = 0.037ps (typical)
SSB Phase Noi se dBc/ Hz
Offset from Carrier Frequency (Hz)
11©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
1.8V Core/1.8V LVCMOS Output Load AC Test Circuit
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2.5V Core/1.8V LVCMOS Output Load AC Test Circuit
SCOPE
Qx
GND
VDD,
1.65V±5%
-1.65V±5%
VDDO
SCOPE
Qx
GND
VDDO
VDD,
0.9V±0.1V
-0.9V±0.1V
SCOPE
Qx
LVCMOS
VDDO
2
GND
VDDO
VDD
0.9V±0.1V
2.4V±0.9V
-0.9V±0.1V
SCOPE
Qx
GND
VDD,
1.25V±5%
-1.25V±5%
VDDO
SCOPE
Qx
LVCMOS
VDDO
2
GND
VDD
VDDO
1.25V±5%
-1.25V±5%
2.05V±5%
SCOPE
Qx
LVCMOS
VDDO
2
GND
12©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Parameter Measurement Information, continued
Output Skew
Propagation Delay
Output Rise/Fall Time
Part-to-Part Skew
Output Duty Cycle/Pulse Width/Period
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
tpLH tpHL
VDDO
2
VDD
2
VDDO
2
VDD
2
CLK
Q0:Q11
20%
80% 80%
20%
tRtF
Q0:Q11
tsk(pp)
V
DDO
2
V
DDO
2
Part 1
Part 2
Qx
Qy
tPW
tPERIOD
VDDO
2
VDDO
2
VDDO
2
tPW
tPERIOD
odc =
Q0:Q11
13©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have int ernal pull- ups o r pul l-do wns; addit iona l
resistance i s no t req uire d but can be a dded for additi onal
protection. A 1k resi stor can be u sed.
Outputs:
LVCMOS Outputs:
All unused LVCMOS output can be left floating. There should be
no trace at tach ed.
14©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Reliability Information
Table 6. JA vs. Air Flow Table for a 32 Lead LQFP
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for 8312 is: 339
JA vs. Air Flow
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
15©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 7. Package Dimensions for 32 Lead LQFP
Reference Document: JEDEC Publication 95, MS-026
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N32
A1.60
A1 0.05 0.10 0.15
A2 1.35 1.40 1.45
b0.30 0.37 0.45
c0.09 0.20
D & E 9.00 Basic
D1 & E1 7.00 Basic
D2 & E2 5.60 Ref.
e0.80 Basic
L0.45 0.60 0.75
0° 7°
ccc 0.10
N32
16©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Ordering Information
Table 8. Ordering Information
Part/Order Number Marking Package Shipping Packaging Temperature
8312AYLF ICS8312AYLF “Lead-Free” 32 Lead LQFP Tray 0C to 85C
8312AYLFT ICS8312AYLF “Lead-Free” 32 Lead LQFP Tape & Reel 0C to 85C
17©2015 Inte grated Device Technology, Inc December 11, 2015
8312 Data sheet
Revision History Sheet
Rev Table Page Description of Change Date
B
T2
T4A - T4F
2
3
Pin Characteristics table - added category CPD.
Power Supply tables - changed IDD & IDDO max. current spec to 10µA and
removed typical value.
2/25/03
CT2
1
2
Features section - corrected Output Skew typo error from 160ps to 150ps.
Pin Characteristics table - changed CIN 4pF max. to 4pF typical. 5/17/04
C T8 11 Added Lead-Free part number to Ordering Information Table. 6/14/04
D
T5A - T5F 7 - 9
10
13
Added Additive Phase Jitter specs to AC Tables.
Added Additive Phase Jitter Plot.
Added Recommendations for Unused Input & Output Pins section.
Updated datasheet to new format.
7/3/08
D T8 16 Removed leaded orderable parts from Ordering Information table 11/14/12
D
1
1
16
16
Removed ICS Chip and HiPerClockS under General Description.
Removed ICS in the part numbers.
Removed reference to leaded parts in the Features Section.
Removed LF note at the bottom of the Ordering Information table.
Removed the quantity of 1000 from the Tape & Reel in the Ordering
information table.
Updated datasheet header and footer.
12/11/15
DISCLAIMER Integrated Device Technology , Inc. (IDT) res erves the right to modify the products and/or s pecifications des cribed herein at any time, with out notice, at IDT's sole discretion. Perfor mance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or impli ed, including, but not limited to, t he suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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IDT or their respective third party owners.
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2015 Integrated Device Technology, Inc. All rights reserved.
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8312 Data sheet