8312 Low Skew, 1-to-12 LVCMOS/LVTTL Fanout Buffer Datasheet General Description Features The 8312 is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The 8312 single-ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. * * * * * Twelve LVCMOS/LVTTL outputs * * 0C to 85C ambient operating temperature The 8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply modes. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the 8312 ideal for high performance, single ended applications that also require a limited output voltage. Block Diagram Maximum output frequency: 250MHz Output skew: 150ps (maximum) Supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V 1.8V/1.8V Available in lead-free (RoHS 6) package GND Q3 VDDO Q2 GND 32 31 30 29 28 27 26 25 Q LE GND 1 24 Q4 VDD 2 23 VDDO CLK_EN 3 22 Q5 CLK 4 21 GND GND 5 20 Q6 OE 6 19 VDDO VDD 7 18 Q7 GND 8 17 GND 12 GND Q8 VDDO 10 11 12 13 14 15 16 Q9 9 GND OE Pullup Q10 Q[0:11] VDDO CLK Pulldown Q1 Q0 D VDDO Pin Assignment Q11 CLK_EN Pullup CLK input supports the following input types: LVCMOS, LVTTL 8312 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View (c)2015 Integrated Device Technology, Inc 1 December 11, 2015 8312 Datasheet Table 1. Pin Descriptions Number Name Type Description 1, 5, 8, 12, 16, 17, 21, 25, 29 GND Power Power supply ground. 2, 7 VDD Power Positive supply pins. 3 CLK_EN Input Pullup 4 CLK Input Pulldown 6 OE Input Pullup 9, 11, 13, 15, 18, 20, 22, 24, 26, 28, 30, 32 Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 10, 14, 19, 23, 27, 31 VDDO Power Output supply pins. Synchronous control for enabling and disabling clock outputs. LVCMOS / LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Q[0:11]. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k CPD Power Dissipation Capacitance (per output) ROUT Output Impedance (c)2015 Integrated Device Technology, Inc Test Conditions Minimum Typical Maximum Units VDDO = 3.465V 19 pF VDDO = 2.625V 18 pF VDDO = 2V 16 pF VDDO = 3.3V 5% 7 VDDO = 2.5V 5% 7 VDDO = 1.8V 0.2V 10 2 December 11, 2015 8312 Datasheet Function Tables Table 3A. Output Enable and Clock Enable Function Table Inputs Outputs OE CLK_EN Q [0:11] 0 X Hi-Z 1 0 LOW 1 1 Follows CLK input Table 3B. Output Enable and Clock Enable Function Table Inputs Outputs OE CLK_EN CLK Q [0:11] 1 1 0 LOW 1 1 1 HIGH (c)2015 Integrated Device Technology, Inc 3 December 11, 2015 8312 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 10 mA IDDO Output Supply Current 10 mA Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5%, TA = 0C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 10 mA IDDO Output Supply Current 10 mA Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V 0.2V, TA = 0C to 85C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 10 mA IDDO Output Supply Current 10 mA (c)2015 Integrated Device Technology, Inc Test Conditions 4 December 11, 2015 8312 Datasheet Table 4D. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 10 mA IDDO Output Supply Current 10 mA Table 4E. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 10 mA IDDO Output Supply Current 10 mA Table 4F. Power Supply DC Characteristics, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0C to 85C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 10 mA IDDO Output Supply Current 10 mA (c)2015 Integrated Device Technology, Inc Test Conditions 5 December 11, 2015 8312 Datasheet Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0C to 85C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Test Conditions Minimum VDD = 3.465V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.625V 1.7 VDD + 0.3 V VDD = 2.0V 0.65*VDD VDD + 0.3 V VDD = 3.465V -0.3 1.3 V VDD = 2.625V -0.3 0.7 V VDD = 2.0V -0.3 0.35*VDD V CLK VDD = VIN = 3.465V or 2.625V or 2.0V 150 A OE, CLK_EN VDD = VIN = 3.465V or 2.625V or 2.0V 5 A Input High Current CLK VDD = 3.465V or 2.625V or 2.0V, VIN = 0V -5 A OE, CLK_EN VDD = 3.465V or 2.625V or 2.0V, VIN = 0V -150 A VDDO = 3.3V 5% 2.6 V VDDO = 2.5V 5%; 1.8 V VDDO = 2.5V 5%; IOH = -1mA 2 V VDDO = 1.8V 0.2V VDD - 0.3 V VDDO = 1.8V 0.2V; IOH = -100A VDD - 0.2 V Input Low Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VDDO = 3.3V 5% 0.5 V VDDO = 2.5V 5%; 0.45 V VDDO = 2.5V 5%; IOL = 1mA 0.4 V VDDO = 1.8V 0.2V 0.35 V VDDO = 1.8V 0.2V; IOL = 100A 0.2 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. (c)2015 Integrated Device Technology, Inc 6 December 11, 2015 8312 Datasheet AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 85C Parameter Symbol Test Conditions Minimum 1.2 Typical Maximum Units fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 250MHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz - 20MHz tsk(o) Output Skew; NOTE 2, 5 125 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 800 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle 200MHz 45 55 % 1.9 250 MHz 2.5 ns 0.037 ps All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = VDDO = 2.5V 5%, TA = 0C to 85C Parameter Symbol fMAX Output Frequency Test Conditions Minimum tpLH Propagation Delay, Low to High; NOTE 1 250MHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz - 20MHz tsk(o) Output Skew; NOTE 2, 5 150 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.1 ns tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle 150MHz 45 55 % 1.4 Typical Maximum 2.3 Units 250 MHz 3.2 ns 0.022 ps All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 7 December 11, 2015 8312 Datasheet Table 5C. AC Characteristics, VDD = VDDO = 1.8V 0.2V, TA = 0C to 85C Parameter Symbol fMAX Output Frequency Test Conditions tpLH Propagation Delay, Low to High; NOTE 1 200MHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz - 20MHz Minimum 1.6 Typical Maximum 3.3 Units 200 MHz 4.8 ns 0.172 ps tsk(o) Output Skew; NOTE 2, 5 140 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 2.3 ns tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps odc Output Duty Cycle 100MHz 45 55 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. Table 5D. AC Characteristics, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0C to 85C Parameter Symbol Test Conditions Minimum fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 250MHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz - 20MHz tsk(o) Output Skew; NOTE 2, 5 135 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 900 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle 150MHz 45 55 % 1.4 Typical Maximum 2.1 Units 250 MHz 2.7 ns 0.045 ps All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 8 December 11, 2015 8312 Datasheet Table 5E. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 85C Parameter Symbol fMAX Output Frequency Test Conditions tpLH Propagation Delay, Low to High; NOTE 1 200MHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz - 20MHz Minimum 1.4 Typical Maximum 2.4 Units 200 MHz 3.4 ns 0.136 ps tsk(o) Output Skew; NOTE 2, 5 145 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.3 ns tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle 100MHz 45 55 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. Table 5F. AC Characteristics, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = 0C to 85C Parameter Symbol Test Conditions Minimum fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 200MHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz - 20MHz tsk(o) Output Skew; NOTE 2, 5 150 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 1.5 ns tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle 100MHz 45 55 % 1.5 Typical Maximum 2.6 Units 200 MHz 3.7 ns 0.114 ps All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. (c)2015 Integrated Device Technology, Inc 9 December 11, 2015 8312 Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter, 3.3V @ 100MHz 12kHz to 20MHz = 0.037ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the (c)2015 Integrated Device Technology, Inc device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 10 December 11, 2015 8312 Datasheet Parameter Measurement Information 1.25V5% 1.65V5% SCOPE VDD, VDDO SCOPE VDD, VDDO Qx Qx GND GND -1.25V5% -1.65V5% 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit 2.05V5% 0.9V0.1V 1.25V5% SCOPE VDD, SCOPE VDD VDDO VDDO Qx LVCMOS Qx GND GND VDDO 2 -0.9V0.1V -1.25V5% 1.8V Core/1.8V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 1.6V5% 2.4V0.9V 0.9V0.1V 0.9V0.1V SCOPE VDD SCOPE VDD VDDO VDDO Qx LVCMOS LVCMOS GND GND VDDO VDDO 2 2 -0.9V0.1V -0.9V0.1V 3.3V Core/1.8V LVCMOS Output Load AC Test Circuit (c)2015 Integrated Device Technology, Inc Qx 2.5V Core/1.8V LVCMOS Output Load AC Test Circuit 11 December 11, 2015 8312 Datasheet Parameter Measurement Information, continued Part 1 V DDO Qx V DDO 2 Qx 2 Part 2 V DDO Qy V DDO 2 tsk(o) Qy Output Skew CLK 2 tsk(pp) Part-to-Part Skew VDD VDD 2 2 VDDO VDDO VDDO 2 2 2 Q0:Q11 t PW t PERIOD VDDO Q0:Q11 VDDO 2 tpLH 2 tpHL odc = Propagation Delay Q0:Q11 t PW t PERIOD Output Duty Cycle/Pulse Width/Period 80% 80% tR tF 20% 20% Output Rise/Fall Time (c)2015 Integrated Device Technology, Inc 12 December 11, 2015 8312 Datasheet Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins: LVCMOS Outputs: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVCMOS output can be left floating. There should be no trace attached. (c)2015 Integrated Device Technology, Inc 13 December 11, 2015 8312 Datasheet Reliability Information Table 6. JA vs. Air Flow Table for a 32 Lead LQFP JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8C/W 55.9C/W 50.1C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9C/W 42.1C/W 39.4C/W NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 8312 is: 339 (c)2015 Integrated Device Technology, Inc 14 December 11, 2015 8312 Datasheet Package Outline and Package Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 7. Package Dimensions for 32 Lead LQFP JEDEC Variation: ABC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 0 7 ccc 0.10 N 32 Reference Document: JEDEC Publication 95, MS-026 (c)2015 Integrated Device Technology, Inc 15 December 11, 2015 8312 Datasheet Ordering Information Table 8. Ordering Information Part/Order Number 8312AYLF 8312AYLFT Marking ICS8312AYLF ICS8312AYLF (c)2015 Integrated Device Technology, Inc Package "Lead-Free" 32 Lead LQFP "Lead-Free" 32 Lead LQFP 16 Shipping Packaging Tray Tape & Reel Temperature 0C to 85C 0C to 85C December 11, 2015 8312 Datasheet Revision History Sheet Rev Table Page B T2 T4A - T4F 2 3 Pin Characteristics table - added category CPD. Power Supply tables - changed IDD & IDDO max. current spec to 10A and removed typical value. 2/25/03 T2 1 2 Features section - corrected Output Skew typo error from 160ps to 150ps. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. 5/17/04 T8 11 Added Lead-Free part number to Ordering Information Table. 6/14/04 T5A - T5F 7-9 10 13 Added Additive Phase Jitter specs to AC Tables. Added Additive Phase Jitter Plot. Added Recommendations for Unused Input & Output Pins section. Updated datasheet to new format. 7/3/08 16 Removed leaded orderable parts from Ordering Information table 11/14/12 1 Removed ICS Chip and HiPerClockS under General Description. Removed ICS in the part numbers. Removed reference to leaded parts in the Features Section. Removed LF note at the bottom of the Ordering Information table. Removed the quantity of 1000 from the Tape & Reel in the Ordering information table. Updated datasheet header and footer. 12/11/15 C C D D D T8 1 16 16 (c)2015 Integrated Device Technology, Inc Description of Change Date 17 December 11, 2015 8312 Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright (c)2015 Integrated Device Technology, Inc. All rights reserved.