MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
MIXED SIGNAL MICROCONTROLLER
1FEATURES
• Ultra-Low Supply Voltage (ULV) Range • ULV Port Logic
– 0.9 V to 1.5 V (1 MHz) – VOL Better Than 0.15 V at 2.5 mA
– 1.5 V to 1.65 V (4 MHz) – VOH Better Than VCC – 0.15 V at 1 mA
• Low Power Consumption – Timer0 PWM Signal Available on All Ports
– Active Mode (AM): 45 µA/MHz (1.3 V) – Timer1 PWM Signal Available on All Ports
– Standby Mode (LPM3, WDT_A Mode): 6 µA • ULV Brownout Circuit (BOR)
– Off Mode (LPM4): 3 µA • ULV RAM Retention Voltage Below BOR Level
• Wake-Up From LPMx in Less Than 5 µs • 32-Bit Watchdog Timer (WDT-A)
• 16-Bit RISC Architecture • Bootstrap Loader in MSP430L092
Development/Prototyping Device
– Extended Instructions • Full Four-Wire JTAG Debug Interface
– Up to 4-MHz System Clock • Family Members Include
• Compact Clock System – MSP430C091
– 1-MHz Internal Trimmable High-Frequency
Clock – 1KB ROM Memory
– 20-kHz Internal Low-Frequency Clock – 128 Bytes RAM + 96 Bytes CRAM
Source (Lockable)
– External Clock Input – MSP430C092
• 16-Bit Timer0_A3 With Three Capture/Compare – 2KB ROM Memory
Registers – 128 Bytes RAM + 96 Bytes CRAM
• 16-Bit Timer1_A3 With Three Capture/Compare (Lockable)
Registers – MSP430L092
• ULV Analog Pool Modes – 2KB Loader ROM With Service
– 8-Bit Analog-to-Digital Converter (ADC) Functions
– 8-Bit Digital-to-Analog Converter (DAC) – 2KB RAM
(1792 + 128 + 96 Bytes Lockable)
– Programmable Comparator (COMP) • For Complete Module Descriptions, See the
– Supply Voltage Monitor (SVM) MSP430x09x Family User’s Guide (SLAU321)
– Temperature Sensor
– Internal Reference Voltage Source
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled internal oscillators allow wake-up from low-power modes to active mode in less than 5 µs.
The MSP430C09x and MSP430L092 series are microcontroller configurations with two 16-bit timers, an
ultra-low-voltage 8-bit analog-to-digital (A/D) converter, an 8-bit digital-to-analog (D/A) converter, and up to 11 I/O
pins.
Typical applications for this device include single-cell systems requiring a full analog signal chain.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
4
3
2
TCK/P2.0/TA 0.2/TA1.2/TA1.1 14
11
12
13
7
6
5
8
9
10 VSS/GND
P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3
P1.5/TA0.2/TA1.2/TA 0.1
P1.6/TA0.2/TA1.2/TA 1.1
VCC
P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN
P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK
RST NMI SVMOUT/ /
TDO/P2.3/TA0.2/TA 1.2/CCI1.0
TDI/P2.2/TA0.2/TA1.2/CxOUT/CCI0.0
TMS/P2.1/TA 0.2/TA1.2/TA0.1
P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3
P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK
PW PACKAGE
(TOP VIEW)
Clock
System
2/(1)KB ROM 128B RAM
+96B CRAM
P2.0...P2.3GND/VSS
MCLK
ACLK
SMCLK
I/O Port P2L
4 I/Os with
Interrupt
Capability
Watchdog
WDTA
32/16-Bit
Timer0_A3
3 CC
Registers
CPU &
Working
Registers
4W-JTAG Analog-
Pool
Reset
Int-Logic
HF-OSC
Timer1_A3
3 CC
Register
VCC
RST/NMI/SVMOUT
CLKIN
VREF
TMS, TCK,
TDI, TDO
ULV-Ref.,
8-Bit ADC,
8-Bit DAC,
Comparator,
SVS
LF-OSC
ULV
Brownout
P1.0...P1.6
I/O Port P1L
7 I/Os with
Interrupt
Capability
Debug
support
CORE
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
ORDERING INFORMATION(1)
PACKAGED DEVICES(2)
TAPLASTIC 14-PIN TSSOP (PW)
MSP430C091SPW
0ºC to 50ºC MSP430C092SPW
MSP430L092SPW
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/package.
Pin Designation, MSP430C091PW, MSP430C092PW
Functional Block Diagram, MSP430C092PW, MSP430C091PW
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1
4
3
2
SPI_CS/TCK/P2.0/TA0.2/TA1.2/TA1.1 14
11
12
13
7
6
5
8
9
10 VSS/GND
P1.2/TA 0.2/TA1.2/ACLK/CCI0.0/AOUT/A3/BOOST
P1.5/TA 0.2/TA1.2/TA 0.1
P1.6/TA 0.2/TA1.2/TA 1.1
VCC
P1.0/TA 0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN
P1.1/TA 0.2/TA1.2/SMCLK/CCI1.1/A1/TA 0CLK
RST/NMI/SVMOUT
SPI_MISO/TDO/P2.3/TA 0.2/TA1.2/CCI1.0
SPI_CLK/TDI/P2.2/TA 0.2/TA1.2/CxOUT/CCI0.0
SPI_MOSI/TMS/P2.1/TA 0.2/TA1.2/TA 0.1
P1.3/TA 0.2/TA1.2/CxOUT/CCI1.0/VREF/A3
P1.4/TA 0.2/TA1.2/MCLK/A0/TA 1CLK
PW PACKAGE
(TOP VIEW)
2kB RAM
(128B+1792B
+96B)
Clock
System
2KB ROM
(Loader)
P2.0...P2.3GND/VSS
MCLK
ACLK
SMCLK
I/O Port P2L
4 I/Os with
Interrupt
Capability
Watchdog
WDTA
32/16-Bit
Timer0_A3
3 CC
Registers
CPU &
Working
Registers
4W-JTAG Analog-
Pool
Reset
Int-Logic
HF-OSC
Timer1_A3
3 CC
Register
VCC
CLKIN
VREF
TMS, TCK,
TDI, TDO
ULV-Ref.,
8-Bit ADC,
8-Bit DAC,
Comparator,
SVS
LF-OSC
ULV
Brownout
P1.0...P1.6
I/O Port P1L
7 I/Os with
Interrupt
Capability
RST/NMI/SVMOUT
Debug
support
CORE
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Pin Designation, MSP430L092PW
Functional Block Diagram, MSP430L092PW
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Table 1. Terminal Functions
TERMINAL I/O(1) DESCRIPTION
NAME NO.
JTAG test clock
General-purpose digital I/O
Timer0_A3 Out2 output
TCK/P2.0/TA0.2/TA1.2/TA1.1 1 I/O Timer1_A3 Out2 output
Timer1_A3 Out1 output
Timer0_A3 CCR2 capture: CCI2A input, compare
Timer1_A3 CCR2 capture: CCI2A input, compare
JTAG test mode select
General-purpose digital I/O
Timer0_A3 Out2 output
TMS/P2.1/TA0.2/TA1.2/TA0.1 2 I/O Timer1_A3 Out2 output
Timer0_A3 Out1 output
Timer0_A3 CCR2 capture: CCI2B input, compare
Timer1_A3 CCR2 capture: CCI2B input, compare
JTAG test data input
General-purpose digital I/O
Timer0_A3 Out2 output
TDI/P2.2/TA0.2/TA1.2/CCI0.0/CxOUT 3 I/O Timer1_A3 Out2 output
Comparator output
Timer0_A3 CCR0 capture: CCI0A input, compare
Test clock input
JTAG test data output
General-purpose digital I/O
TDO/P2.3/TA0.2/TA1.2/CCI1.0 4 I/O Timer0_A3 Out2 output
Timer1_A3 Out2 output
Timer1_A3 CCR0 capture: CCI0A input, compare
Reset input active low
RST/NMI/SVMOUT 5 I/O Non-maskable interrupt input
SVM output
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
P1.0//TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN 6 I/O ACLK output
Timer0_A3 CCR1 capture: CCI1B input, compare
Analog input A2 – A-Pool
Input terminal for external clock
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK 7 I/O SMCLK output
Timer1_A3 CCR1 capture: CCI1B input, compare
Analog input A1 – A-Pool
Timer0_A3 clock signal TACLK input
(1) I = input, O = output, N/A = not available on this package offering
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MSP430L092
MSP430C09x
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SLAS673 –SEPTEMBER 2010
Table 1. Terminal Functions (continued)
TERMINAL I/O(1) DESCRIPTION
NAME NO.
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3 8 I/O ACLK output
Timer0_A3 CCR0 capture: CCI0B input, compare
Analog input A3 – A-Pool
Analog output – A-Pool
General-purpose digital I/O
Timer0_A3 Out2 output
Timer1_A3 Out2 output
P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3 9 I/O Comparator output
Timer1_A3 CCR0 capture: CCI0B input, compare
Analog input A3 – A-Pool
Reference voltage input / output
VSS/GND 10 Analog and digital power supply ground reference
VCC 11 Analog and digital power supply
General-purpose digital I/O
Timer0_A3 Out2 output
P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK 12 I/O Timer1_A3 Out2 output
MCLK Output
Analog input A0 – A-Pool
General-purpose digital I/O
Timer0_A3 Out2 output
P1.5/TA0.2/TA1.2/TA0.1 13 I/O Timer1_A3 OUT2 output
Timer0_A3 OUT1 output
Timer0_A3 CCR1 capture: CCI1A input, compare
General-purpose digital I/O
Timer0_A3 Out2 output
P1.6/TA0.2/TA1.2/TA1.1 14 I/O Timer1_A3 OUT2 output
Timer1_A3 OUT1 output
Timer1_A1 CCR1 capture: CCI1A input, compare
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General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Instruction Set
The instruction set consists of the original 51
instructions with three formats and seven address
modes. Each instruction can operate on word and
byte data. Table 2 shows examples of the three types
of instruction formats, Table 3 shows the address
modes.
Table 2. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 →R5
Single operands, destination only e.g., CALL R8 PC→(TOS), R8 →PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 3. Address Mode Descriptions
ADDRESS MODE S(1) D(1) SYNTAX EXAMPLE OPERATION
Register ● ● MOV Rs, Rd MOV R10, R11 R10 →R11
Indexed ● ● MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2+R5)→M(6+R6)
Symbolic (PC relative) ● ● MOV EDE, TONI M(EDE) →M(TONI)
Absolute ● ● MOV & MEM, & TCDAT M(MEM) →M(TCDAT)
Indirect ●MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) →M(Tab+R6)
M(R10) →R11
Indirect autoincrement ●MOV @Rn+, Rm MOV @R10+, R11 R10 + 2→R10
Immediate ●MOV #X, TONI MOV #45, TONI #45 →M(TONI)
(1) S = source D = destination
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MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active for all sources
– MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active (for LF oscillator and CLKIN as source, HF oscillator is mapped to LF
oscillator as source)
– MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK is disabled
– SMCLK is disabled
– ACLK remains active for all sources
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK is disabled
– SMCLK is disabled
– ACLK remains active (for LF oscillator and CLKIN as source, HF oscillator is mapped to LF oscillator as
source)
• Low-power mode 4 (LPM4)
– CPU is disabled
– MCLK is disabled
– SMCLK is disabled
– ACLK is disabled
– Oscillators are stopped
LPM2 vs LPM3
If only MCLK is feed by the HF oscillator (SELA ≠00, SELS ≠00, SELM = 00 of CCSCTL4 register) the following
behavior is implemented:
• Entering LPM2 turns off the HF oscillator and starts again with the HF oscillator selected for MCLK
• Entering LPM3 turns off the HF oscillator and starts again with the LF oscillator selected for MCLK
The only difference between LPM2 and LPM3 is the selection of the source for MCLK when re-entering active
mode and, therefore, and the level of power savings.
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MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFE0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY
INTERRUPT
System Reset
Power-Up WDTIFG(1) Reset 0x0FFFE 15, highest
External Reset
Watchdog
System NMI SVMIFG, VMAIFG(1) (Non)maskable 0x0FFFC 14
Vacant memory access
User NMI NMIIFG(1)(2) (Non)maskable 0x0FFFA 13
NMI
Timer1_A3 TA1CCR0 CCIFG0(3) Maskable 0x0FFF8 12
Timer1_A3 TA1CCR1 CCIFG1(1)(3) Maskable 0x0FFF6 11
Watchdog Timer_A Interval Timer Mode WDTIFG Maskable 0x0FFF4 10
A-Pool CxIFG Maskable 0x0FFF2 9
I/O Port P1 P1IFG.0 to P1IFG.6(1)(3) Maskable 0x0FFF0 8
Timer0_A3 TA0CCR0 CCIFG0(3) Maskable 0x0FFEE 7
Timer0_A3 TA0CCR1 CCIFG1(1)(3) Maskable 0x0FFEC 6
I/O Port P2 P2IFG.0 to P2IFG.3(1)(3) Maskable 0x0FFEA 5
0x0FFE8 4
Reserved Reserved(4) ⋮ ⋮
0x0FFE0 0
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the
individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and can be accessed via word or byte formats.
Legend rw: Bit can be read and written.
rw-0,1: Bit can be read and written. It is reset or set by PUC.
rw-(0,1): Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Interrupt Enable 1
15 14 13 12 11 10 9 8
SVMIE
r0 r0 r0 r0 r0 r0 r0 rw-0
76543210
JMBOUTIE JMBINIE NMIIE VMAIE OFIE WDTIE
rw-0 rw-0 r0 rw-0 rw-0 r0 rw-0 rw-0
SVMIE SVM interrupt enable
JMBOUTIE
JMBINIE
NMIIE Nonmaskable-interrupt enable
VMAIE Vacant memory access interrupt enable
OFIE
WDTIE Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a
general-purpose timer.
Interrupt Enable 2
15 14 13 12 11 10 9 8
SVMIFG
r0 r0 r0 r0 r0 r0 r0 rw-0
76543210
JMBOUTIFG JMBINIFG NMIIFG VMAIFG OFIFG WDTIFG
rw-0 rw-0 r0 rw-0 rw-0 r0 rw-0 rw-0
SVMIFG Set by SVM when voltage falls below set voltage
JMBOUTIFG
JMBINIFG
NMIIFG Set via RST/NMI pin
VMAIFG Set on vacant memory access
OFIFG
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
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MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Reset Pin Control Register
15 14 13 12 11 10 9 8
r0 r0 r0 r0 r0 r0 r0 r0
76543210
SYSRSTRE SYSRSTUP SYSNMIES SYSNMI
r0 r0 r0 r0 r1 r1 r1 rw-0
SYSRSTRE Indicates resistor present on RST pin
SYSRSTUP Indicates pullup on RST pin
SYSNMIES Indicates NMI edge select
SYSNMI NMI enable on RST/NMI pin
Memory Organization
Table 5. Memory Organization
TYPE MSP430C091 MSP430C092 MSP430L092 MSP430L092 (EMU)(1)
32 B 32 B 32 B 32 B
Primary interrupt ROM
vectors 0x0FFE0(2) – 0x0FFFF 0x0FFE0(2) – 0x0FFFF 0x0FFE0(2) – 0x0FFFF 0x0FFE0(2) – 0x0FFFF
Secondary RAM 0x01C60 – 0x01C7F
interrupt vectors Lockable 864 B 1888 B ROM not available
Application ROM ROM
memory 0x0FC80 – 0x0FFDF 0x0F880 – 0x0FFDF
128 B (BC) 128 B (BC) 2016 B (Loader) Config/loading by tool
Boot Code (BC) / ROM (by TI)
Loader Code 0x0F800 – 0x0F87F 0x0F800 – 0x0F87F 0x0F800 – 0x0FFDF 0x0F800 – 0x0F87F
128B 128B 128 B 128 B
RAM memory RAM 0x02380 – 0x023FF 0x02380 – 0x023FF 0x02380 – 0x023FF 0x02380 – 0x023FF
1792 B 1760 B
LRAM memory RAM
(lockable) 0x01C80 – 0x0237F 0xF900 – 0xFFDF
96 B 96 B 96 B 128 B(3)
CRAM memory RAM
(lockable) 0x01C00 – 0x01C5F 0x01C00 – 0x01C5F 0x01C00 – 0x01C5F 0x0F880 – 0x0F8FF
4 kB 4 kB 4 kB 4 kB
Peripherals Size 0x00000 – 0x00FFF 0x00000 – 0x00FFF 0x00000 – 0x00FFF 0x00000 – 0x00FFF
(1) The MSP430L092 emulates the MSP430C092 device (MSP430C091 emulation via tool and software).
(2) Not the whole interrupt vector range of CSYS is used on MSP430x09x devices (see Table 4).
(3) Resets and interrupt redirections in RAM with alternate interrupt vectors cannot be emulated .
Start-Up Code (SUC)
The MSP430C09x start-up code checks the password and releases control to the application or enables JTAG
on password match, enters LPM4, and waits for a debug session. The behavior of the SUC is described in the
MSP430L092 Loader Code User's Guide (SLAU324).
Loader Code (Loader)
The MSP430L092 loader checks the presence of an external SPI/I2C memory device containing a valid code
signature, loads validated code into the application LRAM, and starts the application. The loader program uses
P1.2 with an external circuit to pump up the voltage required for SPI memory device readout. For complete
description of the features of the loader and its implementation, see the MSP430L092 Loader Code User's Guide
(SLAU324).
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MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
RAM Memory
The RAM memory is split into three ranges for different purposes: application memory, lockable application
memory, and calibration memory.
Lockable application memory and calibration memory can be protected against accidental erasure by setting a
dedicated lock bit in the special functions register (System Maintenance Register).
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x09x Family User's Guide (SLAU321).
Digital I/O
There are two I/O ports implemented: P1 (7 I/O lines) and P2 (4 I/O lines).
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt input capability for all ports on P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 and P2) or word-wise in pairs (P1/P2 combo).
Oscillator and System Clock
The clock system in the MSP430x09x family of devices is supported by the Compact Clock System (CCS)
module that includes support for an internal 20-kHz current-controlled low-frequency oscillator (LF-OSC), an
internal adjustable 1-MHz current-controlled high-frequency oscillator (HF-OSC), and an external clock input from
CLKIN; however, a missing CLKIN signal does not trigger an oscillator failsafe mechanism in this family.
The CCS module is designed to meet the requirements of both low system cost and low power consumption.
The CCS provides a fast turn-on of the oscillators, less than 1 ms. The CCS module provides the following clock
signals:
• Auxiliary clock (ACLK), sourced from the 20-kHz internal LF-OSC, the 1-MHz internal HF-OSC, or CLKIN.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• VLOCLK is an ultra-low-power low-frequency clock that is available as long the device is powered.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11
00
01
10
11
0
1MCLK
CPUOFF
1
Divider
/1/2/4/8/16/32
3
DIVMx
0
1ACLK
OSCOFF
1
Divider
/1/2/4/8/16/32
3
DIVAx
0
1SMCLK
SCG1
1
Divider
/1/2/4/8/16/32
3
DIVSx
SELAx
HF – OSC
SCG0
SELMx
LF-OSC
SELSx
00
01
10
11
00
01
10
11
CLKIN
ACLK enable logic
MCLK enable logic
SMCLK enable logic
VLOCLK
1
0
/2
DIVCLK
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Figure 1. Compact Clock System (CCS) Block Diagram
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
Table 6. WDT_A Signal Connections
DEVICE CLOCK SIGNAL MODULE CLOCK SIGNAL
ACLK ACLK
SMCLK SMCLK
LF-OSC-CLK VLOCLK
LF-OSC-CLK X-CLK
Compact System Module (C-SYS)
The Compact SYS module handles many of the system functions within the device. These include power-on
reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, and
configuration management. It also includes a data exchange mechanism via JTAG called a JTAG mailbox that
can be used in the application.
12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
RST/NMI/
SVMOUT
Brownout
Circuit
& Delay
RSTNMI
clr
Reset
Logic
SWBOR
BOR
POR
PUCReset-
signals
and
violations
... ...
Interrupt
signals
maskable/
unmaskable
Interrupt
Logic
nmi
CPU
irq
SVMOE
from SVM logic
SVMPD
PortsOn
SVMPO
set
SVSEN
SWPOR
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
RST/NMI/SVMOUT System
The reset system of the MSP430x09x family features the functions reset input, reset output, NMI input, SVM
output, and SVS input.
Figure 2. RST/NMI/SVMOUT and PortsOn Logic Block Diagram
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Table 7. System Module Interrupt Vector Registers
INTERRUPT VECTOR WORD
INTERRUPT VECTOR OFFSET PRIORITY
REGISTER ADDRESS
No interrupt pending 00h
Brownout (BOR) 02h Highest
SVMBOR (BOR) 04h
RST/NMI (BOR) 06h
DoBOR (BOR) 08h
Security violation (BOR) 0Ah
SYSRSTIV, System Reset DoPOR(POR) 019Eh 0Ch
WDT timeout (PUC) 0Eh
WDT key violation (PUC) 10h
CCS key violation 12h
PMM key violation 14h
Peripheral area fetch (PUC) 16h
Reserved 18h-3Eh Lowest
No interrupt pending 00h
SVMIFG 02h Highest
VMAIFG 04h
SYSSNIV, System NMI 019Ch
JMBINIFG 06h
JMBOUTIFG 08h
Reserved 0Ah-3Eh Lowest
No interrupt pending 00h
NMIFG 02h Highest
SYSUNIV, User NMI OFIFG 019Ah 04h
BERR 06h
Reserved 08h-3Eh Lowest
No interrupt pending 00h
SYSBERRIV, Bus Error 0198h
Reserved 02h-3Eh Lowest
14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 8. Timer0_A3 Signal Connections
INPUT PIN OUTPUT PIN
DEVICE INPUT MODULE INPUT MODULE DEVICE OUTPUT
NUMBER NUMBER
MODULE BLOCK
SIGNAL SIGNAL OUTPUT SIGNAL SIGNAL
PW PW
7 – P1.1 TA0CLK TACLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
7 – P1.1 TA0CLK TACLK
3 – P2.2 CCI0.0 CCI0A
8 – P1.2 CCI0.0 CCI0B CCR0 TA0 TA0.0
VSS GND
VCC VCC
13 – P1.5 TA0.1 CCI1A 2 – P2.1
6 – P1.0 CCI0.1 CCI1B 13 – P1.5
CCR1 TA1 TA0.1
VSS GND
VCC VCC
1 – P2.0 TA0.2 CCI2A 1-4 – P2.0-P2.3
2 – P2.1 TA0.2 CCI2B 6-9 – P1.0-P1.3
CCR2 TA2 TA0.2
VSS GND 12-14 – P1.4-P1.6
VCC VCC
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Timer1_A3
Timer1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer1_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9. Timer1_A3 Signal Connections
INPUT PIN OUTPUT PIN
DEVICE INPUT MODULE INPUT MODULE DEVICE OUTPUT
NUMBER NUMBER
MODULE BLOCK
SIGNAL SIGNAL OUTPUT SIGNAL SIGNAL
PW PW
12 – P1.4 TA1CLK TACLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
12 – P1.4 TA1CLK TACLK
4 – P2.3 CCI1.0 CCI0A
9 – P1.3 CCI1.0 CCI0B TA1.0
CCR0 TA0
VSS GND
VCC VCC
14 – P1.6 TA1.1 CCI1A 1 – P2.0
7 – P1.1 CCI1.1 CCI1B TA1.1 14 – P1.6
CCR1 TA1
VSS GND
VCC VCC
1 – P2.0 TA1.2 CCI2A 1-4 – P2.0-P2.3
2 – P2.1 TA1.2 CCI2B 6-9 – P1.0-P1.3
CCR2 TA2 TA1.2
VSS GND 12-14 – P1.4-P1.6
VCC VCC
16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
NSELx
+
-
CxIFG logic
CxOUT
Reference
256mV
REFON CMPON
MDB and buffer register
CONVON
APVDIV Register
Vcc
4
8
0000
ADC-DAC-SAR-REG
Up-Dn Counter
Run/
Stop
00
2
set
clr TA0EN
TA0.0
CBSTP
0
1
OSWP
0
1Aout
OSEL
CLKSEL
A0
A1
A3
A2
VREF
SMCLK
SLOPE
ODEN
D/A-8
DBON
TBSTP
TA0.1
TA1EN
TA1.0
De-
Glitching
DFSETx
SBSTP
VREFEN
SLOPE
EOCIFG logic
sEOC
0001
0010
0011
0100
0101
0110
0111
1000
PSELx
4
0000
0001
0010
0011
0100
0101
0110
0111 Pre-Scaler
by 1/2/4/8/16/32
CLKDIVx
SAREN
xCLK
xCLK
from AZ-logic
AZ EN
CT
Start Stop Logic
Clock
Logic
MCLK
VLOCLK 01
10
11
1001
?
SVMIFG logic
R
R
6R
Vcc
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
A-Pool
The analog functions pool (A-Pool) provides a series of functions that can be configured to a digital-to-analog
converter (DAC), multichannel analog-to-digital converter (ADC), supply voltage supervisor (SVS), and
comparator. Input voltage dividers and an internal reference source allow a wide range of combined analog
functions.
Figure 3. A-Pool Block Diagram
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
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Versatile I/O Port P1, P2
The versatile I/O ports P1 and P2 feature device-dependent reset values. The reset values for the MSP430x09x
devices are shown in Table 10.
Table 10. Versatile Port Reset Values
PORT PxOUT PxDIR PxREN PxSEL0 PxSEL1 RESET PORTS ON COMMENT
NUMBER
P1.0 0 0 0 0 0 PUC yes P1.0, input
P1.1 0 0 0 0 0 PUC yes P1.1, input
P1.2 0 0 0 0 0 PUC yes P1.2, input
P1.3 0 0 0 0 0 PUC yes P1.3, input
P1.4 0 0 0 0 0 PUC yes P1.4, input
P1.5 0 0 0 0 0 PUC yes P1.5, input
P1.6 0 0 0 0 0 PUC yes P1.6, input
P1.7 - - - - - - - -
P2.0 1 0 1 1 1 BOR no JTAG TCK, input, pullup
P2.1 1 0 1 1 1 BOR no JTAG TMS, input, pullup
P2.2 1 0 1 1 1 BOR no JTAG TDI, input, pullup
P2.3 0 1 0 1 1 BOR no JTAG TDO, output, pullup
Peripheral File Map
Table 11. Peripherals
BASE
MODULE NAME REGISTER DESCRIPTION REGISTER OFFSET
ADDRESS
Timer1_A interrupt vector TA1IV 2Eh
Capture/compare register 2 TA1CCR2 16h
Capture/compare register 1 TA1CCR1 14h
Capture/compare register 0 TA1CCR0 12h
Timer1_A3 Timer1_A register TA1R 0380h 10h
Capture/compare control 2 TA1CCTL2 06h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 0 TA1CCTL0 02h
Timer1_A control TA1CTL 00h
Timer0_A interrupt vector TA0IV 2Eh
Capture/compare register 2 TA0CCR2 16h
Capture/compare register 1 TA0CCR1 14h
Capture/compare register 0 TA0CCR0 12h
Timer0_A3 Timer1_A register TA0R 0340h 10h
Capture/compare control 2 TA0CCTL2 06h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 0 TA0CCTL0 02h
Timer1_A control TA0CTL 00h
18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Table 11. Peripherals (continued)
BASE
MODULE NAME REGISTER DESCRIPTION REGISTER OFFSET
ADDRESS
Port P2 interrupt Flag P2IFG 1Dh
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt vector word P2IV 1Eh
Port P2 selection 1 P2SEL1 0Dh
Port P2 0200h
Port P2 selection 0 P2SEL0 0Bh
Port P2 pullup/pulldown enable P2REN 07h
Port P2 direction P2DIR 05h
Port P2 output P2OUT 03h
Port P2 input P2IN 01h
Port P1 interrupt Flag P1IFG 1Ch
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt vector word P1IV 0Eh
Port P1 selection 1 P1SEL1 0Ch
Port P1 0200h
Port P1 selection 0 P1SEL0 0Ah
Port P1 pullup/pulldown enable P1REN 06h
Port P1 direction P1DIR 04h
Port P1 output P1OUT 02h
Port P1 input P1IN 00h
Analog pool interrupt vector register APIV 1Eh
Analog pool interrupt enable register APIE 1Ch
Analog pool interrupt flag register APIFG 1Ah
Analog pool fractional value buffer APFRACTB 16h
Analog pool fractional value register APFRACT 14h
A-POOL Analog pool integer value buffer APINTB 01A0h 12h
Analog pool integer value register APINT 10h
Analog pool voltage divider register APVDIV 06h
Analog pool operation mode register APOMR 04h
Analog pool control register APCTL 02h
Analog pool configuration register APCNF 00h
Reset vector generator SYSRSTIV 1Eh
System NMI vector generator SYSSNIV 1Ch
User NMI vector generator SYSUNIV 1Ah
Bus error vector generator SYSBERRIV 18h
System Configuration register SYSCNF 10h
CSYS JTAG mailbox output register #1 SYSJMBO1 0180h 0Eh
JTAG mailbox output register #0 SYSJMBO0 0Ch
JTAG mailbox input register #1 SYSJMBI1 0Ah
JTAG mailbox input register #0 SYSJMBI0 08h
JTAG mailbox control register SYSJMBC 06h
System control register SYSCTL 00h
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 19
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Table 11. Peripherals (continued)
BASE
MODULE NAME REGISTER DESCRIPTION REGISTER OFFSET
ADDRESS
CCS control 15 register CCSCTL15 1Eh
CCS control 8 register CCSCTL8 10h
CCS control 7 register CCSCTL7 0Eh
CCS control 5 register CCSCTL5 0Ah
CCS 0160h
CCS control 4 register CCSCTL4 08h
CCS control 2 register CCSCTL2 04h
CCS control 1 register CCSCTL1 02h
CCS control 0 register CCSCTL0 00h
WDT_A Watchdog timer control WDTCTL 0150h 0Ch
PMM PMM control 0 PMMCTL0 0120h 00h
ET-Wrapper ET Key and select ETKEYSEL 0110h 00h
SFR Reset pin control register SFRRPCR 04h
Special Functions SFR interrupt flag register SFRIFG1 0100h 02h
SFR interrupt enable register SFRIE1 00h
20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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MSP430C09x
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SLAS673 –SEPTEMBER 2010
Absolute Maximum Ratings(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Voltage applied at VCC referenced to VSS (VAMR) –0.3 V to 1.90 V
–0.3 V to VCC + 0.3 V
Voltage applied to any pin (references to VSS)–0.3 V to 1.90 V
Diode current at any device pin(2) ±2.5 mA
Current derating factor when I/O ports are switched in parallel electrically and logically(3) 0.9
Storage temperature range(4) –55°C to 150°C
ESD tolerance, Human-Body Model (HBM) 2000 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS.
(3) The diode current increases to ±4.5 mA when two pins are connected, ± 6.75 mA for three pins.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage during program execution 0.9 1.65 V
VSS Supply voltage (GND reference) 0 V
TAOperating free-air temperature 0 50 °C
CVCC Capacitor on VCC 470 nF
VCC > 0.9 V, tLOW ≥450 ns, tHIGH ≥450 ns 1 MHz
fSYSTEM(1)( System operating frequency
2) VCC > 1.5 V, tLOW ≥113 ns, tHIGH ≥113 ns 4 MHz
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 21
MSP430L092
MSP430C09x
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Active Mode Supply Current (Into VCC) Excluding External Current(1)(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TAMIN TYP MAX UNIT
0.9 V 59 68
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz,
Program executes in RAM, 1.3 V 0°C 72 84
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.65 V 86 101
0.9 V 59 68
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz,
IAM,1MHz Program executes in RAM, 1.3 V 30°C 72 84 µA
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.65 V 86 101
0.9 V 60 70
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz,
Program executes in RAM, 1.3 V 50°C 74 87
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.65 V 88 105
0.9 V 31 35
fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz,
Program executes in RAM, 1.3 V 0°C 33 38
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.65 V 37 42
0.9 V 31 35
fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz
IAM,125kHz Program executes in RAM 1.3 V 30°C 33 38 µA
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.65 V 37 42
0.9 V 32 37
fMCLK = fSMCLK = 125 kHz, fACLK = 20 kHz,
Program executes in RAM, 1.3 V 50°C 35 41
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.65 V 40 48
fMCLK = fSMCLK : 1 to 5 MHz, fACLK = 20 kHz µA/
IAM/MHz Program executes in RAM, CPUOFF = 0, SCG0 = 0, 1.3 V 30°C 45 MHz
SCG1 = 0, OSCOFF = 0
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing "Type2".
Low-Power Mode Supply Current (Into VCC) Excluding External Current(1)(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TAMIN TYP MAX UNIT
0.9 V 6.6 8
1.3 V 0°C 7.6 9
1.65 V 8.6 11
0.9 V 7 9
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz
ILPM0 1.3 V 30°C 8.3 11 µA
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 1.65 V 9.5 12
0.9 V 8.9 12
1.3 V 50°C 11 14
1.65 V 12 17
0.9 V 6.6 8
1.3 V 0°C 7.6 9
1.65 V 8.6 11
0.9 V 7 9
fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz
ILPM1 1.3 V 30°C 8.3 11 µA
CPUOFF = 1, SCG0 = 1, SCG1 = 0, OSCOFF = 0 1.65 V 9,5 12
0.9 V 8.9 12
1.3 V 50°C 11 14
1.65 V 12 17
(1) Current for WDT clocked by ACLK included.
(2) Current for Brownout included.
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www.ti.com
SLAS673 –SEPTEMBER 2010
Low-Power Mode Supply Current (Into VCC) Excluding External Current(1)(2) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TAMIN TYP MAX UNIT
0.9 V 26 30
1.3 V 0°C to 30°C 28 32
1.65 V 29 33
fMCLK = fSMCLK = 1MHz, fACLK = 1MHz
ILPM2,1MHz µA
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 0.9 V 28 32
1.3 V 50°C 30 35
1.65 V 32 38
0.9 V 6.6 8
1.3 V 0°C 7.6 10
1.65 V 8.6 11
0.9 V 7 10
fMCLK = fSMCLK = fACLK = 20 kHz
ILPM2,20kHz 1.3 V 30°C 8.3 12 µA
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 1.65 V 9.5 13
0.9 V 8.9 13
1.3 V 50°C 11 15
1.65 V 12 17
0.9 V 6.6 8
1.3 V 0°C 7.6 9
1.65 V 8.6 11
0.9 V 7.1 9
fMCLK = fSMCLK = fACLK = 20 kHz
ILPM3 1.3 V 30°C 8.3 11 µA
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 1.65 V 9.5 12
0.9 V 8.9 12
1.3 V 50°C 11 14
1.65 V 12 17
0.9 V 3.2 4.7
1.3 V 0°C 5.1 6.3
1.65 V 6.5 8
0.9 V 4 5.7
fMCLK = fSMCLK = fACLK = 20 kHz
ILPM4 1.3 V 30°C 6 7.9 µA
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 1.65 V 7.8 10
0.9 V 6 8.9
1.3 V 50°C 8.6 12
1.65 V 11 16
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 23
MSP430L092
MSP430C09x
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www.ti.com
Ports P1 and P2, RST/NMI/SVMOUT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 0.9 V, IOH = –1 mA(1) for ports P1, P2 VCC – 0.25
VOH VCC = 1.65 V, IOH = –1 mA(1) for ports P1, P2 VCC – 0.15 V
VCC = 0.9 V, IOH = –300 µA(1) for ports P1, P2 VCC – 0.15
VCC = 0.9 V, IOL = 2.5 mA(2) for ports P1, P2 0.2
VOL VCC = 1.65 V, IOL = 2.5 mA(2) for ports P1, P2 0.15 V
VCC = 0.9 V, IOL = 300 µA(2) for ports P1, P2 0.07
VCC = 1.65 V 0.3 × VCC
VIL V
VCC = 0.9 V 0.25 × VCC
VCC = 1.65 V 0.7 × VCC
VIH V
VCC = 0.9 V 0.75 × VCC
VHYS Intrinsic hysteresis 150 mV
VCC = 0.9 V, CL= 15 pF || RL= 750 Ωto VSS on VOH for ports P1, P2 75
VCC = 0.9 V, CL= 15 pF || RL= 320 Ωto VCC on VOL for ports P1, P2 75
Δt/Δv ns/V
VCC = 1.65 V, CL= 25 pF || RL= 1600 Ωto VSS on VOH for ports P1, P2 75
VCC = 1.65 V, CL= 25 pF || RL= 600 Ωto VSS on VOL for ports P1, P2 75
IOH VCC = 0.9 V to 1.65 V for ports P1, P2 –1 mA
IOL VCC = 0.9 V to 1.65 V for ports P1, P2 2.5 mA
ILKG VCC = 0.9 V to 1.65 V (at 50°C) ±100 nA
tINT P0.x, VCC = 0.9 V to 1.65 V 200 ns
RPULL For pullup: VIN = VSS, For pulldown: VIN = VCC for ports P1, P2 30 35 40 kΩ
RRST Pullup on RST/NMI/SVMOUT 30 35 40 kΩ
REXT External pullup resistor on RST terminal (optional) 680 kΩ
CIVIN = VSS or VCC 7 pF
(1) The maximum total current IOH, for all outputs combined should not exceed 5 mA to hold the maximum voltage drop specified.
(2) The maximum total current IOL, for all outputs combined should not exceed 15 mA to hold the maximum voltage drop specified.
24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.825 0.85 0.875 0.9
V = 0.9 V
CC
0°C, 30°C, 50°C
I – Typical High-Level Output Current – mA
OH
V – High-Level Output Voltage – V
OH
0
0.5
1
1.5
2
2.5
3
0 0.05 0.1
V = 0.9 V
CC 0°C, 30°C, 50°C
I – Typical Low-Level Output Current – mA
OL
V – Low-Level Output Voltage – V
OL
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
1.6 1.61 1.62 1.63 1.64 1.65
0°C, 30°C, 50°C
V = 1.65 V
CC
I – Typical High-Level Output Current – mA
OH
V – High-Level Output Voltage – V
OH
0
0.5
1
1.5
2
2.5
3
0 0.01 0.02 0.03 0.04 0.05
0°C, 30°C, 50°C
V = 1.65 V
CC
I – Typical Low-Level Output Current – mA
OL
V – Low-Level Output Voltage – V
OL
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Typical Characteristics – Outputs
TYPICAL LOW-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 4. Figure 5.
TYPICAL LOW-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 6. Figure 7.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 25
0
2
4
6
8
10
12
14
16
0 0.05 0.1 0.15 0.2 0.25
V = 1.65 V
CC
30°C
I – Typical Low-Level Output Current – mA
OL
V – Low-Level Output Voltage – V
OL
-16
-14
-12
-10
-8
-6
-4
-2
0
0.8 1 1.2 1.4 1.6 1.8
V = 1.65 V
CC
30°C
I – Typical High-Level Output Current – mA
OH
V – High-Level Output Voltage – V
OH
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.8 1 1.2 1.4 1.6 1.8
50°C
30°C
0°C
V – Typical Low-Level Input Voltage – V
IL
V – Supply Voltage – V
CC
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.8 1 1.2 1.4 1.6 1.8
0°C
30°C
50°C
V – Typical High-Level Input Voltage – V
IH
V – Supply Voltage – V
CC
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Typical Characteristics – Outputs (continued)
TYPICAL LOW-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT VOLTAGE
vs vs
LARGE SIGNAL OUTPUT CURRENT LARGE SIGNAL OUTPUT CURRENT
Figure 8. Figure 9.
TYPICAL LOW-LEVEL INPUT VOLTAGE TYPICAL LOW-LEVEL INPUT VOLTAGE
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 10. Figure 11.
26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
500
1000
1500
2000
2500
0 16 32 48 64 80 96 112 128
V = 1.3 V
CC
Frequency – kHz
Value in CCSCTL2 Register
0.98
0.99
1
1.01
1.02
0 10 20 30 40 50
0.9 V
1.3 V
1.65 V
Frequency / Frequency30°C
T – Temperature – °C
A
VCC
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
High-Frequency Oscillator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fHFOSC VCC = 0.9 V to 1.65 V (minimum trim range via register) 0.75 1 1.25 MHz
fHFOSC VCC = 0.9 V to 1.65 V (trimmed at 30°C) 0.92 1 1.08 MHz
Duty cycle VCC = 0.9 V to 1.65 V 45 50 55 %
tSTART VCC = 0.9 V to 1.65 V 20 µs
ΔfHFOSC/DT VCC = 0.9 V to 1.65 V, fHFOSC = 1 MHz ±0.07 ±0.15 %/°C
ΔfHFOSC/ΔVCC VCC = 1.0 V to 1.65 V, fHFOSC = 1 MHz ±1 %/V
ΔfHFOSC/ΔVCC VCC = 0.90 V to 1.0 V, fHFOSC = 1 MHz ±1 ±2.5 %/V
%/
ΔfHFOSC/CALSTEP(1) VCC = 0.9 V to 1.65 V, fHFOSC = 1 MHz, ±64 calibration steps 0.1 1 4 Step
IOSC VCC = 0.9 V to 1.65 V, fHFOSC = 1 MHz 22 µA
(1) Normalized to typical frequency
Typical Characteristics – High-Frequency Oscillator
FREQUENCY vs TRIM SETTING
Figure 12.
FREQUENCY vs TEMPERATURE
Figure 13.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 27
10.0
20.0
30.0
40.0
0 10 20 30 40 50 60
VCC
0.9 V
1.0 V
1.3 V
1.65 V
Frequency – kHz
T – Temperature – °C
A
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Low-Frequency Oscillator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fLFOSC VCC = 0.9 V to 1.65 V 6 20 45 kHz
Duty cycle VCC = 0.9 V to 1.65 V 45 50 55 %
tSTART VCC = 0.9 V to 1.65 V 500 µs
IOSC VCC = 0.9 V to 1.65 V, fLFOSC = 20 kHz 0.6 µA
Typical Characteristics – Low-Frequency Oscillator
FREQUENCY vs TEMPERATURE
Figure 14.
Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBOR(Start) 490 mV
V(BOR_IT+) VCC rising, ΔVCC/Δt < 3 V/s 1095 1150 mV
V(BOR_IT–) VCC falling, ΔVCC/Δt < 3 V/s 860 900 mV
Vhys(BOR) 200 mV
VMARGIN VMARGIN = V(BOR-IT–) – VCRIT, (VCRIT < 820 mV)(1) 40 mV
3000(2
td(BOR) µs
)
(1) VCRIT is a temperature depending voltage where the single components of the device become unreliable (the 'L092 provides a safety
margin to ensure overall device function).
(2) Strongly depends on voltage ramp in system (actually a maximum typical value).
28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
254
255
256
257
258
0 10 20 30 40 50 60
VCC
1.65 V
1.3 V
1.0 V
0.9 V
V – Reference Voltage (TYP = 256 mV)
REF
T – Temperature – °C
A
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
A-POOL, External Reference Source
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 0.9 V to 1.65 V, ADC / DAC operational 100 275 mV
VREF VCC = 0.9 V to 1.65 V, ADC / DAC not operational 0 VCC V
IREF(Input) VCC = 0.9 V to 1.65 V, load to external sinks 3 µA
CREF REFON = 0 20 50 pF
A-POOL, Built-In Reference Source
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF VCC = 0.9 V to 1.65 V (±1.5%, overall 3%) 256 mV
IREF VCC = 0.9 V to 1.65 V 10 µA
CREF REFON = 1 20 50 pF
ppm/
TREF VCC = 0.9 V to 1.65 V (ΔV/ΔT × VREF referenced to 25°C) ±250 °C
tSETTLE VCC = 0.9 V to 1.65 V, REFON = 1, CREF = CREF(max)(1) 900(1) µs
IREF(Output) VCC = 0.9 V to 1.65 V, REFON = 1, CREF = CREF(max) 2 µA
(1) As the actual on reference enable signal is synchronized with the LF oscillator.
Typical Characteristics – A-POOL Built-In Reference Source
VOLTAGE vs TEMPERATURE
Figure 15.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 29
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
A-POOL, Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISENSOR VCC = 0.9 V to 1.65 V 2 µA
TCSENSOR VCC = 0.9 V to 1.65 V, TA= 0°C to 50°C (ΔV/ΔT referenced to 30°C) 464 µV/°C
VOFFSET25 VCC = 0.9 V to 1.65 V at TA= 30°C 179 mV
tSETTLE VCC = 0.9 V to 1.65 V (before start of conversion) 15 µs
VSENSOR(1) VCC = 0.9 V to 1.65 V, TA= 0°C to 50°C 179 mV
(1) This formula can be used to calculate the temperature sensor output voltage: VSENSOR = VOFFSET25 + TCSENSOR × (TA– 30°C).
A-POOL, Input Voltage Dividers
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Any Rx in dividers ±1.5
ΔRx/Rx %
Any Rx across switches and internal supply voltage divider (by 4, by 8) ±2
On A0/A1 , VA0/VA1 = 0.5V, ADIV0/ADIV1 = 1 (500-mV range) 120 200 300
RIN On A2/A3 , VA2/VA3 = 0.5V, ADIV2/ADIV4 = 1 (1-V range) 80 133 190 kΩ
On A2/A3 , VA2/VA3 = 0.5V, ADIV2+ADIV3/ADIV4+ADIV5 = 1 (2-V range) 70 114 150
ΔIVCC ADIV7 = 1 (supply voltage divider on) 2 µA
A-POOL, DAC-8
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF VCC = 0.9 V to 1.65 V 256 mV
On ±1 LSB steps (6t), VCC = 0.9 V to 1.65 V, external VREF 2
tSETTLE µs
Between all codes > 20 on AOUT (6t), VCC = 0.9 V to 1.65 V, external VREF 14
VCC = 0.9 V to 1.65 V, external VREF,
EI ±3 LSB
add ±7 mV for VOUT offset(1) for codes > 7
VCC = 0.9 V to 1.65 V, external VREF,
ED ±1 LSB
add ±7 mV for VOUT offset(1) for codes > 7
(1) This offset can be compensated using software.
A-POOL, Comparator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN VCC = 0.9 V to 1.65 V 0 275 mV
Overdrive = 20 mV 0.5
tpd Overdrive = 5 mV 0.5 µs
Overdrive = 1 mV 1
A-POOL, AOUT Terminal
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT > 50 mV 5
(accuracy ±1% of VOUT)
| ILOAD | VCC = 0.9 V to 1.65 V, CLOAD = 25 pF µA
VOUT > 20 mV 2
(accuracy ±1% of VOUT)
tSETTLE VCC = 0.9 V to 1.65 V, CLOAD = 25 pF, ± 1% (6t) (for AOUT 20 to 256 mV) 4 µs
30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
A-POOL, ADC-8 Counter
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fCNT VCC = 0.9 V to 1.65 V 1 MHz
tCONV Full conversion (all codes), fCNT = 1 MHz 256 µs
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOP Operating temperature 0°C to 70°C, fCPU = 1MHz 900 mV
VRET Operating temperature 0°C to 70°C (tracks BOL level) 700 mV
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 31
P1REN.x
00
01
10
11
P1DIR.x
00
01
10
11
P1OUT.x
SMCLK
TA 0.2
TA 1.2
P1SEL 0.x
P1SEL 1.x
0
1Vcc
Vss
P1IN.x
P1IRQ.x P1IE.x
P1IES.x Set
Q
Pad Logic
P1IFG.x
to A-Pool
PSELx=y # NSELx=y
P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN
to Clock System
EN1
EN2
DModule X IN
#
PortsOn
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
PORT SCHEMATICS
Port P1, P1.0 Input/Output
Table 12. Port P1 (P1.0) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x FUNCTION RSELx/ASE
P1DIR.x P1SEL1.x P1SEL0.x Lx
P1.0 (I/O) I:0, O:1 0 0 0
Timer_A0.2 1 0 1 0
Timer_A1.2 1 1 0 0
P1.0/TA0.2/TA1.2/ACLK/ 0 ACLK 1 1 1 0
CCI0.1/A2/CLKIN Timer A0, CCI1B 0 ≠0≠0 X
A2 X X X 2
CLKIN (via Bypass) X X X X
(1) X = Don't care
32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P1REN.x
00
01
10
11
P1DIR.x
00
01
10
11
P1OUT.x
from Module
TA 0.2
TA 1.2
P1SEL 0.x
P1SEL 1.x
0
1Vcc
Vss
P1IN.x
EN1
EN2
DModule X IN
#
Pad Logic
to A-Pool
PSELx=y # NSELx=y
P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK
P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK
PortsOn
P1IRQ.x P1IE.x
P1IES.x Set
Q
P1IFG.x
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Port P1, P1.1 and P1.4 Input/Output
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 33
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Table 13. Port P1 (P1.1, P1.4) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x FUNCTION RSELx/ASE
P1DIR.x P1SEL1.x P1SEL0.x Lx
P1.1 (I/O) I:0, O:1 0 0 0
Timer_A0.2 1 0 1 0
Timer_A1.2 1 1 0 0
P1.1/TA0.2/TA1.2/SMCLK/ 1 SMCLK 1 1 1 0
CCI1.1/A1/TA0CLK A1 X X X 1
TimerA0 CLK X ≠0≠0 X
Timer A1, CCI1B 0 ≠0≠0 X
P1.4 (I/O) I:0, O:1 0 0 0
Timer_A0.2 1 0 1 0
Timer_A1.2 1 1 0 0
P1.4/TA0.2/TA1.2/MCLK/ 4
A0/TA1CLK MCLK 1 1 1 0
A0 X X X 0
TimerA1 CLK 0 ≠0≠0 X
(1) X = Don't care
34 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P1REN .x
00
01
10
11
P1DIR.x
00
01
10
11
P1OUT .x
from Module
TA 0.2
TA 1.2
P1SEL0.x
P1SEL1.x
0
1Vcc
Vss
P1IN.x
EN1
EN2
DModule X IN
#
from A-Pool
from A-Pool
P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3
P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3
Pad Logic
to A-Pool
PSELx=y # NSELx=y
PortsOn
P1IRQ.x P1IE.x
P1IES.x Set
Q
P1IFG.x
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Port P1, P1.2 and P1.3 Input/Output
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 35
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Table 14. Port P1 (P1.2, P1.3) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x FUNCTION RSELx/ASE
P1DIR.x P1SEL1.x P1SEL0.x Analog Out
Lx
P1.2 (I/O) I:0, O:1 0 0 0 0
Timer_A0.2 1 0 1 0 0
Timer_A1.2 1 1 0 0 0
P1.2/TA0.2/TA1.2/ACLK/ 2 ACLK 1 1 1 0 0
CCI0.0/AOUT/A3 Timer A0, CCI0B 0 ≠0≠0 X X
A3 X X X 3 X
AOUT(2) X X X X 1
P1.3 (I/O) I:0, O:1 0 0 0 0
Timer_A0.2 1 0 1 0 0
Timer_A1.2 1 1 0 0 0
P1.3/TA0.2/TA1.2/CxOUT/ 3 CxOUT 1 1 1 0 0
CCI1.0//VREF/A3 Timer A1, CCI0B 0 ≠0≠0 X X
A3 X X X 3 X
VREF(2) X X X X 1
(1) X = Don't care
(2) An analog output enable overrides the digital output control.
36 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P1REN.x
00
01
10
11
P1DIR.x
00
01
10
11
P1OUT.x
Module X OUT
TA 0.2
TA 1.2
P1SEL0.x
P1SEL1.x
0
1Vcc
Vss
P1IN.x
EN1
EN2
DModule X IN
#
Pad Logic
P1.5/TA 0.2/TA1.2/TA0.1
P1.6/TA 0.2/TA1.2/TA1.1
PortsOn
P1IRQ.x P1IE.x
P1IES.x Set
Q
P1IFG.x
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Port P1, P1.5 and P1.6 Input/Output
Table 15. Port P1 (P1.5, P1.6) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL1.x P1SEL0.x
P1.5 (I/O) I:0, O:1 0 0
Timer_A0.2 1 0 1
P1.5/TA0.2/TA1.2/TA0.1 5 Timer_A1.2 1 1 0
Timer A0.1 1 1 1
Timer_A0.CCI1A 0 ≠0≠0
P1.6 (I/O) I:0, O:1 0 0
Timer_A0.2 1 0 1
P1.6/TA0.2/TA1.2/TA1.1 6 Timer_A1.2 1 1 0
Timer A1.1 1 1 1
Timer_A1.CCI1A 0 ≠0≠0
(1) X = Don't care
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 37
P2REN.x
00
01
10
11
P2DIR.x
00
01
10
11
P2OUT.x
Module X OUT
TA 0.2
TA 1.2
P2SEL0.x
P2SEL1.x
0
1Vcc
Vss
P2IN.x
EN1
EN2
DModule X IN
#
Pad Logic
TCK/P2.0/TA0.2/TA1.2/TA 1.1
TMS/P2.1/TA0.2/TA 1.2/TA0.1
TDI/P2.2/TA0.2/TA 1.2/CxOUT/CCI0.0
to JTAG
from JTAG
PortsOn
P2IRQ.x P2IE.x
P2IES.x Set
Q
P2IFG.x
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Port P2, P2.0 to P2.2, Input/Output
38 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430L092
MSP430C09x
www.ti.com
SLAS673 –SEPTEMBER 2010
Table 16. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL1.x P2SEL0.x JTAG Mode
P2.0 (I/O) I:0, O:1 0 0 0
Timer_A0.2 1 0 1 0
Timer_A1.2 1 1 0 0
TCK/P2.0/TA0.2/ 0
TA1.2/TA1.1 Timer_A1.1 1 1 1 0
Timer_A0.CCI2A and Timer_A1.CCI2A 0 ≠0≠0 0
JTAG-TCK(2)(3)(4) X X X 1
P2.1 (I/O) I:0, O:1 0 0 0
Timer_A0.2 1 0 1 0
Timer_A1.2 1 1 0 0
TMS/P2.1/TA0.2/ 1
TA1.2/TA0.1 Timer_A0.1 1 1 1 0
Timer_A0.CCI2B and Timer_A1.CCI2B 0 ≠0≠0 0
JTAG-TMS(2)(3)(4) X X X 1
P2.2 (I/O) I:0, O:1 0 0 0
Timer_A0.2 1 0 1 0
Timer_A1.2 1 1 0 0
TDI/P2.2/TA0.2/TA1.2/ 2
CxOUT/CCI0.0 CxOUT 1 1 1 0
Timer_A0.CCI0A 0 ≠0≠0 0
JTAG-TDI(2)(3)(4) X X X 1
(1) X = Don't care
(2) JTAG signals TMS,TCK and TDI read as "1" when nor configured as explicit JTAG terminals
(3) JTAG overrides digital output control when configured as explicit JTAG terminals
(4) JTAG function with enabled pullup resistors is default after power up
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 39
P2REN.x
00
01
10
11
P2DIR.x
00
01
10
11
P2OUT.x
TDO from JTAG
TA 0.2
TA 1.2
P2SEL0.x
P2SEL1.x
0
1Vcc
Vss
P2IN.x
EN1
EN2
DModule X IN
#
Pad Logic
TDO/P2.3/TA0.2/TA 1.2/CCI1.0
to JTAG
from JTAG
PortsOn
P2IRQ.x P2IE.x
P2IES.x Set
Q
P2IFG.x
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010
www.ti.com
Port P2, P2.3, Input/Output
Table 17. Port P2 (P2.3) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL1.x P2SEL0.x
P2.0 (I/O) I:0, O:1 0 0
Timer_A0.2 1 0 1
TDO/P2.0/TA0.2/TA1.2/ 3 Timer_A1.2 1 1 0
CCI1.0 JTAG-TDO(2)(3) 1 1 1
Timer_A1.CCI0A 0 ≠0≠0
(1) X = Don't care
40 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430L092CY PREVIEW DIESALE Y 0 TBD Call TI Call TI
MSP430L092SPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430L092SPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP®Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
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Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
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