Vishay Siliconix
Si5457DC
New Product
Document Number: 67013
S10-2011-Rev. A, 06-Sep-10
www.vishay.com
1
P-Channel 20 V (D-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Portable Devices
- Load Switch
- Charger Switch
- Battery Switch
- DC/DC Converter
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)I
D (A) Qg (Typ.)
- 20
0.036 at VGS = - 4.5 V - 6a
12.5 nC0.041 at VGS = - 3.6 V - 6a
0.056 at VGS = - 2.5 V - 6a
Ordering Information: Si5457DC-T1-GE3 (Lead (Pb)-free and Halogen-free)
Marking Code
BT XXX
Lot Traceability
and Date Code
Part #
Code
Bottom View
1206-8 ChipFET
D
D
D
G
D
D
D
S
1
S
G
D
P-Channel MOSFET
Notes:
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See solder profile (www.vishay.com/ppg?73257). The 1206-8 ChipFET is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 95 °C/W.
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter Symbol Limit Unit
Drain-Source Voltage VDS - 20 V
Gate-Source Voltage VGS ± 12
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
ID
- 6a
A
TC = 70 °C - 6a
TA = 25 °C - 6a, b, c
TA = 70 °C - 5.2b, c
Pulsed Drain Current IDM - 20
Continuous Source-Drain Diode Current TC = 25 °C IS
- 4.8
TA = 25 °C - 1.9b, c
Maximum Power Dissipation
TC = 25 °C
PD
5.7
W
TC = 70 °C 3
TA = 25 °C 2.3b, c
TA = 70 °C 1.2b, c
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
Soldering Recommendations (Peak Temperature)d, e 260
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientb, f t ≤ 5 s RthJA 45 55 °C/W
Maximum Junction-to-Foot (Drain) Steady State RthJF 18 22
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Document Number: 67013
S10-2011-Rev. A, 06-Sep-10
Vishay Siliconix
Si5457DC
New Product
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 20 V
VDS Temperature Coefficient ΔVDS/TJ ID = - 250 µA - 14 mV/°C
VGS(th) Temperature Coefficient ΔVGS(th)/TJ 3.2
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.6 - 1.4 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 12 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 20 V, VGS = 0 V - 1 µA
VDS = - 20 V, VGS = 0 V, TJ = 85 °C - 5
On-State Drain CurrentaID(on) VDS ≤ - 5 V, VGS = - 4.5 V - 20 A
Drain-Source On-State ResistanceaRDS(on)
VGS = - 4.5 V, ID = - 4.9 A 0.030 0.036
Ω
VGS = - 3.6 V, ID = - 4.6 A 0.034 0.041
VGS = - 2.5 V, ID = - 2.0 A 0.046 0.056
Forward Transconductanceagfs VDS = - 10 V, ID = - 4.9 A 16 S
Dynamicb
Input Capacitance Ciss
VDS = - 10 V, VGS = 0 V, f = 1 MHz
1000
pFOutput Capacitance Coss 225
Reverse Transfer Capacitance Crss 195
Total Gate Charge Qg
VDS = - 10 V, VGS = - 10 V, ID = - 6.5 A 25 38
nC
VDS = - 10 V, VGS = - 4.5 V, ID = - 6.5 A
12.5 19
Gate-Source Charge Qgs 2
Gate-Drain Charge Qgd 4
Gate Resistance Rgf = 1 MHz 0.9 4.6 9.2 Ω
Tur n - O n D e l ay Time td(on)
VDD = - 10 V, RL = 1.9 Ω
ID ≅ - 5.2 A, VGEN = - 4.5 V, Rg = 1 Ω
25 50
ns
Rise Time tr20 40
Turn-Off Delay Time td(off) 30 60
Fall Time tf12 25
Tur n - O n D e l ay Time td(on)
VDD = - 10 V, RL = - 1.9 Ω
ID ≅ - 5.2 A, VGEN = - 10 V, Rg = 1 Ω
10 20
Rise Time tr10 20
Turn-Off Delay Time td(off) 27 55
Fall Time tf12 25
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISTC = 25 °C - 6 A
Pulse Diode Forward Current ISM - 20
Body Diode Voltage VSD IS = - 5.2 A, VGS = 0 V - 0.8 - 1.2 V
Body Diode Reverse Recovery Time trr
IF = - 5.2 A, dI/dt = 100 A/µs, TJ = 25 °C
20 40 ns
Body Diode Reverse Recovery Charge Qrr 10 20 nC
Reverse Recovery Fall Time ta10 ns
Reverse Recovery Rise Time tb10
Document Number: 67013
S10-2011-Rev. A, 06-Sep-10
www.vishay.com
3
Vishay Siliconix
Si5457DC
New Product
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On Resistance vs. Drain Current
Gate Charge
0
4
8
12
16
20
0 0.5 1.0 1.5 2.0 2.5 3.0
VGS =5Vthru3V
VGS =2.5V
VGS =1.5V
VGS =2V
VDS - Drain-to-Source Voltage (V)
ID - Drain Current (A)
0
0.02
0.04
0.06
0.08
048121620
VGS =2.5V
VGS =3.6V
VGS =4.5V
RDS(on) - On-Resistance (Ω)
ID - Drain Current (A)
0
2
4
6
8
10
0 5 10 15 20 25 30
ID=6.5A
VDS =10V
VDS =16V
VDS =5V
Qg - Total Gate Charge (nC)
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
TC=-55 °C
0
1
2
3
4
5
0 0.5 1.0 1.5 2.0
TC= 125 °C
TC= 25 °C
VGS - Gate-to-Source Voltage (V)
ID - Drain Current (A)
0
300
600
900
1200
1500
1800
036912
Ciss
Coss
Crss
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
VGS =4.5V;3.6V;I
D=4.9A
VGS =2.5V;I
D=2A
TJ - Junction Temperature (°C)
(Normalized)
RDS(on) - On-Resistance
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Document Number: 67013
S10-2011-Rev. A, 06-Sep-10
Vishay Siliconix
Si5457DC
New Product
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Forward Diode Voltage vs. Temperature
Threshold Voltage
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1.0 1.2
TJ= 25 °C
TJ= 150 °C
VSD - Source-to-Drain Voltage (V)
IS - Source Current (A)
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
- 50 - 25 0 25 50 75 100 125 150
ID= 250 μA
VGS(th) (V)
TJ - Temperature (°C)
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power
0
0.02
0.04
0.06
0.08
0.10
0.12
012345
ID=4.9A
TJ=25 °C
TJ= 125 °C
RDS(on) - On-Resistance (Ω)
VGS - Gate-to-Source Voltage (V)
0
30
50
10
20
Power (W)
Time (s)
40
1 100 6001010-1
10-2
10-3
Safe Operating Area, Junction-to-Ambient
100
1
0.1 1 10 100
0.01
10
0.1
TA=25 °C
Single Pulse
1s
10 s
Limited by RDS(on)*
BVDSS Limited
1ms
10 ms
DC
100 ms
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specied
ID - Drain Current (A)
Document Number: 67013
S10-2011-Rev. A, 06-Sep-10
www.vishay.com
5
Vishay Siliconix
Si5457DC
New Product
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Current Derating*
0
3
6
9
12
0 25 50 75 100 125 150
Package Limited
TC - Case Temperature (°C)
ID - Drain Current (A)
Power Derating
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Document Number: 67013
S10-2011-Rev. A, 06-Sep-10
Vishay Siliconix
Si5457DC
New Product
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?67013.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 1 10 60010-1
10-4 100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 95 °C/W
3. T JM - T
A = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
Normalized Thermal Transient Impedance, Junction-to-Foot
10-3 10-2 11010-1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
Package Information
Vishay Siliconix
Document Number: 71151
15-Jan-04
www.vishay.com
1
1206-8 ChipFETR
c
EE1
e
D
A
6578
3421
4
L
5678
4321
4
S b
2X 0.10/0.13 R
Backside View
x
NOTES:
1. All dimensions are in millimeaters.
2. Mold gate burrs shall not exceed 0.13 mm per side.
3. Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4. Dimensions exclusive of mold gate burrs.
5. No mold flash allowed on the top and bottom lead surface.
DETAIL X
C1
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A1.00 −1.10 0.039 −0.043
b0.25 0.30 0.35 0.010 0.012 0.014
c0.1 0.15 0.20 0.004 0.006 0.008
c1 0−0.038 0 −0.0015
D2.95 3.05 3.10 0.116 0.120 0.122
E1.825 1.90 1.975 0.072 0.075 0.078
E11.55 1.65 1.70 0.061 0.065 0.067
e0.65 BSC 0.0256 BSC
L0.28 −0.42 0.011 −0.017
S0.55 BSC 0.022 BSC
5_Nom 5_Nom
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
AN811
Vishay Siliconix
Document Number: 71126
12-Dec-03
www.vishay.com
1
Single-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
This technical note discusses the single-channel ChipFET
1206-8 pin-out, package outline, pad patterns, evaluation
board layout, and thermal performance.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the single-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thermal performance.
The legs of the device are very short, again helping to reduce
the thermal path to the external heatsink/pcb and allowing a
larger die to be fitted in the device if necessary.
Single 1206-8 ChipFET
D
D
D
G
D
D
D
S
1
Bottom View
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
FIGURE 2. Footprint With Copper Spreading
80 mil
68 mil
28 mil
26 mil
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins
1,2,3,6.7,8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0054 sq. in. or
3.51 sq. mm). This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the single device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the
Vishay Siliconix Evaluation Board described in the next
section (Figure 3).
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE SINGLE 1206-8
The ChipFET 1206-08 evaluation board measures 0.6 in by
0.5 in. Its copper pad pattern consists of an increased pad area
around the six drain leads on the top-side—approximately
0.0482 sq. in. 31.1 sq. mm—and vias added through to the
underside of the board, again with a maximized copper pad
area of approximately the board-size dimensions. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
AN811
Vishay Siliconix
www.vishay.com
2
Document Number: 71126
12-Dec-03
Front of Board
FIGURE 3.
Back of Board
vishay.com
ChipFETr
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 15_C/W typical, 20_C/W
maximum for the single device. The “foot” is the drain lead of
the device as it connects with the body. This is identical to the
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
The typical RQja for the single-channel 1206-8 ChipFET is
80_C/W steady state, compared with 68_C/W for the SO-8.
Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W
for the SO-8.
Testing
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
thermal performance on two different board sizes and three
different pad patterns. The results display the thermal
performance out to steady state and produce a graphic
account of how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the single 1206-8
ChipFET are :
1) Minimum recommended pad pattern (see
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
156_C/W
2) The evaluation board with the pad pattern
described on Figure 3.
111_C/W
3) Industry standard 1” square pcb with
maximum copper both sides.
78_C/W
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 45_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 33_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
pcb.
Time (Secs)
FIGURE 4. Single 1206−8 ChipFET
Thermal Resistance (C/W)
0
1
160
40
80
100 1000
120
1010-1
10-2
10-3
10-4
10-5
1” Square PCB
Single EVB
Min. Footprint
SUMMARY
The thermal results for the single-channel 1206-8 ChipFET
package display similar power dissipation performance to the
SO-8 with a footprint reduction of 80%. Careful design of the
package has allowed for this performance to be achieved. The
short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
ASSOCIATED DOCUMENT
1206-8 ChipFET Dual Thermal performance, AN812
(http://www.vishay.com/doc?71127).
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72593
2Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.080
(2.032)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.093
(2.357)
0.036
(0.914)
0.022
(0.559)
0.026
(0.650)
0.016
(0.406)
0.010
(0.244)
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Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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