1
DSC-2748/9
JULY 2003
IDT72413
CMOS PARALLEL FIFO WITH FLAGS 64 x 5
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERCIAL TEMPERATURE RANGE
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
FEATURES:
• First-ln/First-Out Dual-Port memory—45MHz
• 64 x 5 organization
• Low-power consumption
— Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth
• Half-Full and Almost-Full/Empty status flags
• High-speed data communications applications
• Bidirectional and rate buffer applications
• High-performance CMOS technology
• Available in plastic DIP and SOIC
• Industrial temperature range (–40°°
°°
°C to +85°°
°°
°C) is available
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads
and empties data on a first-in-first-out basis. It is expandable in bit width. All speed
versions are cascad-able in depth.
The FIFO has a Half-Full Flag, which signals when it has 32 or more words
in memory. The Almost-Full/Empty Flag is active when there are 56 or more
words in memory or when there are 8 or less words in memory.
This device is pin and functionally compatible to the MMI67413. It operates
at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering
applications. This FIFO can be used as a rate buffer, between two digital systems
of varying data rates, in high-speed tape drivers, hard disk controllers, data
communications controllers anD graphics controllers.
The IDT72413 is fabricated using IDTs high-performance CMOS process.
This process maintains the speed and high output drive capability of TTL circuits
in low-power CMOS.
FUNCTIONAL BLOCK DIAGRAM
2748 drw 01
DATA
IN
(D
0-4
FIFO
INPUT
STAGE
64 x 5
MEMORY
ARRAY
FIFO
OUTPUT
STAGE
INPUT
CONTROL
LOGIC
REGISTER
CONTROL
LOGIC
OUTPUT
CONTROL
LOGIC
FLAG
CONTROL
LOGIC
)
(MR)
MASTER
RESET
INPUT
READY
SHIFT
IN
(IR)
(SI)
DATA
OUT
(Q
0-4
)
SHIFT
OUT
OUPUT
READY
(SO)
(OR)
OUPUT ENABLE
(OE)
HALF-FULL (HF)
ALMOST-FULL/
EMPTY (AF/E)
2
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial Unit
VTERM Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TSTG Storage –55 to +125 °C
Temperature
IOUT DC Output –50 to +50 mA
Current
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
Commercial
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V
VIL(1) Input Low Voltage — — 0.8 V
TAOperating Temperature 0 — 70 ° C
Commercial
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 5 pF
COUT Output Capacitance VOUT = 0V 7 pF
NOTE: 2748 tbl 02
1. Characterized values, not currently tested.
PLASTIC DIP (P20-1, ORDER CODE: P)
SOIC (SO20-2, ORDER CODE: SO)
TOP VIEW
5
6
7
8
9
10
HF
IR
SI
1
2
3
4
20
19
18
17
16
15
14
13
Vcc
12
11
OE
SO
D
0
D
1
D
2
D
3
AF/E
OR
Q
0
Q
1
Q
2
Q
3
D
4
GND
Q
4
MR
2748 drw 02
IDT72413
Commercial
fIN = 45, 35, 25 MHz
Symbol Parameter Test Conditions Min. Max. Unit
IIL Low-Level Input Current VCC = Max., GND ≤ VI ≤ VCC –10 — µ A
IIH High-Level Input Current VCC = Max., GND ≤ VI ≤ VCC — 10µA
VOL Low-Level Output Current VCC = Min. IOL (Q0-4) 24 mA — 0.4 V
IOL (IR, OR)(1) 8mA
IOL (HF, AF/E) 8mA
VOH High-Level Output Current VCC = Min. IOH (Q0-4) –4mA 2.4 — V
IOH (IR, OR) –4mA
IOH (HF, AF/E) –4mA
IOS(2) Output Short-Circuit Current VCC = Max. VO = 0V –20 –110 mA
IHZ HIGH Impedance Output Current VCC = Max. VO = 2.4V — 20 µA
ILZ LOW Impedance Output Current VCC = Max. VO = 0.4V –20 — µA
ICC(3,4) Active Supply Current VCC = Max., OE = HIGH — 60 mA
Inputs LOW, f = 25MHz
NOTES:
1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25MHz.
2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested.
3. Tested with outputs open (IOUT = 0).
4. For frequencies greater than 25MHz, ICC = 60mA + (1.5mA x [f –25MHz]) commercial.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C t o +70°C)
3
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
OPERATING CONDITIONS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C t o +70°C) Commercial
IDT72413L45 IDT72413L35 IDT72413L25
Symbol Parameter Figure Min. Max. Min. Max. Min. Max. Unit
tSIH(1) Shift in HIGH Time 2 9 — 9 — 16 — ns
tSIL(1) Shift in LOW TIme 2 1 1 — 1 7 — 2 0 — ns
tIDS Input Data Set-up 2 0 — 0 — 0 — ns
tIDH Input Data Hold Time 2 13 — 15 — 25 — ns
tSOH(1) Shift Out HIGH Time 5 9 — 9 — 16 — ns
tSOL Shift Out LOW Time 5 11 — 17 — 20 — ns
tMRW Master Reset Pulse 8 20 — 30 — 35 — ns
tMRS Master Reset Pulse to SI 8 20 — 35 — 35 — ns
NOTE:
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling
are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.
A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C t o +70°C) Commercial
IDT72413L45 IDT72413L35 IDT72413L25
Symbol Parameter Figure Min. Max. Min. Max. Min. Max. Unit
fIN Shift In Rate 2 — 45 — 35 — 25 MHz
tIRL(1) Shift In ↑ to Input Ready LOW 2 — 18 — 18 — 28 ns
tIRH(1) Shift In ↓ to Input Ready HIGH 2 — 18 — 20 — 25 ns
fOUT Shift Out Rate 5 — 45 — 35 — 25 MHz
tORL(1) Shift Out ↓ to Output Ready LOW 5 — 18 — 18 — 28 ns
tORH(1) Shift Out ↓ to Output Ready HIGH 5 — 19 — 20 — 25 ns
tODH(1) Output Data Hold Previous Word 5 5 — 5 — 5 — ns
tODS Output Data Shift Next Word 5 — 19 — 20 — 20 ns
tPT Data Throughput or "Fall-Through" 4, 7 — 25 — 28 — 40 ns
tMRORL Master Reset ↓ to Output Ready LOW 8 — 25 — 28 — 30 ns
tMRIRH(3) Master Reset ↑ to Input Ready HIGH 8 — 25 — 28 — 30 ns
tMRIRL(2) Master Reset ↓ to Input Ready LOW 8 — 25 — 28 — 30 ns
tMRQ Master Reset ↓ to Outputs LOW 8 — 20 — 25 — 35 ns
tMRHF Master Reset ↓ to Half-Full Flag 8 — 25 — 28 — 40 ns
tMRAFE Master Reset ↓ to AF/E Flag 8 — 25 — 28 — 40 ns
tIPH(3) Input Ready Pulse HIGH 4 5 — 5 — 5 — ns
tOPH(3) Output Ready Pulse HIGH 7 5 — 5 — 5 — ns
tORD(3) Output Ready ↑ HIGH to Valid Data 5 — 5 — 5 — 7 ns
tAEH Shift Out ↑ to AF/E HIGH 9 — 28 — 28 — 40 ns
tAEL Shift In ↑ to AF/E 9 — 28 — 28 — 40 ns
tAFL Shift Out ↑ to AF/E LOW 10 — 28 — 28 — 40 ns
tAFH Shift In ↑ to AF/E HIGH 10 — 28 — 28 — 40 n s
tHFH Shift In ↑ to HF HIGH 11 — 28 — 28 — 40 n s
tHFL Shift Out ↑ to HF LOW 11 — 28 — 28 — 40 ns
tPHZ(3) Output Disable Delay 12 — 12 — 12 — 15 ns
tPLZ(3) 12 — 12 — 12 — 15
tPLZ(3) Output Enable Delay 12 — 15 — 15 — 20 ns
tPHZ(3) 12 — 15 — 15 — 20
NOTES:
1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling
are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.
A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
2 . If the FIFO is full, (IR = HIGH), MR ↑ forces IR to go LOW, and MR ↓ causes IR to go HIGH.
3. Guaranteed by design but not currently tested.
4
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
Figure 1. Output Load
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
2748 tbl 07
or equivalent circuit
*Including scope and jig
RESISTOR VALUES FOR
STANDARD TEST LOAD
IOL R1 R2
24mA 200Ω300Ω
12mA 390Ω760Ω
8mA 600Ω1200Ω
FUNCTIONAL DESCRIPTION:
The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture
as opposed to the traditional shift register approach. This FIFO architecture has
a write pointer, a read pointer and control logic, which allow simultaneous read
and write operations. The write pointer is incremented by the falling edge of the
Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift
Out (SO). The Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is valid data on the
output. Output Enable (OE) provides the capability of three-stating the FIFO
outputs.
FIFO RESET
The FIFO must be reset upon power up using the Master Reset (MR) signal.
This causes the FIFO to enter an empty state signified by Output Ready (OR)
being LOW and Input Ready (IR) being HIGH. In this state, the data outputs
(Q0-4) will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads
input data into the first word location of the FIFO and causes the lnput Ready
(IR) to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved
to the next word position and lR goes HlGH indicating the readiness to accept
new data. If the FIFO is full, IR will remain LOW until a word of data is shifted
out.
DATA OUTPUT
Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes
the internal read pointer to be advanced to the next word location. If data is
present, valid data will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The
last valid word read from the FIFO will remain at the FlFOs output when it is empty.
When the FIFO is not empty OR goes LOW on the LOW-to-HlGH transition of
SO.
FALL-THROUGH MODE
The FIFO operates in a Fall-Through Mode when data gets shifted into an
empty FIFO. After the fall-through delay the data propagates to the output. When
the data reaches the output, the Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is completely full. When
data is shifted out of the full FIFO a location is available for new data. After a fall-
through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data
can be written to the FIFO. The fall-through delay of a RAM-based FIFO (one
clock cycle) is far less than the delay of a Shift register-based FIFO.
SIGNAL DESCRIPTIONS:
INPUTS:
DATA INPUT (D0-4)
Data input lines. The IDT72413 has a 5-bit data input.
R1
30pF*
R2
5V
TEST POINT
2748 drw 03
2K‰
30pF*
5V
OUTPUT
STANDARD TEST LOAD DESIGN TEST LOAD
5
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2 . Input Data is loaded into the FIFO.
3. IR goes LOW indicating the FIFO is unavailable for new data.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full, then IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
Figure 3. The Machanism of Shifting Data Into the FIFO
Figure 2. Input Timing
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When SI is HIGH, data
can be written to the FIFO via the D0-4 lines. The data has to meet set-up and
hold time requirements with respect to the rising edge of SI.
SHIFT OUT (SO)
Shift Out controls the outputs data from the FIFO.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within. Upon power up, the
FIFO should be cleared with a Master Reset. Master Reset is active LOW.
HALF-FULL FLAG (HF)
Half-Full Flag signals when the FIFO has 32 or more words in it.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input data to be written
to it. When IR is LOW, the FIFO is unavailable for new input data, IR is also
used to cascade many FIFOs together, as shown in Figure 13.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q0-4) contains valid data. When
OR is LOW, the FIFO is unavailable for new output data. OR is also used to
cascade many FIFOs together, as shown in Figure 13.
OUTPUT ENABLE (OE)
Output Enable is used to enable the FIFO outputs onto a bus. OE is active
LOW.
ALMOST-FULL/EMPTY FLAG (AF/E)
Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words)
or 1/8 from empty (8 or less words).
OUTPUTS:
DATA OUTPUT (Q0-4)
Data output lines, three-state. The IDT72413 has a 5-bit output.
SI
IR
INPUT DATA
tIRL
2748 drw 04
1/fIN 1/fIN
tSIH tSIL
tIRH
tIDH
tIDS
SI
IR
INPUT DATA STABLE DATA
(2)
(3) (5)
2748 drw 05
(6)
(4)
(1)
(7)
6
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
Figure 6. The Mechanism of Shifting Data Out of the FIFO
NOTES:
1. OR HIGH indicates that data is available and a SO pulse may be applied.
2. SO goes HIGH causing the next step.
3. OR goes LOW.
4. Read pointer is incremented.
5. OR goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns.
6. If the FIFO has only one word loaded (A DATA) , OR stays LOW and the A-DATA remains unchanged at the outputs.
7. SO pulses applied when OR is LOW will be ignored.
NOTES:
1. FIFO is initially full.
2. SO pulse is applied.
3 . SI is held HIGH.
4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.
5 . The write pointer is incremented. SI should not go LOW until (tPT + tIPH).
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
NOTES:
1. This data is loaded consecutively A, B, C.
2. Output data changes on the falling edge of SO after a valid SO sequence, i.e., OR and SO are both HIGH together.
Figure 5. Output TIming
STABLE DATA
SO
SI
IR
INPUT DATA
(2)
(3)
(1)
tIPH
tPT
(4)
(5)
2748 drw 06
SO
OR
OUTPUT DATA
tORL
2748 drw 07
1/fOUT 1/fOUT
tSOH tSOL
tRH
tODH
tORD
C-DATAB-DATA
A-DATA
tODS
(2)
(1)
SO
OR
OUTPUT DATA A- DATA
(2)
(3) (5)
2748 drw 08
(6)
(4)
(1)
(7)
AorB
B- DATA
7
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. FIFO initailly empty.
Figure 7. tPT and tOPH Specification
NOTE:
1. FIFO contains 9 words (one more than Almost-Empty).
Figure 9. tAEH and tAEL Specifications
NOTE:
1. FIFO is partially full. Figure 8. Master Reset Timing
SI
SO
OR (1)
tOPH
tPT
2748 drw 09
MR
IR
OR
tMRW
2748 drw 10
SI
DATA OUTPUTS
HF
AF/E
tMRIRL
tMRORL
tMRIRH
tMRS
tMRQ
tMRHF
tMRAFE
(1)
(1)
SO
AF/E
SI
(1)
tAEL
2748 drw 11
tSOH
tAEH
tSIH
8
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
NOTES:
1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
2. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
Figure 12. Enable and Disable
NOTE:
1. FIFO contains 55 words (one short of Almost-Full).
Figure 10. tAFH and tAFL Specifications
SI
HF
SO
(1)
tHFL
2748 drw 13
tSIH
tHFH
tSOH
NOTE:
1. FIFO contains 31 words (one short of Half-Full).
Figure 11. tHFL and tHFH Specifications
SI
HF
SO
(1)
tHFL
2748 drw 13
tSIH
tHFH
tSOH
2748 drw 14
OE
WAVEFORM 2
WAVEFORM 1
(1)
t
PZL
(2)
V
T
V
T
3V
0V
t
PZH
V
T
V
T
4.5V
0V
t
PLZ
t
PHZ
0.5V
0.5V
1.5V
V
OL
V
OH
1.5V
9
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.
Figure 14. Application for IDT72413 for Two Asynchronous Systems
NOTE:
1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement
is due to the different fall-through times of the FIFOs.
Figure 13. 64 x 15 FIFO with IDT72413
2748 drw 15
D
0
D
1
D
2
D
3
IR
SI
Q
0
Q
1
Q
2
Q
3
SO
OR
MR
COMPOSITE
OUTPUT
READY
SHIFT IN
COMPOSITE
INPUT
READY
HF AF/E
OE
D
4
Q
4
D
0
D
1
D
2
D
3
IR
SI
Q
0
Q
1
Q
2
Q
3
SO
OR
MR
HF AF/E
OE
D
4
Q
4
D
0
D
1
D
2
D
3
IR
SI
Q
0
Q
1
Q
2
Q
3
SO
OR
MR
HF AF/E
OE
D
4
Q
4
OUTPUT
ENABLE
MASTER
RESET
SHIFT OUT
2748 drw 16
SYSTEM 1
ENBL SI
TWO
IDT72413
64 x 8
OR
SO
IR
SI
8-BITS 8-BITS
SYSTEM 2
IO RDY
ALMOST-FULL/
EMPTY
HALF-FULL FLAG
INTERRUPTINTERRUPT
10
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.
Figure 15. 128 x 5 Depth Expansion
ORDERING INFORMATION
Plastic DIP (300 mil, P20-1)
Small Outline IC (300 mil, J-bend, SOIC SO20-2)
Commercial (0°C to +70°C)
Low Power
2748 drw18
Commercial
IDT XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
72413 64 x 5 - FIFO
Shift Frequency (f
S
)
Speed in MHz
P
SO
45
35
25
L
NOTE:
1. Industrial temperature range is available by special order.
D
0
D1
D
2
D3
IR
SI
Q
0
Q
1
Q
2
Q
3
SO
OR
D
0
D1
D
2
D3
IR
SI
Q
0
Q
1
Q
2
Q
3
SO
OR
MR
SHIFT IN
INPUT READY
DATA IN
MR
D4Q
4D4Q
4MR
2748 drw 17
OUTPUT READ
Y
SHIFT OUT
DATA OUT
DATASHEET DOCUMENT HISTORY
07/10/2003 pgs. 1, 2, 3, and 10.
