M25P32-VMP6G/4 - Micron Technology, Inc.

November 2008 Rev 11 1/54

M25P32

32-Mbit, low voltage, serial Flash memory

with 75 MHz SPI bus interface

Features

32 Mbit of Flash memory

2.7 V to 3.6 V single supply voltage

SPI bus compatible serial interface

75 MHz clock rate (maximum)

VPP = 9 V for Fast Program/Erase mode

(optional)

Page Program (up to 256 bytes)

– in 0.64 ms (typical)

Sector Erase (512 Kbit) in 0.6 s (typical)

Bulk Erase:

– in 23 s (typical)

– in 17 s (typical with VPP = 9 V)

Deep Power-down mode 1 μA (typical)

Electronic Signatures

– JEDEC standard two-byte signature

(2016h)

– Unique ID code (UID) +16 bytes of CFI

data

– RES instruction, one-byte, signature (15h),

for backward compatibility

Hardware Write Protection of the memory area

selected using the BP0, BP1 and BP2 bits

More than 100 000 Erase/Program cycles per

sector

More than 20 year data retention

Packages

– RoHS compliant

Automotive certified parts available

VDFPN8 (ME)

8 × 6 mm (MLP8)

VFQFPN8 (MP)

6 × 5 mm

SO16 (MF)

SO8W (MW)

208 mils

300 mils width

www.Numonyx.com

Contents M25P32
2/54   
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . .  . . . . .  . . .  . . . . . . . . .  . . . . . . . . . . . . . . . . . 9
1 Serial data output (Q)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
2 Serial data input (D)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
3 Serial Clock (C)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
4 Chip Select (S)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
6 Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . .  10
7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
SPI modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1 Page Programming   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
2 Sector Erase and Bulk Erase  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
3 Polling during a Write, Program or Erase cycle  . . . . . . . . . . . . . . . . . . . .  13
4 Fast Program/Erase mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
5 Active Power, Standby Power and Deep Power-down modes  . . . . . . . . .  13
6 Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
7 Protection modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
8 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
Me mory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1 Write Enable (WREN)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
2 Write Disable (WRDI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
3 Read Identification (RDID)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
4 Read Status Register (RDSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
4.1 WIP bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

M25P32 Contents
 3/54
4.2 WEL bit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 BP2, BP1, BP0 bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 SRWD bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Write Status Register (WRSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . .  29
8 Page Program (PP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
9 Sector Erase (SE)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32
10 Bulk Erase (BE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
11 Deep Power-down (DP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
12 Release from Deep Power-down and Read Electronic Signature (RES) .  35
Power-up and Power-down  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Initial delivery st ate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Ma ximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Part numbering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of tables M25P32
4/54   
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Memory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 6. Status Register format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Protection modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Data Retention and Endurance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15. AC characteristics (T9HX technology)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 17. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, mechanical data. . . . . . 47
Table 18. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. SO8W 8 lead Plastic Small Outline, 208 mils body width, package
 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 21. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

M25P32 List of figures
 5/54
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SO connections  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bus Master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence  . . . . . . . . . . . . . 23
Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence  . . . . . . . . . . 25
Figure 12. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 28
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Page Program (PP) instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. Bulk Erase (BE) instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. Release from Deep Power-down and Read Electronic Signature (RES)
instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 24. Write Protect Setup and Hold timing during WRSR when SRWD=1  . . . . . . . . . . . . . . . . . 44
Figure 25. Hold timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. Output timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 27. VPPH timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 28. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, package outline . . . . . . 47
Figure 30. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 31. SO8W 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . . . . . 49

Description M25P32

6/54

1 Description

The M25P32 is a 32 Mbit (4M x 8) Serial Flash memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program

instruction.

An enhanced Fast Program/Erase mode is available to speed up operations in factory

environment. The device enters this mode whenever the VPPH voltage is applied to the Write

Protect/Enhanced Program Supply Voltage pin (W/VPP).

The memory is organized as 64 sectors, each containing 256 pages. Each page is 256

bytes wide. Thus, the whole memory can be viewed as consisting of 16384 pages, or

4,194,304 bytes.

The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,

using the Sector Erase instruction.

In order to meet environmental requirements, Numonyx offers the M25P32 in Lead-free and

RoHS compliant packages.

M25P32 Description

7/54

Figure 1. Logic diagram

Figure 2. VDFPN conne ctions

1. There is an exposed central pad on the underside of the MLP8 package. This is pulled, internally, to VSS,

and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Package mechanical section for package dimensions, and how to identify pin-1.

Table 1. S ignal names

Signal name Function Direction

C Serial Clock Input

D Serial Data input Input

Q Serial Data output Output

SChip Select Input

W/VPP Write Protect/Enhanced Program supply voltage Input

HOLD Hold Input

VCC Supply voltage Input

VSS Ground

AI07483b

VCC

M25P32

HOLD

VSS

W/VPP

AI08518b

5DVSS C

HOLDQ

M25P32

W/VPP

Description M25P32

8/54

Figure 3. SO connection s

1. DU = Don’t Use

2. See Package mechanical section for package dimensions, and how to identify pin-1.

AI07484c

DU DU

VCC

HOLD

DUDU

M25P32

QVSS

W/VPP

M25P32 Signal description

9/54

2 Signal description

2.1 Serial data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,

the device will be in the Standby Power mode (this is not the Deep Power-down mode).

Driving Chip Select (S) Low enables the device, placing it in the Active Power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

Signal description M25P32

10/54

2.6 Write Protect/Enhanced Program supply voltage (W/VPP)

W/VPP is both a control input and a power supply pin. The two functions are selected by the

voltage range applied to the pin.

If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control

input. This input signal is used to freeze the size of the area of memory that is protected

against program or erase instructions (as specified by the values in the BP2, BP1 and BP0

bits of the Status Register).

If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must

be stable until the Program/Erase algorithm is completed.

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

M25P32 SPI modes

11/54

3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

CPOL=0, CPHA=0

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 5, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. Bus Master and memory device s on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only

one device is selected at a time, so only one device drives the Serial Data Output (Q) line at

a time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure

that the M25P32 is not selected if the Bus Master leaves the S line in the high impedance

state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at

the same time (for example, when the Bus Master is reset), the clock line (C) must be

connected to an external pull-down resistor so that, when all inputs/outputs become high

impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and

C do not become High at the same time, and so, that the tSHCH requirement is met). The

typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic

capacitance of the bus line) is shorter than the time during which the Bus Master leaves the

SPI bus in high impedance.

AI12836b

SPI Bus Master

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

RR R

VCC VCC VCC

VSS VSS VSS

SPI modes M25P32

12/54

Example: Cp = 50 pF, that is R*Cp = 5 μs <=> the application must ensure that the Bus

Master never leaves the SPI bus in the high impedance state for a time period shorter than

5μs.

Figure 5. SPI modes supported

AI01438B

MSB

CPHA

CPOL

MSB

M25P32 Op erati n g fe atures

13/54

4 Operating features

4.1 Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is

one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This

is followed by the internal Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few bytes (see Page Program (PP)).

4.2 Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be

achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the

entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of

duration tSE or tBE).

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

4.3 Polling during a Write, Program or Erase cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase

(SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP

, tSE, or tBE). The

Write In Progress (WIP) bit is provided in the Status Register so that the application program

can monitor its value, polling it to establish when the previous Write cycle, Program cycle or

Erase cycle is complete.

4.4 Fast Program/Erase mode

The Fast Program/Erase mode is used to speed up programming/erasing. The device

enters the Fast Program/Erase mode during the Page Program, Sector Erase or Bulk Erase

instruction whenever a voltage equal to VPPH is applied to the W/VPP pin.

The use of the Fast Program/Erase mode requires specific operating conditions in addition

to the normal ones (VCC must be within the normal operating range):

the voltage applied to the W/VPP pin must be equal to VPPH (see Table 1 0 )

ambient temperature, TA must be 25 °C ±10 °C,

the cumulated time during which W/VPP is at VPPH should be less than 80 hours

4.5 Active Power, Standby Power and Deep Power-dow n modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode.

Ope rating features M25P32

14/54

When Chip Select (S) is High, the device is deselected, but could remain in the Active

Power mode until all internal cycles have completed (Program, Erase, Write Status

drops to ICC1.

The Deep Power-down mode is entered when the specific instruction (the Deep Power-

down (DP) instruction) is executed. The device consumption drops further to ICC2. The

device remains in this mode until another specific instruction (the Release from Deep

Power-down and Read Electronic Signature (RES) instruction) is executed.

While in the Deep Power-down mode, the device ignores all Write, Program and Erase

instructions (see Deep Power-down (DP)) This can be used as an extra software protection

mechanism, when the device is not in active use, to protect the device from inadvertent

Write, Program or Erase instructions.

4.6 Status Register

The Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a

detailed description of the Status Register bits.

4.7 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M25P32 features the following data protection mechanisms:

Power On Reset and an internal timer (tPUW) can provide protection against

inadvertent changes while the power supply is outside the operating specification.

Program, Erase and Write Status Register instructions are checked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for

execution.

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

– Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Page Program (PP) instruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completion

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as

read-only. This is the Software Protected Mode (SPM).

The Write Protect (W/VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and

Status Register Write Disable (SRWD) bit to be protected. This is the Hardware

Protected Mode (HPM).

In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection, as all Write, Program and Erase instructions are ignored.

M25P32 Op erati n g fe atures

15/54

4.8 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence. However, taking this signal Low does not terminate any

Write Status Register, Program or Erase cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (S) Low.

The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low (as shown in Figure 6).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes

Low. (This is shown in Figure 6).

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration

of the Hold condition. This is to ensure that the state of the internal logic remains unchanged

from the moment of entering the Hold condition.

If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the Hold condition.

Table 2. Pr otected area sizes

Status Register

content Memory content

BP2

bit BP1

bit BP0

bit Protected area Unprotected area

0 0 0 none All sectors(1) (64 sectors: 0 to 63)

1. The device is ready to accept a Bulk Erase instruction only if, all Block Protect (BP2, BP1, BP0) are 0.

0 0 1 Upper 64th (Sector 63) Lower 63/64ths (63 sectors: 0 to 62)

0 1 0 Upper 32nd (two sectors: 62 and 63) Lower 31/32nds (62 sectors: 0 to 61)

0 1 1

Upper sixteenth (four sectors: 60 to

63) Lower 15/16ths (60 sectors: 0 to 59)

1 0 0 Upper eighth (eight sectors: 56 to 63) Lower seven-eighths (56 sectors: 0 to 55)

1 0 1

Upper quarter (sixteen sectors: 48 to

63) Lower three-quarters (48 sectors: 0 to 47)

1 1 0

Upper half (thirty-two sectors: 32 to

63) Lower half (32 sectors: 0 to 31)

1 1 1 All sectors (64 sectors: 0 to 63) none

Ope rating features M25P32

16/54

Figure 6. Hold co nditi on activation

AI02029D

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

M25P32 Memory orga niza tion

17/54

5 Memory organization

The memory is organized as:

4,194,304 bytes (8 bits each)

64 sectors (512 Kbits, 65536 bytes each)

16384 pages (256 bytes each).

Each page can be individually programmed (bits are programmed from 1 to 0). The device is

Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.

Figure 7. Block di agra m

AI08519b

HOLD

W/V

Control Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Size of the

read-only

memory are

Status

00000h

3FFFFFh

000FFh

Memory organization M25P32

18/54

Table 3. Memory organization

Sector Address range

63 3F0000h 3FFFFFh

62 3E0000h 3EFFFFh

61 3D0000h 3DFFFFh

60 3C0000h 3CFFFFh

59 3B0000h 3BFFFFh

58 3A0000h 3AFFFFh

57 390000h 39FFFFh

56 380000h 38FFFFh

55 370000h 37FFFFh

54 360000h 36FFFFh

53 350000h 35FFFFh

52 340000h 34FFFFh

51 330000h 33FFFFh

50 320000h 32FFFFh

49 310000h 31FFFFh

48 300000h 30FFFFh

47 2F0000h 2FFFFFh

46 2E0000h 2EFFFFh

45 2D0000h 2DFFFFh

44 2C0000h 2CFFFFh

43 2B0000h 2BFFFFh

42 2A0000h 2AFFFFh

41 290000h 29FFFFh

40 280000h 28FFFFh

39 270000h 27FFFFh

38 260000h 26FFFFh

37 250000h 25FFFFh

36 240000h 24FFFFh

35 230000h 23FFFFh

34 220000h 22FFFFh

33 210000h 21FFFFh

32 200000h 20FFFFh

31 1F0000h 1FFFFFh

30 1E0000h 1EFFFFh

29 1D0000h 1DFFFFh

M25P32 Memory orga niza tion

19/54

28 1C0000h 1CFFFFh

27 1B0000h 1BFFFFh

26 1A0000h 1AFFFFh

25 190000h 19FFFFh

24 180000h 18FFFFh

23 170000h 17FFFFh

22 160000h 16FFFFh

21 150000h 15FFFFh

20 140000h 14FFFFh

19 130000h 13FFFFh

18 120000h 12FFFFh

17 110000h 11FFFFh

16 100000h 10FFFFh

15 0F0000h 0FFFFFh

14 0E0000h 0EFFFFh

13 0D0000h 0DFFFFh

12 0C0000h 0CFFFFh

11 0B0000h 0BFFFFh

10 0A0000h 0AFFFFh

9 090000h 09FFFFh

8 080000h 08FFFFh

7 070000h 07FFFFh

6 060000h 06FFFFh

5 050000h 05FFFFh

4 040000h 04FFFFh

3 030000h 03FFFFh

2 020000h 02FFFFh

1 010000h 01FFFFh

0 000000h 00FFFFh

Table 3. Memory organization (continued)

Sector Address range

Instructions M25P32

20/54

6 Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most

significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Ta bl e 4 .

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),

Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-

down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence

is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the

data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status

instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the

instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when

the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of

eight.

All attempts to access the memory array during a Write Status Register cycle, Program

cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program

cycle or Erase cycle continues unaffected.

M25P32 Instructions

21/54

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector

Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figu r e 8. Write Enable (WREN) inst ruction seq uence

Table 4. Instruction set

Instruction Description One-by te instruction

code Address

bytes Dummy

bytes Data

bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID Read Identification 1001 1111 9Fh 0 0 1 to 20

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

READ Read Data bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data bytes at higher

speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RES

Release from Deep Power-

down, and Read Electronic

Signature 1010 1011 ABh

0 3 1 to ∞

Release from Deep Power-

down 0 0 0

AI02281E

21 34567

High Impedance

Instruction

Instructions M25P32

22/54

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Page Program (PP) instruction completion

Sector Erase (SE) instruction completion

Bulk Erase (BE) instruction completion

Fig u re 9. Wr it e Disable (WRD I) instruction se q u ence

AI03750D

21 34567

High Impedance

Instruction

M25P32 Instructions

23/54

6.3 Read Identification (RDID)

The Read Identification (RDID) instruction allows to read the device identification data:

Manufacturer identification (one byte)

Device identification (two bytes)

A Unique ID code (UID) followed by 16 bytes of CFI data

The manufacturer identification is assigned by JEDEC, and has the value 20h for

STMicroelectronics. The device identification is assigned by the device manufacturer, and

indicates the memory type in the first byte (20h), and the memory capacity of the device in

the second byte (16h). The UID is set to 10h and indicates that 16 bytes, related to the CFI

content, are following.

Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is

not decoded, and has no effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. After this, the 24-bit device identification, stored in the

memory, the 8-bit Unique ID code followed by 16 bytes of CFI content will be shifted out on

Serial Data Output (Q). Each bit is shifted out during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 10.

The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in

the Standby Power mode, the device waits to be selected, so that it can receive, decode and

execute instructions.

Figure 10. Read Identification (R DID) instruction sequence and data-out seque nce

Table 5. Read Identification (RDID) data-out sequence

Man u f act u rer ide n tifi ca t i o n Device identification UID CFI content

Memory type Memory cap acity

20h 20h 16h 10h 16 bytes

213456789101112131415

Instruction

AI06809c

Manufacturer Identification

High Impedance

MSB

Device Identification

MSB

15 14 13 3 2 1 0

16 17 18 28 29 30 31

MSB

UID + CFI Data

Instructions M25P32

24/54

6.4 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write Status

check the Write In Progress (WIP) bit before sending a new instruction to the device. It is

also possible to read the Status Register continuously, as shown in Figure 11.

The status and control bits of the Status Register are as follows:

6.4.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

0 no such cycle is in progress.

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write Status Register, Program or Erase instruction is accepted.

6.4.3 BP2, BP1, BP0 bits

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to

be software protected against Program and Erase instructions. These bits are written with

the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,

BP1, BP0) bits is set to 1, the relevant memory area (as defined in Tab l e 2 ) becomes

protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect

(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not

been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,

BP1, BP0) bits are 0.

Table 6. Status Re g ister format

b7 b0

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

M25P32 Instructions

25/54

6.4.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect

(W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status

this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become

read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

Figure 11. Read Status Regist er (RDSR) instruction sequence and data-out

sequence

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

Instructions M25P32

26/54

6.5 Write Stat us Registe r (WRSR )

The Write Status Register (WRSR) instruction allows new values to be written to the Status

have been executed. After the Write Enable (WREN) instruction has been decoded and

executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 12.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the

Status Register. b6 and b5 are always read as 0.

Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.

If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is

initiated. While the Write Status Register cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)

bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.

When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as

read-only, as defined in Ta bl e 2 . The Write Status Register (WRSR) instruction also allows

the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the

Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write

Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM).

The Write Status Register (WRSR) instruction is not executed once the Hardware Protected

Mode (HPM) is entered.

Figure 12. Wr ite Status Register (W RSR) i nstruct ion seque nce

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

M25P32 Instructions

27/54

The protection features of the device are summarized in Table 7.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect (W/VPP) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W/VPP):

If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has previously been set by a Write

Enable (WREN) instruction.

If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register

even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not

accepted for execution). As a consequence, all the data bytes in the memory area that

are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be

entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect

(W/VPP) Low

or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write

Protect (W/VPP) High.

If Write Protect (W/VPP) is permanently tied High, the Hardware Protected Mode (HPM) can

never be activated, and only the Software Protected Mode (SPM), using the Block Protect

(BP2, BP1, BP0) bits of the Status Register, can be used.

Table 7. Protection m odes

W/VPP

signal SRWD

bit Mode Wri te Protection of the

St atus Register

Memory content

Protected area(1)

1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in

Table 2.

Unprotected area(1)

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the SRWD,

BP2, BP1 and BP0 bits

can be changed

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program and

Sector Erase

instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the SRWD,

BP2, BP1 and BP0 bits

cannot be changed

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program and

Sector Erase

instructions

Instructions M25P32

28/54

6.6 Read Data Bytes (READ )

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum

frequency fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

Fig u re 13. Read D ata Bytes (RE AD) inst ruct ion seque nce and data-out sequence

1. Address bits A23 to A22 are Don’t Care.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

M25P32 Instructions

29/54

6.7 Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each

bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 14.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)

instruction. When the highest address is reached, the address counter rolls over to

000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any

Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.

Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction se quenc e

and data-out sequence

1. Address bits A23 to A22 are Don’t Care.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

Instructions M25P32

30/54

6.8 Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable (WREN) instruction has been

decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, three address bytes and at least one data byte on Serial Data Input (D).

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes

beyond the end of the current page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 data bytes are guaranteed to be programmed correctly within the same page. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few bytes.

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register

may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is

reset.

A Page Program (PP) instruction applied to a page which is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 2 and Ta ble 3 ) is not executed.

M25P32 Instructions

31/54

Figure 15. Page Program (PP) i nst ruct ion sequence

1. Address bits A23 to A22 are Don’t Care.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

Instructions M25P32

32/54

6.9 Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write

Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data Input (D). Any address inside the

Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is

initiated. While the Sector Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 2 and Ta ble 3 ) is not executed.

Fig ur e 16. Sector E rase (SE) instruction sequence

1. Address bits A23 to A22 are Don’t Care.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M25P32 Instructions

33/54

6.10 Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write

Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)

is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the

Bulk Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk

Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits

are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.

Figure 17. Bulk Erase (BE) instruction sequence

AI03752D

21 345670

Instruction

Instructions M25P32

34/54

6.11 Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the Deep Power-down mode). It can also be used as a software

protection mechanism, while the device is not in active use, as in this mode, the device

ignores all Write, Program and Erase instructions.

Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power

mode (if there is no internal cycle currently in progress). But this mode is not the Deep

Power-down mode. The Deep Power-down mode can only be entered by executing the

Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to

ICC2, as specified in Table 14).

To take the device out of Deep Power-down mode, the Release from Deep Power-down and

Read Electronic Signature (RES) instruction must be issued. No other instruction must be

issued while the device is in Deep Power-down mode.

The Release from Deep Power-down and Read Electronic Signature (RES) instruction also

allows the Electronic Signature of the device to be output on Serial Data Output (Q).

The Deep Power-down mode automatically stops at Power-down, and the device always

Powers-up in the Standby Power mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 18.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced

to ICC2 and the Deep Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 18. Deep Power-do wn (DP ) instruction sequen ce

AI03753D

21 345670t

Deep Power-down Mode

Stand-by Mode

Instruction

M25P32 Instructions

35/54

6.12 Release from Deep Power-down and Read Electronic

Signature (RES)

To take the device out of Deep Power-down mode, the Release from Deep Power-down and

Read Electronic Signature (RES) instruction must be issued. No other instruction must be

issued while the device is in Deep Power-down mode.

The instruction can also be used to read, on Serial Data Output (Q), the old-style 8-bit

Electronic Signature, whose value for the M25P32 is 15h.

Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic

Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic

Signature is supported for reasons of backward compatibility, only, and should not be used

for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic

Signature, and the Read Identifier (RDID) instruction.

Except while an Erase, Program or Write Status Register cycle is in progress, the Release

from Deep Power-down and Read Electronic Signature (RES) instruction always provides

access to the old-style 8-bit Electronic Signature of the device, and can be applied even if

the Deep Power-down mode has not been entered.

Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while

an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no

effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. The instruction code is followed

by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge

of Serial Clock (C). Then, the old-style 8-bit Electronic Signature, stored in the memory, is

shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 19.

The Release from Deep Power-down and Read Electronic Signature (RES) instruction is

terminated by driving Chip Select (S) High after the Electronic Signature has been read at

least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is

driven Low, cause the Electronic Signature to be output repeatedly.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the

device was not previously in the Deep Power-down mode, the transition to the Standby

Power mode is immediate. If the device was previously in the Deep Power-down mode,

though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S)

must remain High for at least tRES2(max), as specified in Table 1 4 . Once in the Standby

Power mode, the device waits to be selected, so that it can receive, decode and execute

instructions.

Instructions M25P32

36/54

Figure 19. Release from Deep P ower -down and Read Elect ronic Sign atu re (RES )

instruc tion seq uenc e and data-ou t sequenc e

1. The value of the 8-bit Electronic Signature, for the M25P32, is 15h.

Figure 20. Release from Deep Power-down (RES) instruction sequence

Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before

the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 20),

still ensures that the device is put into Standby Power mode. If the device was not previously in the Deep

Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously

in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES1,

and Chip Select (S) must remain High for at least tRES1(max), as specified in Table 14. Once in the

Standby Power mode, the device waits to be selected, so that it can receive, decode and execute

instructions.

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic Signature Out

Instruction 3 Dummy Bytes

MSB

Stand-by Mod

Deep Power-down Mode

MSB

tRES2

AI04078B

21 345670t

RES1

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

M25P32 Pow er- up and Power-down

37/54

7 Power-up and Power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL

VSS at Power-down

A safe configuration is provided in Section 3: SPI modes.

To avoid data corruption and inadvertent write operations during Power-up, a Power On

Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less

than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and

the device does not respond to any instruction.

Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of

tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the

correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min).

No Write Status Register, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold

tVSL after VCC passed the VCC(min) level

These values are specified in Table 8.

If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be

selected for READ instructions even if the tPUW delay is not yet fully elapsed.

At Power-up, the device is in the following state:

The device is in the Standby mode (not the Deep Power-down mode).

The Write Enable Latch (WEL) bit is reset.

The Write In Progress (WIP) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each

device in a system should have the VCC rail decoupled by a suitable capacitor close to the

package pins. (Generally, this capacitor is of the order of 100 nF).

At Power-down, when VCC drops from the operating voltage, to below the Power On Reset

(POR) threshold value, VWI, all operations are disabled and the device does not respond to

any instruction. (The designer needs to be aware that if a Power-down occurs while a Write,

Program or Erase cycle is in progress, some data corruption can result.)

Power-up and Pow er- down M25P32

38/54

Figure 21. Power-up tim i ng

Table 8. Powe r- up tim i ng and VWI threshold

Symbol Parameter Min. Max. Unit

tVSL(1)

1. These parameters are characterized only.

VCC(min) to S low 30 μs

tPUW(1) Time delay to Write instruction 1 10 ms

VWI(1) Write Inhibit voltage 1.5 2.5 V

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

tim

Read Access allowed Device fully

accessible

CC(max)

M25P32 Ini t ial delivery stat e

39/54

8 Initial delivery state

The device is delivered with the memory array erased: all bits are set to 1 (each byte

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

9 Maximum rating

Stressing the device outside the ratings listed in Tabl e 9 may cause permanent damage to

the device. These are stress ratings only, and operation of the device at these, or any other

conditions outside those indicated in the Operating sections of this specification, is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability. Refer also to the STMicroelectronics SURE Program and other relevant

quality documents.

Table 9. Absolu te ma ximum ra ti n g s

Symbol Parameter Min. Max. Unit

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering see (1)

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly) and the European

directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

°C

VIO Input and output voltage (with respect to Ground) –0.6 VCC +

0.6 V

VCC Supply voltage –0.6 4.0 V

VPP Fast Program/Erase voltage –0.2 10.0 V

VESD Electrostatic Discharge Voltage (Human Body model) (2)

2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

–2000 2000 V

DC and AC parameters M25P32

40/54

10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC Characteristic tables that

follow are derived from tests performed under the Measurement Conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

1. Output Hi-Z is defined as the point where data out is no longer driven.

Fig ur e 22. AC meas ur ement I/O waveform

Table 10. Operating conditions

Symbol Parameter Min. Typ. Max. Unit

VCC Supply voltage 2.7 3.6 V

VPPH

Supply voltage on W/VPP pin for Fast Program/Erase

mode 8.5 9.5 V

TAAmbient Operating Temperature (grade 6)(1)

1. "Autograde 6 and Standard parts (grade 6) are tested to 85 °C, but the Autograde 6 will follow the HRCF.

–40 85 °C

TAAmbient Operating Temperature (grade 3)(2)

2. Autograde 3 is tested to 125 °C.

–40 125 °C

TAVPP

Ambient operating temperature for fast Program/Erase

mode 15 25 35 °C

Table 11. Da ta Retention and Endurance

Parameter Condition Min. Max. Unit

Program / erase cycles Grade 3, Autograde 6, Grade 6 100,000 Cycles per sector

Data retention at 55°C 20 years

Table 12. AC measurement co n ditions

Symbol Parameter Min. Max. Unit

CLLoad capacitance 30 pF

Input rise and fall times 5 ns

Input pulse voltages 0.2VCC to 0.8VCC V

Input timing reference voltages 0.3VCC to 0.7VCC V

Output timing reference voltages VCC / 2 V

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

0.5VCC

M2 5P32 DC and AC p ar amete rs

41/54

Table 13. Capacitan ce(1)

1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 20 MHz.

Symbol Parameter Test condition Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

CIN Input capacitance (other pins) VIN = 0 V 6 pF

Table 14. DC ch aracteristics

Symbol Parameter Test condition ( in addition

to thos e i n Table 10)Min. Max. Unit

ILI Input leakage current ± 2 μA

ILO Output leakage current ± 2 μA

ICC1 Standby current S = VCC, VIN = VSS or VCC 50 μA

ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 μA

ICC3 Operating current (READ)

C = 0.1VCC / 0.9.VCC at

75 MHz, Q = open 12 mA

C = 0.1VCC / 0.9.VCC at

33 MHz, Q = open 4mA

ICC4 Operating current (PP) S = VCC 15 mA

ICC5 Operating current (WRSR) S = VCC 15 mA

ICC6 Operating current (SE) S = VCC 15 mA

ICC7 Operating current (BE) S = VCC 15 mA

ICCPP

Operating current for Fast

Program/Erase mode S = VCC, VPP = VPPH 20 mA

IPP

VPP operating current in Fast

Program/Erase mode S = VCC, VPP = VPPH 20 mA

VIL Input low voltage – 0.5 0.3VCC V

VIH Input high voltage 0.7VCC VCC+0.4 V

VOL Output low voltage IOL = 1.6 mA 0.4 V

VOH Output high voltage IOH = –100 μAV

CC–0.2 V

DC and AC parameters M25P32

42/54

Table 15. AC characteristics (T9HX technology)

Applies only to product s made with T9HX te chnology, identi fied with Process digit “4”(1)

Test conditions specifi ed in Table 10 and Table 12

Symbol Alt. Parameter Min. Typ.(2) Max. Unit

fCfC

Clock frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,

RDID, RDSR, WRSR

D.C. 75 MHz

fRClock frequency for READ instructions D.C. 33 MHz

tCH(3) tCLH Clock High time 9 ns

tCL(2) tCLL Clock Low time 9 ns

tCLCH(4) Clock rise time(5) (peak to peak) 0.1 V/ns

tCHCL(4) Clock fall time(5) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (relative to C) 5 ns

tCHSL S not active hold time (relative to C) 5 ns

tDVCH tDSU Data In setup time 2 ns

tCHDX tDH Data In hold time 5 ns

tCHSH S active hold time (relative to C) 5 ns

tSHCH S not active setup time (relative to C) 5 ns

tSHSL tCSH S deselect time 100 ns

tSHQZ(4) tDIS Output Disable time 8 ns

tCLQV tVClock Low to Output valid 8 ns

tCLQX tHO Output hold time 0 ns

tHLCH HOLD setup time (relative to C) 5 ns

tCHHH HOLD hold time (relative to C) 5 ns

tHHCH HOLD setup time (relative to C) 5 ns

tCHHL HOLD hold time (relative to C) 5 ns

tHHQX(4) tLZ HOLD to Output Low-Z 8 ns

tHLQZ(4) tHZ HOLD to Output High-Z 8 ns

tWHSL(6) Write Protect setup time 20 ns

tSHWL(6) Write Protect hold time 100 ns

tVPPHSL(7) Enhanced Program supply voltage High to Chip Select

Low 200 ns

tDP(4) S High to Deep Power-down mode 3 μs

tRES1(4) S High to Standby mode without Electronic Signature

Read 30 μs

tRES2(4) S High to Standby mode with Electronic Signature

Read 30 μs

M2 5P32 DC and AC p ar amete rs

43/54

Figure 23. Serial input timing

tWWrite Status Register cycle time 1.3 15 ms

tPP (8)

Page Program cycle time (256 bytes) 0.64

5msPage Program cycle time (n bytes) int(n/8) × 0.02(9)

Page Program cycle time (VPP = VPPH) (256 bytes) 0.64

tSE

Sector Erase cycle time 0.6

Sector Erase cycle time (VPP = VPPH)0.6

tBE

Bulk Erase cycle time 23

80 s

Bulk Erase cycle time (VPP = VPPH)13

1. Details of how to find the Technology Process in the marking are given in AN1995, see also Section 12: Part numbering.

2. Typical values given for TA = 25 °C.

3. tCH + tCL must be greater than or equal to 1/ fC

4. Value guaranteed by characterization, not 100% tested in production.

5. Expressed as a slew-rate.

6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

7. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is

known.

8. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one

sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤ 256)

9. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.

Table 15. AC characteristics (T9HX technology) (continu ed)

Applies only to product s made with T9HX te chnology, identi fied with Process digit “4”(1)

Test conditions specifi ed in Table 10 and Table 12

Symbol Alt. Parameter Min. Typ.(2) Max. Unit

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

DC and AC parameters M25P32

44/54

Figure 24. Write Protect Setu p and Hold timing during WRSR when SRWD=1

Figure 25. Hold timing

High Impedance

W/V

tWHSL tSHWL

AI07439

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

M2 5P32 DC and AC p ar amete rs

45/54

Figure 26. Output timing

Figure 27. V PPH tim i n g

AI01449e

LSB OUT

ADDR.LSB IN

tSHQ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

W/VPP

PPH

PP, SE, BE

ai12092

tVPPHSL

End of PP, SE or BE

(identified by WPI polling)

Package mechanical M25P32

46/54

11 Package mechanical

Fig u re 28. V DF P N8 (MLP 8) 8-le ad Very thin Dual Flat Pack ag e No lead, 8 × 6 mm ,

package outline

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 16. VDF P N8 (MLP8) 8-lead Very th in Du al Flat Pack ag e No lead , 8 × 6 mm,

package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 8.00 0.3150

D2 5.16 0.2031

ddd 0.05 0.0020

E 6.00 0.2362

E2 4.80 0.1890

e 1.27 – – 0.0500 – –

K 0.82 0.0323

L 0.50 0.45 0.60 0.0197 0.0177 0.0236

L1 0.15 0.0059

N8 8

VDFPN-02

A1 ddd

M25P32 Pac kag e mechanical

47/54

Figure 29. SO16 wide – 16-lead Plastic Sm all Outline, 300 mils body width, pack age

outline

1. Drawing is not to scale.

Table 17. SO16 wi de – 16 -lea d Plas tic Sm al l Ou tlin e, 300 mils body wi dth,

mechanical data

Symbol millimeters inches

Typ. Min. Max. Typ. Min. Max.

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 10.10 10.50 0.398 0.413

E 7.40 7.60 0.291 0.299

e 1.27 – – 0.050 – –

H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016 0.050

θ0° 8° 0° 8°

ddd 0.10 0.004

SO-H

LA1

ddd

h x 45˚

Package mechanical M25P32

48/54

Figure 30. V FQFP N 8 (MLP8 ) 8-le ad Ver y thin Fine Pitch Qua d Flat Pac kag e No lead,

6 × 5 mm, package outline

1. Drawing is not to scale.

Table 18. VFQFPN8 (MLP8 ) 8-lead Ver y thin Fine Pitch Qua d Flat Pac kag e No lead,

6 × 5 m m, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.85 0.80 1.00 0.0335 0.0315 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.30 0.1575 0.1496 0.1693

e 1.27 – – 0.0500 – –

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

Θ12° 12°

VFQFPN-01

eE2

M25P32 Pac kag e mechanical

49/54

Figu r e 31. SO 8W 8 lead Plastic Sm all Outli n e, 208 mils body wi dth, packa g e ou tline

1. Drawing is not to scale.

Table 19. SO8W 8 lead Plastic Sma ll Ou tline, 208 mils body width, packa ge

mechanical dat a

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.50 0.098

A1 0.00 0.25 0.000 0.010

A2 1.51 2.00 0.059 0.079

b 0.40 0.35 0.51 0.016 0.014 0.020

c 0.20 0.10 0.35 0.008 0.004 0.014

CP 0.10 0.004

D 6.05 0.238

E 5.02 6.22 0.198 0.245

E1 7.62 8.89 0.300 0.350

e 1.27 – – 0.050 – –

k 0° 10° 0° 10°

L 0.50 0.80 0.020 0.031

N8 8

6L_ME

LA1 k

Part numbering M25P32

50/54

12 Part numbering

Table 20. Ordering information scheme

Example: M25P32 – V MN 6 T P B A

Device Type

M25P = Serial Flash Memory for Code Storage

Device Function

32 = 32 Mbit (4M x 8)

Operating Voltage

V = VCC = 2.7 to 3.6 V

Operating Voltage

V = VCC = 2.7 to 3.6 V

Package

MF = SO16 (300 mils width)

ME = VDFPN8 8 × 6 mm (MLP8)(1)

MW = SO8W (208 mils width)

MP = VFQFPN 6 × 5 mm (MLP8)

MN = SO8N (150 mils width)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3 = Automotive temperature range, –40 to 125 °C.(2)

Device tested with high reliability certified flow(3)

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

P or G = RoHS compliant

Lithography

B = 110 nm, Fa. 2 Diffusion Plant

/4 = 110 nm, Catania Diffusion Plant

Automotive Grade

A = Automotive, –40 to 85 °C.(3)

blank = standard –40 to 85 °C device

1. Not for new design; please use VFQFPN8 6 x 5 mm.

2. Please contact your nearest Numonyx Sales office for Automotive Package options availability.

M25P32 Par t numberin g

51/54

Note: For a list of available options (speed, package, etc.), for further information on any aspect of

this device or when ordering parts operating at 75 MHz (0.11 μm, process digit “4”), please

contact your nearest Numonyx Sales Office.

The category of second Level Interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on the inner box label.

3. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive envirnoment.

The High Reliability Certified Flow (HRCF) is described in the quality note NNEE9801. Please ask your nearest

Numonyx sales office for a copy.

Revisio n  history M25P32
52/54   
13 Revision history
         
Table 21. Document revision history
Date Revision Changes
28-Apr-2003 0.1 Target Specification Document written in brief form
15-May-2003 0.2 Target Specification Document written in full
20-Jun-2003 0.3 8x6 MLP8 and SO16(300 mil) packages added
18-Jul-2003 0.4 tPP, tSE and tBE revised
24-Sep-2003 0.5 SO16 package code changed. Output Timing Reference Voltage 
changed.
04-Dec-2003 0.6
Table of contents, warning about exposed paddle on MLP8, and Pb-free 
options added.
Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. Change of naming 
for VDFPN8 package.
10-Dec-2003 1.0 Document promoted to Product Preview
01-Apr-2004 2.0
Document promoted to Preliminary Data. Soldering temperature 
information clarified for RoHS compliant devices. Device grade 
information clarified
05-Aug-2004 3.0 Device grade information further clarified
01-Oct-2004 4.0
Document promoted to mature datasheet. Footnotes removed from P and 
G options in Ordering Information table. Minor wording improvements 
made.
01-Apr-2005 5.0
Read Identification (RDID), Deep Power-down (DP) and Release from 
Deep Power-down and Read Electronic Signature (RES) instructions, and 
Active Power, Standby Power and Deep Power-down modes paragraph 
clarified.
01-Aug-2005 6.0 Updated Page Program (PP) instructions in Page Programming, Page 
Program (PP) and Table 14: AC characteristics.
23-Jan-2006 7.0
Fast Program/Erase mode added and Power-up specified for Fast 
Program/Erase mode in Power-up and Power-down section. W pin 
changed to W/VPP
. (see Write Protect/Enhanced Program supply voltage 
(W/VPP) description).
tVPPHSL added to Table 14: AC characteristics and tPP for Fast 
Program/Erase mode added. Figure 27: VPPH timing inserted. Note 2 
added below Figure 28 All packages are RoHS compliant. Blank option 
removed under Plating Technology in Table 20
10-Feb-2006 8.0 VDFPN8 package specifications updated (see Section 11: Package 
mechanical).
28-Nov-2006 9
MLP8 5 × 6 mm and SO8W packages added (see Section 11: Package 
mechanical). VCC supply voltage and VSS ground descriptions added.
Figure 4: Bus Master and memory devices on the SPI bus updated and 
explanation added below. 
Table 9: Absolute maximum ratings: VIO max modified and TLEAD added.
Products in T9HX technology introduced (see Table 15: AC 
characteristics (T9HX technology)). Small text changes.

M25P32 Revision hi story
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15-Jun-2007 10
Section 7: Power-up and Power-down modified.
Read Identification instruction modified in Section 6.3: Read Identification 
(RDID).
Inserted UID and CFI content columns in Table 5: Read Identification 
(RDID) data-out sequence.
Modified Data bytes for RDID instruction in Table 4: Instruction set.
Modified Q signal in Figure 10: Read Identification (RDID) instruction 
sequence and data-out sequence.
Modified Test condition and maximum value for ICC3 in Table 14: DC 
characteristics.
Modified the maximum value for fC in Table 15: AC characteristics (T9HX 
technology).
Table 14: AC characteristics removed.
31-Oct-2008 11
To provide support for the Automotive market, added the following:
– Automotive bullet to cover page;
– Grade 3 and grade 6 information to Table 10.: Operating conditions;
–Table 11.: Data Retention and Endurance;
– Automotive information to Table 20.: Ordering information scheme.
Table 21. Document revision history
Date Revision Changes

M25P32

54/54

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