General Description
The MAX1270/MAX1271 are multirange, 12-bit data-
acquisition systems (DAS) that require only a single
+5V supply for operation, yet accept signals at their
analog inputs that can span above the power-supply
rail and below ground. These systems provide eight
analog input channels that are independently software
programmable for a variety of ranges: ±10V, ±5V, 0 to
+10V, 0 to +5V for the MAX1270; ±VREF, ±VREF/2, 0 to
VREF, 0 to VREF/2 for the MAX1271. This range switch-
ing increases the effective dynamic range to 14 bits and
provides the flexibility to interface 4–20mA, ±12V, and
±15V powered sensors directly to a single +5V system.
In addition, these converters are fault protected to
±16.5V; a fault condition on any channel will not affect
the conversion result of the selected channel. Other fea-
tures include a 5MHz bandwidth track/hold, software-
selectable internal/external clock, 110ksps throughput
rate, and internal 4.096V or external reference operation.
The MAX1270/MAX1271 serial interface directly
connects to SPI™/QSPI™ and MICROWIRE™ devices
without external logic.
A hardware shutdown input (SHDN) and two software-
programmable power-down modes, standby (STBYPD)
or full power-down (FULLPD), are provided for low-cur-
rent shutdown between conversions. In standby mode,
the reference buffer remains active, eliminating startup
delays.
The MAX1270/MAX1271 are available in 24-pin narrow
PDIP or space-saving 28-pin SSOP packages.
Applications
Features
♦12-Bit Resolution, 0.5 LSB Linearity
♦+5V Single-Supply Operation
♦SPI/QSPI and MICROWIRE-Compatible
3-Wire Interface
♦Four Software-Selectable Input Ranges
MAX1270: 0 to +10V, 0 to +5V, ±10V, ±5V
MAX1271: 0 to VREF, 0 to VREF/2, ±VREF,
±VREF/2
♦Eight Analog Input Channels
♦110ksps Sampling Rate
♦±16.5V Overvoltage-Tolerant Input Multiplexer
♦Internal 4.096V or External Reference
♦Two Power-Down Modes
♦Internal or External Clock
♦24-Pin Narrow PDIP or 28-Pin SSOP Packages
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
________________________________________________________________ Maxim Integrated Products 1
VDD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
DGND
4.7µF
0.1µF
0.01µF
SHDN
MAX1270
MAX1271
+5V
ANALOG
INPUTS
CS
SCLK
DIN
DOUT
SSTRB
I/O
SCK
MOSI
MISO
REF
REFADJ
AGND
MC68HCXX
Typical Operating Circuit
PART
TEMP RANGE
PIN-PACKAGE INL
(LSB)
MAX1270ACNG
0°C to +70°C 24 Narrow PDIP
±0.5
MAX1270BCNG
0°C to +70°C 24 Narrow PDIP
±1
MAX1270ACAI
0°C to +70°C
28 SSOP
±0.5
MAX1270BCAI
0°C to +70°C
28 SSOP ±1
Ordering Information
19-4782; Rev 2; 9/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations appear at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
EVALUATION KIT
AVAILABLE
Industrial Control Systems
Data-Acquisition Systems
Battery-Powered
Instruments
Automatic Testing
Robotics
Medical Instruments
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz,
50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= TMIN to TMAX, unless
otherwise noted. Typical values are TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND............................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND ......................................................... ±16.5V
REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V)
SSTRB, DOUT to DGND.............................-0.3V to (VDD + 0.3V)
SHDN, CS, DIN, SCLK to DGND..............................-0.3V to +6V
Max Current into Any Pin ....................................................50mA
Continuous Power Dissipation (TA= +70°C)
24-Pin Narrow DIP (derate 13.33mW/°C above +70°C)..1067mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW
Operating Temperature Ranges
MAX127_C_ _......................................................0°C to +70°C
MAX127_E_ _......................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
ACCURACY (Note 1)
Resolution 12 Bits
MAX127_A
±0.5
Integral Nonlinearity INL MAX127_B
±1.0
LSB
Differential Nonlinearity DNL No missing codes over temperature ±1LSB
MAX127_A ±3
Unipolar MAX127_B ±5
MAX127_A ±5
Offset Error Bipolar MAX127_B ±10
LSB
Unipolar
±0.1
Channel-to-Channel Offset Error
Matching Bipolar
±0.3
LSB
MAX127_A ±7
Unipolar MAX127_B ±10
MAX127_A ±7
Gain Error (Note 2) Bipolar MAX127_B ±10
LSB
Unipolar, external reference ±3
Gain Error Temperature
Coefficient (Note 2) Bipolar, external reference ±5
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10VP-P (MAX1270), or ±4.096VP-P (MAX1271), fSAMPLE = 110ksps
(MAX127_B), fSAMPLE = 100ksps (MAX127_A))
Signal-to-Noise + Distortion Ratio
SINAD 70 dB
Total Harmonic Distortion THD Up to the 5th harmonic -87 -78 dB
Spurious-Free Dynamic Range SFDR 80 dB
50kHz (Note 3) -86
Channel-to-Channel Crosstalk DC, VIN = ±16.5V -96 dB
Aperture Delay External clock mode 15 ns
External clock mode
<50
ps
Aperture Jitter Internal clock mode 10 ns
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz,
50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= TMIN to TMAX, unless
otherwise noted. Typical values are TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
MAX127_A, fCLK = 1.8MHz 3.3
Track/Hold Acquisition Time tACQ MAX127_B, fCLK = 2.0MHz 3.0 µs
±10V or ±VREF
range 5
±5V or ±VREF/2
range 2.5
0 to 10V or 0 to
VREF range 2.5
Small-Signal Bandwidth -3dB rolloff
0 to 5V or 0 to
VREF/2 range
1.25
MHz
RNG = 1 0 10
MAX1270 RNG = 0 0 5
RNG = 1 0
VREF
Unipolar (BIP =
0), Table 3 MAX1271 RNG = 0 0
VREF/2
RNG = 1 -10
+10
MAX1270 RNG = 0 -5 +5
RNG = 1
-VREF +VREF
Input Voltage Range
(Table 3) VIN
Bipolar (BIP =
1), Table 3 MAX1271 RNG = 0
-VREF/2
+VREF/
2
V
0 to 10V
range -10
+720
MAX1270 0 to 5V
range -10
+360
Unipolar
MAX1271 -10 0.1
+10
±10V
range
-1200 +720
MAX1270
±5V range -600 +360
±VREF
range
-1200 +10
Input Current IIN
Bipolar
MAX1271 ±VREF/2
range
-600 +10
µA
Unipolar 21
Dynamic Resistance
∆VIN/∆IIN
Bipolar 16 kΩ
Input Capacitance (Note 4) 40 pF
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz,
50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= TMIN to TMAX, unless
otherwise noted. Typical values are TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
INTERNAL REFERENCE
REF Output Voltage VREF TA = +25°C
4.076 4.096 4.116
V
MAX1270_C/MAX1271_C
±15
REF Output Tempco
TC VREF
MAX1270_E/MAX1271_E
±30
ppm/°C
Output Short-Circuit Current 30 mA
Load Regulation 0 to 0.5mA output current (Note 5) 10 mV
Capacitive Bypass at REF 4.7 µF
Capacitive Bypass at REFADJ
0.01
µF
REFADJ Output Voltage
2.465 2.500 2.535
V
REFADJ Adjustment Range Figure 1
±1.5
%
Buffer Voltage Gain
1.638
V/V
REFERENCE INPUT (Reference buffer disabled, reference input applied to REF)
Input Voltage Range
2.40 4.18
V
Normal or STBYPD 400
Input Current VREF = 4.18V FULLPD 1 µA
Normal or STBYPD 10 kΩ
Input Resistance VREF = 4.18V FULLPD
4.18
MΩ
REFADJ Threshold for Buffer
Disable VDD -
0.5 V
POWER REQUIREMENT
Supply Voltage VDD
4.75 5.25
V
Bipolar range 18
Normal Unipolar range 6 10 mA
STBYPD power-down mode (Note 6)
700
850
Supply Current IDD
FULLPD power-down mode
120
220 µA
External reference = 4.096V
±0.1 ±0.5
Power-Supply Rejection
Ratio (Note 7) PSRR Internal reference
±0.5
LSB
TIMING
MAX127_A 0.1 1.8
External Clock Frequency Range
fSCLK MAX127_B 0.1 2.0
MHz
MAX127_A 3.3
External clock mode
(Note 8) MAX127_B 3.0
Acquisition Phase Internal clock mode, Figure 9 3 5 µs
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz,
50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA= TMIN to TMAX, unless
otherwise noted. Typical values are TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
MAX127_A 6.6
External clock mode
(Note 8) MAX127_B 6.0
Conversion Time tCONV Internal clock mode, Figure 9 6 7.7 11 µs
MAX127_A 100
External clock mode MAX127_B 110
Throughput Rate Internal clock mode 43
ksps
Bandgap Reference Startup Time
Power-up (Note 9)
200
µs
CREF = 4.7µF 8
Reference Buffer Settling Time To 0.1mV, REF bypass
capacitor fully
discharged CREF = 33µF 60 ms
DIGITAL INPUTS (DIN, SCLK, CS, and SHDN)
Input High Threshold Voltage VIH 2.4 V
Input Low Threshold Voltage VIL 0.8 V
Input Hysteresis VHYS 0.2 V
Input Leakage Current IIN VIN = 0 to VDD -10
+10
µA
Input Capacitance CIN (Note 4) 15 pF
DIGITAL OUTPUTS (DOUT, SSTRB)
ISINK = 5mA 0.4
Output Voltage Low VOL ISINK = 16mA 0.4 V
Output Voltage High VOH ISOURCE = 0.5mA VDD -
0.5 V
Tri-State Leakage Current ILCS = VDD -10
+10
µA
Tri-State Output Capacitance COUT CS = VDD (Note 4) 15 pF
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
6_______________________________________________________________________________________
Note 1: Accuracy specifications tested at VDD = +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply
rejection test.
Note 2: External reference: VREF = 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels. VIN = ±5V (MAX1270), VIN = ±4V (MAX1271).
Note 4: Guaranteed by design, not production tested.
Note 5: Use static external loads during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges.
Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6).
Note 9: Not production tested. Provided for design guidance only.
TIMING CHARACTERISTICS
(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK =
2.0MHz (MAX127_B); fCLK = 1.8MHz (MAX127_A); TA= TMIN to TMAX, unless otherwise noted. Typical values are TA= +25°C.)
(Figures 2, 5, 7, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIN to SCLK Setup tDS
100
ns
DIN to SCLK Hold tDH 0ns
SCLK Fall to Output Data Valid tDO 20
170
ns
CS Fall to Output Enable tDV CLOAD = 100pF
120
ns
CS Rise to Output Disable tTR CLOAD = 100pF
100
ns
CS to SCLK Rise Setup tCSS
100
ns
CS to SCLK Rise Hold tCSH 0ns
SCLK Pulse-Width High tCH
200
ns
SCLK Pulse-Width Low tCL
200
ns
SCLK Fall to SSTRB tSSTRB CLOAD = 100pF
200
ns
CS to SSTRB Output Enable tSDV CLOAD = 100pF, external clock mode only
200
ns
CS to SSTRB Output Disable tSTR CLOAD = 100pF, external clock mode only
200
ns
SSTRB Rise to SCLK Rise tSCK Internal clock mode only (Note 4) 0 ns
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 7
Typical Operating Characteristics
(Typical Operating Circuit, VDD = +5V; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock, fCLK = 2MHz;
110ksps; TA= +25°C, unless otherwise noted.)
0
5
15
10
20
25
02134567
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1270/1 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.5
5.7
6.1
5.9
6.3
6.5
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
MAX1270/1 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
50
150
450
350
250
650
550
750
-40 10-15 35 60 85
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
MAX1270/1 toc03
TEMPERATURE (°C)
STANDBY SUPPLY CURRENT (µA)
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
50
70
110
90
130
150
-40 10-15 35 60 85
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1270/1 toc04
TEMPERATURE (°C)
FULL POWER-DOWN SUPPLY CURRENT (µA)
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
0.1
0.2
0.6
0.5
0.4
0.3
0.7
0.8
-40 10-15 35 60 85
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
MAX1270/1 toc07
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB)
BIPOLAR MODE
UNIPOLAR MODE
0.996
0.997
0.999
0.998
1.000
1.001
-40 10-15 35 60 85
NORMALIZED REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1270/1 toc05
TEMPERATURE (°C)
NORMALIZED REFERENCE VOLTAGE
0
0.05
0.25
0.20
0.15
0.10
0.30
0.35
-40 10-15 35 60 85
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
MAX1270/1 toc06
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
BIPOLAR MODE
UNIPOLAR MODE
-0.15
-0.10
0.05
0
-0.05
0.10
0.15
0 1638819 2457 3276 4095
INTEGRAL NONLINEARITY vs.
DIGITAL CODE
MAX1270/1 toc08
DIGITAL CODE
INTEGRAL NONLINEARITY (LSB)
-120
-100
-40
-60
-80
-20
0
0 20k10k 30k 40k 50k
FTT PLOT
MAX1270/1 toc09
FREQUENCY (Hz)
AMPLITUDE (dB)
fIN = 10kHz
fSAMPLE = 110ksps
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
8_______________________________________________________________________________________
Pin Description
PIN
PDIP
SSOP
NAME FUNCTION
11 V
DD +5V Supply. Bypass with a 0.1µF capacitor to AGND.
2, 4
2, 3 DGND Digital Ground
3, 9,
22, 24
4, 7, 8,
11, 22,
24, 25, 28
N.C. No Connection. No internal connection.
55SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed.
66 CS Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high,
DOUT is high impedance.
79 DIN Serial Data Input. Data is clocked in on the rising edge of SCLK.
810
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low after the falling edge of the eighth
SCLK and returns high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. High impedance when CS is high in external
clock mode.
10
12 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is
high.
11
13 SHDN Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation.
12
14 AGND Analog Ground
13–20
15–21, 23 CH0–CH7
Analog Input Channels
21
26
REFADJ
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
Connect to VDD when using an external reference at REF.
23
27 REF Refer ence- Buffer O utp ut/AD C Re fer ence Inp ut. In i nt er nal r efer enc e m od e, the r ef er ence b uffer
p r ovi d es a 4.096V nom i nal outp ut, exter nal l y ad j ustab l e to RE FAD J. In exter nal r efer ence m od e,
d i sab l e the i nter nal r efer ence b y p ul l i ng RE FA D J to V
D D
and ap p l yi ng the exter nal r efer ence to R E F.
0
1
2
3
4
5
6
7
8
0.1 1 10 100 1000
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING STANDBY)
MAX1270-toc10
CONVERSION RATE (ksps)
AVERAGE SUPPLY CURRENT (mA)
VDD = 5V, INTERNAL REFERENCE,
fCLK = 2MHz
EXTERNAL CLOCK MODE.
LOW-RANGE UNIPOLAR MODE.
VCH_ = 0
0
1
2
3
4
5
6
7
8
0.1 1 10 100 1000
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING FULLPD)
MAX1270-toc11
CONVERSION RATE (ksps)
AVERAGE SUPPLY CURRENT (mA)
VDD = 5V, INTERNAL REFERENCE,
fCLK = 2MHz
EXTERNAL CLOCK MODE.
LOW-RANGE UNIPOLAR MODE.
VCH_ = 0
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VDD = +5V; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock, fCLK = 2MHz;
110ksps; TA= +25°C, unless otherwise noted.)
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 9
Detailed Description
Converter Operation
The MAX1270/MAX1271 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 3 shows the block diagram of the
MAX1270/MAX1271.
Analog-Input Track/Hold
The T/H enters tracking/acquisition mode on the falling
edge of the sixth clock in the 8-bit input control word,
and enters hold/conversion mode when the timed
acquisition interval (six clock cycles, 3µs minimum)
ends. In internal clock mode, the acquisition is timed by
two external clock cycles and four internal clock cycles.
When operating in bipolar (MAX1270 and MAX1271) or
unipolar mode (MAX1270) the signal applied at the
input channel is rescaled through the resistor-divider
network formed by R1, R2, and R3 (Figure 4); a low
impedance (<4Ω) input source is recommended to
minimize gain error. When the MAX1271 is configured
for unipolar mode, the channel input resistance (RIN)
becomes a fixed 5.12kΩ(typ). Source impedances
below 15kΩ(0 to VREF) and 5kΩ(0 to VREF/2) do not
significantly affect the AC performance of the ADC.
The acquisition time (tACQ) is a function of the source
output resistance, the channel input resistance, and the
T/H capacitance. Higher source impedances can be
used if an input capacitor is connected between the
analog inputs and AGND. Note that the input capacitor
forms an RC filter with the input source impedance, lim-
iting the ADC’s signal bandwidth.
100kΩ
510kΩ
24kΩ
REFADJ
+5V
MAX1270
MAX1271
0.01µF
CH2
CH1
CH0
SHDN
CH3
CH4
CH5
CH6
CH7
REFADJ
REF
VDD
AGND
DGND
MAX1270
MAX1271
12-BIT SAR ADC
IN
REF
CLOCK
OUT
T/H
2.5V
REFERENCE
ANALOG
INPUT
MUX
AND SIGNAL
CONDITIONING
Av =
1.638
INT
CLOCK
DIN SSTRB DOUT CS SCLK
SERIAL INTERFACE LOGIC
10kΩ
+4.096V
0.5mA
DOUT
OR
SSTRB
+5V
a) HIGH IMPEDANCE TO VOH, VOL TO
VOH AND VOH TO HIGH IMPEDANCE HIGH IMPEDANCE TO VOH, VOL TO
VOH AND VOH TO HIGH IMPEDANCE
b)
CLOAD CLOAD
5mA
DOUT
OR
SSTRB
Figure 1. Reference-Adjust Circuit
Figure 3. Block Diagram
Figure 2. Output Load Circuit for Timing Characteristics
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
10 ______________________________________________________________________________________
Input Bandwidth
The ADC’s input small-signal bandwidth depends on the
selected input range and varies from 1.5MHz to 5MHz
(see Electrical Characteristics). The MAX1270B/
MAX1271B maximum sampling rate is 110ksps (100ksps
for the MAX1270A/MAX1271A). By using undersampling
techniques, it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-aliasing filtering is rec-
ommended.
Input Range and Protection
The MAX1270/MAX1271 have software-selectable input
ranges. Each analog input channel can be indepen-
dently programmed to one of four ranges by setting the
appropriate control bits (RNG, BIP) in the control byte
(Table 1). The MAX1270 has selectable input ranges
extending to ±10V (±VREF x 2.441), while the MAX1271
has selectable input ranges extending to ±VREF. Figure
4 shows the equivalent input circuit.
A resistor network on each analog input provides
±16.5V fault protection for all channels. Whether or not
the channel is on, this circuit limits the current going
into or out of the pin to less than 2mA. This provides an
added layer of protection when momentary overvolt-
ages occur at the selected input channel, when a neg-
ative signal is applied to the input, and when the device
is configured for unipolar mode. The overvoltage pro-
tection is active even if the device is in power-down
mode or if VDD = 0.
Digital Interface
The MAX1270/MAX1271 feature a serial interface that is
fully compatible with SPI/QSPI and MICROWIRE devices.
For SPI/QSPI, set CPOL = 0, CPHA = 0 in the SPI control
registers of the microcontroller. Figure 5 shows detailed
serial-interface timing information. See Table 1 for details
on programming the input control byte.
tCSH tCSS tCL
tDS tDH
tDV
tCH
tDO tTR
tCSH
CS
SCLK
DIN
DOUT
Figure 5. Detailed Serial-Interface Timing
R3
5.12kΩ
R2
R1
CH_
S1
S2
S3
S4
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLDTRACK
TRACKHOLD
OFF
ON
CHOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kΩ (MAX1270)
or 5.12kΩ (MAX1271)
R2 = 8.67kΩ (MAX1270)
or ∞ (MAX1271)
Figure 4. Equivalent Input Circuit
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 11
Table 1. Control-Byte Format
BIT 7
(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(LSB)
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
BIT NAME DESCRIPTION
7 (MSB) START First logic 1 after CS goes low defines the beginning of the control byte.
6, 5, 4 SEL2, SEL1,
SEL0 These 3 bits select the desired “on” channel (Table 2).
3RNG Selects the full-scale input voltage range (Table 3).
2BIP Selects the unipolar or bipolar conversion mode (Table 3).
1, 0 (LSB) PD1, PD0 Select clock and power-down modes (Table 4).
Table 2. Channel Selection
SEL2 SEL1 SEL0 CHANNEL
000 CH0
001 CH1
010 CH2
011 CH3
100 CH4
101 CH5
110 CH6
111 CH7
Table 4. Power-Down and Clock Selection
PD1
PD0
MODE
00
Normal operation (always on), internal clock
mode.
01
Normal operation (always on), external clock
mode.
10
Standby power-down mode (STBYPD), clock
mode unaffected.
11
Full power-down mode (FULLPD), clock mode
unaffected.
Table 3. Range and Polarity Selection for MAX1270/MAX1271
RANGE AND POLARITY SELECTION FOR THE MAX1270
INPUT RANGE RNG BIP Negative
FULL SCALE
ZERO
SCALE (V) FULL SCALE
0 to +5V 0 0 — 0 VREF x 1.2207
0 to +10V 1 0 — 0 VREF x 2.4414
±5V 0 1 -VREF x 1.2207 0 VREF x 1.2207
±10V 1 1 -VREF x 2.4414 0 VREF x 2.4414
RANGE AND POLARITY SELECTION FOR THE MAX1271
INPUT RANGE RNG BIP Negative
FULL SCALE
ZERO
SCALE (V) FULL SCALE
0 to VREF/2 0 0 — 0 VREF/2
0 to VREF 10 — 0 V
REF
±VREF/2 0 1 -VREF/2 0 VREF/2
±VREF 11 -V
REF 0V
REF
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
12 ______________________________________________________________________________________
Input Data Format
Input data (control byte) is clocked in at DIN at the ris-
ing edge of SCLK. CS enables communication with the
MAX1270/MAX1271. After CS falls, the first arriving
logic 1 bit represents the start bit (MSB) of the input
control byte. The start bit is defined as:
The first high bit clocked into DIN with CS low
anytime the converter is idle; e.g., after VDD is
applied. OR
The first high bit clocked into DIN after bit 6
(D6) of a conversion in progress is clocked
onto DOUT.
Output Data Format
Output data is clocked out on the falling edge of SCLK
at DOUT, MSB first (D11). In unipolar mode, the output
is straight binary. For bipolar mode, the output is two’s
complement binary. For output binary codes, refer to
the Transfer Function section.
How to Start a Conversion
The MAX1270/MAX1271 use either an external serial
clock or the internal clock to complete an acquisition
and perform a conversion. In both clock modes, the
external clock shifts data in and out. See Table 4 for
details on programming clock modes.
The falling edge of CS does not start a conversion on
the MAX1270/MAX1271; a control byte is required for
each conversion. Acquisition starts after the sixth bit is
programmed in the input control byte. Conversion
starts when the acquisition time, six clock cycles,
expires.
Keep CS low during successive conversions. If a start-
bit is received after CS transitions from high to low, but
before the output bit 6 (D6) becomes available, the cur-
rent conversion will terminate and a new conversion will
begin.
External Clock Mode (PD1 = 0, PD0 = 1)
In external clock mode, the clock shifts data in and out
of the MAX1270/MAX1271 and controls the acquisition
and conversion timings. When acquisition is done,
SSTRB pulses high for one clock cycle and conversion
begins. Successive-approximation bit decisions appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). Additional SCLK falling edges will result in
zeros appearing at DOUT. Figure 7 shows the SSTRB
timing in external clock mode.
SSTRB and DOUT go into a high-impedance state
when CS goes high; after the next CS falling edge,
SSTRB and DOUT will output a logic low.
The conversion must be completed in some minimum
time, or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the clock period exceeds 10µs, or if serial-clock inter-
ruptions could cause the conversion interval to exceed
120µs. The fastest the MAX1270/MAX1271 can run is
18 clocks per conversion in external clock mode, and
with a clock rate of 2MHz, the maximum sampling rate
is 111 ksps (Figure 8). In order to achieve maximum
throughput, keep CS low, use external clock mode with
a continuous SCLK, and start the following control byte
after bit 6 (D6) of the conversion in progress is clocked
onto DOUT.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 18 zeros.
SSTRB
CS
SCLK
DIN
DOUT
181213 14 24 25
START
SEL2 SEL1 SEL0 BIPRNG PD1 PD0
LSB
D11
MSB
MSB
D10 D9 D1 D0LSB
ACQUISITION
6 SCLK
FILLED WITH
ZEROS
CONVERSION
12 SCLK
A/D STATE
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
Figure 6. External Clock Mode—25 Clocks/Conversion Timing
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 13
Internal Clock Mode (PD1 = 0, PD0 = 0)
In internal clock mode, the MAX1270/MAX1271 gener-
ate their conversion clock internally. This frees the
microprocessor from the burden of running the acquisi-
tion and the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
convenience, at any clock rate from 0 to typically
10MHz.
SSTRB goes low after the falling edge of the last bit
(PD0) of the control byte has been shifted in, and
returns high when the conversion is complete.
Acquisition is completed and conversion begins on the
falling edge of the 4th internal clock pulse after the con-
trol byte; conversion ends on the falling edge of the
16th internal clock pulse (12 internal clock cycle pulses
are used for conversion). SSTRB will remain low for a
maximum of 15µs, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data while the conversion is in progress.
The MSB of the result byte (D11) is present at DOUT
starting at the falling edge of the last internal clock of
conversion. Successive falling edges of SCLK will shift
the remaining data out of this register (Figure 9).
Additional SCLK edges will result in zeros on DOUT.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Pulling CS high prevents data from being clocked in
and tri-states DOUT, but does not adversely affect a
tSDV
tSSTRB
SCLK 12
tSTR
SSTRB
SCLK
CS
tSSTRB
HIGH-Z HIGH-Z
Figure 7. External Clock Mode—SSTRB Detailed Timing
CS
SCLK
DIN
DOUT
A/D STATE
13
19 24 26 31 32
14
16 37
START
SEL2 SEL1 SEL0
BIPRNG PD1 PD0
D11 D10 D9 D7D8 D6 D5 D4 D2D3 D1 D0
LSB
81
MSB
LSBMSB
START
SEL2 SEL1 SEL0
BIPRNG PD1 PD0
START
SEL2
CONTROL BYTE 0
RESULT
CONTROL BYTE 1 CONTROL BYTE 2
18 SCLK
18 SCLK
SSTRB
D10D11 D9 D8 D6D7 D5
RESULT 1
ACQUISITION
6 SCLK CONVERSION
12 SCLK ACQUISITION
6 SCLK CONVERSION
12 SCLK
HIGH-Z
HIGH-Z
Figure 8. External Clock Mode—18 Clocks/Conversion Timing
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
14 ______________________________________________________________________________________
conversion in progress. Figure 10 shows the SSTRB
timing in internal clock mode.
Internal clock mode conversions can be completed
with 13 external clocks per conversion but require a
waiting period of 15µs for the conversion to be com-
pleted (Figure 11).
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clock cycles. Sixteen clock cycles
per conversion (as shown in Figure 12) is typically the
most convenient way for a microcontroller to drive the
MAX1270/MAX1271.
Applications Information
Power-On Reset
The MAX1270/MAX1271 power up in normal operation
(all internal circuitry active) and internal clock mode,
waiting for a start bit. The contents of the output data
register are cleared at power-up.
Internal or External Reference
The MAX1270/MAX1271 operate with either an internal
or external reference. An external reference is connect-
ed to either REF or REFADJ (Figure 13). The REFADJ
internal buffer gain is trimmed to 1.638V to provide
4.096V at REF from a 2.5V reference.
SSTRB
CS
SCLK
DIN
DOUT
1820
START
SEL2 SEL1 SEL0 RNG BIP PD1 PD0
D11 D10 D1 D0
ACQUISITION
FILLED WITH ZEROS
CONVERSION
A/D STATE
910 19
16 INT CLK
12 INT CLK
MSB LSB
MSB LSB
2 EXT SCLK
+4 INT CLK
HIGH-Z HIGH-Z HIGH-Z
Figure 9. Internal Clock Mode—20 SCLK/Conversion Timing
SCLK #8
tSSTRB
tCSH tSCK tCSS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
SSTRB
SCLK
CS
Figure 10. Internal Clock Mode—SSTRB Detailed Timing
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 15
Internal Reference
The internally trimmed 2.50V reference is amplified
through the REFADJ buffer to provide 4.096V at REF.
Bypass REF with a 4.7µF capacitor to AGND and
REFADJ with a 0.01µF capacitor to AGND (Figure 13a).
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
External Reference
To use the REF input directly, disable the internal buffer
by tying REFADJ to VDD (Figure 13b). Using the
REFADJ input eliminates the need to buffer the refer-
ence externally. When a reference is applied at
REFADJ, bypass REFADJ with a 0.01µF capacitor to
AGND. Note that when an external reference is applied
at REFADJ, the voltage at REF is given by:
VREF = 1.6384 x VREFADJ (2.4 < VREF < 4.18)
(Figure 13c). At REF and REFADJ, the input impedance
is a minimum of 10kΩfor DC currents. During conver-
sions, an external reference at REF must be able to deliv-
er 400µA DC load currents and must have an output
impedance of 10Ωor less. If the reference has higher
output impedance or is noisy, bypass REF with a 4.7µF
capacitor to AGND as close to the chip as possible.
With an external reference voltage of less than 4.096V
at REF or less than 2.5V at REFADJ, the increase in the
ratio of RMS noise to the LSB value (full-scale / 4096)
results in performance degradation (loss of effective
bits).
CS
SCLK
DIN
DOUT
A/D STATE
18
9
242214
16
START SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
D11 D10 D9 D7D8 D6 D5 D4 D2D3 D1 D0
START SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
START
SEL0SEL1SEL2
CONTROL BYTE Ø
RESULT Ø
CONTROL BYTE 1 CONTROL BYTE 2
13 SCLK
13 SCLK
SSTRB
D10D11 D9 D8 D6D7 D5 D4 D3
RESULT 1
ACQUISITION CONVERSION ACQUISITION CONVERSION
HIGH-Z
Figure 11. Internal Clock Mode—13 Clocks/Conversion Timing
CS
SCLK
DIN
DOUT
A/D STATE IDLE
9 24
25 32
16 17
START START
SEL2 SEL1 SEL0 BIPRNG PD1 PD0
D11 D10 D9 D7D8 D6 D5 D4 D2D3 D1 D0
START
SEL2 SEL1 SEL0 BIPRNG PD1 PD0
CONTROL BYTE Ø
RESULT Ø
CONTROL BYTE 1 CB 2
16 SCLK
16 SCLK
SSTRB
D10
D11
D9 D8 D6D7 D5 D4 D3
RESULT 1
ACQUISITION CONVERSION ACQUISITION CONVERSION
HIGH-ZHIGH-Z HIGH-Z
18
Figure 12. Internal Clock Mode—16 Clocks/Conversion Timing
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
16 ______________________________________________________________________________________
Power-Down Mode
To save power, configure the converter into low-current
shutdown mode between conversions. Two program-
mable power-down modes are available in addition to a
hardware shutdown. Select STBYPD or FULLPD by pro-
gramming PD0 and PD1 in the input control byte
(Table 4). When software power-down is asserted, it
becomes effective only after the end of conversion. For
example, if the control byte contains PD1 = 0, then the
chip remains powered up. If PD1 = 1, then the chip
powers down at the end of conversion. In all power-
down modes, the interface remains active and conver-
sion results can be read. Input overvoltage protection is
active in all power-down modes.
The first logical 1 on DIN after CS falls is interpreted as
a start condition, and powers up the MAX1270/
MAX1271 from a software selected STBYPD or FULLPD
condition.
For hardware-controlled power-down (FULLPD), pull
SHDN low. When hardware shutdown is asserted, it
becomes effective immediately, and any conversion in
progress is aborted.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at REF. This is a DC state that does not
degrade after power-down of any duration.
In FULLPD mode, only the bandgap reference is active.
Connect a 33µF capacitor between REF and AGND to
maintain the reference voltage between conversions
and to reduce transients when the buffer is enabled
and disabled. Throughput rates down to 1ksps can be
achieved without allotting extra acquisition time for ref-
erence recovery prior to conversion. This allows con-
version to begin immediately after power-up. If the
discharge of the REF capacitor during FULLPD
exceeds the desired limits for accuracy (less than a
fraction of an LSB), run a STBYPD power-down cycle
prior to starting conversions. Take into account that the
reference buffer recharges the bypass capacitor at an
80mV/ms slew rate, and add 50µs for settling time.
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts down the MAX1270/MAX1271 after each conversion
without requiring any start-up time on the next conversion.
REF
10kΩ
2.5V
2.5V
REFADJ
AV = 1.638
MAX1270
MAX1271
4.7µF
CREF
0.01µF
Figure 13c. External Reference—Reference at REFADJ
REF
VDD
10kΩ
2.5V
4.096V
REFADJ
AV = 1.638
MAX1270
MAX1271
4.7µF
CREF
Figure 13b. External Reference—Reference at REF
REF
10kΩ
2.5V
REFADJ
0.01µF
AV = 1.638
MAX1270
MAX1271
4.7µF
CREF
Figure 13a. Internal Reference
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 17
Transfer Function
Output data coding for the MAX1270/MAX1271 is bina-
ry in unipolar mode with 1 LSB = (FS / 4096) and two’s
complement binary in bipolar mode with 1 LSB = [(2 x
| FS | ) / 4096]. Code transitions occur halfway between
successive-integer LSB values. Figures 14a and 14b
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively. For full-scale
values, refer to Table 3.
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system
performance. Use a ground plane for best perfor-
mance. To reduce crosstalk and noise injection, keep
analog and digital signals separate. Connect analog
grounds and DGND in a star configuration to AGND.
For noise-free operation, ensure the ground return from
AGND to the supply ground is low impedance and as
short as possible. Connect the logic grounds directly to
the supply ground. Bypass VDD with 0.1µF and 4.7µF
capacitors to AGND to minimize highand low-frequency
fluctuations. If the supply is excessively noisy, connect
a 5Ωresistor between the supply and VDD, as shown in
Figure 15.
VDD
GND
DGND
DGNDAGND
+5V
+5V
SUPPLY
R* = 5Ω
DIGITAL
CIRCUITRY
4.7µF
0.1µF
MAX1270
MAX1271
**
*OPTIONAL
**CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE.
Figure 15. Power-Supply Grounding Connections
OUTPUT CODE
INPUT VOLTAGE (LSB)
0FS
FS - 3/2LSB
1 LSB =
FULL-SCALE
TRANSITION
123
11... 111
11... 110
11... 101
00... 011
00... 010
00... 001
00... 000
FS
4096
Figure 14a. Unipolar Transfer Function
OUTPUT CODE
INPUT VOLTAGE (LSB)
0 +FS - 1 LSB
1 LSB =
-FS
011... 111
011... 110
000... 001
000... 000
111... 111
100... 010
100... 001
100... 000
2|FS|
4096
Figure 14b. Bipolar Transfer Function
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
18 ______________________________________________________________________________________
Ordering Information (continued)
Pin Configurations
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
N.C.
REF
N.C.
REFADJDGND
N.C.
DGND
VDD
CH7
CH6
CH5
CH4SSTRB
DIN
CS
SCLK
16
15
14
13
9
10
11
12
CH3
CH2
CH1
CH0AGND
SHDN
DOUT
N.C.
PDIP
MAX1270
MAX1271
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
N.C.
REF
REFADJ
N.C.
N.C.
CH7
CH0
N.C.
CH6
CH5
CH4
CH3
CH2
CH1
AGND
SHDN
DOUT
N.C.
SSTRB
DIN
N.C.
N.C.
CS
SCLK
N.C.
DGND
DGND
VDD
SSOP
TOP VIEW
MAX1270
MAX1271
Chip Information
TRANSISTOR COUNT: 4219
SUBSTRATE CONNECTED TO AGND
PART
TEMP RANGE
PIN-PACKAGE INL
(LSB)
MAX1270AENG
-40°C to +85°C 24 Narrow PDIP
±0.5
MAX1270BENG
-40°C to +85°C 24 Narrow PDIP
±1
MAX1270AEAI
-40°C to +85°C
28 SSOP
±0.5
MAX1270BEAI
-40°C to +85°C
28 SSOP ±1
MAX1271ACNG
0°C to +70°C 24 Narrow PDIP
±0.5
MAX1271BCNG
0°C to +70°C 24 Narrow PDIP
±1
MAX1271ACAI
0°C to +70°C
28 SSOP
±0.5
MAX1271BCAI
0°C to +70°C
28 SSOP ±1
MAX1271AENG
-40°C to +85°C 24 Narrow PDIP
±0.5
MAX1271BENG
-40°C to +85°C 24 Narrow PDIP
±1
MAX1271AEAI
-40°C to +85°C
28 SSOP
±0.5
MAX1271BEAI
-40°C to +85°C
28 SSOP ±1
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________ 19
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PDIPN.EPS
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
SSOP.EPS
PACKAGE OUTLINE, SSOP, 5.3 MM
1
1
21-0056 C
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
7.90
H
L
0∞
0.301
0.025
8∞
0.311
0.037
0∞
7.65
0.63
8∞
0.95
MAX
5.38
MILLIMETERS
B
C
D
E
e
A1
DIM
A
SEE VARIATIONS
0.0256 BSC
0.010
0.004
0.205
0.002
0.015
0.008
0.212
0.008
INCHES
MIN MAX
0.078
0.65 BSC
0.25
0.09
5.20
0.05
0.38
0.20
0.21
MIN
1.73 1.99
MILLIMETERS
6.07
6.07
10.07
8.07
7.07
INCHES
D
D
D
D
D
0.239
0.239
0.397
0.317
0.278
MIN
0.249
0.249
0.407
0.328
0.289
MAX MIN
6.33
6.33
10.33
8.33
7.33
14L
16L
28L
24L
20L
MAX N
A
D
eA1 L
C
HE
N
12
B
0.068
