1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O and SRAM (W30) 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Preliminary Datasheet Product Features Flash Performance -- 70 ns Initial Access Speed -- 25 ns Page-Mode Read Speed -- 20 ns Burst-Mode Read Speed -- Burst and Page Mode in All Blocks and across All Partition Boundaries -- Enhanced Factory Programming: 3.5 s per Word Program Time -- Programmable WAIT Signal Polarity Flash Power -- VCC = 1.70 V - 1.90 V -- VCCQ = 2.20 V - 3.30 V -- Standby Current = 6 A (typ.) -- Read Current = 7 mA (4 word burst, typ.) Flash Software -- 5/9 s (typ.) Program/Erase Suspend Latency Time -- Intel(R) Flash Data Integrator (FDI) and Common Flash Interface (CFI) Compatible Quality and Reliability -- Operating Temperature: -25 C to +85 C -- 100K Minimum Erase Cycles -- 0.18 m ETOXTM VII Process Flash Architecture -- Multiple 4-Mbit Partitions -- Dual Operation: RWW or RWE -- Parameter Block Size = 4-Kword -- Main block size = 32-Kword -- Top and Bottom Parameter Devices Flash Security -- 128-bit Protection Register: 64 Unique Device Identifier Bits; 64 User OTP Protection Register Bits -- Absolute Write Protection with VPP at Ground -- Program and Erase Lockout during Power Transitions -- Individual and Instantaneous Block Locking/ Unlocking with Lock-Down SRAM -- 70 ns Access Speed -- 16-bit Data Bus -- Low Voltage Data Retention -- S-VCC = 2.20 V - 3.30 V Density and Packaging -- 32-Mbit Discrete in VF BGA Package -- 64-Mbit Discrete in BGA* Package -- 56 Active Ball Matrix, 0.75 mm Ball-Pitch in BGA* and VF BGA Packages -- 32/4-, 64/8- and 128/TBD- Mbit (Flash + SRAM) in a 80-Ball Stacked-CSP Package (14 mm x 8 mm) -- 16-bit Data Bus The 1.8 Volt Intel(R)Wireless Flash Memory with 3 Volt I/O combines state-of-the-art Intel(R) Flash technology with low power SRAM to provide the most versatile and compact memory solution for high performance, low power, board constraint memory applications. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O offers a multi-partition, dual-operation flash architecture that enables the device to read from one partition while programming or erasing in another partition. This Read-While-Write or Read-While-Erase capability makes it possible to achieve higher data throughput rates as compared to single partition devices and it allows two processors to interleave code execution because program and erase operations can now occur as background processes. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O incorporates a new Enhanced Factory Programming (EFP) mode to improve 12 V factory programming performance. This new feature helps eliminate manufacturing bottlenecks associated with programming high density flash devices. Compare the EFP program time of 3.5 s per word to the standard factory program time of 8.0 s per word and save significant factory programming time for improved factory efficiency. Additionally, the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O includes block lock-down, programmable WAIT signal polarity and is supported by an array of software tools. All these features make this product a perfect solution for any demanding memory application. Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. 290702-002 March 2001 Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 1.8 Volt Intel(R) Wireless Flash Memory (with 3 Volt I/O and SRAM) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2000 - 2001. *Other names and brands may be claimed as the property of others. Preliminary 28F320W30, 28F3204W30, 28F6408W30, 28F640W30 Contents 1.0 Product Introduction .................................................................................................1 1.1 1.2 2.0 Product Description .................................................................................................. 2 2.1 2.2 2.3 2.4 2.5 2.6 3.0 4.2 4.3 4.4 4.5 4.6 Read Array ..........................................................................................................12 4.1.1 Asynchronous Mode...............................................................................12 4.1.2 Synchronous Mode ................................................................................12 Set Configuration Register (CR)..........................................................................13 4.2.1 Read Mode (RM)....................................................................................14 4.2.2 First Latency Count (LC2-0) ..................................................................14 4.2.3 WAIT Signal Polarity (WT) .....................................................................16 4.2.4 WAIT Signal Function.............................................................................17 4.2.5 Data Output Configuration (DOC) ..........................................................17 4.2.6 WAIT Configuration (WC).......................................................................18 4.2.7 Burst Sequence (BS)..............................................................................19 4.2.8 Clock Configuration (CC) .......................................................................20 4.2.9 Burst Wrap (BW) ....................................................................................21 4.2.10 Burst Length (BL2-0) .............................................................................21 Read Query Register...........................................................................................21 Read ID Register.................................................................................................21 Read Status Register ..........................................................................................22 4.5.1 Clear Status Register .............................................................................24 Read-While-Write/Erase......................................................................................24 Program and Erase Voltages...............................................................................24 5.1 5.2 5.3 5.4 Preliminary Bus Operations...................................................................................................... 9 Flash Command Definitions .................................................................................. 9 Flash Read Modes ...................................................................................................12 4.1 5.0 Product Overview .................................................................................................. 2 Package Diagram.................................................................................................. 3 Package Dimensions............................................................................................. 4 Signal Descriptions................................................................................................ 5 Block Diagram ....................................................................................................... 6 Flash Memory Map................................................................................................ 6 Product Operations ................................................................................................... 9 3.1 3.2 4.0 Document Purpose................................................................................................ 1 Nomenclature ........................................................................................................1 Factory Program Mode........................................................................................24 Programming Voltage Protection (VPP)..............................................................25 Enhanced Factory Programming (EFP) ..............................................................25 5.3.1 EFP Requirements and Considerations .................................................26 5.3.2 Setup Phase...........................................................................................26 5.3.3 Program Phase ......................................................................................26 5.3.4 Verify Phase ...........................................................................................27 5.3.5 Exit Phase ..............................................................................................27 Write Protection (VPP < VPPLK) ...........................................................................27 iii 28F320W30, 28F3204W30, 28F6408W30, 28F640W30 6.0 Flash Erase Mode .................................................................................................... 27 6.1 6.2 7.0 Block Erase ......................................................................................................... 27 Erase Protection (VPP < VPPLK) .......................................................................... 28 Flash Suspend/Resume Modes.......................................................................... 28 7.1 7.2 8.0 Program/Erase Suspend..................................................................................... 28 Program/Erase Resume...................................................................................... 28 Flash Security Modes ............................................................................................. 29 8.1 8.2 8.3 8.4 8.5 9.0 Block Lock........................................................................................................... 29 Block Unlock ....................................................................................................... 30 Lock-Down Block ................................................................................................ 30 Block Lock Operations during Erase Suspend.................................................... 30 WP# Lock-Down Control..................................................................................... 30 Flash Protection Register ..................................................................................... 32 9.1 9.2 9.3 10.0 Protection Register Read .................................................................................... 32 Program Protection Register ............................................................................... 32 Protection Register Lock ..................................................................................... 33 Power and Reset Considerations ...................................................................... 34 10.1 10.2 10.3 11.0 Electrical Specifications........................................................................................ 35 11.1 11.2 11.3 11.4 11.5 12.0 Flash Read Operations ....................................................................................... 40 Flash Write Operations ....................................................................................... 49 Flash Program and Erase Operations................................................................. 51 Reset Operations ................................................................................................ 51 SRAM AC Characteristics ..................................................................................... 53 13.1 13.2 13.3 14.0 Absolute Maximum Ratings ................................................................................ 35 Extended Temperature Operation....................................................................... 35 DC Characteristics .............................................................................................. 36 Discrete Capacitance (32-Mbit VF BGA Package) ............................................. 38 Stacked Capacitance (32/4 and 64/8 Stacked-CSP Package) ........................... 39 Flash AC Characteristics ...................................................................................... 40 12.1 12.2 12.3 12.4 13.0 Power-Up/Down Characteristics ......................................................................... 34 Power Supply Decoupling ................................................................................... 34 Flash Reset Characteristics ................................................................................ 34 SRAM Read Operation ....................................................................................... 53 SRAM Write Operation........................................................................................ 55 SRAM Data Retention Operation ........................................................................ 56 Ordering Information .............................................................................................. 58 Appendix A Flash Write State Machine (WSM) ................................................................ 59 Appendix B Flowcharts ............................................................................................................. 61 Appendix C Common Flash Interface ................................................................................. 68 iv Preliminary 28F320W30, 28F3204W30, 28F6408W30, 28F640W30 Revision History Date of Revision Preliminary Version Description 09/19/00 -001 Original Version 03/14/01 -002 28F3208W30 product references removed (product was discontinued) 28F640W30 product added Revised Table 2, Signal Descriptions (DQ15-0, ADV#, WAIT, S-UB#, S-LB#, VCCQ) Revised Section 3.1, Bus Operations Revised Table 5, Command Bus Definitions, Notes 1 and 2 Revised Section 4.2.2, First Latency Count (LC2-0); revised Figure 6, Data Output with LC Setting at Code 3; added Figure 7, First Access Latency Configuration Revised Section 4.2.3, WAIT Signal Polarity (WT) Added Section 4.2.4, WAIT Signal Function Revised Section 4.2.5, Data Output Configuration (DOC) Added Figure 8, Data Output Configuration with WAIT Signal Delay Revised Table 13, Status Register DWS and PWS Description Revised entire Section 5.0, Program and Erase Voltages Revised entire Section 5.3, Enhanced Factory Programming (EFP) Revised entire Section 8.0, Flash Security Modes Revised entire Section 9.0, Flash Protection Register; added Table 15, Simultaneous Operations Allowed with the Protection Register Revised Section 10.1, Power-Up/Down Characteristics Revised Section 11.3, DC Characteristics. Changed ICCS,ICCWS, ICCES Specs from 18 A to 21A; changed ICCR Spec from 12 mA to 15 mA (burst length = 4) Added Figure 20, WAIT Signal in Synchronous Non-Read Array Operation Waveform Added Figure 21, WAIT Signal in Asynchronous Page-Mode Read Operation Waveform Added Figure 22, WAIT Signal in Asynchronous Single-Word Read Operation Waveform Revised Figure 23, Write Waveform Revised Section 12.4, Reset Operations Clarified Section 13.2, SRAM Write Operation, Note 2 Revised Section 14.0, Ordering Information Minor text edits v 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 1.0 Product Introduction 1.1 Document Purpose This document contains information pertaining to the 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O and SRAM. Section 1.0 provides a product introduction. Section 2.0 provides a product description. Section 3.0 describes general device operations. Sections 4.0 through 9.0 describe the flash functionality. Section 10 describes device power and reset considerations. Section 11.0 describes the device electrical specifications. Section 12.0 describes the flash AC characteristics. Section 13.0 describes the SRAM AC characteristics. Section 14.0 describes ordering information. 1.2 Nomenclature * Block: a group of flash bits that share common erase circuitry and erase simultaneously. * Partition: Partition is a group of blocks that share erase and program circuitry and a common status register. If one block is erasing or one word is programming, only the status register, rather than array data, is available when any address within the partition is read. * * * * * Preliminary Main Block: a flash block of 32-Kwords. Parameter Block: a flash block of 4-Kwords. Main Partition: a partition that only contains main blocks. Parameter Partition: a partition that contains both main and parameter blocks. Top/Bottom Parameter Device: parameter blocks are located at the top/bottom of the flash memory map. A top/bottom parameter partition contains 15 blocks; 7 main blocks and 8 parameter blocks. 1 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 2.0 Product Description 2.1 Product Overview Intel(R) 1.8 Volt Wireless Flash Memory with 3 Volt I/O and SRAM combines flash and SRAM into one package. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O divides the flash memory into many separate 4-Mbit partitions. By doing this, the device can perform simultaneous readwhile-write or read-while-erase operations. With this new architecture, the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O can read from one partition while programming or erasing in another partition. This read-while-write or read-while-erase capability greatly increases data throughput performance. Each partition contains eight 32-Kword blocks, called "main blocks." However, for a top or bottom parameter device, the upper or lower 32-Kword block is segmented into eight, separate 4-Kword blocks, called "parameter blocks." Parameter blocks are ideally suited for frequently updated variables or boot code storage. Both main and parameter blocks support page and burst mode reads. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O also incorporates a new Enhanced Factory Programming (EFP) mode. In EFP mode, this device provides the fastest NOR flash factory programming time possible at 3.5 s per data word. This feature can greatly reduce factory flash programming time and thereby increase manufacturing efficiency. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O offers both hardware and software forms of data protection. Software can individually lock and unlock any block for "on-the-fly" run-time data protection. For absolute data protection, all blocks are locked when the VPP voltage falls below the VPP lockout threshold. Upon initial power up or return from reset, the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O defaults to page mode. To enable burst mode, write and configure the configuration register. While in burst mode, the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O is synchronized with the host CPU. Additionally, a configurable WAIT signal can be used to provide easy flash-toCPU synchronization. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O maintains compatibility with Intel(R) Command User Interface (CUI), Common Flash Interface (CFI), and Intel(R) Flash Data Integrator (FDI) software tools. CUI is used to control the flash device, CFI is used to obtain specific product information, and FDI is used for data management. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM offers two low-power savings features: Automatic Power Savings (APS) and standby mode. The flash device automatically enters APS following the completion of any read cycle. Flash and SRAM standby modes are enabled when the appropriate chip select signals are de-asserted. Finally, the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O provides program and erase suspend/resume operations to allow system software to service higher priority tasks. It offers a 128-bit protection register that can be used for unique device identification and/or system security purposes. Combined, all these features make the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM an ideal solution for any high-performance, low-power, board-constrained memory application. 2 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 2.2 Package Diagram Figure 1. 80-Ball Matrix, 0.80 mm Ball Pitch, Stacked-CSP for 32/4-, 64/8- and 128/TBD-Mbit Devices (Flash + SRAM) 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A B B DU DU A4 A18 DU DU DU DU A21 A11 A11 A21 A22 A12 A12 A22 F-VSS A9 A13 A13 A9 A20 A10 A15 A15 A10 A8 A14 A16 A16 DU DU A19 A18 A4 S-VSS A23 S-LB# A5 A24 A17 A3 A7 A2 S-UB# A6 A1 C C A19 SWE# S-VSS F-CLK F-CLK SWE# S-VSS D D A5 S-LB# A23 S-VSS S-CS2 S-VCC S-VCC S-CS2 E E A3 A17 A24 F-VPP F-VCC A2 A7 A25 F-WP# F-ADV# F-VSS F-VCC F-VPP A20 F-ADV# F-WP A8 F-WE# F-RST# DQ13 DQ5 DQ10 DQ2 DQ8 A0 DQ1 DQ0 S-OE# F F A25 G D G A1 A6 S-UB# F-RST# F-WE# A0 DQ8 DQ2 DQ10 A14 H H DQ5 F-WAIT DU DU DQ7 DU DU DQ7 DQ14 DQ12 DQ3 DQ6 DQ15 DU DU DQ15 DQ6 DQ4 DQ11 DQ9 F-VCCQ S-Vss S-VSS F-VCCQ DU S-VCC S-VCC DU DU S-VSS F-VSS F-VCC F-VCCQ F-VSSQ DQ13 F-WAIT J J S-OE# DQ0 DQ1 DQ3 S-CS1# F-OE# DQ9 DQ11 F-CE# DU DU S-VSS F-VSSQ F-VCCQ DQ12 DQ14 K K DQ4 F-OE S-CS1# L L S-VCC S-VCC DU F-VCC S-VSS F-VSSQ F-CE# M M F-VSS S-VSS F-VSSQ S-VSS S-VSS N N P DU DU Top View - Ball Side Down Complete Ink Mark Not Shown P Bottom View - Ball Side Up DU DU DU DU DU DU E NOTES: 1. On lower density devices, upper address balls can be treated as no connects. For example, on a 32-Mbit device, A23-21 will be no connects. Preliminary 3 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 2. 56-Ball Matrix, 0.75 mm Ball Pitch, VF BGA Package and BGA* Package for the 32Mbit and 64-Mbit Discrete Devices 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A A11 A8 vSS vCC vPP A18 A6 A4 A4 A6 A18 vPP vCC VSS A8 A11 A12 A9 A20 CLK RST# A17 A5 A3 A3 A5 A17 RST# CLK A20 A9 A12 A13 A10 ADV# WE# A19 A7 A2 A7 A19 B B C C A21 A2 WE# ADV# A21 A10 A13 D D A15 A14 WAIT A16 D12 WP# A 22 A1 A1 A22 WP# D12 A16 WAIT A14 A15 E E VCCQ D15 D6 D4 D2 D1 CE# A0 A0 CE# D1 D2 D4 D6 D15 VCCQ VSS D14 D13 D11 D10 D9 D0 OE# OE# D0 D9 D10 D11 D13 D14 VSS D7 VSSQ D5 vCC D3 VCCQ D8 V SSQ V SSQ D8 VCCQ D3 V CC D5 VSSQ D7 F F G G Top View - Ball Side Down Complete Ink Mark Not Shown Bottom View - Ball Side Up NOTE: 1. All balls will be populated; however, addresses A21 and A22 will be NC. 2.3 Table 1. 4 Package Dimensions Package Outline Dimensions Package Type Device Density Dimension-D ( 0.1 mm) Dimension-E ( 0.1 mm) Height (max.) (mm) VF BGA 32 Mbit 7.7 mm 9.0 mm 1.0 mm BGA* 64 Mbit 7.7 mm 9.0 mm 1.0 mm Stacked-CSP 32/4, 64/8 14.0 mm 8.0 mm 1.4 mm Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 2.4 Signal Descriptions Table 2. Symbol A25-0 DQ15-0 Type I I/O Signal Descriptions (Sheet 1 of 2) Name and Function ADDRESS: Device address. Addresses are internally latched during read and write cycles. 32-Mbit flash: A20-0; 64-Mbit flash: A21-0; 128-Mbit flash: A22-0; 4-Mbit SRAM: A17-0; 8-Mbit SRAM: A18-0 DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs data during query, id reads, memory, status register, protection register, and configuration code reads. Data signals float when the chip or outputs are deselected. Data is internally latched during writes. Query accesses and status register accesses use DQ0-DQ7. All other accesses use DQ0-DQ15. ADV# I FLASH ADDRESS VALID: Internally latches addresses. In page mode, addresses are internally latched on the rising edge of ADV#. In burst mode, address internally latched on the rising edge of ADV# or rising/ falling edge of CLK, whichever occurs first. Connect ADV# to GND when the flash device is operating in asynchronous mode only. CE# I FLASH CHIP ENABLE: Enables/disables flash device. CE#-low enables the device. CE#-high disables the device and places the device into standby mode. CE# high places data and WAIT signals at a High-Z level. S-CS1# I SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders and sense amplifiers. S-CS1# is active low. S-CS1# high deselects the SRAM memory device and reduces power consumption to standby levels. S-CS2 I SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders and sense amplifiers. S-CS2 is active high. S-CS2 low deselects the SRAM memory device and reduces power consumption to standby levels. CLK I FLASH CLOCK: Synchronizes the device to the system bus frequency. (Used only in burst mode.) OE# I FLASH OUTPUT ENABLE: Enables/disables device output buffers. OE# low enables the device output buffers. OE# high disables the device output buffers and places all outputs at a High-Z level. S-OE# I SRAM OUTPUT ENABLE: Activates the SRAM outputs through the data buffers during a read operation. S-OE# is active low. RST# I FLASH RESET: Enables/disables device operation. RST# low initializes internal circuitry and disables device operation. RST# high enables device operation. WAIT O FLASH WAIT: Indicates valid data in burst read mode. WAIT is at High-Z until the configuration register bit CR.10 is set, which also determines its polarity when asserted. WE# I FLASH WRITE ENABLE: Enables/disables device write buffers. WE# low enables the device write buffers. Data is latched on the rising edge of WE#. WE# high disables the device write buffers. S-WE# I SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low. S-UB# I SRAM UPPER BYTE ENABLE: Enables the upper bytes for SRAM (DQ15-8). S-UB# is active low. S-UB# and S-LB# must be tied together to restrict x16 mode. S-LB# I SRAM LOWER BYTE ENABLE: Enables the lower bytes for SRAM (DQ7-0). S-LB# is active low. S-UB# and S-LB# must be tied together to restrict x16 mode. WP# I FLASH WRITE PROTECT: Enables/disables the device lock-down function. WP# low enables the lockdown mechanism and blocks marked lock-down cannot be unlocked by system software. WP# high disables the lock-down mechanism and blocks marked lock-down can be unlocked by system software. VPP Pwr FLASH PROGRAM/ERASE POWER: Hardware erase and program protection. A valid VPP voltage on this ball allows erase or programming. Memory contents cannot be altered when VPP < VPPLK. Block erase and program at invalid VPP voltages should not be attempted. Set VPP = VCC for in-system read, program, and erase operations. VPP must remain above VPP1Min to perform in-system operations. VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be VPP2 for a cumulative total, not to exceed 80 hours maximum. Extended use of this ball at VPP2 may reduce block cycling capability. VCC Pwr FLASH POWER SUPPLY: Flash operations at invalid VCC voltages should not be attempted. VCCQ Pwr FLASH OUTPUT POWER SUPPLY: Enables all input and output signals to be driven at VCCQ. Preliminary 5 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Table 2. Signal Descriptions (Sheet 2 of 2) Symbol Type Name and Function VSS Pwr FLASH POWER SUPPLY GROUND: Balls for internal device circuitry must be connected to system ground. VSSQ Pwr FLASH OUTPUT POWER SUPPLY GROUND: Balls for internal device circuitry must be connected to system ground. S-VCC Pwr SRAM POWER SUPPLY: Device operations at invalid S-VCC voltages should not be attempted. S-VSS Pwr SRAM GROUND: Balls for all internal device circuitry must be connected to system ground. DU DON'T USE: Do not use this ball. This ball should not be connected to any power supplies, control signals and/or any other ball and must be floated. NC NO CONNECT: No internal connection. Can be driven or floated. NOTE: For non-discrete devices, all flash signals are prefixed with F_ before its signal's name. 2.5 Block Diagram Figure 3. 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O and SLRAM Block Diagram VCC VCCQ VPP VSS VSSQ CE# ADV# OE# CLK WAIT WE# 32, 64, 128 Mbit RST# Flash Memory WP# A 18-20 / A 19-21 or A 19-22 DQ15-0 A0-17 / A 0-18 S-SC 1# S-SC 2 4 or 8 Mbit S-OE# SRAM S-WE# S-LB# S-UB# S-V CC 2.6 S-V SS Flash Memory Map The 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O memory is divided into separate partitions to support the read-while-write/erase function. Each partition is 4-Mbits in size and can operate independently from other partitions. 6 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 A 32-Mbit device will have eight partitions; a 64-Mbit device will have 16 partitions; a 128-Mbit device will have 32 partitions. Each main block is 32-Kword in size. The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O supports CPUs that boot from either the top or bottom of the flash memory map. A top parameter flash device has the highest addressable 32-Kword block divided into eight smaller blocks. Conversely, a bottom parameter flash device has the lowest addressable 32-Kword block divided into eight smaller blocks. Each of these eight 4Kword blocks are called parameter blocks. Parameter blocks are useful for frequently stored data variables. Their smaller block size allows them to erase faster than main blocks. Page- and burstmode reads are also permitted in all blocks and across all partition boundaries. It should be mentioned that the SRAM does not adhere to this multi-partition architecture. The SRAM memory is organized as a single memory array. Preliminary 7 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 4. Flash Memory Map 32 Mbit Top Parameter Device divides the highest 32-Kword main block into eight 4-Kword parameter blocks xxF000 - xxFFFF xxE000 - xxEFFF xxD000 - xxDFFF xxC000 - xxCFFF xxB000 - xxBFFF xA000 - xxAFFF xx9000 - xx9FFF xx8000 - xx8FFF Partition 7 8 Blocks Start - Stop Addr 1F8000 - 1FFFFF 1F0000 - 1F7FFF 1E8000 - 1EFFFF 1E0000 - 1E7FFF 1D8000 - 1DFFFF 1D0000 - 1D7FFF 1C8000 - 1CFFFF 1C0000 - 1C7FFF Partition 6 8 Main Blocks 180000 - 1BFFFF Partition 5 8 Main Blocks 140000 - 17FFFF 8 Main Blocks Start - Stop Addr F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF Partition 4 8 Main Blocks 100000 - 13FFFF Partition 3 8 Main Blocks C0000 - FFFFF Partition 2 8 Main Blocks 80000 - BFFFF Partition 1 8 Main Blocks 40000 - 7FFFF 64 Mbit Partition 15 8 Blocks Start - Stop Addr 3F8000 - 3FFFFF 3F0000 - 3F7FFF 3E8000 - 3E7FFF 3E0000 - 3E7FFF 3D8000 - 3D7FFF 3D0000 - 3D7FFF 3C8000 - 3CFFFF 3C0000 - 3C7FFF 28 Mbit Partition 14 8 Main Blocks 380000 - 3BFFFF 60 Mbit Partition 30 8 Main Blocks 780000 - 7BFFFF 124 Mbit 24 Mbit 20 Mbit 16 Mbit 12 Mbit 8 Mbit . . . . . . Partition 1 8 Main Blocks 40000 - 7FFFF 4 Mbit Bottom Parameter Device divides the lowest 32-Kword main block into eight 4-Kword parameter blocks 128 Mbit Partition 31 8 Blocks Start - Stop Addr 7F8000 - 7FFFFF 7F0000 - 7F7FFF 7E8000 - 7E7FFF 7E0000 - 7E7FFF 7D8000 - 7D7FFF 7D0000 - 7D7FFF 7C8000 - 7CFFFF 7C0000 - 7C7FFF Partition 0 8 Blocks Start - Stop Addr 38000 - 3FFFF 30000 - 37FFF 28000 - 2FFFF 20000 - 27FFF 18000 - 1FFFF 10000 - 17FFF 08000 - 0FFFF 00000 - 07FFF . . . . . . 8 Mbit 4 Mbit Partition 0 8 Blocks Start - Stop Addr 38000 - 3FFFF 30000 - 37FFF 28000 - 2FFFF 20000 - 27FFF 18000 - 1FFFF 10000 - 17FFF 08000 - 0FFFF 00000 - 07FFF 0 Partition 1 8 Main Blocks 40000 - 7FFFF 8 Mbit 4 Mbit Partition 0 8 Blocks Start - Stop Addr 38000 - 3FFFF 30000 - 37FFF 28000 - 2FFFF 20000 - 27FFF 18000 - 1FFFF 10000 - 17FFF 08000 - 0FFFF 00000 - 07FFF 0 7000 - 7FFF 6000 - 6FFF 5000 - 5FFF 4000 - 4FFF 3000 - 3FFF 2000 - 2FFF 1000 - 1FFF 0000 - 0FFF NOTES: 1. Partition size: 4 Mbit/256 Kword/512 Kbytes. 2. Main block size: 32 Kword/64 Kbytes. 3. Parameter block size: 4 Kword/8 Kbytes. 4. All partitions have 8 main blocks, except for top/bottom parameter partitions. 5. Top/bottom parameter partitions have 15 blocks, 7 main and 8 parameter. 8 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 3.0 Product Operations 3.1 Bus Operations The 1.8 Volt Intel(R) Wireless Flash Memory's on-chip Write State Machine (WSM) manages erase and program algorithms. The local CPU controls the in-system read, program, and erase operations of the flash device. Bus cycles to and from the flash device conform to standard microprocessor bus operations. RST#, CE#, OE#, WE#, and ADV# signals control the flash. WAIT informs the CPU of valid data during burst reads. S-OE#, S-WE#, S-CS1#, S-CS2, S-LB# and S-UB# control the SRAM. S-UB# and S-LB# must be tied together to restrict x16 mode. Table 3 summarizes bus operations. FLASH Standby 3 VIH VIH X X X High-Z Reset 3 VIL X X X X High-Z Write 4, 5 VIH VIL VIH VIL VIL Read 5 Output Disable 3 SRAM Standby and Data Retention Write Flash must be in High-Z Any Valid FLASH Mode Flash must be in High-Z High-Z DOUT High-Z Any Valid SRAM Mode High-Z High-Z High-Z High-Z 3, 6 5 SRAM must be in High-Z DQ High-Z [15:0] Valid X S-UB# S-LB#7 VIL VIH S-WE# VIH VIH S-OE# ADV# VIL VIL S-CS2 WE# VIL VIH S-CS1# OE# VIH 3 Read WAIT CE# 1,2, 5 Output Disable Mode RST# Bus Operations Note Table 3. SRAM must be in High Z DIN VIL VIH VIL VIH VIL DOUT VIL VIH VIH VIH X High-Z VIH X X X X High-Z X VIL X X X High-Z VIL VIH VIH VIL VIL DIN NOTES: 1. Manufacturer and device ID codes are accessed by Read ID Register command. 2. Query and status register accesses use only DQ7-0. All other accesses use DQ15-0. 3. X must be VIL or VIH for control signals and addresses. 4. Refer to Table 5, "Command Bus Definitions" on page 11 for valid DIN during a write operation. 5. Two devices may not drive the memory bus at the same time. 6. The SRAM can be placed into data retention mode by lowering the S-VCC to the VDR limit when in standby mode. 7. Always tie S-UB# and S-LB# together. 3.2 Flash Command Definitions Device operations are selected by writing specific commands to the Command User Interface (CUI). Table 4, "Command Code and Descriptions" on page 10 lists all possible command codes and descriptions. Table 5, "Command Bus Definitions" on page 11 further defines command bus cycle operations. Since commands are partition-specific, it is important to write commands within the target partition range. Multi-cycle command writes to the flash memory partition must be issued sequentially without intervening command writes. For example, an Erase Setup command to partition X must be immediately followed by the Erase Confirm command in order to be executed properly. The address given during the Erase Confirm command determines the location of the erase. If the Erase Preliminary 9 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Confirm command is given to partition X, then the command will be executed, and a block in partition X will be erased. Alternatively, if the Erase Confirm command is given to partition Y, the command will still be executed, and a block in partition Y will be erased. Any other command given to ANY partition prior to the Erase Confirm command will result in a command sequence error, which is posted in the status register. After the erase has successfully started in partition X or Y, read cycles can occur in any other partition. Mode Table 4. Instruction Code FFh Read 70h 90h 98h 50h Program 40h 10h 30h D0h Command Code and Descriptions (Sheet 1 of 2) Command Read Array Read Status Register Read ID Register, Read Configuration Register Read Query Register Clear Status Register Word Program Setup Alternate Word Program Setup Enhanced Factory Programming Setup Enhanced Factory Programming Confirm Description Places addressed partition in read array mode. Places addressed partition in read status register mode. A partition automatically enters the read status register mode after a valid Program/Erase command is executed. Puts the addressed partition in read device identifier mode. The device outputs manufacturer and device ID codes, configuration register settings, block lock status and protection register data. Data is output on DQ15-0. Puts the addressed partition in read query mode. The device outputs Common Flash Interface (CFI) information on DQ7-0. Clears status register bits 1, 3, 4 and 5. The WSM can set (1) and reset (0) bits 0, 2, 6 and 7. The preferred first bus cycle program command that prepares the WSM for a program operation. The second bus cycle command latches the address and data. A Read Array command is required to read array data after programming. Equivalent to a Word Program Setup command (40h). Activates Enhanced Factory Programming mode (EFP). The first bus cycle sets up the command. If the second bus cycle is a Confirm command (D0h), subsequent writes provide program data. All other commands are ignored once EFP mode begins. If the first command was Enhanced Factory Programming Setup (30h), the CUI latches the address, confirms command data, and prepares the device for EFP mode. Prepares the WSM for a block erase operation. The device erases the block addressed by the Erase Confirm command. If the next command is not Erase Confirm, the CUI Block Erase Setup D0h Erase Confirm B0h Program or Erase Suspend D0h Suspend Resume 60h Lock Setup 01h Lock Block D0h Unlock Block 2Fh Lock-Down Block Locking Suspend Erase 20h 10 (a) sets status register bits SR.4 and SR.5 to "1," (b) places the partition in the read status register mode (c) waits for another command. If the first command was Erase Setup (20h), the WSM latches address and data and erases the block indicated by the erase confirm cycle address. During program/erase, the partition responds only to Read Status Register, Program Suspend, and Erase Suspend commands. CE# or OE# toggle updates status register data. This command issued at any device address initiates suspension of the currently executing program/erase operation. The status register, invoked by a Read Status Register command, indicates successful operation suspension by setting (1) status bits SR.2 (program suspend) or SR.6 (erase suspend) and SR.7. The WSM remains in the suspend mode regardless of control signal states, except RST# = VIL. This command issued at any device address resumes suspended program or erase operation. Prepares the WSM lock configuration. If the next command is not Block-Lock, Unlock, or Lock-Down the WSM sets SR.4 and SR.5 to indicate command sequence error. If the previous command was Lock Setup (60h), the CUI locks the addressed block. After a Lock Setup (60h) command the CUI latches the address and unlocks the addressed block. If previously Locked-down, the operation has no effect. After a Lock Setup (60h) command, the CUI latches the address and locks-down the addressed block. Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Configuration Protection Mode Table 4. Command Code and Descriptions (Sheet 2 of 2) Instruction Code Command Description C0h Prepares the WSM for a protection register program operation. The second bus cycle Protection Program latches address and data. To read array data after programming, issue a Read Array Setup command. 60h Configuration Setup 03h Set Configuration Register Prepares the WSM for device configuration. If Set Configuration Register is not the next command, the WSM sets SR.4 and SR.5 to indicate command sequence error. If the previous command was Configuration Setup (60h), the WSM writes data into the configuration register via A15-0. Following a Set Configuration Register command, subsequent read operations access array data. NOTE: Unassigned instruction codes should not be used. Intel reserves the right to redefine these codes for future functions. CONFIG- PROTECURATION TION LOCK PROGRAM ERASE READ Mode Table 5. Command Bus Definitions Command Bus Cycles First Bus Cycle Second Bus Cycle Oper Addr(1) Data(2,3) Oper Addr(1) Data(2,3) Read Array 1 Write PnA FFh Read ID Register 2 Write XnA 90h Read XnA+IA IC Read Query Register 2 Write PnA 98h Read PnA+QA QD Read Status Register 2 Write PnA 70h Read BA SRD Clear Status Register 1 Write XX 50h Block Erase 2 Write BA 20h Write BA D0h Word Program 2 Write WA 40h/10h Write WA WD Enhanced Factory Program >2 Write WA 30h Write WA D0h Program/Erase Suspend 1 Write XX B0h Program/Erase Resume 1 Write XX D0h Lock Block 2 Write BA 60h Write BA 01h Unlock Block 2 Write BA 60h Write BA D0h Lock-Down Block 2 Write BA 60h Write BA 2Fh Protection Program 2 Write PA C0h Write PA PD Lock Protection Program 2 Write LPA C0h Write LPA FFFDh Set Configuration Register 2 Write CD 60h Write CD 03h NOTES: 1. First cycle command addresses should be the same as the operation's target address. Examples: the firstcycle address for the Read ID Register command should be the same as the Identification Code address (IA); the first cycle address for the Program command should be the same as the word address (WA) to be programmed; the first cycle address for the Erase/Program Suspend command should be the same as the address within the block to be suspended; etc. XX = Any valid address within the device. IA = Identification code address. BA = Address within the block. LPA = Lock Protection Address is obtained from the CFI (via the Read Query command). Intel(R)1.8 Volt Preliminary 11 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Wireless Flash Memory Flash Memory family's LPA is at 0080h. PA = User programmable 4-word protection address in the device identification plane. PnA = Address within the partition. XnA = Base Address where X can be partition, main block or parameter block. See Figure 11, "Device Identification Codes" on page 21 for details. QA = Query code address. WA = Word address of memory location to be written. 2. SRD = Data read from the status register on DQ7-0. WD = Data to be written at location WA. IC = Identifier code data. PD =User programmable 4-word protection data. QD = Query code data on DQ7-0. CD = Configuration register code data presented on device addresses A15-0. AMAX-16 address bits can select any partition. See Table 6, "Configuration Register Bits" on page 13 for configuration register bits descriptions. 3. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. . 4.0 Flash Read Modes 4.1 Read Array 4.1.1 Asynchronous Mode The 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O supports asynchronous reads. An asynchronous read is executed by implementing a read operation without the use of the CLK signal. During an asynchronous read operation, the CLK signal is ignored. If asynchronous reads will be the only read mode of operation, it is recommended that the CLK signal be held at a valid VIH level. Page mode is the default read mode after power-up or reset. A page-mode read outputs 4 words of asynchronous data; however, by manipulating certain control signals, the device can be made to output less than 4 words. After power-up or reset, it is not necessary to execute the Read Array command before accessing the flash memory. However, to perform a flash read at any other time, it is necessary to execute the Read Array command before accessing the flash memory. Page mode is permitted in all blocks, across all partition boundaries and operates independent of VPP. A single-word read can be used to access register information. During asynchronous reads, the address is latched on the rising edge of ADV#. Upon completion of reading the array, the device automatically enters an Automatic Power Savings (APS) mode. APS mode consumes power comparable to standby mode. 4.1.2 Synchronous Mode The 1.8 Volt Intel(R) Wireless Flash Memory supports synchronous reads. A synchronous read is executed by implementing a read operation with the use of the CLK signal. During a synchronous read operation, the CLK signal edge (rising or falling) controls flash array access. A burst-mode read is synchronized to the CLK signal and outputs a 4-, 8- or continuous-word data stream based on configuration register settings. However, by manipulating certain control signals, the device can be made to output less then 4-, 8- or continuous-words. 12 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Burst mode is not the default mode after power-up or a device reset. To perform a burst-mode read, the configuration register must be set. To set the configuration register, refer to Section 4.2, "Set Configuration Register (CR)" on page 13. After setting the configuration register, if the first device operation is a burst-mode read, it is not necessary to execute the Read Array command before accessing the flash memory. However, to perform a flash read at any other time, it is necessary to execute the Read Array command before accessing the flash memory array. Burst mode is permitted in all blocks, across all partition boundaries and operates independently of VPP. A single-word burst-mode read cannot be used to access register information. In burst mode, the address is latched by either the rising edge of ADV# or the rising edge of CLK with ADV# low, whichever occurs first. Upon completion of reading the array, the device automatically enters an Automatic Power Savings (APS) mode. APS mode consumes power comparable to standby mode. 4.2 Set Configuration Register (CR) The configuration register is 16 bits wide. This register is used to configure the burst mode parameters. Therefore, if using page mode, it is not necessary to set this register. To set the configuration register, execute the Set Configuration Register command. The 16 bits of data used by this command must be placed on address lines A15-0. All other address lines must be held low (VIL). After setting the configuration register, if the first device operation is a flash burst-mode read, it is not necessary to execute the Read Array command before accessing the flash memory. However, to perform a burst-mode read at any other time, it is necessary to execute the Read Array command before accessing the flash memory. Table 6. Configuration Register Bits Configuration Register Bits2 A15 A14 RM 1 R 0 A13 LC2-0 A12 A11 A10 WT A9 DOC A8 WC A7 BS A6 CC A5 A4 1 1 R 0 R A3 A2 BW BL2-0 A1 A0 0 NOTES: 1. `R' bits are reserved bits. These bits and all other address lines must be set low. 2. On power-up or return from reset, all bits are set to "1." Preliminary 13 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 . Table 7. Configuration Register Bit Settings Bit Name Read Mode (RM) CR.15 First Latency Count (LC2-0) CR.13 - CR.11 WAIT Polarity (WT) CR.10 Data Output Configuration (DOC) CR.9 WAIT Configuration (WC) CR.8 Burst Sequence (BS) CR.7 Clock Configuration (CC) CR.6 Burst Wrap (BW) CR.3 Burst Length (BL2-0) CR.2 - CR.0 4.2.1 Setting 0 = Burst or synchronous mode. 1 = Page or asynchronous mode. Code 0 = 000. Reserved. Code 1 = 001. Reserved. Code 2 = 010. Code 3 = 011. Code 4 = 100. Code 5 = 101. Code 6 = 110. Reserved. Code 7 = 111. Reserved. 0 = active low signal. 1 = active high signal 0 = hold data for one clock cycle. 1 = hold data for two clock cycles. 0 = WAIT signal asserted during 16-word row boundary transition. 1 = WAIT signal assert one data cycle before 16-word row boundary transition. 0 = Intel burst sequence. 1 = linear burst sequence. 0 = falling edge of clock. 1 = rising edge of clock. 0 = Wrap enabled. 1 = Wrap disabled. 001 = 4 Word burst mode. 010 = 8 Word burst mode. 011 = Reserved. 111 = Continuous burst mode. Read Mode (RM) CR.15 sets the flash read mode. The two read modes are page mode (default mode) and burst mode. The flash device can only be configured for one of these modes at any one time. 4.2.2 First Latency Count (LC2-0) The First Access Latency Count configuration tells the device how many clocks must elapse from ADV#-high (VIH) before the first data word should be driven onto its data pins. The input clock frequency determines this value. See Table 6, "Configuration Register Bits" on page 13 for latency values. Figure 7, "First Access Latency Configuration" on page 16 shows data output latency from ADV#-active for different latencies. Use these equations to calculate First Access Latency Count: {1/ Frequency} = CLK Period (1) n (CLK Period) tAVQV (ns) + tADD-DELAY (ns) + tDATA (ns) (2) n-2 = First Access Latency Count (LC) * 14 (3) Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 n: # of Clock periods (rounded up to the next integer) *Must use LC = n - 1 when the starting address is not aligned to a four-word boundary and CR.3 = 1 (No Wrap). Table 8. First Latency Count (LC) Aligned to 4-word Boundary Wait Asserted on 16-Word Boundary Crossing disabled no yes, occurs on every occurrence disabled yes no 4 or 8 enabled no no n-2 4 or 8 enabled yes no n-1 continuous X X yes, occurs once LC Setting Mode Wrap n-1 4 or 8 n-2 4 or 8 n-2 Figure 5. Word Boundary Word 0 - 3 0 1 2 Word 4 - 7 3 4 5 6 Word 8 - B 7 8 9 A Word C - F B C D E F 16 Word Boundary 4 Word Boundary NOTE: 1. The 16-word boundary is the end of device word-line. Parameters defined by CPU: tADD-DELAY = Clock to CE#, ADV#, or Address Valid whichever occurs last. tDATA = Data set up to Clock. Parameters defined by flash: tAVQV = Address to Output Delay. Example: CPU Clock Speed = 52 MHz tADD-DELAY = 6 ns (typical speed from CPU) (max) tDATA = 4 ns (typical speed from CPU) (min) tAVQV = 70 ns (from AC Characteristic - Read Only Operations Table) From Eq. (1): 1/52 (MHz) = 19.2 ns From Eq. (2) n(19.2 ns) 70 ns + 6 ns + 4 ns n(19.2 ns) 80 ns n 80/19.2 = 4.17 = 5 (Integer) From Eq. (3) n-2=5-2=3 First Access Latency Count Setting to the CR is Code 3. (Figure 6, "Data Output with LC Setting at Code 3" on page 16 displays example data) Preliminary 15 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 The formula tAVQV (ns) + tADD-DELAY (ns) + tDATA (ns) is also known as initial access time. Figure 6 shows the data output available and valid after four clocks from ADV# going low in the first clock period with the LC setting at 3. Figure 6. Data Output with LC Setting at Code 3 tADD CLK (C) tDATA 1st 3rd 2nd 4th 5th CE# ADV# AMAX-0 Valid Address Code 3 Valid Output High Z DQ15-0 (D/Q) Valid Output R103 Figure 7. First Access Latency Configuration CLK [C] Address [A] Valid Address ADV# [V] Code 0 (Reserved) DQ 15-0 [D/Q] Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Code 1 (Reserved) Valid Output DQ 15-0 [D/Q] DQ 15-0 [D/Q] DQ 15-0 [D/Q] DQ 15-0 [D/Q] DQ 15-0 [D/Q] DQ 15-0 [D/Q] DQ 15-0 [D/Q] Code 2 Code 3 Code 4 Code 5 Code 6 (Reserved) Code 7 (Reserved) Valid Output FREQCONF.WMF 4.2.3 WAIT Signal Polarity (WT) The WAIT signal polarity is set by register bit CR.10 (WT). * When CR.10 = 0, WAIT is active low. A `0' on the WAIT signal indicates the "asserted" state. 16 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 * When CR.10 = 1, WAIT is active high. A `1' on the WAIT signal indicates the "asserted" state. * WAIT signal "asserted" means that the WAIT signal is indicating a "wait" condition. * WAIT signal "deasserted" means that the WAIT signal is NOT indicating a "wait" condition (i.e., the bus is valid). WAIT is High-Z until the device is active (CE# = VIL). In synchronous read array mode, when the device is active (CE# = VIL) and data is valid, CR.10 (WT) determines if WAIT goes to VOH or VOL. The WAIT signal is only "deasserted" when data is valid on the bus. Invalid data drives the WAIT signal to "asserted" state. In asynchronous page mode, WAIT is always set to an "asserted" state (CR.10 = 1) 4.2.4 WAIT Signal Function The WAIT signal indicates data valid when the device is operating in synchronous burst mode (CR.15 is set to "0"), and when addressing a partition that is currently in read array mode. The WAIT signal is only "deasserted" when data is valid on the bus. The WAIT signal polarity is set by CR.10. When the device is operating in synchronous non-read-array mode, such as read status, read ID, or read query, WAIT is set to an "asserted" state as determined by CR.10. Figure 20 on page 46 displays WAIT Signal in Synchronous Non-Read Array Operation Waveform. When the device is operating in asynchronous page mode or asynchronous single word read mode, WAIT is set to an "asserted" state as determined by CR.10. See Figure 21, "WAIT Signal in Asynchronous Page-Mode Read Operation Waveform" on page 47 and Figure 22, "WAIT Signal in Asynchronous Single-Word Read Operation Waveform" on page 48. From a system perspective, the WAIT signal will be in the asserted state (based on CR.10) when the device is operating in synchronous non-read array mode (such as Read ID, Read Query, or Read Status), or if the device is operating in asynchronous mode (CR.15 is set to "1"). In these cases, the system software should ignore (mask) the WAIT signal, as it does not convey any useful information about the validity of what is appearing on the data bus. Systems may tie several components' WAIT signals together. 4.2.5 Data Output Configuration (DOC) The Data Output Configuration bit (CR.9) determines whether a data word remains valid on the data bus for one or two clock cycles. The processor's minimum data set-up time and the flash memory's clock-to-data output delay determine whether one or two clocks are needed. If the Data Output Configuration is set at one-clock data hold, this corresponds to a one-clock data cycle; if the Data Output Configuration is set at two-clock data hold, this corresponds to a twoclock data cycle. This configuration bit's setting depends on the system and CPU characteristics. Refer to Figure 8, "Data Output Configuration with WAIT Signal Delay" on page 18 for clarification. A method for determining what this configuration should be set at is shown below: To set the device at one clock data hold for subsequent reads, the following condition must be satisfied: tCHQV (ns) + tDATA (ns) One CLK Period (ns) Preliminary 17 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 As an example, a clock frequency of 52 MHz will be used. The clock period is 19.2 ns. This data is applied to the formula above for the subsequent reads assuming the data output hold time is one clock: 14 ns + 4 ns 19.2 ns This equation is satisfied and data output will be available and valid at every clock period. If tDATA is long, hold for two cycles. Now assume the clock frequency is 66 MHz. This corresponds to a 15 ns period. The initial access time is calculated to be 80 ns (LC 4). This condition satisfies tAVQV (ns) + tADD-DELAY (ns) + tDATA (ns) = 70 ns + 6 ns + 4 ns = 80 ns, as shown above in the First Access Latency Count equations. However, the data output hold time of one clock violates the one-clock data hold condition: tCHQV (ns) + tDATA (ns) One CLK Period 14 ns + 4 ns = 18 ns is not less than one clock period of 15 ns. To satisfy the formula above, the data output hold time must be set at 2 clocks to correctly allow for data output setup time. This formula is also satisfied if the CPU has tDATA (ns) 1 ns, which yields: 14 ns + 1 ns 15 ns In page mode reads, the initial access time can be determined by the formula: tADD-DELAY (ns) + tDATA (ns) + tAVQV (ns) and subsequent reads in page mode are defined by: tAPA (ns) + tDATA (ns) (minimum time) Figure 8. Data Output Configuration with WAIT Signal Delay CLK [C] WAIT (CR.8 = 1) Note 1 tCHQV WAIT (CR.8 = 0) 1 CLK Data Hold Note 1 Valid Output DQ15-0 [Q] WAIT (CR.8 = 0) WAIT (CR.8 = 1) Valid Output Valid Output Note 1 tCHTL/H tCHQV 2 CLK Data Hold DQ15-0 [Q] Note 1 Valid Output Valid Output Note1: WAIT shown active high (CR.10 = 1) 4.2.6 WAIT Configuration (WC) CR.8 sets the WAIT signal delay. The WAIT signal delay determines when the WAIT signal is asserted. The WAIT signal can be asserted either one clock before or at the time of the misaligned 16-word boundary crossing. An asserted WAIT signal indicates invalid data on the data bus. 18 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 In synchronous mode, WAIT is active when CE# is asserted. The WAIT signal is asserted if a burst-mode read is misaligned to a 4-word boundary. By misaligned, we imply that the address must be on a mod-4 boundary; such as xx00h, xx04h, xx08h or xx0Ch. If the address is aligned to a 4-word boundary, the "delay" will never be seen. Also, a "delay" will only occur once per burstmode read sequence. When a misaligned burst-mode read crosses a 16-word boundary, the device must deselect one row in order to select the next row. It is this selecting/de-selecting (or energizing/ de-energizing) of memory rows that causes the device to "delay" output data. It is the assertion of the WAIT signal that informs the interfacing processor of this pending flash "delay." During the "delay," subsequent data reads are prohibited. The WAIT signal is asserted depending on the burst starting address and latency count. If the starting address is aligned to the 4-word boundary, a delay will not occur. If the starting address is aligned to the end of a 4-word boundary, a delay equal to one clock cycle less than the latency count will occur (worst case scenario). See Table 9, "WAIT Delay" on page 19. If the starting address falls between, the delay will be dependent upon the latency count value and the starting address as indicated in Table 9. In 4- and 8-word burst modes with burst wrap enabled, the device will not assert the WAIT signal. However, with the burst wrap disabled, the flash device will assert the WAIT signal if a burst-mode read is misaligned and crosses a 16-word boundary. With wrap disabled, the burst mode will read 4 or 8 consecutive words based on the initial address. If the initial address is aligned on a mod-4 boundary, the WAIT signal will not be asserted. However, if the initial address is misaligned on a mod-4 boundary and crosses the 16-word boundary limit, the WAIT signal will be asserted. In continuous-word burst mode, the burst wrap feature does not apply and the WAIT signal is only asserted on the first 16-word boundary crossing. The WAIT signal is inactive or at a High-Z state when accessing register information. Table 9. 4.2.7 WAIT Delay Starting Burst Address WAIT Delay in Clock Cycles After Crossing 16-Word Boundary 4-Word Boundary xx0h, xx4h, xx8h, xxCh No Delay Start of Boundary xx1h, xx5h, xx9h, xxDh LC - 3 xx2h, xx6h, xxAh, xxEh LC - 2 xx3h, xx7h, xxBh, xxFh LC - 1 End of Boundary Burst Sequence (BS) CR.7 sets the burst sequence. The burst sequence determines the 4- or 8-word output order. In 4- or 8-word burst modes, the burst sequence is defined as either linear or Intel. In continuous burst mode, the burst sequence is always linear. The burst sequence depends on the interfacing processor's characteristics. Preliminary 19 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Table 10. Sequence and Burst Length Burst Addressing Sequence (Decimal) Start Addr (Decimal) 4.2.8 Wrap (CR.3) 4-Word Burst Length (CR2-0 = 001) 8-Word Burst Length (CR2-0 = 010) Continuous Burst (CR2-0 = 111) Linear Intel Linear Intel Linear 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-... 0 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-... 2 0 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-... 3 0 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-... 5-6-7-8-9-10-11-... 6 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-... 7 0 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-... ... NA 0-1-2-3-4-5-6-... 1 1 1-2-3-4 NA 1-2-3-4-5-6-7-8 NA 1-2-3-4-5-6-7-... 2 1 2-3-4-5 NA 2-3-4-5-6-7-8-9 NA 2-3-4-5-6-7-8-... 3 1 3-4-5-6 NA 3-4-5-6-7-8-9-10 NA 3-4-5-6-7-8-9-... 4 1 4-5-6-7-8-9-10-11 NA 4-5-6-7-8-9-10-... 5 1 5-6-7-8-9-10-11-12 NA 5-6-7-8-9-10-11-... 6 1 6-7-8-9-10-11-12-13 NA 6-7-8-9-10-11-12-... 7 1 7-8-9-10-11-12-1314 NA 7-8-9-10-11-12-13-... ... ... 0-1-2-3-4-5-6-7 ... NA ... 0-1-2-3 ... 1 ... 0 ... 15-16-17-18-19-20-21... ... 0 ... 15 ... 14-15-16-17-18-19-20... ... 0 ... 14 ... ... 4-5-6-7-8-9-10-... 5-4-7-6-1-0-3-2 ... 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 ... 4-5-6-7-0-1-2-3 ... 0 0 ... 4 5 ... 0 1 ... 0 14 1 14-15-16-17-18-19-20... 15 1 15-16-17-18-19-20-21... Clock Configuration (CC) CR.6 sets the clock configuration. The clock configuration determines which edge of the clock the flash device will respond to while in burst mode. The device can be configured to either track on the rising or falling edge of the clock. 20 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 4.2.9 Burst Wrap (BW) CR.3 sets the burst wrap. The burst wrap determines how the device will handle a burst-mode read that crosses a 16-word row boundary. Wrap can be set to have either the burst mode wrap around to the same row or have the burst read consecutive addresses. Wrap applies to 4- and 8-word burst modes only. Wrap has no effect in continuous burst mode. In 4- and 8-word burst mode with wrap enabled, the WAIT signal will not be asserted. In 4- and 8word burst mode with wrap disabled, the WAIT signal will be asserted only if a 16-word row boundary is crossed. 4.2.10 Burst Length (BL2-0) CR.2-CR.0 sets the burst length. The burst length determines the maximum number of consecutive words the device will output during a burst-mode read. 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O supports 4-, 8- and continuous-word burst lengths. 4.3 Read Query Register The query plane comes to the foreground and occupies a 4-Mbit address range at the partition supplied by the Read Query command address. The mode outputs Common Flash Interface (CFI) data when partition addresses are read. Appendix C, "Common Flash Interface" on page 68 shows query mode information and addresses. Issuing a Read Query command to a partition that is programming or erasing places that partition's outputs in read query mode while the partition continues to program or erase in the background. The Read Query command is subject to read restrictions dependent on the parameter partition availability. Refer to Table 15, "Simultaneous Operations Allowed with the Protection Register" on page 32 for details. 4.4 Read ID Register The Identification (ID) Register contains various product information, such as manufacturer ID, device ID, block lock status, protection register information, and configuration register settings. To obtain any information from the ID register, execute the Read ID Register command. Information contained in this register can only be accessed by executing a single-word asynchronous read. Table 11. Device Identification Codes Address(1,2,3) Item Manufacturer Code PBA + 000000h 32 Mbit Device Code: 64 Mbit 128 Mbit -T -B -T -B -T -B PBA + 000001h PBA + 000001h PBA + 000001h Data 0089h 8852h 8853h 8854h 8855h 8856h 8857h Block Lock Configuration(4) * Block Is Unlocked * Block Is Locked * Block Is Not Locked-Down * Block Is Locked-Down Preliminary MBBA + 000002h or PBBA + 000002h, depends on block DQ0 = 0 DQ0 = 1 DQ1 = 0 DQ1 = 1 21 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Table 11. Device Identification Codes Address(1,2,3) Data Configuration Register Settings PBA + 000005h CD(5) Protection Register Lock Status PBA + 000080h PR-LK(6) PBA +000081h - 000088h PR(7) Item Protection Register Data NOTES: 1. PBA = Partition Base Address. PBA = AMAX - 18. 2. MBBA = Main Block Base Address. MBBA = AMAX - 15. 3. PBBA = Parameter Block Base Address. PBBA = AMAX - 12. 4. See the Block Lock Status section for valid lock status. 5. CD = Configuration Register Settings. 6. PR-LK = Protection Register Lock status. 7. PR = Protection Register data. 4.5 Read Status Register The status register is 8 bits wide. The status register contains information pertaining to the current condition of the flash device and its partitions. To determine a partition's status, execute the Read Status Register command. To read status register data, execute a signal-word asynchronous read. A status register bit is considered set if its value is a one (1) and cleared if its value is a zero (0). Status register data is output on DQ7-0; DQ15-8 outputs 00h. Each partition has its own status register data. Information contained in this register can only be accessed by executing a singleword asynchronous read. 22 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Table 12. Status Register Definitions DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DWS ESS ES PS VPPS PSS DPS PWS SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 SR bit Bit Name SR.7 Device WSM Status (DWS) SR.6 Erase Suspend Status (ESS) SR.5 Erase Suspend (ES) SR.4 Program Status (PS) SR.3 VPP Status (VPPS) SR.2 SR.1 SR.0 NOTES 0 = Device busy with a program or erase operation. 1 = Device ready. For EFP, see Table 13. 0 = No erase operation, if any, is being suspended. 1 = An erase operation is being suspended. 0 = Block erase successful. 1 = Block erase error. One of three bits set to indicate a command sequence error. 0 = Word program successful. 1 = Word program error. One of three bits set to indicate a command sequence error. 0 = VPP voltage level > VPPLK. 1 = VPP voltage level < VPPLK. Hardware program/erase lockout. Note: This bit does not provide continuous VPP feedback. Signal functionality is not guaranteed when VPP VPP1 or VPP2. 0 = No program operation, if any, is being suspended. Program Suspend Status (PSS) 1 = A program operation is being suspended. 0 = Block unlocked. Device Protect Status (DPS) 1 = An erase or program operation was attempted on a locked block. WP# = VIL. 0 = No other partition is busy. Partition Write/Erase Status (PWS) 1 = Another partition is busy performing an erase or program operation. For EFP, see Table 13. Table 13. Status Register DWS and PWS Description DWS (SR.7) PWS (SR.0) 0 0 0 1 1 0 Description The addressed partition is performing a program/erase operation. No other partition is active. Enhanced Factory Programming: device is finished programming or verifying data or is ready for data. A partition other than the one currently addressed is performing a program/erase operation. Enhanced Factory Programming: the device is either programming or verifying data. No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR.6 and SR.2) indicate whether other partitions are suspended. Enhanced Factory Programming: the device has exited EFP mode. 1 1 Preliminary Won't occur in standard program or erase modes. Enhanced Factory Programming: this combination will not occur. 23 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 4.5.1 Clear Status Register To clear the status register, execute the Clear Status Register command. When the status register is cleared, only bits 1, 3, 4, and 5 are cleared. A status register bit is considered set if its value is a one (1) and cleared if its value is a zero (0). Since bits 0, 2, 6 and 7 indicated different error conditions and/or device states, these bits can only be set and cleared by the WSM and are not cleared when a Clear Status Register command is given. The status register should be cleared before implementing any program or erase operations. After executing the Clear Status Register command, the device returns to read array mode. A device reset also clears the status register. 4.6 Read-While-Write/Erase 1.8 Volt Intel(R) Wireless Flash Memory supports a new flash multi-partition architecture. By dividing the flash memory into many separate partitions, the device is capable of reading from one partition while programing or erasing in another partition; hence the terms, Read-While-Write (RWW) and Read-While-Erase (RWE). These features greatly enhance flash data storage performance. To perform a RWW operation, execute the Word Program command to one partition. While this operation is being performed by the flash WSM, execute the Read Array command to another partition. To perform a RWE operation, execute the Block Erase command to one partition. While this operation is being performed by the flash WSM, execute the Read Array command to another partition. 1.8 Volt Intel Wireless Flash Memory does not support simultaneous program and erase operations. Attempting to perform operations such as these will result in a command sequence error. Only one partition may be programming or erasing while another is reading. 5.0 Program and Erase Voltages The 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O and SRAM memory provides insystem program and erase at VPP1. For factory programming, it also includes a low-cost, backward-compatible 12 V programming feature. It also includes an Enhanced Factory Programming (EFP) feature. 5.1 Factory Program Mode The standard factory programming mode uses the same commands and algorithm as the Word Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through the VCC pin. Note that if VPP is driven by a logic signal, VPP1 must remain above the VPP1Min value to perform in-system flash modifications. When VPP is connected to a 12 V power supply, the device draws program and erase current directly from the VPP pin. This eliminates the need for an external switching transistor to control the VPP voltage. Figure 9, "Example of VPP Power Supply Configurations shows examples of flash power supply usage in various configurations. 24 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 The 12 V VPP mode enhances programming performance during the short time period typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during program and erase operations as specified in Section 11.2, "Extended Temperature Operation" on page 35. VPP may be connected to 12 V for a total of tPPH hours maximum. Stressing the device beyond these limits may cause permanent damage. 5.2 Programming Voltage Protection (VPP) In addition to the flexible block locking, holding the VPP programming voltage low can provide absolute hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or erase operations will result in an error displayed in the status register bit SR.3 (set to 1). Figure 9. Example of VPP Power Supply Configurations System supply 12 V supply 10K VCC VPP * 12 V fast programming * Absolute write protection with VPP VPPLK System supply (Note 1) 12 V supply VCC System supply Prot# (logic signal) VPP * Low-voltage programming * Absolute write protection via logic signal System supply VPP * Low voltage and 12 V fast programming VCC VCC VPP * Low-voltage programming NOTE: If the VCC supply can sink adequate current, an appropriately valued resistor can be used. 5.3 Enhanced Factory Programming (EFP) EFP substantially improves device programming performance via a number of enhancements to the conventional 12-volt word program algorithm. EFP's more efficient WSM algorithm eliminates the traditional overhead delays of conventional word program mode in both the host programming system and the flash device. Changes to the flowchart and internal routine were developed because of today's beat-rate-sensitive manufacturing environments; a balance between programming speed and cycling performance was struck. After a single command sequence, host programmer bus cycles write data words followed by status checks to determine when the next data word is ready to be accepted. This modification essentially cuts write bus cycles in half. Following each internal program pulse, the WSM automatically increments the device's address to the next physical location. Now, programming equipment can sequentially stream program data throughout an entire block without having to setup and present each new address. In combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to device programming. Additionally, EFP speeds up programming by performing internal code verification. With this, PROM programmers can rely on the device to verify that it's been programmed properly. From the device side, EFP streamlines internal overhead by eliminating the delays previously associated to switch voltages between programming and verify levels at each memory-word location. Preliminary 25 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 EFP consists of four phases: setup, program, verify and exit. Refer to Figure 32, "Enhanced Factory Program Flowchart" on page 63 for a detailed graphical representation on how to implement EFP. 5.3.1 EFP Requirements and Considerations EFP requirements: * * * * Ambient temperature: TA= 25 C 5 C VCC within specified operating range VPP within specified VPP2 range Target block unlocked EFP considerations: * * * * Block cycling below 10 erase cycles(1) RWW not supported(2) EFP programs one block at a time EFP cannot be suspended (1) Recommended for optimum performance. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. (2) Code or data cannot be read from another partition during EFP. 5.3.2 Setup Phase After receiving the EFP Setup (30h) and Confirm (D0h) command sequence, device SR.7 transitions from a `1' to a `0' indicating that the WSM is busy with EFP algorithm startup. A delay before checking SR.7 is required to allow the WSM time to perform all of its setups and checks (VPP level and block lock status). If an error is detected, status register bits SR.4, SR.3 and/or SR.1 are set and EFP operation terminates. 5.3.3 Program Phase After setup completion, the host programming system must check SR.0 to determine "data-stream ready" status (SR.0=0). Each subsequent write after this is a program-data write to the flash array. Each cell within the memory word to be programmed to `0' will receive one WSM pulse; additional pulses, if required, occur in the verify phase. SR.0=1 indicates that the WSM is busy applying the program pulse. The host programmer must poll the device's status register for the "program done" state after each data-stream write. SR.0=0 indicates that the appropriate cell(s) within the accessed memory location have received their single WSM program pulse, and that the device is now ready for the next word. Although the host may check full status for errors at any time, it is only necessary on a block basis, after EFP exit. Addresses must remain within the target block. Supplying an address outside the target block immediately terminates the program phase; the WSM then enters the EFP verify phase. 26 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 The address can either hold constant or it can increment. The device compares the incoming address to that stored from the setup phase (WA0); if they match, the WSM programs the new data word at the next sequential memory location. If they differ, the WSM jumps to the new address location. The program phase concludes when the host programming system writes to a different block address; data supplied must be FFFFh. Upon program phase completion, the device enters the EFP verify phase. 5.3.4 Verify Phase A high percentage of the flash bits program on the first WSM pulse. However, for those cells that do not completely program on their first attempt, EFP internal verification identifies them and applies additional pulses as required. The verify phase is identical in flow to that of the program phase, except that instead of programming incoming data, the WSM compares the verify-stream data to that which was previously programmed into the block. If the data compares correctly, the host programmer proceeds to the next word. If not, the host waits while the WSM applies an additional pulse(s). The host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. It then reissues each data word in the same order it did during the program phase. Like programming, the host may write each subsequent data word to WA0 or it may increment up through the block addresses. The verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be FFFFh. Upon verify phase completion, the device enters the EFP exit phase. 5.3.5 Exit Phase SR.7=1 indicates that the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. After EFP exit, any valid CUI command can be issued. 5.4 Write Protection (VPP < VPPLK) If the VPP voltage is below the VPP lockout threshold, word programming is prohibited. To ensure proper word program operation, VPP must be set to one of the two valid VPP ranges. To determine program status, poll the status register and analyze the bits. When VPP is at VPP1, program currents are drawn through the VCC supply. If VPP is driven by a logic signal, VPP1 must remain above the VPP1 minimum value in order to program erase mode. 6.0 Flash Erase Mode 6.1 Block Erase Flash erasing is performed on a block-by-block basis; therefore, only one block may be erased at any given time. Once a block is erased, all bits within that block will read as a logic level one (1). Preliminary 27 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 To erase a block, execute the Block Erase command. To determine the status of a block erase, poll the status register and analyze the bits. If the device is put in standby mode during an erase operation, the device will continue to erase until to operation is complete; then it will enter standby mode. Refer to Figure 33, "Block Erase Flowchart" on page 64 for a detailed flow on how to implement a block erase operation. 6.2 Erase Protection (VPP < VPPLK) If the VPP voltage is below the VPP lockout threshold voltage, block erasure is prohibited. To ensure proper block erase operation, VPP must be set to one of the two valid VPP levels. To determine block erase status, poll the status register and analyze the bits. When VPP is at VPP1, erase currents are drawn through the VCC supply. If VPP is driven by a logic signal, VPP1 must remain above the VPP1 minimum value in order to erase a block. 7.0 Flash Suspend/Resume Modes 7.1 Program/Erase Suspend To suspend program or erase, execute the suspend command. Suspend halts any in-progress word programming or block erase operation. The Suspend command can be written to any device address, and the partition being addressed remains in its previous command state. A Suspend command allows data to be accessed from any memory location other than those suspended. A program operation can be suspended to allow a read. An erase operation can be suspended to allow word programming or device reads within any except the suspended block. A program operation nested within an erase suspend can be suspended to read the flash device. Once the program/erase process starts, a suspend can only occur at certain points in the program/erase algorithm. Erase cannot resume until program operations initiated during the erase suspend are complete. All device read functions are permitted during suspend. During a suspend, VPP must remain at a valid program level and WP# must not change. Also, a minimum time is required between issuing a Program or Erase command and then issuing a Suspend command. 7.2 Program/Erase Resume The Resume command (D0H) instructs the WSM to continue programming/erasing and automatically clears status register bits SR.2 (or SR.6) and SR.7. The Resume command can be written to any partition. If status register error bits are set, the status register can be cleared before issuing the next instruction. RST# must remain at VIH. See Figure 31, "Program Suspend/Resume Flowchart" on page 62 and Figure 34, "Erase Suspend/Resume Flowchart" on page 65. If a suspended partition was placed in read array, read status register, read identifier (ID), or read query mode during the suspend, the device will remain in that mode and output data corresponding to that mode after the program or erase operation is resumed. After resuming a suspend operation, 28 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 always issue the Read Mode command appropriate to the read operation. To read status after resuming a suspended operation, issue a Read Status Register command (70H) to return the suspended partition to status mode. 8.0 Flash Security Modes The 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O offers both hardware and software security features to protect the flash data. The software security feature is used by executing the Lock Block command. The hardware security feature is used by executing the Lock-Down Block command AND by asserting the WP# and VPP signals. For details on VPP data security, refer to Section 5.4, "Write Protection (VPP < VPPLK)" on page 27 and Section 6.2, "Erase Protection (VPP < VPPLK)" on page 28. Refer to Figure 10, "Block Locking State Diagram for a state diagram of the flash security features. Also see Figure 35, "Locking Operations Flowchart" on page 66. Figure 10. Block Locking State Diagram (X) (Y) (Z) WP# DQ 1 DQ 0 Power-up or Reset 0 0 0 0 1 1 1 1 (001) or (101) (101) Initial Lock-Down Cmd or Assert WP # (011) Block LockedDown Block Locked 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Block Status unlocked locked; default invalid locked down unlocked locked unlocked locked Notes: 1.) X = WP# = write protect signal. 2.) Y = DQ 1 = Lock-down status. 3.) Z = DQ 0 = Lock status. Unlock Cmd (000) Unlock Cmd (110) Unassert WP# (111) Lock Cmd (101) Lock Cmd (001) Block Unlocked (100) Initial Lock-Down Cmd or Assert WP# (011) NOTES: 1. The notation (X,Y,Z) denotes the locking state of a block, The current locking state of a block is defined by the state of WP# and the two bits of the block-lock status DQ1-0. 2. Solid line indicates WP# asserted (low). Dashed line indicates WP# unasserted (high). 8.1 Block Lock All blocks default to locked (states [001] or [101]) upon power-up or reset. Locked blocks are fully protected from alteration. Attempted program or erase operations to a locked block will return an error in status register bit SR.1. A locked block's status can be changed to unlocked or lock-down using the appropriate software commands. Writing the Lock Block command sequence can lock an unlocked block. Preliminary 29 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 8.2 Block Unlock Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to locked when the device is reset or powered down. An unlocked block can be locked or locked-down using the appropriate software commands. If it's not locked-down, a locked block can be unlocked by writing the Unlock Block command sequence. 8.3 Lock-Down Block Locked-down blocks (state [011]) are protected from program and erase operations, but unlike locked blocks, software commands alone cannot change their protection status. A locked-down block can only be unlocked when WP# is high. When WP# is low, all locked-down blocks revert to locked. A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence. Locked-down blocks revert to the locked state at device reset or power-down. 8.4 Block Lock Operations during Erase Suspend Block lock configurations can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. Useful when another block requires immediate updating. To change block locking during an erase operation, first write the Erase Suspend command. After checking SR.6 to determine that the erase operation has suspended, write the desired lock command sequence to a block; the lock status will be changed. After completing lock, unlock, read, or program operations, resume the erase operation with the Erase Resume command (D0h). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits will change immediately. But when resumed, the erase operation will complete. Locking operations cannot occur during program suspend. Appendix A, "Flash Write State Machine (WSM)" shows valid commands during erase suspend. 8.5 WP# Lock-Down Control WP# allows block lock-down to be overridden. Table 14 defines device write protection methodology. WP# controls the lock-down function. WP# = VIL(0) protects locked-down blocks [011] from program, erase, and lock status changes. When WP# = VIH(1), the locked-down blocks revert to locked [111]. A software command can then individually unlock a block [110] for erase or program. These blocks can then be re-locked [111] while WP# remains high. When WP# returns low, previously locked-down blocks revert to the lock-down state [011] regardless of changes made while WP# was high. Device reset or power-down resets all blocks to the locked state [101] or [001]. 30 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 . Table 14. Write Protection Truth Table Preliminary VPP WP# RST# Write Protection X X VIL Reset mode, device Inaccessible VIL X VIH Program and Erase Prohibited > VPPLK VIL VIH All Lock-down Blocks are Locked >VPPLK VIH VIH All Lock-down Blocks are Unlockable 31 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 9.0 Flash Protection Register The 1.8 Volt Intel(R) Wireless Flash Memory includes a 128-bit protection register. This protection register can be used to increase system security and/or for identification purposes. The protection register value can match the flash component to the system's CPU or ASIC to prevent device substitution. The lower 64-bit segments within the protection register are programmed by Intel with a unique number in each flash device. The upper 64-bit segments within the protection register are left for the customer to program. Once programmed, the customer segment can be locked to prevent further reprogramming. The protection register shares some of the same internal flash resources as the parameter partition. Therefore, read-while-write is only allowed between the protection register and main partitions. Table 15 describes the operation allowed using read-while-write/erase with the protection register. Table 15. Simultaneous Operations Allowed with the Protection Register Protection Register Parameter Partition Array Data Main Partition Read Conditional- See Notes Write/Erase Conditional- See Notes Read Write/Erase Read Read Write/Erase Write No Access Allowed Read No Access Allowed Write/Erase Read 9.1 Notes While programming or erasing in a main partition, the protection register may be read from any other partition. Reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers from parameter partition addresses is not allowed. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers in a partition that is different from the one being programed/erased, and also different from the parameter partition, is allowed. While programming the protection register, reads are only allowed in the other main partitions. Access to the parameter partition is not allowed. This is because programming of the protection register can only occur in the parameter partition, so it will exist in status mode. While programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. Reads in other main partitions are supported. Protection Register Read Writing the Read Identifier command allows the protection register data to be read 16 bits at a time from addresses shown in Table 11, "Device Identification Codes" on page 21. The ID plane, containing the protection registers, appears over partition addresses corresponding to the partition address supplied with the command. Writing the Read Array command returns the device to read array mode. 9.2 Program Protection Register The Protection Program command should be issued only at the bottom partition followed by the data to be programed at the specified location. It programs the 64-bit user protection register 16 bits at a time. Table 11, "Device Identification Codes" on page 21 and Table 16, "Protection Register 32 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Addressing" on page 33 show allowable addresses. See also Figure 36, "Protection Register Programming Flowchart" on page 67. Issuing a Protection Program command outside the register's address space results in a status register error (SR.4 = 1). Table 16. Protection Register Addressing Word Use ID Offset A7 A6 A5 A4 A3 A2 A1 A0 Word LOCK Both PBA+000080h 1 0 0 0 0 0 0 0 LOCK 0 Intel PBA+000081h 1 0 0 0 0 0 0 1 0 1 Intel PBA+000082h 1 0 0 0 0 0 1 0 1 2 Intel PBA+000083h 1 0 0 0 0 0 1 1 2 3 Intel PBA+000084h 1 0 0 0 0 1 0 0 3 4 Customer PBA+000085h 1 0 0 0 0 1 0 1 4 5 Customer PBA+000086h 1 0 0 0 0 1 1 0 5 6 Customer PBA+000087h 1 0 0 0 0 1 1 1 6 7 Customer PBA+000088h 1 0 0 0 1 0 0 0 7 NOTE: Addresses A17-A8 should be set to zero. AMAX-A18 = partition base address (PBA). 9.3 Protection Register Lock The protection register's user-programmable segment is lockable by programming "0" to the PR-LOCK register bits "1" using the Protection Program command (Figure 11). PR-LOCK register bit "0" is programmed to 0 at the Intel factory to protect the unique device number. PR-LOCK register bit "1" can be programmed by the user to lock the 64-bit user register. This bit is set using the Protection Program command to program "FFFDh" into PR-LOCK register 0. After PR-LOCK register bits have been programmed, no further changes can be made to the protection register's stored values. Protection Program commands written to a locked section result in a status register error (program error bit SR.4 and lock error bit SR.1 are set to 1). Once locked, protection register states are not reversible. Figure 11. Protection Register Locking 0088h 0085h 0084h 0081h 0080h Preliminary 4 Words (64 bits) User Programmed 4 Words (64 bits) Intel Factory Programmed 1 Word (16bits) Lock Register 0 33 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 10.0 Power and Reset Considerations 10.1 Power-Up/Down Characteristics In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up VCC, VCCQ and S-VCC together. Conversely, VCC, VCCQ and S-VCC must power-down together. It is also recommended to power-up VPP with or slightly after VCC. Conversely, VPP must powerdown with or slightly before VCC. If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMin before applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCCMin. Power supply transitions should only occur when RST# is low. 10.2 Power Supply Decoupling When the device is accessed, many internal conditions change. Circuits are enabled to charge pumps and voltages are switched. All this internal activity produces transient signals. The magnitude of these transient signals depends on the device and the system capacitive and inductive loading. To minimize the effect of these transient signals, a 0.1 F ceramic decoupling capacitor is required across each VCC, VCCQ, VPP, S-VCC to system ground. Capacitors should also be placed as close as possible to the package balls. 10.3 Flash Reset Characteristics By holding the flash device in reset during power-up/down transitions, invalid bus conditions can be masked. The flash device enters a reset mode when RST# is driven low. In reset mode, internal flash circuitry is turned off and outputs are placed in a high-impedance state. After return from reset, a certain amount of time is required before the flash device is capable of performing normal operations. Upon return from reset, the flash device defaults to page mode. If RST# is driven low during a program or erase operation, the operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Figure 24, "Reset Operations Waveforms" on page 52 for detailed information regarding reset timings. 34 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 11.0 Electrical Specifications 11.1 Absolute Maximum Ratings Parameter Note Maximum Rating Temperature under Bias -25 C to +85 C Storage Temperature -65 C to +125 C Voltage On Any Signals (except VCC, VCCQ, VPP and S-VCC) 1 -0.5 V to +3.80 V VPP Voltage 1,2,3 VCC Voltage 1 -0.2 V to +2.40 V VCCQ and S-VCC Voltage 1 -0.2 V to +3.36 V Output Short Circuit Current 4 100 mA -0.2 V to +14 V NOTES: 1. All specified voltages are with respect to VSS. Minimum DC voltage is -0.5 V on input/output signals and -0.2 V on VCC and VPP supplies. During transitions, this level may undershoot to -2.0 V for periods <20 ns which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. 3. VPP program voltage is normally VPP1. VPP can be VPP2 for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. 4. Output shorted for no more than one second. No more than one output shorted at a time. NOTICE: This datasheet contains preliminary information on new products in production. Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Warning: 11.2 Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Extended Temperature Operation Symbol Preliminary Parameter Note Min Max Unit TA Operating Temperature -25 85 C VCC VCC Supply Voltage 1.70 1.90 V V VCCQ, S-VCC Flash I/O and SRAM Supply Voltages 2 2.20 3.30 VPP1 VPP Voltage Supply (Logic Level) 1 0.90 1.90 VPP2 Factory Programming VPP 1 11.4 12.6 tPPH Maximum VPP Hours VPP = VPP2 1 Main and Parameter Blocks VPP = VCC 1 Block Erase Cycles Main Blocks VPP = VPP2 Parameter Blocks VPP = VPP2 V 80 Hours 1 1000 Cycles 1 2500 100,000 35 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 NOTES: 1. In normal operation, the VPP program voltage is VPP1. VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles at extended temperature on parameter blocks. 2. VCCQ and S-VCC must be tied together, except when in Data Retention Mode. 11.3 Sym DC Characteristics Parameter (1) ILI Input Load Current ILO Output Leakage Current DQ15-0, WAIT Devic e Note Flash/ SRAM 1 Flash/ SRAM Min Typ Max Unit 2 A Test Condition VCC = VCCMax VCCQ = VCCQMax 1 10 A S-VCC = S-VCCMax Inputs = VCCQ or VSS VCC = VCCMax Flash ICCS ICC ICC2 Operating Power Supply Current (cycle time = 1 s) Operating Power Supply Current (min cycle time) Average VCC Read Current 21 A VCCQ = VCCQMax CE# = VCC RST# =VCC or VSS 4-Mbit SRAM 1 8-Mbit SRAM 1 40 A 4-Mbit SRAM 1 10 mA 20 A S-VCC = S-VCCMax S-CS1# = S-VCC S-CS2 = S-VCC or S-VSS Inputs = S-VCC or S-VSS IIO = 0 mA, S-CS1# = VIL S-SC2 = S-WE# = VIH 8-Mbit SRAM 1 20 mA 4-Mbit SRAM 1 45 mA 8-Mbit SRAM 1 Flash 2 Inputs = VIL or VIH Cycle time = min 100% duty IIO = 0 mA, S-CS1# = VIL S-SC2 = VIH 65 mA 4 7 mA 4-Word Read 7 15 mA 4 -Word Burst 9 16 mA OE# = VIH 8-Word Burst Inputs = VIH or VIL 12 22 mA Continuous Burst 18 40 mA VPP = VPP1 8 15 mA VPP = VPP2 Inputs = VIL or VIH VCC = VCCMax Synchronous CLK = 40 MHz Flash ICCW VCC Program Current Flash ICCE VCC Block Erase Current Flash ICCWS VCC Program Suspend Current Flash ICCES VCC Erase Suspend Current Flash 36 6 Standby Current Asynchronous Page Mode Read ICCR 1 2, 3 4, 5 18 40 mA VPP = VPP1 8 15 mA VPP = VPP2 4 6 21 A CE# = VCCQ 4, 7 6 21 A CE# = VCC 4, 6 CE# = VIL Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Parameter (1) Sym IPPS (IPPWS, IPPES) Devic e Note Flash 4 Min Typ Max Unit Test Condition 0.2 5 A VPP1 VCC 2 15 A VPP VCC 0.05 0.10 VPP Standby Current VPP Program Suspend Current VPP Erase Suspend Current IPPR VPP Read Current Flash IPPW VPP Program Current Flash IPPE VPP Erase Current Flash VIL Input Low Voltage Flash / SRAM 9 0 0.4 V VIH Input High Voltage Flash / SRAM 9 VCCQ - 0.4 VCCQ V VOL Output Low Voltage Flash / SRAM 0.1 V 4 mA 8 22 0.05 0.10 8 22 4 VPP = VPP1 VPP = VPP2 mA VPP = VPP1 VPP = VPP2 VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VOH Output High Voltage Flash / SRAM VCC = VCCMin VCCQ - 0.1 V VCCQ = VCCQMin IOH = -100 A VPPLK VPP Lock-Out Voltage Flash VLKO VCC Lock Voltage Flash 1.0 V VLKOQ VCCQ Lock-Out Voltage Flash 0.90 V 8 0.4 V NOTES: 1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25 C. 2. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. 3. The burst wrap bit (CR.3) determines whether 4-, or 8-word burst accesses wrap within the burst-length boundary, or whether they cross word-length boundaries to perform linear accesses. In the no-wrap mode (CR.3 = 1), the device operates similar to continuous linear burst mode, but consumes less power. 4. Sampled, not 100% tested. 5. VCC read + program current is the summation of VCC read and VCC program currents. 6. VCC read + erase current is the summation of VCC read and VCC block erase currents. 7. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. 8. Erase and program operations are inhibited when VPP VPPLK and not guaranteed outside valid VPP1 and VPP2 ranges. 9. VIL can undershoot to -0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less. AC I/O Test Conditions Preliminary 37 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 12. AC Input/Output Reference Waveform VCCQ Input Test Points VCCQ/2 VCCQ/2 Output 0V NOTES: 1. AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCC = VCCMin. 2. Timing conditions apply to both flash and SRAM. Figure 13. Transient Equivalent Testing Load Circuit VCCQ R1 Device Under Test Out CL R2 NOTES: 1. See table for component values. 2. Test configuration component value for worst case speed conditions. 3. CL includes jig capacitance. 11.4 Test Configuration CL (pF) R1 () R2 () VCCQMin Standard Test 30 25K 25K Discrete Capacitance (32-Mbit VF BGA Package) TA = +25C, f = 1 MHz Sym Parameter(1) Typ Max Unit Condition CIN Input Capacitance 6 8 pF VIN = 0.0 V COUT Output Capacitance 8 12 pF VOUT = 0.0 V CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V NOTE: 1. Sampled, not 100% tested. 38 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 11.5 Stacked Capacitance (32/4 and 64/8 Stacked-CSP Package) TA = +25C, f = 1 MHz Sym Parameter(1) Typ Max Unit Condition CIN Input Capacitance 16 18 pF VIN = 0.0 V COUT Output Capacitance 18 22 pF VOUT = 0.0 V CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V NOTE: 1. Sampled, not 100% tested. Preliminary 39 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 12.0 Flash AC Characteristics 12.1 Flash Read Operations Speed # -70 -85 Parameter (1,2) Sym Unit Note Min 70 R1 tAVAV Read Cycle Time 3 R2 tAVQV Address to Output Delay 3 R3 tELQV CE# Low to Output Delay R4 tGLQV OE# Low to Output Delay R5 tPHQV RST# High to Output Delay R7 tGLQX OE# Low to Output in Low-Z 5, 6 R8 tEHQZ CE# High to Output in High-Z 6 R9 tGHQZ OE# High to Output in High-Z 5, 6 R10 tOH CE#, (OE#) High to Output in Low-Z 5, 6 R101 tAVVH R102 5 Max Min Max 85 ns 70 85 ns 70 85 ns 30 30 ns 150 150 ns 0 0 25 ns 25 25 25 ns ns 0 0 ns Address Setup to ADV# High 10 10 ns tELVH CE# Low to ADV# High 10 10 ns R103 tVLQV ADV# Low to Output Delay R104 tVLVH ADV# Pulse Width Low R105 tVHVL ADV# Pulse Width High R106 tVHAX R108 R200 70 85 ns 10 10 ns 6 10 10 ns Address Hold from ADV# High 4 9 9 ns tAPA Page Address Access Time 4 fCLK CLK Frequency R201 tCLK CLK Period 25 30 ns R202 tCH/L CLK High or Low Time 9.5 9.5 ns R203 tCHCL CLK Fall or Rise Time R301 tAVCH Address Valid Setup to CLK 9 9 ns R302 tVLCH ADV# Low Setup to CLK 10 10 ns R303 tELCH CE# Low Setup to CLK 9 9 ns R304 tCHQV CLK to Output Delay R305 tCHQX Output Hold from CLK R306 tCHAX Address Hold from CLK R307 tCHTL/ CLK to WAIT Asserted 25 25 ns 40 33 MHz 3 5 20 4 22 ns ns 5 5 ns 10 10 ns 20 22 ns 20 22 ns H R308 tELTL OE# Low to WAIT Active R309 tEHTZ CE# (OE#) High to WAIT High-Z R310 tEHEL CE# Pulse Width High 40 7 6, 7 7 25 20 25 20 ns ns Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 NOTES: 1. See Figure 12, "AC Input/Output Reference Waveform" on page 38 for timing measurements and maximum allowable input slew rate. 2. AC specifications assume the data bus voltage is less than or equal to VCCQ when a read operation is initiated. 3. tAVAV = 85 ns for 128-Mbit device. 4. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. 5. OE# may be delayed by up to tELQV- tGLQV after the falling edge of CE# without impact to tELQV. 6. Sampled, not 100% tested. 7. Applies only to subsequent synchronous reads. Figure 14. Single Word Asynchronous Read Waveform R1 Address [A] VIH Valid Address VIL R2 CE# [E] VIH VIL R3 OE# [G] R8 VIH R4 VIL R7 WE# [W] R9 VIH VIL Data [D/Q] VOH High Z Valid Output VOL R5 RST# [P] R10 VIH VIL Generic_Async_Rd Preliminary 41 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 15. Single Word Latched Asynchronous Read Waveform R1 AMAX-2 [A] VIH VIL A1-0 [A] Valid Address Valid Address VIH Valid Address VIL Valid Address R2 R101 R105 ADV# [V] R106 VIH VIL R104 R103 CE# [E] VIH R3 VIL R102 OE# [G] R4 R8 VIH VIL R7 WE# [W] R9 VIH VIL Data [D/Q] VOH High Z Valid Output VOL R5 RST# [P] R10 VIH VIL Generic_Latch_Async_Rd 42 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 16. Page Mode Read Waveform R1 AMAX-2 [A] VIH VIL Valid Address R2 A1-0 [A] VIH Valid Address VIL Valid Address Valid Address Valid Address R101 R105 ADV# [V] R106 VIH VIL R104 R103 CE# [E] VIH R3 VIL R102 OE# [G] R4 R8 VIH VIL R7 WE# [W] R9 VIH VIL R108 Data [D/Q] VOH High Z Valid Output VOL R5 RST# [P] Valid Output Valid Output R10 VIH VIL Preliminary Valid Output Generic_Pg_Rd 43 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 17. Single Word Burst Read Waveform CLK [C] VIH Note 1 VIL R301 Address [A] VIH R306 Valid Address VIL R2 R101 R105 ADV# [V] R106 VIH R302 VIL R104 R103 CE# [E] VIH R3 VIL R102 OE# [G] R4 R8 VIH VIL R303 WE# [W] R7 R9 VIH R309 VIL R308 WAIT [T] VOH High Z R10 High Z Note 2 VOL R304 Data [D/Q] VOH High Z R305 Valid Output VOL R5 RST# [P] VIH VIL Generic_1W_Sync_Rd NOTES: 1. Section 4.2.2, "First Latency Count (LC2-0)" on page 14 describes how to insert clock cycles during the initial access. 2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data. 44 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 18. 4 Word Burst Read Waveform VIH CLK [C] VIL 0 R301 VIH Address [A] Note 1 1 R306 Valid Address VIL R2 R101 R105 ADV# [V] R106 VIH R302 VIL R104 R103 CE# [E] VIH R310 R3 VIL R102 OE# [G] R4 R8 VIH VIL R303 WE# [W] R7 R9 VIH R309 R308 VIL R10 R307 WAIT [T] VOH High Z High Z Note 2 V OL R304 Data [D/Q] VOH High Z R305 Valid Output V OL Valid Output Valid Output Valid Output High Z R5 RST# [P] VIH VIL NOTES: 1. Section 4.2.2, "First Latency Count (LC2-0)" on page 14 describes how to insert clock cycles during the initial access. 2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data. Figure 19. Clock Input AC Waveform R201 CLK [C] V IH V IL R202 R203 CLKINPUT.WMF Preliminary 45 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 20. WAIT Signal in Synchronous Non-Read-Array Operation Waveform CLK [C] VIH Note 1 VIL R301 Address [A] VIH R306 Valid Address VIL R2 R101 R105 ADV# [V] R106 VIH R302 VIL R104 R103 CE# [E] VIH R3 VIL R102 OE# [G] R4 R8 VIH VIL R303 WE# [W] R7 R9 VIH R309 VIL R308 WAIT [T] VOH R10 High Z High Z Note 2 VOL R304 Data [D/Q] VOH High Z R305 Valid Output VOL R5 RST# [P] VIH VIL NOTES: 1. WAIT signal is in "asserted" state. 2. WAIT shown active low. 46 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 21. WAIT Signal in Asynchronous Page-Mode Read Operation Waveform R1 AMAX-2 [A] VIH Valid Address VIL R2 A1-0 [A] VIH Valid Address VIL Valid Address Valid Address Valid Address R101 R105 ADV# [V] R106 VIH VIL R104 R107 R103 CE# [E] VIH R3 VIL R102 R4 R8 R6 OE# [G] VIH VIL R7 WE# [W] R9 VIH VIL WAIT [T] VOH High Z Note 2 High Z R108 VOL Data [D/Q] VOH High Z Valid Output VOL R5 RST# [P] Valid Output Valid Output Valid Output R10 VIH VIL NOTES: 1. WAIT signal is in "asserted" state. 2. WAIT shown active low. Preliminary 47 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 22. WAIT Signal in Asynchronous Single-Word Read Operation Waveform R1 Address [A] VIH Valid Address VIL R2 CE# [E] VIH VIL R3 OE# [G] R8 VIH R4 VIL R7 WE# [W] R9 VIH VIL WAIT [T] VOH High Z High Z Note 2 VOL R6 Data [D/Q] VOH High Z Valid Output VOL R5 RST# [P] R10 VIH VIL NOTES: 1. WAIT signal is in "asserted" state. 2. WAIT shown active low. 48 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 12.2 Flash Write Operations Speed # -70 -85 Parameter (1,2) Sym Unit Note W1 tPHWL (tPHEL) W2 tELWL (tWLEL) W3 tWLWH (tELEH) WE# (CE#) Write Pulse Width Low W4 tDVWH (tDVEH) W5 RST# High Recovery to WE# (CE#) Low Min Max Min Max 150 150 ns 0 0 ns 45 60 ns Data Setup to WE# (CE#) High 45 60 ns tAVWH (tAVEH) Address Setup to WE# (CE#) High 45 60 ns W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 0 ns W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High 0 0 ns W8 tWHAX (tEHAX) Address Hold from WE# (CE#) High 0 0 ns W9 tWHWL (tEHEL) WE# (CE#) Pulse Width High 5, 6, 7 25 25 ns W10 tVPWH (tVPEH) VPP Setup to WE# (CE#) High 3 200 200 ns CE# (WE#) Setup to WE# (CE#) Low 4 W11 tQVVL VPP Hold from Valid Status Register Data 3, 8 0 0 ns W12 tQVBL WP# Hold from Valid Status Register Data 3, 8 0 0 ns W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High 3 200 200 ns W14 tWHGL (tEHGL) Write Recovery before Read 0 0 ns W16 tWHQV WE# High to Valid Data tAVQV + 40 tAVQV + 50 ns 6 NOTES: 1. Write timing characteristics during erase suspend are the same as during write-only operations. 2. A write operation can be terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first); hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low (whichever is last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 6. System designers should take this into account and may insert a software No-Op instruction to delay the first read after issuing a command. 7. For commands other than resume commands. 8. VPP should be held at VPP1 or VPP2 until block erase or program success is determined. Preliminary 49 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 23. Write Waveform Note 1 VIH Address [A] VIL Note 2 Note 3 Valid Address Note 4 Valid Address Note 5 Valid Address W5 W8 ADV# [V] VIH VIL VIH CE# (WE#) [E(W)] Note 6 VIL W2 OE# [G] W6 VIH VIL W3 W9 W14 VIH WE# (CE#) [W(E)] Note 6 VIL W1 Data [D/Q] W7 W16 VIH Data In Valid Data Data In VIL W4 RST# [P] VIH VIL WP# [B] W13 W12 W10 W11 VIH VIL VPP1/2 VPP [V] VPPLK VIL NOTE: 1. VCC power-up and standby. 2. Write Program or Erase Setup command. 3. Write valid address and data (for program) or Erase Confirm command. 4. Automated program/erase delay. 5. Read status register data (SRD) to determine program/erase operation completion. 6. OE# and CE# must be driven active (low) and WE# must be de-asserted (high) for read operations. 50 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 12.3 Flash Program and Erase Operations Extended Temperatures F-VPP2 F-VPP1 Unit # Operation Symbol Parameter Notes Typ Max Typ Max 1-Word 1,2,3,4 12 150 8 130 1,3,4 N/A N/A 3.5 16 4-KW Parameter 1,2,3,4 0.05 0.23 0.03 0.07 s tBWMB 32-KW Main 1,2,3,4 0.4 1.8 0.24 0.6 s tBWPB 4-KW Parameter 1,2,3,4, 5 n/a n/a 0.015 n/a s 32-KW Main 1,2,3,4, 5 n/a n/a 0.12 n/a s 4-KW Parameter 1,2,3,4 0.3 2.5 0.25 2.5 s 32-KW Main 1,2,3,4 0.7 4 0.4 4 s tWHQV1/ tEHQV1 tBWPB Program Time Word s Enhanced Factory Programming Mode Block EFP Mode tBWMB W0 Erase Time Suspend Latency EFP Latency tWHQV2/ tEHQV2 Block tWHRH1/ tEHRH1 Program Suspend 1,2,3,4 5 10 5 10 tWHRH2/ tEHRH2 Erase Suspend 1,2,3,4 9 20 9 20 tEFP-SETUP EFP Setup 1,3,4 N/A N/A N/A 5 tEFP-TRAN Program to Verify Transition 1,3,4 N/A N/A 2.7 5.6 tEFP-VERIFY Verify 1,3,4 N/A N/A 1.7 130 s s NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. 2. Excludes external system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, not 100% tested. 5. Exact results may vary based on system overhead. 12.4 Reset Operations # Symbol P1 tPLPH P2 tPLRH P3 tVCCPH Parameter Note Min RST# Low to Reset during Read 1, 2, 3, 4 100 RST# Low to Reset during Block Erase 1, 3, 4, 5 20 RST# Low to Reset during Program 1, 3, 4, 5 10 VCC Power Valid to RST# High 1, 3, 4, 5, 6 Max Unit ns s 60 NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. The device may reset if tPLPH is <tPLPHMin, but this is not guaranteed. 3. Not applicable if RST# is tied to VCC. 4. Sampled, not 100% tested. 5. If RST# tied to VCC supply, device not ready until "P3"s after VCC >=VCCMin. Preliminary 51 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 6. If RST# tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until after VCC >=VCCMin. Figure 24. Reset Operations Waveforms P1 (A) Reset during read mode RST# [P] VIL P2 (B) Reset during program or block erase P1 P2 RST# [P] Abort Complete R5 VIH VIL P2 (C) Reset during program or block erase P1 P2 R5 VIH RST# [P] Abort Complete R5 VIH VIL P3 (D) VCC Power-up to RST# high VCC VCC 0V RESET.WMF 52 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 13.0 SRAM AC Characteristics 13.1 SRAM Read Operation # Parameter1 Sym Density 4/8 Mbit S-VCC 2.2 V - 3.3 V Unit Speed Note -70 -85 Min Max Min Max R1 tRC Read Cycle Time 70 - 85 - ns R2 tAA Address to Output Delay - 70 - 85 ns S-CS1#, S-CS2 to Output Delay - 70 - 85 ns R3 tCO1, tCO2 R4 tOE S-OE# to Output Delay - 35 - 40 ns R5 tBA S-UB#, S-LB# to Output Delay - 70 - 85 ns 2, 3 5 - 5 - ns 2 0 - 0 - ns 2, 3, 4 0 25 0 30 ns 2, 4 0 25 0 30 ns 0 - 0 - ns R6 R7 R8 tLZ1, tLZ2 tOLZ tHZ1, tHZ2 S-CS1#, S-CS2 to Output in Low-Z S-OE# to Output in Low-Z S-CS1#, S-CS2 to Output in High-Z R9 tOHZ S-OE# to Output in High-Z R10 tOH Output Hold from Address, S-CS1#, S-CS2, or S-OE# Change, Whichever Occurs First R11 tBLZ S-UB#, S-LB# to Output in Low-Z 2 0 - 0 - ns R12 tBHZ S-UB#, S-LB# to Output in High-Z 2 0 25 0 30 ns NOTE: 1. See Figure 25, "AC Waveform: SRAM Read Operation" on page 54. 2. Sampled, but not 100% tested. 3. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) for a given device and from device-to-device interconnection. 4. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. Preliminary 53 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 25. AC Waveform: SRAM Read Operation Standby Device Address Selection Data Valid VIH ADDRESSES (A) Address Stable VIL R1 VIH CS1# (E1) VIL VIH CS2 (E2) R3 VIL R2 OE# (G) R8 VIH VIL WE# (W) R9 VIH R4 VIL DATA (D/Q) VOH VOL UB#, LB# VIH R7 High Z R10 R6 High Z Valid Output R11 R5 R12 VIH 54 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 13.2 # SRAM Write Operation Parameter1 Sym Density 4/8 Mbit S-VCC 2.2 V - 3.3 V Unit Speed -70 -85 Note Min Max Min Max W1 tWC Write Cycle Time 2 70 - 85 - ns W2 tAS Address Setup to S-WE# (S-CS1#) and S-UB#, S-LB# Going Low 4 0 - 0 - ns W3 tWP S-WE# (S-CS1#) Pulse Width 3 55 - 60 - ns W4 tDW Data to Write Time Overlap 30 - 35 - ns W5 tAW Address Setup to S-WE# (S-CS1#) Going High 60 - 70 - ns W6 tCW S-SC1# (S-WE#) Setup to S-WE# (S-CS1#) Going High and S-SC2 Going Low 60 - 70 - ns W7 tDH Data Hold Time from S-WE# (S-CS1#) High 0 - 0 - ns W8 tWR Write Recovery W9 tBW S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going High 5 0 - 0 - ns 60 - 70 - ns NOTES: 1. See Figure 26, "AC Waveform: SRAM Write Operation" on page 56. 2. A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins when S-CS1# goes low and S-WE# goes low with asserting S-UB# and S-LB# for x16 operation. S-UB# and S-LB# must be tied together to restrict x16 mode. A write ends at the earliest transition when S-CS1# goes high and S-WE# goes high. The tWP is measured from the beginning of write to the end of write. 3. tCW is measured from S-CS1# going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change; tWR applied in case a write ends as S-CS1# or S-WE# going high. Preliminary 55 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 26. AC Waveform: SRAM Write Operation Device Address Selection Standby VIH ADDRESSES (A) Address Stable VIL W1 VIH CS1# (E1) W8 VIL VIH CS2 (E2) OE# (G) VIL W6 VIH W5 VIL WE# (W) W3 VIH VIL W7 W4 DATA (D/Q) VOH High Z High Z Data In VOL W2 W9 VIH UB#, LB# 13.3 Sym VIH SRAM Data Retention Operation Parameter Device Note Min Typ Max Unit VDR S-VCC for Data Retention 4/8Mbit 1, 2 1.5 - 3.3 V S-CS1# S-VCC - 0.2 V - - 5 IDR Data Retention Current A - - 25 S-VCC = 1.5 V S-CS1# S-VCC - 0.2 V tSDR Data Retention Setup Time 4/8Mbit 1 0 - - ns See Data Retention Waveform tRDR Recovery Time 4/8Mbit 1 tRC - - ns 4-Mbit 1, 2 8-Mbit Test Conditions NOTES: 1. Typical values at nominal S-VCC, TA = +25 C. 2. S-CS1# > S-VCC - 0.2 V, S-CS2 > S-VCC - 0.2 V (S-CS1# controlled) or S-CS2 < 0.2 V (S-CS2 controlled). 56 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 27. SRAM Data Retention Waveform tSDR S-CS1# controlled Data Retention Mode tRDR S-VCC VIHMAX S-CS1# (E1) VIHMIN VDR S-VSS S-CS1# S-CS2 controlled tSDR Data Retention Mode tRDR S-VCC S-CS2 VIHMIN S-CS2 (E2) VDR VILMAX S-VSS Preliminary 57 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 14.0 Ordering Information Figure 28. Component Ordering Breakdown RD2 8 F 6 4 0 8 W3 0 T 7 0 Package Designator, Extended Temperature (-25 C to +85 C) GE = 0.75 MM VF BGA RD = Stacked CSP GT = 0.75 MM BGA* Access Speed 70 ns 85 ns Parameter Partition T = Top Parameter Device B = Bottom Parameter Device Product line designator for all Intel(R) Flash products Product Family W30 = 1.8 Volt Intel(R) Wireless Flash Memory with 3 Volt I/O and SRAM VCC = 1.70 V - 1.90 V VCCQ = 2.20 V - 3.30 V Flash Density 320 = x16 (32-Mbit) 640 = x16 (64-Mbit) 128 = x16 (128-Mbit) SRAM Density for Stacked-CSP Products Only 4 = x16 (4-Mbit) 8 = x16 (8-Mbit) Table 17. Valid Component Combinations 128 M 64 M 32M Stacked-CSP 58 VF BGA RD28F3204W30T70 GE28F320W30T70 RD28F3204W30B70 GE28F320W30B70 RD28F3204W30T85 GE28F320W30T85 RD28F3204W30B85 GE28F320W30B85 BGA* RD28F6408W30T70 GT28F640W30T70 RD28F6408W30B70 GT28F640W30B70 RD28F6408W30T85 GT28F640W30T85 RD28F6408W30B85 GT28F640W30B85 TBD TBD Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Appendix A Flash Write State Machine (WSM) This table shows the command state transitions based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state does not depend on the partition's output state. Figure 29. Write State Machine -- Next State Table (Sheet 1 of 2) Chip Next State after Command Input Write State Machine (WSM) Next State Table Current Chip (8) Read (3) Array Program (4,5) Setup Erase (4,5) Setup Enhanced BE Confirm, Factory P/E Resume, Pgm ULB (4) State Setup Ready (FFH) (10H/40H) (20H) (30H) Ready Program Setup Erase Setup EFP Setup Lock/CR Setup OTP Ready (Lock Error) (9) Confirm (D0H) Program/ Erase Suspend Read Status (B0H) (70H) Register (6) (50H) Read ID/Query (90H, 98H) Ready Ready Setup Clear Status Ready (Lock Error) OTP Busy Busy Setup Program Program Busy Busy Program Busy Program Suspend Pgm Busy Setup Ready (Error) Erase Busy Busy Suspend Erase Suspend Pgm in Erase Susp Setup Erase Suspend Pgm Susp in Erase Susp Program in Erase Suspend Busy Program in Erase Suspend Busy Program Suspend in Erase Suspend Pgm in Erase Susp Busy Program Suspend in Erase Suspend Erase Suspend (Lock Error) Erase Susp Erase Suspend (Lock Error) EFP Busy Ready (Error) Lock/CR Setup in Erase Suspend Enhanced Factory Program Erase Busy Erase Busy Program in Erase Suspend Busy Busy Suspend Ready (Error) Erase Susp Erase Suspend Setup Program Busy Program Suspend Erase Busy Erase Program in Erase Suspend Pgm Susp Suspend Setup Ready (Error) (7) EFP Busy EFP Busy EFP Verify Verify Busy (7) Output Next State Table (1) Output Next State after Command Input Pgm Setup, Erase Setup, OTP Setup, Pgm in Erase Susp Setup, EFP Setup, EFP Busy, Verify Busy Status Lock/CR Setup, Lock/CR Setup in Erase Susp Status OTP Busy Ready, Pgm Busy, Pgm Suspend, Erase Busy, Erase Suspend, Pgm In Erase Susp Busy, Pgm Susp In Erase Susp Preliminary Status (3) Array Status Output does not change Status Output does not change ID/Query 59 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 29. Write State Machine -- Next State Table (Sheet 2 of 2) C h ip N e x t S ta te a fte r C o m m a n d In p u t Write State Machine (WSM) Next State Table C u rre n t C h ip S ta te (8 ) L ock, U n lo c k , L o c k -d o w n , C R s e tu p (5 ) C o n firm (5 ) (6 0 H ) (C 0 H ) R eady L o c k /C R S e tu p OTP S e tu p L o c k /C R S e tu p R e a d y (L o c k E rro r) Lo ckD ow n B lo c k L ock B lo c k OTP S e tu p (9 ) C o n firm (9 ) (9 ) (0 1 H ) (2 F H ) (0 3 H ) R eady R eady R eady E nhanced Fact P gm E x it (b lk a d d <> W A0) (X X X X H ) Ille g a l com m an ds or E F P d a ta (2 ) (o th e r c o d e s ) N /A R e a d y (L o c k E rro r) O TP B usy B usy P ro g ra m R eady S e tu p P ro g ra m B u s y N /A B usy P ro g ra m B u s y R eady S uspe nd P ro g ra m S u s p e n d S e tu p R e a d y (E rro r) B usy E ra s e S uspe nd P ro g ra m in E ra s e S u s p e n d N /A E ra s e B u s y L o c k /C R S e tu p in E ra s e S u s p E ra s e B u s y E ra s e S u s p e n d S e tu p P ro g ra m in E ra s e S u s p e n d B u s y B usy P ro g ra m in E ra s e S u s p e n d B u s y S uspe nd L o c k /C R S e tu p in E ra s e Suspend E nhan ced F a c to ry P ro g ra m WSM O p e ra tio n C o m p le te s R eady S e tu p OTP W rite C R C o n firm R eady N /A E ra s e S uspend P ro g ra m S u s p e n d in E ra s e S u s p e n d E ra s e S u s p e n d (L o c k E rro r) E ra s e S u s p S e tu p E ra s e S u s p E ra s e S u s p E ra s e S u s p e n d (L o c k E rro r) N /A R e a d y (E rro r) (7 ) E FP B usy EFP Busy E F P V e rify V e rify B u s y (7 ) (7 ) E F P V e rify E F P B u sy R eady E F P V e rify (7 ) R eady Output Next State Table (1) O u tp u t N e x t S ta te a fte r C o m m a n d In p u t P g m S e tu p , E ra s e S e tu p , O T P S e tu p , P g m in E ra s e S u s p S e tu p , E F P S e tu p , EFP Busy, V e rify B u s y S ta tu s L o c k /C R S e tu p , L o c k /C R S e tu p in E ra s e S u s p S ta tu s A rra y S ta tu s O u tp u t d o e s not cha nge O TP B usy R eady, P gm B usy, Pgm S uspend, E ra s e B u s y , E ra s e S u s p e n d , P g m In E ra s e S u s p B u s y , P g m S u s p In E ra s e S u s p S ta tu s O u tp u t d o e s n o t c h a n g e A rra y O u tp u t d o e s n ot chang e NOTES: 1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command address. A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued. Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state does not depend on the partition's output state. For example, if partition #1's output state is Read Array and partition #4's output state is Read Status, every read from partition #4 (without issuing a new command) outputs the Status register. 2. Illegal commands are those not defined in the command set. 3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in undermined data when a partition address is read. 4. Both cycles of 2-cycle commands should be issued to the same partition address. If they are issued to different partitions, the second write determines the active partition. Both partitions will output status information when read. 5. If the WSM is active, both cycles of a 2-cycle command are ignored. This differs from previous Intel devices. 6. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend). 7. EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if Block Address = address at EFP Confirm command. Any other commands are treated as data. 8. The "current state" is that of the WSM, not the partition. 9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then move to the Ready State. 60 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Appendix B Flowcharts Figure 30. Programming Flowchart WORD PROGRAM PROCEDURE Bus Command Operation Start Program Word Write 40h, Word Address Data/ Confirm Write Program Setup Data = 40h Addr = Location to program (WA) Write Data Data = Data to program (WD) Addr = Location to program (WA) Write Data Word Address Read Suspend Program Loop Read Status Register Standby No SR.7 = 0 Suspend Program 1 Comments Status register data. Toggle CE# or OE# to update Status register Check SR.7 1 = WSM ready 0 = WSM busy Yes Repeat for subsequent programming operations. Full Status register check can be done after each program or after a sequence of program operations. Full Status Check (if desired) Write FFh after the last operation to enter read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register SR.3 = Bus Command Operation 1 SR.4 = Standby Check SR.3 1 = VPP error Standby Check SR.4 1 = Data program error Standby Check SR.1 1 = Attempted program to locked block Program aborted VPP Range Error 0 1 Program Error 1 Device Protect Error Comments 0 SR.1 = 0 Program Successful Preliminary SR.3 MUST be cleared before the Write State Machine will allow further program attempts Only the Clear Staus Register command clears SR.1, 3, 4. If an error is detected, clear the status register before attempting a program retry or other error recovery. PGM_WRD.WMF 61 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 31. Program Suspend/Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Bus Command Operation Start Program Suspend Write B0h Any Address Read Status Write Program Suspend Write Read Status Write 70h Same Partition SR.7 = 0 Data = B0h Addr = Block to suspend (BA) Data = 70h Addr = Same partition Status register data Toggle CE# or OE# to update Status register Addr = Suspended block (BA) Read Read Status Register Comments Standby Check SR.7 1 = WSM ready 0 = WSM busy Standby Check SR.2 1 = Program suspended 0 = Program completed 1 SR.2 = Read 0 Program Completed 1 Array Write Write FFh Susp Partition Read Array Read array data from block other than the one being programmed Read Read Array Data Done Reading Program Yes Resume Program Resume Data = D0h Addr = Suspended block (BA) If the suspended partition was placed in Read Array mode: No Write Read Array Write D0h Any Address Write FFh Pgm'd Partition Program Resumed Read Array Data Read Read Status Return partition to Status mode: Data = 70h Addr = Same partition Status Write 70h Same Partition 62 Write Data = FFh Addr = Block address to read (BA) PGM_SUS.WMF Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 32. Enhanced Factory Program Flowchart ENHANCED FACTORY PROGRAMMING PROCEDURE EFP Setup EFP Program EFP Verify EFP Exit Start Read Status Register Read Status Register Read Status Register SR.0=1=N Write 30h Address = WA0 SR.0=1=N Write D0h Address = WA0 Read Status Register EFP Setup Done? SR.7=0=Y EFP setup time SR.0=1=N Data Stream Ready? Write Data Address = WA0 Write Data Address = WA0 Full Status Check Procedure Read Status Register Read Status Register Operation Complete SR.0 = 0 = Y N Last Data? Last Data? Y Check VPP & Lock errors (SR.3, SR.1) SR.7 = 1 = Y Verify Done? SR.0 = 0 = Y SR.7 = 1 = N EFP Exited? SR.0 = 0 = Y Program Done? N SR.7=0=N Verify Stream Ready? SR.0 = 0 = Y SR.0=1=N VPP = 12V Unlock Block Y Write FFFFh Address BBA Write FFFFh Address BBA Exit EFP Setup Bus State Comments EFP Program Bus State Read Write Unlock Block VPP = 12V Unlock block Write EFP Setup Data = 30h Address = WA0 Standby EFP Data = D0h Confirm Address = WA0 Write (note 1) Write Standby Setup Time Read Refer to Program and Erase Operations Table. Status Register Check SR.7 Standby 0 = EFP ready 1 = EFP not ready If SR.7 = 1: Error Check SR.3, SR.1 Standby Condition SR.3 = 1 = VPP error Check SR.1 = 1 = locked block EFP Setup Done? Comments Status Register Status Register Data Check SR.0 Stream 0 = Ready for data Ready? 1 = Not ready for data Standby Verify Check SR.0 Stream 0 = Ready for verify Ready? 1 = Not ready for verify Data = Data to program Address = WA0 Write (note 2) Status Register Check SR.0 Program 0 = Program done Standby Done? 1 = Program not done Write Comments Read Read Standby EFP Verify Bus State Last Data? Device automatically increments address. Exit Data = FFFFh Program Address not within same Phase BBA Data = Word to verify Address = WA0 Read Status Register Standby (note 3) Verify Done? Check SR.0 0 = Verify done 1 = Verify not done Standby Last Data? Device automatically increments address. Write Exit Verify Phase Data = FFFFh Address not within same BBA EFP Exit 1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base Address) must remain constant throughout the program phase data stream; WA can be held constant at the first address location, or it can be written to sequence up through the addresses within the block. Writing to a BBA not equal to that of the block currently being written to terminates the EFP program phase, and instructs the device to enter the EFP verify phase. 2. For proper verification to occur , the verify data stream must be presented to the device in the same sequence as that of the program phase data stream. Writing to a BBA not equal to WA terminates the EFP verify phase, and instructs the device to exit EFP . 3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive additional program-pulse attempts during the EFP verify phase. The device will report any program failure by setting SR.4=1; this check can be performed during the full status check after EFP has been exited for that block, and will indicate any error within the entire data stream. Preliminary Read Standby Status Register Check SR.7 EFP 0 = Exit not finished Exited? 1 = Exit completed Repeat for subsequent operations. After EFP exit, a Full Status Check can determine if any program error occurred. See the Full Status Check procedure in the Word Program flowchart. 63 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 33. Block Erase Flowchart BLOCK ERASE PROCEDURE Bus Command Comments Operation Block Data = 20h Erase Write Addr = Block to be erased (BA) Setup Start Block Erase Write 20h Block Address Erase Write Confirm Write D0h and Block Address Erase Confirm Read Suspend Erase Loop Read Status Register No SR.7 = 0 Suspend Erase 1 Standby Data = D0h Addr = Block to be erased (BA) Status register data. Toggle CE# or OE# to update Status register data Check SR.7 1 = WSM ready 0 = WSM busy Yes Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures. Full Erase Status Check (if desired) Write FFh after the last operation to enter read array mode. Block Erase Complete FULL ERASE STATUS CHECK PROCEDURE Read Status Register SR.3 = Bus Command Operation 1 SR.4,5 = Standby Check SR.3 1 = VPP error Standby Check SR.4,5 Both 1 = Command sequence error Standby Check SR.5 1 = Block erase error VPP Range Error 0 1 Command Sequence Error 1 Block Erase Error Comments 0 SR.5 = 0 SR.1 = 0 Block Erase Successful 64 1 Erase of Locked Block Aborted Check SR.1 1 = Attempted erase of locked block Erase aborted SR. 1 and 3 MUST be cleared before the Write State Machine will allow further erase attempts. Standby Only the Clear Staus Register command clears SR.1, 3, 4, 5. If an error is detected, clear the Status register before attempting an erase retry or other error recovery. ERAS_BLK.WMF Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 34. Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Bus Command Operation Start Erase Suspend Write Write B0h Any Address Read Write Status Write 70h Same Partition Erase Data = B0h Suspend Addr = Any address Read Status Read Status Register SR.6 = Read or Program? Read Array Data No Check SR.7 1 = WSM ready 0 = WSM busy Standby Check SR.6 1 = Erase suspended 0 = Erase completed Erase Completed 0 Write 1 Read Standby 0 1 Program Loop Write Yes Resume Array Write FFh Erased Partition Erase Resumed Read Array Data Program Resume Data = D0h Addr = Any address Write Read Status Return partition to Status mode: Data = 70h Addr = Same partition Status Write 70h Same Partition Preliminary Read Write D0h Any Address Read Read array or program data from/to block other than the one being erased If the suspended partition was placed in Read Array mode or a Program Loop: Done? Erase Read Array Data = FFh or 40h or Program Addr = Block to program or read Read or Write Program Data = 70h Addr = Same partition Status register data. Toggle CE# or OE# to update Status register Addr = Same partition Read SR.7 = Comments ERAS_SUS.WMF 65 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 35. Locking Operations Flowchart LOCKING OPERATIONS PROCEDURE Bus Command Operation Start Lock Setup Write Write 60h Block Address Lock Confirm Write Write 01,D0,2Fh Block Address Read Optional Data = 60h Addr = Block to lock/unlock/lock-down (BA) Lock, Data = Unlock, or Lockdown Confirm Addr = 01h (Lock block) D0h (Unlock block) 2Fh (Lockdown block) Block to lock/unlock/lock-down (BA) ID Plane Write (Optional) Write 90h Locking Change? Yes Array Read ID Plane Data = 90h Addr = Block address offset +2 (BA+2) Read Block Lock Block Lock status data (Optional) Status Addr = Block address offset +2 (BA+2) Read Block Lock Status Read Lock Setup Comments No Confirm locking change on DQ 1, DQ 0. (See Block Locking State Transitions Table for valid combinations.) Standby (Optional) Write Read Array Data = FFh Addr = Block address (BA) Write FFh Partition Address Lock Change Complete 66 LOCK_OP.WMF Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Figure 36. Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Bus Command Comments Operation Protection Data = C0H Write Program Addr = First Location to Program Setup Start Program Setup Write C0h Addr=Prot addr Confirm Write Data Write Protect. Register Address / Data Read Read Status Register Standby SR.7 = 1? Protection Data = Data to Program Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Protection Program operations addresses must be within the protection register address space. Addresses outside this space will return an error. No Yes Repeat for subsequent programming operations. Full Status Check (if desired) Full Status register check can be done after each program or after a sequence of program operations. Write FFh after the last operation to enter read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data Bus Command Operation Standby SR.3, SR.4 = 1,1 SR.1, SR.4 = Program Successful Preliminary 0,1 1,1 SR.1 SR.3 SR.4 0 1 1 VPP Error VPP Range Error Standby SR.1, SR.4 = Comments Programming Error Locked-Register Program Aborted Standby 0 0 1 Prot. Reg. Prog. Error 1 0 1 Register Locked: Aborted SR.3 MUST be cleared before the Write State Machine will allow further program attempts. Only the Clear Staus Register command clears SR.1, 3, 4. If an error is detected, clear the Status register before attempting a program retry or other error recovery. PROTFLOW.WMF 67 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Appendix C Common Flash Interface This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. C.1 Query Structure Output The Query database allows system software to obtain information for controlling the flash device. This section describes the device's CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII "Q" and "R," appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table C1. Summary of Query Structure Output as a Function of Device and Mode Hex Offset 00010: 00011: 00012: Device Device Addresses Hex Code 51 52 59 ASCII Value "Q" "R" "Y" Table C2. Example of Query Structure Output of x16- and x8 Devices Offset A -A 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... 68 Word Addressing: Hex Code D -D 0051 0052 0059 P_ID P_ID P P A_IDLO A_IDHI ... Value "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Offset A -A 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... Byte Addressing: Hex Code Value D -D 51 "Q" 52 "R" 59 "Y" P_ID PrVendor P_ID ID # P_ID ID # ... ... Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 C.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure subsections and address locations are summarized below. Table C3. Query Structure Offset 00000h 00001h (2) 00004-Fh 00010h 0001Bh 00027h P (3) Sub-Section Name Block Status register Reserved CFI query identification string System interface information Device geometry definition Primary Intel-specific Extended Query Table (1) Manufacturer Code Device Code Block-specific information Reserved for vendor-specific information Command set ID and vendor data offset Device timing & voltage information Flash device layout Vendor-defined additional information specific to the Primary Vendor Algorithm NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 32K-word). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table. C.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. Only issuing another operation to the block resets this bit. The Block Status Register is accessed from word address 02h within each block. Table C4. Block Status Register Offset Length Description (1) (BA+2)h 1 Block Lock Status Register BSR.0 Block lock status 0 = Unlocked 1 = Locked BSR.1 Block lock-down status 0 = Not locked down 1 = Locked down BSR 2-7: Reserved for future use Add. Value BA+2 --00 or --01 BA+2 (bit 0): 0 or 1 BA+2 (bit 1): 0 or 1 BA+2 (bit 2-7): 0 NOTE: BA = The beginning location of a Block Address (i.e., 008000h is block 1's (64KB block) beginning location in word mode). Preliminary 69 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 C.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table C5. CFI Identification Offset Length Description 10h 3 Query-unique ASCII string "QRY" 13h 2 15h 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address 17h 2 19h 2 Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Hex Add. Code Value 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13: --03 14: --00 15: --39 16: --00 17: --00 18: --00 19: --00 1A: --00 Table C6. System Interface Information 70 Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 20h 21h 22h 23h 24h 25h 26h 1 1 1 1 1 1 1 1 Description Hex Add. Code Value 1B: --17 1.7V VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1D: VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1E: VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts n 1F: "n" such that typical single word program time-out = 2 -sec n 20: "n" such that typical max. buffer write time-out = 2 -sec n 21: "n" such that typical block erase time-out = 2 m-sec n 22: "n" such that typical full chip erase time-out = 2 m-sec n "n" such that maximum word program time-out = 2 times typical 23: n 24: "n" such that maximum buffer write time-out = 2 times typical n 25: "n" such that maximum block erase time-out = 2 times typical n 26: "n" such that maximum chip erase time-out = 2 times typical --19 1.9V --B4 11.4V --C6 12.6V --04 --00 --0A --00 --04 --00 --03 --00 16s NA 1s NA 256s NA 8s NA Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 C.5 Device Geometry Definition Table C7. Device Geometry Definition Offset 27h 28h Length Description n "n" such that device size = 2 in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 2 2Ah 2 2Ch 1 2Dh 31h 35h 4 4 4 Preliminary 6 5 4 3 2 1 0 x512 x256 x128 x64 x32 x16 x8 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- n "n" such that maximum number of bytes in write buffer = 2 Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information - Bottom paramenter device Erase Block Region x-3 Information - Top Paramenter device bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes -B --15 --01 --00 --00 --00 --05 --07 --00 --20 --00 --06 --00 --00 --01 --07 --00 --00 --01 32 Mbit -T --15 --01 --00 --00 --00 --05 --07 --00 --00 --01 --06 --00 --00 --01 --07 --00 --20 --00 -B --16 --01 --00 --00 --00 --09 --07 --00 --20 --00 --06 --00 --00 --01 --07 --00 --00 --01 64 Mbit -T --16 --01 --00 --00 --00 --09 --07 --00 --00 --01 --06 --00 --00 --01 --07 --00 --20 --00 -B --17 --01 --00 --00 --00 --11 --07 --00 --20 --00 --06 --00 --00 --01 --07 --00 --00 --01 -T --17 --01 --00 --00 --00 --11 --07 --00 --00 --01 --06 --00 --00 --01 --07 --00 --20 --00 See table below 28: --01 x16 29: 2A: 2B: 2C: --00 --00 --00 0 See table below 2D: 2E: 2F: 30: 31: 32: 33: 34: Erase Block Region 3-x Information for Bottom parameter device 35: Erase Block Region 1 Information for Top paramenter device 36: bits 0-15 = y, y+1 = number of identical-size erase blocks 37: bits 16-31 = z, region erase block(s) size are z x 256 bytes 38: 16 Mbit Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: 7 x1K Code 27: See table below See table below See table below 128 Mbit -B -T --18 --18 --01 --01 --00 --00 --00 --00 --00 --00 --21 --21 --07 --07 --00 --00 --20 --00 --00 --01 --06 --06 --00 --00 --00 --00 --01 --01 --07 --07 --00 --00 --00 --20 --01 --00 71 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 C.6 Intel-Specific Extended Query Table Table C8. Primary Vendor-Specific Extended Query (1) P = 39h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h 72 Length 3 1 1 4 (P+9)h 1 (P+A)h (P+B)h 2 (P+C)h 1 (P+D)h 1 Description (Optional flash features and commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 10-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of Optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Add. 39: 3A: 3B: 3C: 3D: 3E: 3F: 40: 41: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 42: Hex Code Value --50 "P" --52 "R" --49 "I" --31 "1" --33 "3" --E6 --03 --00 --00 =0 No =1 Yes =1 Yes =0 No =0 No =1 Yes =1 Yes =1 Yes =1 Yes =1 Yes --01 bit 0 43: 44: bit 0 bit 1 45: =1 --03 --00 =1 =1 --18 Yes Yes Yes 1.8V 46: --C0 12.0V Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Table C9. Protection Register Information (1) P = 39h (P+E)h (P+F)h (P+10)h (P+11)h (P+12)h Length 1 4 Hex Description (Optional flash features and commands) Add. Code Value Number of Protection register fields in JEDEC ID space. 47: --01 1 "00h," indicates that 256 protection fields are available Protection Field 1: Protection Description 48: --80 80h This field describes user-available One Time Programmable 49: --00 00h (OTP) Protection register bytes. Some are pre-programmed 4A: --03 8 byte with device-unique serial numbers. Others are user 4B: --03 8 byte programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes Jedec-plane physical low address bits 8-15 = Lock/bytes Jedec-plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user programmable bytes Table C10. Burst Read Information (1) P = 39h (P+13)h Length 1 Description (Optional flash features and commands) Page Mode Read capability Hex Add. Code Value 4C: --03 8 byte n bits 0-7 = "n" such that 2 HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no (P+14)h 1 (P+15)h 1 Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 Bits 3-7 = Reserved 4D: --03 3 4E: --01 4 4F: 50: --02 --07 8 Cont n+1 bits 0-2 "n" such that 2 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the Read Configuration Register bits 0-2 if the device is configured for its maximum word width. See offset 28h for (P+16)h (P+17)h 1 1 Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Table C11. Partition and Erase-block Region Information Bottom (1) P = 39h (P+18)h Preliminary Top (1) Description P = 39h (Optional flash features and commands) (P+18)h Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. See table below Address Bot Top Len 1 51: 51: 73 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Partition Region 1 Information (1) P = 39h Description Bottom Top (Optional flash features and commands) (P+19)h (P+19)h Number of identical partitions within the partition region (P+1A)h (P+1A)h (P+1B)h (P+1B)h Simultaneous program and erase operations allowed in other partitions while a partition in this region is in Read mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1C)h (P+1C)h Simultaneous program and erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1D)h (P+1D)h Simultaneous program and erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1E)h (P+1E)h Partitions' erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in "bulk" x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one (P+1F)h (P+1F)h Partition Region 1 Erase Block Region 1 Information (P+20)h (P+20)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+21)h (P+21)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+22)h (P+22)h (P+23)h (P+23)h Partition 1 (Erase Region 1) Minimum block erase cycles x 1000 (P+24)h (P+24)h (P+25)h (P+25)h Partition 1 (erase region 1) bits per cell; internal error correction bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+26)h (P+26)h Partition 1 (erase region 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) (P+27)h (P+28)h (P+29)h (P+2A)h (P+2B)h (P+2C)h (P+2D)h (P+2E)h 74 Partition Region 1 Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes (bottom parameter device only) Partition 1 (Erase Region 2) minimum block erase cycles x 1000 (bottom parameter device only) Partition 1 (Erase Region 2) bits per cell (bottom parameter device only) bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use Partition 1 (Erase Region 2) pagemode and synchronous mode capabilities defined in Table 10 (bottom parameter device only) bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) See table below Address Bot Top Len 2 52: 52: 53: 53: 1 54: 54: 1 55: 55: 1 56: 56: 1 57: 57: 4 1 58: 59: 5A: 5B: 5C: 5D: 5E: 58: 59: 5A: 5B: 5C: 5D: 5E: 1 5F: 5F: 4 1 60: 61: 62: 63: 64: 65: 66: 1 67: 2 2 Preliminary 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Partition Region 2 Information (1) P = 39h Description Bottom Top (Optional flash features and commands) (P+2F)h (P+27)h Number of identical partitions within the partition region (P+30)h (P+28)h (P+31)h (P+29)h Simultaneous program and erase operations allowed in other partitions while a partition in this region is in Read mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+32)h (P+2A)h Simultaneous program and erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+33)h (P+2B)h Simultaneous program and erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+34)h (P+2C)h Partitions' erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in "bulk" x = number of erase block regions w/ contiguous same-size (P+35)h (P+2D)h Partition Region 2 Erase Block Region 1 Information (P+36)h (P+2E)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+37)h (P+2F)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+38)h (P+30)h (P+39)h (P+31)h Partition 2 (Erase Region 1) (P+3A)h (P+32)h Minimum block erase cycles x 1000 (P+3B)h (P+33)h Partition 2 (Erase Region 1) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+3C)h (P+34)h Partition 2 (erase region 1) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) (P+35)h Partition Region 2 Erase Block Region 2 Information (P+36)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+37)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+38)h (top parameter device only) (P+39)h Partition 2 (Erase Region 2) minimum block erase cycles x 1000 (P+3A)h (top parameter device only) (P+3B)h Partition 2 (Erase Region 2) bits per cell (top parameter only) bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+3C)h Partition 2 (Erase Region 2) pagemode and synchronous mode capabilities as defined in Table 10. (top parameter only) bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) (P+3D)h (P+3D)h Features Space definitions (Reserved for future use) (P+3E)h (P+3E)h Reserved for future use Preliminary See table below Address Bot Top Len 2 68: 60: 69: 61: 1 6A: 62: 1 6B: 63: 1 6C: 64: 1 6D: 65: 4 1 6E: 6F: 70: 71: 72: 73: 74: 66: 67: 68: 69: 6A: 6B: 6C: 1 75: 6D: 2 4 1 6E: 6F: 70: 71: 72: 73: 74: 1 75: 2 TBD Resv'd 76: 77: 76: 77: 75 28F6408W30, 28F3204W30, 28F320W30, 28F640W30 Partition and Erase-block Region Information Address 51: 52: 53: 54: 55: 56: 57: 58: 59: 5A: 5B: 5C: 5D: 5E: 5F: 60: 61: 62: 63: 64: 65: 66: 67: 68: 69: 6A: 6B: 6C: 6D: 6E: 6F: 70: 71: 72: 73: 74: 75: 16 Mbit -B --02 --01 --00 --01 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --02 --06 --00 --00 --01 --64 --00 --01 --03 --03 --00 --01 --00 --00 --03 --07 --00 --00 --01 --64 --00 --01 --03 32 Mbit -T --02 --03 --00 --01 --00 --00 --03 --07 --00 --00 --01 --64 --00 --01 --03 --01 --00 --01 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --20 --00 --64 --00 --01 --02 -B --02 --01 --00 --01 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --01 --00 --00 --07 --07 --00 --00 --01 --64 --00 --01 --03 64Mbit -T --02 --07 --00 --01 --00 --00 --07 --07 --00 --00 --01 --64 --00 --01 --03 --01 --00 --01 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --20 --00 --64 --00 --01 --02 -B --02 --01 --00 --01 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --02 --06 --00 --00 --01 --64 --00 --01 --03 --0F --00 --01 --00 --00 --F --07 --00 --00 --01 --64 --00 --01 --03 -T --02 --0F --00 --01 --00 --00 --F --07 --00 --00 --01 --64 --00 --01 --03 --01 --00 --01 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --20 --00 --64 --00 --01 --02 128Mbit -B -T --02 --02 --01 --1F --00 --00 --01 --01 --00 --00 --00 --00 --02 --1F --07 --07 --00 --00 --20 --00 --00 --01 --64 --64 --00 --00 --01 --01 --02 --03 --06 --01 --00 --00 --00 --01 --01 --00 --64 --00 --00 --02 --01 --06 --03 --00 --1F --00 --00 --01 --01 --64 --00 --00 --00 --01 --1F --03 --07 --07 --00 --00 --00 --20 --01 --00 --64 --64 --00 --00 --01 --01 --03 --02 NOTES: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. For a 16Mb the 1.8 Volt Intel(R) Wireless Flash memory z1 = 0100h = 256 256 * 256 = 64K, y1 = 17h = 23d y1+1 = 24 24 * 64K = 11/2MB Partition 2's offset is 0018 0000h bytes (000C 0000h words). 3. TPD - Top parameter device; BPD - Bottom parameter device. 4. Partition: Each partition is 4Mb in size. It can contain main blocks OR a combination of both main and parameter blocks. 5. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains all the partitions that are made up of main blocks only. B. contains the partition that is made up of the parameter and the main blocks. 76 Preliminary