DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DDR SDRAM Registered Module
184pin Registered Module based on 512Mb C-die
with 72-bit ECC
Revision 0.0
September. 2004
66 TSOP-II and 60 ball FBGA with Pb-Free
(RoHS compliant)
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Revision History
Revision 0.0 (September, 2004)
- First relea se
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Ordering Information
Operating Frequencies
Part Number Density Organization Component Composition Height
M312L6523CUS-CB3/A2/B0 512MB 64M x 72 64Mx8( K4H510838C) * 9EA 1,200mil
M312L2923CUS-CB3/A2/B0 1GB 128M x 72 64Mx8( K4H510838C) * 18EA 1,200mil
M312L2920CUS-CB3/A2/B0 1GB 128M x 72 128Mx4( K4H510438C) * 18EA 1,200mil
M312L5628CU0-CA2/B0 2GB 256M x 72 st.256Mx4( K4H1G0638C) * 18EA 1,200mil
M312L6523CZ0-CCC/B3/A2/B0 512MB 64Mx72 64Mx8( K4H510838C) * 9EA 1,125mil
M312L2923CZ0-CCC/B3/A2/B0 1GB 128M x 72 64Mx8( K4H510838C) * 18EA 1,125mil
M312L2920CZ0-CCC/B3/A2/B0 1GB 128M x 72 128Mx4( K4H510438C) * 18EA 1,125mil
M312L5720CZ0-CCC/B3/A2/B0 2GB 256M x 72 128Mx4( K4H510438C) * 36EA 1,200mil
CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5)
Speed @CL2 - 133MHz 133MHz 100MHz
Speed @CL2.5 166MHz 166MHz 133MHz 133MHz
Speed @CL3 200MHz - - -
CL-tRCD-tRP 3-3-3 2.5-3-3 2-3-3 2.5-3-3
184Pin Registered DIMM based on 512Mb C-die (x4, x8)
Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• SSTL_2 Interface
• 66pin TSOP II and 60 ball FBGA Pb-Free package
• RoHS compliant
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Pin Configuration (Front side/back side)
Note :
1. * : These pins are not used in this module.
2. Pins 111, 158 are NC for 1row module & used for 2row module.
3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
/RESET
VSS
DQ8
DQ9
DQS1
VDDQ
*CK1
*/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
*CK2
*/CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8/DQS17
A10
CB6
VDDQ
CB7
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5/DQS14
VSS
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
VDD
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Pin Description
Pin Name Function Pin Name Function
A0 ~ A12 Address input (Multiplexed) DM0 ~ DM8 Data - in mask
BA0 ~ BA1 Bank Select Address VDD Power supply
(2.5V for DDR266/333, 2.6V for DDR400)
DQ0 ~ DQ63 Data input/output VDDQ Power Supply for DQS
(2.5V for DDR266/333, 2.6V for DDR400)
DQS0 ~ DQS17 Data Strobe input/output VSS Ground
CK0,CK0 ~ CK2, CK2 Clock input VREF Power supply for reference
CKE0, CKE1(for double banks) Clock enable input VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V )
CS0, CS1(for double banks) Chip select input SDA Serial data I/O
RAS Row address strobe SCL Serial clock
CAS Column address strobe SA0 ~ 2 Address in EEPROM
WE Write enable NC No connection
CB0 ~ CB7 Check bit(Data-in/dat a-out)
KEY
KEY
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
512MB, 64M x 72 ECC Module (M312L6523CUS) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
VSS D0 - D8
VDD/VDDQ D0 - D8
D0 - D8
VREF
VDDSPD SPD
D0 - D8
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
RCS0
DQS0
DM0
DM/ CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DM1
DM/ CS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DM2
DM/ CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DM3
DM/ CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4
DM/ CS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM5
DM/ CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6
DM/ CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DM7
DM/ CS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 6
I/O 5
I/O 3
I/O 1
I/O 7
I/O 4
I/O 2
I/O 0
I/O 0
I/O 2
I/O 5
I/O 6
I/O 1
I/O 3
I/O 4
I/O 7
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 7
I/O 4
I/O 2
I/O 0
I/O 6
I/O 5
I/O 3
I/O 1
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
DQS8
DM8
DM/ CS DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
I/O 5
I/O 4
I/O 2
I/O 0
I/O 7
I/O 6
I/O 3
I/O 1
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
PLL*
CK0,CK0
PCK
RAS
CAS
CKE0
BA0-BA1
A0-A12
R
E
G
I
S
T
E
R
CS0
PCK RESET
RCS0
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
RWE
BA0 -BA1 : SDRAMs DQ0 - D8
A0 -A12 : SDRAMs D0 - D8
RAS : SDRAM s D0 - D8
CAS : SDRAM s D0 - D8
CKE : SDRAMs D0 - D8
WE: SDRA Ms D0 - D8
WE
* Wire per Clock Loading table/wiring Diagrams
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
1GB, 128M x 72 ECC Module (M312L2923CUS) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
RCS0
DQS0
DM0
DM/ CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DM1
DM/ CS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DM2
DM/ CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DM3
DM/ CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4
DM/ CS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM5
DM/ CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6
DM/ CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DM7
DM/ CS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 6
I/O 5
I/O 3
I/O 1
I/O 7
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 2
I/O 1
I/O 6
I/O 4
I/O 3
I/O 0
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 7
I/O 4
I/O 2
I/O 0
I/O 6
I/O 5
I/O 3
I/O 1
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
DM/ CS DQS
D9
DM/ CS DQS
D10
DM/ CS DQS
D11
DM/ CS DQS
D12
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
DM/ CS DQS
D13
DM/ CS DQS
D14
DM/ CS DQS
D15
DM/ CS DQS
D16
RCS1
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 1
I/O 2
I/O 4
I/O 6
I/O 0
I/O 3
I/O 5
I/O 7
I/O 0
I/O 2
I/O 5
I/O 6
I/O 1
I/O 3
I/O 4
I/O 7
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 0
I/O 3
I/O 5
I/O 7
I/O 1
I/O 2
I/O 4
I/O 6
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 1
I/O 3
I/O 5
I/O 7
I/O 0
I/O 2
I/O 4
I/O 6
VSS D0 - D17
VDD/VDDQ D0 - D17
D0 - D17
VREF
VDDSPD SPD
D0 - D17
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
DQS8
DM8
DM/ CS DQS
D8
I/O 5
I/O 4
I/O 2
I/O 0
I/O 7
I/O 6
I/O 3
I/O 1
DM/ CS DQS
D17
I/O 2
I/O 3
I/O 5
I/O 7
I/O 0
I/O 1
I/O 4
I/O 6
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
PCK
RAS
CAS
CKE0
CKE1
CS1
BA0-BA1
A0-A12
CS0
WE
PCK RESET
RCS1
RCS0
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
RWE
RCKE1
BA0 -BA1 : SDRAMs DQ0 - D17
A0 -A12 : SDRAMs D0 - D17
RAS : SD RAMs D0 - D17
CAS : SD RAMs DQ0 - D1 7
CKE : SDRAMs D0 - D8
CKE : SDRAMs D9 - D17
WE: SDRAMs D0 - D17
R
E
G
I
S
T
E
R
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
1GB, 128M x 72 ECC Module (M312L2920CUS) (Populated as 1 bank of x4 DDR SDRAM Module)
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQS0
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DQS9
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DQS13
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQS16
RCS0
DQS4
DQS1
DQS5
DQS2
DQS3
DQS15
DQS6
DQS7
DQ15
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DQS8 DQS17
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintaine d as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
RAS
CAS
CKE0
BA0-BA1
A0-A12
S0
RS0
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
RWE
BA0 -BA1 : SDRAMs DQ0 - D17
A0 -A12 : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D17
WE: SDRA M s D 0 - D 1 7
R
E
G
I
S
T
E
R
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D8
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D0
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D1
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D2
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D3
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D4
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D5
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D6
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D7
CS DM
VSS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D17
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D10
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D11
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D12
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D13
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D14
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D15
CS DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D16
CS DM
DQS10
RESET
PCK
PCK
WE
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
VSS
D0 - D17
D0 - D17
VDD/VDDQ D0 - D17
D0 - D17
VREF
Strap: see Note 4
VDDSPD SPD
(DM0)
(DM1)
(DM2)
(DM3)
(DM4)
(DM5)
(DM6)
(DM7)
(DM8)
Functional Block Diagram
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQS0
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM0/DQS9
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM2/DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM3/DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM4/DQS13
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM5/DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM7/DQS16
RCS0
RCS1
DQS4
DQS1
DQS5
DQS2
DQS3
DM6/DQS15
DQS6
DQS7
DQ15
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D0
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D1
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D2
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D3
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D4
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D5
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D6
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D7
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D10
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D11
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D12
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D13
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D14
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D15
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D16
DM
DM1/DQS10
VSS
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D18
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D19
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D20
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D21
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D22
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D23
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D24
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D25
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D27
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D28
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D29
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D30
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D31
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D32
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D33
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D34
DM
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RA0 - RA12 A0-An: SDRAMs D0 - D35
RAS: SDRAMs D0 - D35
RCAS CAS: SDRAMs D0 - D35
RCKE1 CKE: SDRAMs D18 - D35
PCK
WE: SDRAMs D0 - D 3 5
RCKE0
RBA0 - RBA1 BA0-BAn: SDRAMs D0 - D35
RAS
CAS
CKE0
CKE1
RCS1
CS1
BA0-BA1
A0-A12
R
E
G
I
S
T
E
R
RRAS
RWE
CS0
RCS0
WE
PCK
RESET
CKE: SDRAMs D0 - D17
PLL
CK0,CK0
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
VSS
D0 - D35
D0 - D35
VDD/VDDQ D0 - D35
D0 - D35
VREF
VDDSPD SPD
2GB, 256M x 72 ECC Module [ M312L5628CU0 ] (Populated as 2 bank of x4 DDR SDRAM Module)
Functional Block Diagram
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DQS8 DM8/DQS17
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D8
DM DQS
I/O 3
I/O 2
I/O 1
I/O 0
D17
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D26
DM DQS
I/O 3
I/O 2
I/O 1
I/O 0
D35
DM
CS CS CS
CS CS CS CS
CS CS CS CS
CS CS CS CS
CS CS CS CS
CS CS CS CS
CS CS CS CS
CS CS CS CS
CS CS CS CS
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 0
I/O 2
I/O 4
I/O 7
D0
DM0
I/O 3
I/O 1
I/O 6
I/O 5
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM
D1
DM1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
D2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
D3
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
D4
DM4
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
D5
DM5
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
D6
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
D7
DM7
RCS0
CS CS
CS CS
CS
CS
CS
CS
DQS0
DQS
DQS4
DQS1 DQS5
DQS
DQS
DQS
DM6
DQS6
DQS7
DQ15
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DM
D8
CS DQS
DQS
DQS
DQS
DQS
PCK
RAS
CAS
CKE0
BA0-BA1
A0-A12
R
E
G
I
S
T
E
R
CS0
PCK RESET
RCS0
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
RWE
BA0 -BA1 : DDR SDRAMs D0 - D8
A0 -A12 : DDR SDRAMs D0 - D8
RAS : DDR SDRAMs D0 - D8
CAS : DDR SDRAMs D0 - D8
CKE : DDR SDRAMs D0 - D8
WE: DDR SDRAMs D0 - D8
WE
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
VSS DDR SDRAMs D0 - D8
VDD/VDDQ DDR SDRAMs D0 - D8
DDR SDRAMs D0 - D8
VREF
VDDSPD SPD
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
512MB, 64M x 72 ECC Module (M312L6523CZ0) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
DM2
DQS2
DM3
DQS3
DM8
DQS8
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 0
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 0
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
1GB, 128M x 72 ECC Module (M312L2923CZ0) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
RCS0
DQS0
DM0
DM/ CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
DQS1
DM1
DM/ CS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DM2
DM/ CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DM3
DM/ CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM4
DM/ CS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DM5
DM/ CS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DM6
DM/ CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DM7
DM/ CS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
DM/ CS DQS
D9
DM/ CS DQS
D10
DM/ CS DQS
D11
DM/ CS DQS
D12
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
DM/ CS DQS
D13
DM/ CS DQS
D14
DM/ CS DQS
D15
DM/ CS DQS
D16
RCS1
VSS D0 - D17
VDD/VDDQ D0 - D17
D0 - D17
VREF
VDDSPD SPD
D0 - D17
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
DQS8
DM8
DM/ CS DQS
D8
DM/ CS DQS
D17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
PCK
RAS
CAS
CKE0
CKE1
CS1
BA0-BA1
A0-A12
CS0
WE
PCK RESET
RCS1
RCS0
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
RWE
RCKE1
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 : DDR SDRAM D0 - D17
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
WE: DDR SDRAM D0 - D17
R
E
G
I
S
T
E
R
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
1GB, 128M x 72 ECC Module (M312L2920CZ0) (Populated as 1 bank of x4 DDR SDRAM Module)
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQS0
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DQS9
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DQS13
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQS16
RCS0
DQS4
DQS1
DQS5
DQS2
DQS3
DQS15
DQS6
DQS7
DQ15
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DQS8 DQS17
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintaine d as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
RAS
CAS
CKE0
BA0-BA1
A0-A12
CS0
RCS0_2
RCS0_1
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0A
RWE
RCKE0B
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 :DDR SDRAM D0 - D17
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
WE:DDR SDRAM D0 - D17
R
E
G
I
S
T
E
R
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D8
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D0
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D1
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D2
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D3
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D4
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D5
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D6
CS DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D7
CS DM
VSS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
CS DM
DQS
D10
CS DM
DQS
D11
CS DM
DQS
D12
CS DM
DQS10
RESET
PCK
PCK
WE
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
VSS
D0 - D17
D0 - D17
VDD/VDDQ D0 - D17
D0 - D17
VREF
VDDSPD SPD
(DM0)
(DM1)
(DM2)
(DM3)
(DM4)
(DM5)
(DM6)
(DM7)
(DM8)
Functional Block Diagram
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS
D13
CS DM
DQS
D14
CS DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS
D15
CS DM
DQS
D16
CS DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQS
D17
CS DM
I/O 0
I/O 1
I/O 2
I/O 3
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQS0
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DQS9
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DQS13
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQS16
RCS0
RCS1
DQS4
DQS1
DQS5
DQS2
DQS3
DQS15
DQS6
DQS7
DQ15
DQS
D0
CS DM
DQS
D1
DM
DQS
D2
DM
DQS
D3
DM
DQS
D4
DM
DQS
D5
DM
DQS
D6
DM
DQS
D7
DM
DQS10
VSS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D18
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D19
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D20
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D21
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D22
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D23
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D24
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D25
DM
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be cha nged.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RA0 - RA12 A0-A12:
DDR SDRAM
D0 - D35
RAS:
DDR SDRAM
D0 - D35
RCAS CAS:
DDR SDRAM
D0 - D35
RCKE1 CKE:
DDR SDRAM
D18 - D35
PCK
WE:
DDR SDRAM
D0 - D35
RCKE0
RBA0 - RBA1 BA0-BA1:
DDR SDRAM
D0 - D35
RAS
CAS
CKE0
CKE1
RCS1
CS1
BA0-BA1
A0-A12
R
E
G
I
S
T
E
R
RRAS
RWE
CS0
RCS0
WE
PCK
RESET
CKE:
DDR SDRAM
D0 - D17
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL SDA
WP
VSS
D0 - D35
D0 - D35
VDD/VDDQ D0 - D35
D0 - D35
VREF
VDDSPD SPD
2GB, 256M x 72 ECC Module [M312L5720CZ0] (Populated as 2 bank of x4 DDR SDRAM Module)
Functional Block Diagram
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
CB0
CB1
CB2
CB3
DQS8 DQS
D8
DM DQS
I/O 0
I/O 1
I/O 2
I/O 3
D26
DM CB4
CB5
CB6
CB7
DQS17
(DM0)
(DM1)
(DM2)
(DM3)
(DM4)
(DM5)
(DM6)
(DM7)
(DM8)
CS
CS CS
CS CS
CS CS
CS CS
CS CS
CS CS
CS CS
CS CS
DQS
D9
DM DQS
I/O 3
I/O 2
I/O 1
I/O 0
D27
DM
CS CS
DQS
D10
DM
DQS
D11
DM
DQS
D12
DM
DQS
D13
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D28
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D29
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D30
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D31
DM
CS CS
CS CS
CS CS
CS CS
DQS
D14
DM
DQS
D15
DM
DQS
D16
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D32
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D33
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D34
DM
DQS
D17
DM DQS
I/O 3
I/O 2
I/O 1
I/O 0
D35
DM
CS CS
CS CS
CS CS
CS CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD supply relative to Vss VDD,VDDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1.5 * # of component W
Short circuit current IOS 50 mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter Symbol Min Max Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) VDD 2.3 2.7 V
Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDD 2.5 2.7 V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/33 3) VDDQ 2.3 2.7 V
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDDQ 2.5 2.7 V
I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1
I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V2
Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V
Input logic low voltage VIL(DC) -0.3 VREF-0.15 V
Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V
Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V 3
V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4
Input leakage current II-2 2 uA
Output leakage current IOZ -5 5 uA
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9mA
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to
peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-
ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum
difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to mini-
mum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
Note :
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DDR SDRAM IDD spec table
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes
IDD0 1,695 1,355 1,355 mA
IDD1 1,920 1,580 1,580 mA
IDD2P 420 345 345 mA
IDD2F 1,020 770 770 mA
IDD2Q 600 525 525 mA
IDD3P 645 570 570 mA
IDD3N 1,110 860 860 mA
IDD4R 1,965 1,625 1,625 mA
IDD4W 2,100 1,670 1,670 mA
IDD5 2,550 2,210 2,210 mA
IDD6 Normal 420 345 345 mA
Low power 405 330 330 mA Optional
IDD7A 3,900 3,335 3,335 mA
M312L6523CUS [ (64M x 8) * 9 , 512MB Module ]
M312L2923CUS [ (64M x 8) * 18 , 1GB Module ]
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes
IDD0 2,180 1,970 1,970 mA
IDD1 2,410 2,190 2,190 mA
IDD2P 590 540 540 mA
IDD2F 1,415 1,290 1,290 mA
IDD2Q 950 900 900 mA
IDD3P 1,040 990 990 mA
IDD3N 1,595 1,470 1,470 mA
IDD4R 2,450 2,240 2,240 mA
IDD4W 2,585 2,280 2,280 mA
IDD5 3,040 2,820 2,820 mA
IDD6 Normal 590 540 540 mA
Low power 560 510 510 mA Optional
IDD7A 4,390 3,950 3,950 mA
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DDR SDRAM IDD spec table
M312L2920CUS [ (128M x 4) * 18 , 1GB Module ]
M312L5628CU0 [ (st.256M x 4) * 18 , 2GB Module ]
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes
IDD0 2,640 2,340 2,340 mA
IDD1 3,090 2,790 2,790 mA
IDD2P 465 415 415 mA
IDD2F 1,290 1,170 1,170 mA
IDD2Q 830 780 780 mA
IDD3P 920 870 870 mA
IDD3N 1,470 1,350 1,350 mA
IDD4R 3,180 2,880 2,880 mA
IDD4W 3,450 2,970 2,970 mA
IDD5 4,350 4,050 4,050 mA
IDD6 Normal 465 420 420 mA
Low power 430 380 380 mA Optional
IDD7A 7,050 6,300 6,300 mA
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes
IDD0 3,610 3,310 3,310 mA
IDD1 4,060 3,760 3,760 mA
IDD2P 810 760 760 mA
IDD2F 2,080 1,960 1,960 mA
IDD2Q 1,530 1,480 1,480 mA
IDD3P 1,710 1,660 1,660 mA
IDD3N 2,440 2,320 2,320 mA
IDD4R 4,150 3,850 3,850 mA
IDD4W 4,420 3,940 3,940 mA
IDD5 5,320 5,020 5,020 mA
IDD6 Normal 810 760 760 mA
Low power 735 685 685 mA Optional
IDD7A 8,020 7,270 7,270 mA
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DDR SDRAM IDD spec table
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit Notes
IDD0 1,790 1,695 1,355 1,355 mA
IDD1 2,010 1,920 1,580 1,580 mA
IDD2P 420 420 345 345 mA
IDD2F 1,020 1,020 770 770 mA
IDD2Q 600 600 525 525 mA
IDD3P 780 645 570 570 mA
IDD3N 1,290 1,110 860 860 mA
IDD4R 2,100 1,965 1,625 1,625 mA
IDD4W 2,280 2,100 1,670 1,670 mA
IDD5 2,730 2,550 2,210 2,210 mA
IDD6 Normal 420 420 345 345 mA
Low power 405 405 330 330 mA Optional
IDD7A 3,990 3,900 3,335 3,335 mA
M312L6523CZ0 [ (64M x 8) * 9 , 512MB Module ]
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit Notes
IDD0 2,450 2,180 1,970 1,970 mA
IDD1 2,680 2,410 2,190 2,190 mA
IDD2P 590 590 540 540 mA
IDD2F 1,415 1,415 1,290 1,290 mA
IDD2Q 950 950 900 900 mA
IDD3P 1,310 1,040 990 990 mA
IDD3N 1,960 1,595 1,470 1,470 mA
IDD4R 2,770 2,450 2,240 2,240 mA
IDD4W 2,950 2,585 2,280 2,280 mA
IDD5 3,400 3,040 2,820 2,820 mA
IDD6 Normal 590 590 540 540 mA
Low power 560 560 510 510 mA Optional
IDD7A 4,660 4,390 3,950 3,950 mA
M312L2923BG0 [ (64M x 8) * 18 , 1GB Module ]
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
DDR SDRAM IDD spec table
M312L5720BG0 [ (128M x 4) * 36, 2GB Module ]
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit Notes
IDD0 4,150 3,610 3,310 3,310 mA
IDD1 4,600 4,060 3,760 3,760 mA
IDD2P 810 810 760 760 mA
IDD2F 2,080 2,080 1,960 1,960 mA
IDD2Q 1,530 1,530 1,480 1,480 mA
IDD3P 2,250 1,710 1,660 1,660 mA
IDD3N 3,160 2,440 2,320 2,320 mA
IDD4R 4,780 4,150 3,850 3,850 mA
IDD4W 5,140 4,420 3,940 3,940 mA
IDD5 6,040 5,320 5,020 5,020 mA
IDD6 Normal 810 810 760 760 mA
Low power 735 735 685 685 mA Optional
IDD7A 8,560 8,020 7,270 7,270 mA
M312L2920BG0 [ (128M x 4) * 18 , 1GB Module ]
(VDD=2.7V, T = 10°C)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit Notes
IDD0 2,820 2,640 2,340 2,340 mA
IDD1 3,270 3,090 2,790 2,790 mA
IDD2P 470 465 415 415 mA
IDD2F 1,290 1,290 1,170 1,170 mA
IDD2Q 830 830 780 780 mA
IDD3P 1,190 920 870 870 mA
IDD3N 1,830 1,470 1,350 1,350 mA
IDD4R 3,450 3,180 2,880 2,880 mA
IDD4W 3,810 3,450 2,970 2,970 mA
IDD5 4,710 4,350 4,050 4,050 mA
IDD6 Normal 465 465 420 420 mA
Low power 430 430 380 380 mA Optional
IDD7A 7,230 7,050 6,300 6,300 mA
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Output Load Circuit (SSTL_2)
Output Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
RT=50Ω
Vtt=0.5*VDDQ
Input/Output Cap acit ance (TA= 25°C, f=100MHz)
Parameter Symbol M312L6523CUS,M312L2920CUS M312L2923CUS,M312L5720CU0 Unit
Min Max Min Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )CIN1 9 11 9 11 pF
Input capacitance(CKE0) CIN2 9 11 9 11 pF
Input capacitance( CS0) CIN3 9 11 9 11 pF
Input capacitance( CLK0, CLK0 ) CIN411121112pF
Input capacit ance(DM0~DM8) CIN5 10 11 14 16 pF
Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 11 14 16 pF
Data input/output capacitance (CB0~CB7) Cout2 10 11 14 16 pF
Parameter Symbol M312L6523CZ0,M312L2920CZ0 M312L2923CZ0,M312L5720CZ0 Unit
Min Max Min Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )CIN1 9 11 9 11 pF
Input capacitance(CKE0) CIN2 9 11 9 11 pF
Input capacitance( CS0) CIN3 9 11 9 11 pF
Input capacitance( CLK0, CLK0 ) CIN411121112pF
Input capacit ance(DM0~DM8) CIN5 10 11 13 15 pF
Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 11 13 15 pF
Data input/output capacitance (CB0~CB7) Cout2 10 11 13 15 pF
AC Operating Conditions
Parameter/Condition Symbol Min Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V
Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1
Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2
Output Load Circuit (SSTL_2)
Output Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
RT=50Ω
Vtt=0.5*VDDQ
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
AC Timming Parameters & Specifications
Parameter Symbol CC
(DDR400@CL=3.0) B3
(DDR333@CL=2.5) A2
(DDR266@CL=2.0) B0
(DDR266@CL=2.5) Unit Note
Min Max Min Max Min Max Min Max
Row cycle time tRC 55 60 65 65 ns
Refresh row cycle time tRFC 70 72 75 75 ns
Row active time tRAS 40 70K 42 70K 45 120K 45 120K ns
RAS to CAS delay tRCD 15 18 20 20 ns
Row precharge time tRP 15 18 20 20 ns
Row active to Row active delay tRRD 10 12 15 15 ns
Write recovery time tWR 15 15 15 15 ns
Last data in to Read commandtWTR2111tCK
Clock cycle time CL=2.0 tCK - - 7.5 12 7.5 12 10 12 ns
CL=2.5 6 12 6 12 7.5 12 7.5 12 ns
CL=3.0 510------
Clock high level width tCH 0.45 0.550.450.550.450.550.450.55tCK
Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS-out access time from CK/CK tDQSCK -0.55 +0.55 -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns
Output data access time from CK/CK tAC -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns
Data strobe ed ge to ouput data edge tDQSQ - 0.4 - 0.45 - 0.5 - 0.5 ns 22
Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
CK to valid DQS-in tDQ SS 0 .72 1.250.751.250.751.250.751.25tCK
DQS-in setup time tWPRES0000ns13
DQS-in hold time tWPRE 0.25 0.25 0.25 0.25 tCK
DQS falling edge to CK rising -setup time tDSS 0.2 0.2 0.2 0.2 tCK
DQS falling edge from CK risin g-hold time tDSH 0.2 0.2 0.2 0.2 tCK
DQS-in high level width tDQSH 0.35 0.35 0.35 0.35 tCK
DQS-in low level wid th tDQSL 0.35 0.35 0.35 0.35 tCK
Address and Control Input setup time( fast) tIS 0.6 0.75 0.9 0.9 ns 15, 17~19
Address and Control Input hold time(fast) tIH 0.6 0.75 0.9 0.9 ns 15, 17~19
Address and Control Input setup tIS 0.7 0.8 1.0 1.0 ns 16~19
Address and Control Input hold time(slow) tIH 0.7 0.8 1.0 1.0 ns 16~19
Data-out high impedence time from CK/CK tHZ - +0.65 - +0.7 - +0.75 - +0.75 ns 11
Data-out lo w impedence time from CK/CK tLZ -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11
Mode register set cycle time tMRD 10 12 15 15 ns
DQ & DM setup time to DQS tDS 0.4 0.45 0.5 0.5 ns j, k
DQ & DM hold time to DQS tDH 0.4 0.45 0.5 0.5 ns j, k
Control & Address input pulse width tIPW 2.2 2.2 2.2 2.2 ns 18
DQ & DM input pulse wid th tDIPW 1.75 1.75 1.75 1.75 ns 18
Exit self refresh to non-Read command tXSNR 75 75 75 75 ns
Exit self refresh to read command tXSRD 200 200 200 200 tCK
Refresh interval time tREFI 7.8 7.8 7.8 7.8 us 14
Output DQS valid window tQH tHP
-tQHS -tHP
-tQHS -tHP
-tQHS -tHP
-tQHS -ns21
Clock half period tHP tCLmin
or tCHmin -tCLmin
or tCHmin -tCLmin
or tCHmin -tCLmin
or tCHmin -ns20, 21
Data hold skew factor tQHS 0.5 0.55 0.75 0.75 ns 21
DQS write postamble time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 12
Active to Read with Auto precharge
command tRAP 15 18 20 20
Autoprecharge write recovery +
Precharge time tDAL (tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK) tCK 23
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure
proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR333 DDR266 DDR200
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Units Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD 0.5 4.0 V/ns a, m
Input Slew Rate ∆tIS ∆tIH Units Notes
0.5 V/ns 0 0 ps i
0.4 V/ns +50 0 ps i
0.3 V/ns +100 0 ps i
Input Slew Rate ∆tDS ∆tDH Units Notes
0.5 V/ns 0 0 ps k
0.4 V/ns +75 +75 ps k
0.3 V/ns +150 +150 ps k
Delta Slew Rate ∆tDS ∆tDH Units Notes
+/- 0.0 V/ns 0 0 ps j
+/- 0.25 V/ns +50 +50 ps j
+/- 0.5 V/ns +100 +100 ps j
Slew Rate Characteristic Typical Range
(V/ns) Minimum
(V/ns) Maximum
(V/ns) Notes
Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h
Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h
Slew Rate Characteristic Typical Range
(V/ns) Minimum
(V/ns) Maximum
(V/ns) Notes
Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h
Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h
AC CHARACTERISTICS DDR266B DDR200
PARAMETER MIN MAX MIN MAX Notes
Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD 0.67 1.5 e,m
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
Output Test point
VDDQ
50Ω
Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temper ature and
voltage range. For a given output, it represent s the maxi mum dif ference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS an d tDH in the case where DQ, DM, and DQS slew rates dif fer, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delt a rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
Output Test point
VSSQ
50Ω
Figure 2 : Pullup slew rate test load
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9
A11, A12 Note
Register Extended MRS H X L L L L OP CODE 1, 2
Register Mode Register Set H X L L L L OP CODE 1, 2
Refresh
Auto Refresh HHLL LH X 3
Self
Refresh
Entry L 3
Exit L H LHHH X3
HX XX 3
Bank Active & Row Addr. H X L L H H V Row Address
(A0~A9, A11,A12)
Read &
Column Address Auto Precharge Disable HXLHLHV
LColumn
Address 4
Auto Precharge Enable H 4
Write &
Column Address Auto Precharge Disable HXLHLLV
LColumn
Address 4
Auto Precharge Enable H 4, 6
Burst Stop H X L H H L X 7
Precharge Bank Selection HXLLHL
VL X
All Banks X H 5
Active Power Down Entry H L HX XX XLVVV
Exit L H X X X X
Precharge Power Down Mode Entry H L HX XX
X
LHHH
Exit L H HX XX
LVVV
DM H X X 8
No operation (NOP) : Not defined H X HX XX X9
LHHH 9
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Dat a-in are masked at the both edges (W rite DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Units : Inches (Millimeters)
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 DDR SDRAM, TSOPII
SDRAM Part No : K4H510838C
A B
REG
PLL
A B
5.25 ± 0.005
5.171
(131.350)
(133.350 ± 0.13)
(30.48 +/-0.15)
1.2 +/-0.06
5.077
(128.950)
0.393
(10.00)
(19.80)
0.78
(17.80)
0.7
0.10 MCBA
R (2.00)
0.0787
(3.00 Min)
0.118 Min
REG
0.157 Max
0.050 ± 0.0039
(1.270 ± 0.10)
(3.99 Max)
(4.00)
(0.157)
Physical Dimensions : 64M x 72 (M312L6523CUS)
0.050
0.0078 ±0.006
(0.20 ±0.15)
(1.270)
0.100 ± 0.0079
(2.50 ± 0.2 )
Detail B
0.250
(6.350)
Detail A
0.071
(1.80)
0.039 ± 0.002
(1.000 ± 0.050)
(3.80)
2.175
0.10 MCA
0.1496
(3.00 Min)
0.118 Min
R (2.00)
0.0787
(4.00 ± 0.1)
0.1575 ± 0.004
MB
0.100
(2.30)
2.500 +0.1/-0.0
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Units : Inches (Millimeters)
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8, 128Mx4 DDRSDRAM, TSOPII
SDRAM Part No. : K4H510838C, K4H510438C
A B
REG
PLL
A B
5.25 ± 0.005
5.171
(131.350)
(133.350 ± 0.13)
5.077
(128.950)
0.393
(10.00)
(19.80)
0.78
(17.80)
0.7
0.10 MCBA
R (2.00)
0.0787
REG
0.157 Max
0.050 ± 0.0039
(1.270 ± 0.10)
(3.99 Max)
(4.00)
(0.157)
Physical Dimensions: 128Mx72 (M312L2923CUS), 128Mx72 (M312L2920CUS)
(30.48 +/-0.15)
1.2 +/-0.06
(3.00 Min)
0.118 Min
0.050
0.0078 ±0.006
(0.20 ±0.15)
(1.270)
0.100 ± 0.0079
(2.50 ± 0.2 )
Detail B
0.250
(6.350)
Detail A
0.071
(1.80)
0.039 ± 0.002
(1.000 ± 0.050)
(3.80)
2.175
0.10 MCA
0.1496
(3.00 Min)
0.118 Min
R (2.00)
0.0787
(4.00 ± 0.1)
0.1575 ± 0.004
MB
0.100
(2.30)
2.500 +0.1/-0.0
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Units : Inches (Millimeters)
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is st.256Mx4 SDRAM, 66TSOPII
SDRAM Part NO : K4H1G0638C
A B
PLL
A B
5.25 ± 0.005
5.171
(131.350)
(133.350 ± 0.13)
5.077
(128.950)
0.393
(10.00)
(19.80)
0.78
(17.80)
0.7
0.10 MCBA
R (2.00)
0.0787
Reg.
0.268 Max
0.050 ± 0.0039
(1.270 ± 0.10)
(6.81 Max)
(4.00)
(0.157)
Physical Dimensions: st.256Mx72 (M312L5628CU0)
(30.48 +/-0.15)
1.2 +/-0.06
(3.00 Min)
0.118 Min
0.100
(2.30)
2.500 +0.1/-0.0
0.050
0.0078 ±0.006
(0.20 ±0.15)
(1.270)
0.100 ± 0.0079
(2.50 ± 0.2 )
Detail B
0.250
(6.350)
Detail A
0.071
(1.80)
0.039 ± 0.002
(1.000 ± 0.050)
(3.80)
2.175
0.10 MCA
0.1496
(3.00 Min)
0.118 Min
R (2.00)
0.0787
(4.00 ± 0.1)
0.1575 ± 0.004
MB
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 DDR SDRAM, FBGA
DDR SDRAM Part No. : K4H510838C-Z***,
Physical Dimensions: 64Mx72 (M312L6523CZ0)
133.35 A
128.95 A
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
64.77 P2 49.53 P3
120.65 P1
19.80 B1
28.575 +/-0.15 B
6.35
ab
10.00 B2
192
Detail BDetail A
3.80 W
X1 X2
6.35 X
2.175 4.175
V1.80
D1.0 +/-0.05
0.20 +/- 0.15 T
2.50 G
E
1.27
MAX 0.178 D1
Units : Millimeters
2.99 MAX
12.00
18493
1.27 +/-0.1
2x DIA. 2.50 +0.1/-0.00 N
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No. : K4H510838C-Z***, K4H510438C-Z***
Physical Dimensions: 128Mx72 (M312L2923CZ0), (M312L2920CZ0)
133.35 A
128.95 A
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
64.77 P2 49.53 P3
120.65 P1
19.80 B1
28.575 +/-0.15 B
6.35
ab
10.00 B2
192
Detail BDet ail A
3.80 W
X1 X2
6.35 X
2.175 4.175
V1.80
D1.0 +/-0.05
0.20 +/- 0.15 T
2.50 G
E
1.27
MAX 0.178 D1
Units : Millimeters
18493
3.99 MAX
12.00
1.27 +/-0.1
2x DIA. 2.50 +0.1/-0.00 N
DDR SDRAM
512MB, 1GB, 2GB Registered DIMM
Rev. 0.0 September, 2004
Preliminary
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No : K4H510438C-Z***
Physical Dimensions: 256Mx72 (M312L5720CZ0)
Units : Millimeters
133.35 A
128.95 A
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
64.77 P2 49.53 P3
120.65 P1
19.80 B1
30.48 +/-0.15 B
6.35
ab
10.00 B2
192
Detail BDet ail A
3.80 W
X1 X2
6.35 X
2.175 4.175
V1.80
D1.0 +/-0.05
0.20 +/- 0.15 T
2.50 +/-0.2 G
E
1.27
MAX 0.178 D1
3.99 MAX
12.0 10.0
18493
1.27 +/-0.1
2x DIA. 2.50 +0.1/-0.00 N
