M28W640HSU70ZA6E - Numonyx - Product.Network

November 2008 Rev 3 1/72

M28W640HCT

M28W640HCB

64 Mbit (4 Mb x 16, boot block)

3 V supply Flash memory

Features

Supply voltage

–V

DD = 2.7 V to 3.6 V

–V

PP = 12 V for fast program (optional)

Access times: 70 ns

Asynchronous Page Read mode

– Page width: 4 words

– Page access: 25 ns

– Random access: 70 ns

Programming time:

–10μs typical

– Double Word Programming option

– Quadruple Word Programming option

Common Flash interface

Memory blocks

– Parameter blocks (top or bottom location)

– Main blocks

Block locking

– All blocks locked at power-up

– Any combination of blocks can be locked

–WP

for block lock-down

Security

– 128 bit user programmable OTP cells

– 64 bit unique device identifier

Automatic standby mode

Program and Erase Suspend

100,000 program/erase cycles per block

Electronic signature

– Manufacturer code: 20h

– Top device code, M28W640HCT: 8848h

– Bottom device code, M28W640HCB:

8849h

Packages

– RoHS compliant

TSOP48 (N)

12 x 20 mm

FBGA

TFBGA48 (ZB)

6.39 x 10.5 mm

www.numonyx.com

Content s M2 8W640HCT , M28W640HCB
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Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 Address inputs (A0-A21)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
3 Chip Enable (E)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
4 Output Enable (G)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
5 Write Enable (W)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
6 Write Protect (WP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
7 Reset (RP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
8 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
9 VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
Bus operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
3 Output Disable  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
4 Standby   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
5 Automatic Standby  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
6 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1 Read Memory Array command   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
4 Read CFI Query command   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
5 Block Erase command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
6 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
7 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
8 Quadruple Word Program command  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
9 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19

M28W640HCT, M28W640HCB Contents
 3/72
10 Program/Erase Suspend command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
11 Program/Erase Resume command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
12 Protection Register Program command  . . . . . . . . . . . . . . . . . . . . . . . . . .  20
13 Block Lock command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
14 Block Unlock command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
15 Block Lock-down command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1 Reading a block’s lock status  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
2 Locked state  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
3 Unlocked state  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
4 Lock-down state  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
5 Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . .  26
Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1 Program/Erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
2 Erase Suspend status (bit 6)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
3 Erase status (bit 5)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
4 Program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
5 VPP status (bit 3)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
6 Program Suspend status (bit 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
7 Block Protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
8 Reserved (bit 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ap pe n dix  A Bloc k  addr e ss tables. . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .  . . . . . . 45
Ap pe n d ix  B Comm o n F la s h  int e r f ac e  (C F I ) . . . . . .  . . . . . . . . . . . . . . . . .  . . . . . . 5 3

Content s M2 8W640HCT , M28W640HCB

4/72

Appendix C Flowcharts and pseudocodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Appendix D Com mand interface and Program/Erase controller st ate . . . . . . . 67

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

M28W640HCT, M28W640HCB List of tables
 5/72
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 6. Read block lock signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Program, Erase times and Program/Erase endurance cycles  . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Block Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Write AC characteristics, Write Enable controlled  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Power-up and Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 42
Table 21. TFBGA48 6.39 x 10.5 mm - 8 x 6 ball array, 0.75 mm pitch, package mechanical data  . . 43
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Top boot block addresses, M28W640HCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Bottom boot block addresses, M28W640HCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 25. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 26. CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 27. CFI query system interface information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 28. Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 30. Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 31. Write state machine current/next  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 32. Write state machine current/next  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 33. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

List of figures M28W64 0H CT, M28 W640HCB
6/72   
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Protection register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Power-up and Reset AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline  . . . . . . . . . . . . 42
Figure 14. TFBGA48 6.39 x 10.5 mm - 8 x 6 ball array, 0.75 mm pitch, bottom view package outline 43
Figure 15. Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. Double Word Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 17. Quadruple Word Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18. Program Suspend & Resume flowchart and pseudocode  . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 19. Erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 20. Erase Suspend & Resume flowchart and pseudocode  . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 21. Locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 22. Protection Register Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 66

M28W640HCT, M28W640HCB Description

7/72

1 Description

The M28W640HCT and M28W640HCB are 64 Mbit (4 Mbit x 16) non-volatile Flash

memories that can be erased electrically at block level and programmed in-system on a

word-by-word basis using a 2.7 V to 3.6 V VDD supply. An optional 12V VPP power supply is

provided to speed up customer programming.

The devices feature an asymmetrical blocked architecture. They have an array of 135

blocks: 8 parameter blocks of 4 Kwords and 127 main blocks of 32 Kwords. The

M28W640HCT has the parameter blocks at the top of the memory address space while the

M28W640HCB locates the parameter blocks starting from the bottom. The memory maps

are shown in Figure 4: Block addresses.

The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme

that allows any block to be locked or unlocked with no latency, enabling instant code and

data protection. All blocks have three levels of protection. They can be locked and locked-

down individually preventing any accidental programming or erasure. There is an additional

hardware protection against program and erase. When VPP ≤ VPPLK all blocks are protected

against program or erase. All blocks are locked at power-up.

Each block can be erased separately. Erase can be suspended in order to perform either

read or program in any other block and then resumed. Program can be suspended to read

data in any other block and then resumed. Each block can be programmed and erased over

100,000 cycles.

The device includes a 192-bit protection register to increase the protection of a system

design. The protection register is divided into a 64-bit segment and a 128-bit segment. The

64-bit segment contains a unique device number written by Numonyx, while the second one

is one-time-programmable by the user. The user programmable segment can be

permanently protected. Figure 5, shows the protection register memory map.

Program and Erase commands are written to the command interface of the memory. An on-

chip Program/Erase controller takes care of the timings necessary for program and erase

operations. The end of a program or erase operation can be detected and any error

conditions identified. The command set required to control the memory is consistent with

JEDEC standards.

The memory is offered in TSOP48 (12 × 20 mm) and TFBGA48 (6.39 × 10.5 mm, 0.75 mm

pitch) packages and is supplied with all the bits erased (set to ’1’).

Description M 28W 640H CT , M28W640HCB

8/72

Figure 1. Logic diagram

Table 1. Signal n ames

Name Description Direction

A0-A21 Address inputs Inputs

DQ0-DQ15 Data input/output I/O

EChip Enable Input

GOutput Enable Input

WWrite Enable Input

RP Reset Input

WP Write Protect Input

VDD Power supply Power supply

VPP Optional supply voltage for fast program & erase Power supply

VSS Ground Power supply

NC Not connected internally –

AI09903

A0-A21

DQ0-DQ1

VDD

M28W640HCT

M28W640HCB

VSS

VPP

M28W640HCT, M28W640HCB Description

9/72

Figure 2. TSOP connections

1. All VDD pins must be connected to the power supply.

2. All VSS pins must be connected to the ground.

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15

VDD

DQ4

DQ5

DQ7

VPP

AI09904c

M28W640HCT

M28W640HCB

24 25

DQ8

A20

A19

A18

DQ1

DQ11

A12

A13

A16

A11

VDD

A15

A14 VSS

VSS

A21

Description M 28W 640H CT , M28W640HCB

10/72

Figure 3. TFBGA connections (top view through pac ka ge)

1. All VDD pins must be connected to the power supply.

2. All VSS pins must be connected to the ground.

AI04380c

87654321

A7VPP

A8A11

A13

A0EDQ8DQ5DQ14A16

VSS

DQ0DQ9DQ3DQ6

DQ15

VDD

DQ1DQ10VDD

DQ7VSS

DQ2

A5A17WA10

A14

A1A3A6A9A12A15

RP A18

DQ4

DQ13 G

DQ12

DQ11

WP A19

A20

A21

M28W640HCT, M28W640HCB Description

11/72

Figure 4. Block addresses

1. Also see Appendix A, Tables 23 and 24 for a full listing of the block addresses.

Figure 5. Protection register mem ory map

AI09905b

4 Kwords

3FFFFF

3FF000

32 Kwords

00FFFF

008000

32 Kwords

007FFF

000000

M28W640HCT

Top boot block addresses

4 Kwords

3F8FFF

3F8000

32 Kwords

3F0000

3F7FFF

Total of 8

4 Kword blocks

Total of 127

32 Kword blocks

4 Kwords

3FFFFF

3F8000 32 Kwords

32 Kwords

000FFF

000000

M28W640HCB

Bottom boot block addresses

4 Kwords

3F7FFF

00FFFF 32 Kwords

3F0000

008000

Total of 127

32 Kword blocks

Total of 8

4 Kword blocks

007FFF

007000

AI05520b

User programmable OTP

Unique device number

Protection register lock 1 0

8Ch

85h

84h

81h

80h

PROTECTION REGISTER

Signal descriptions M28W640HCT, M28W640HCB

12/72

2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1 Address inputs (A0-A21)

The Address inputs select the cells in the memory array to access during bus read

operations. During bus write operations they control the commands sent to the command

interface of the internal state machine.

2.2 Data input/output (DQ0-DQ15)

The Data I/O outputs the data stored at the selected address during a bus read operation or

inputs a command or the data to be programmed during a write bus operation.

2.3 Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active

mode. When Chip Enable is at VIH the memory is deselected, the outputs are high

impedance and the power consumption is reduced to the standby level.

2.4 Output Enable (G)

The Output Enable controls data outputs during the bus read operation of the memory.

2.5 Write Enable (W)

The Write Enable controls the bus write operation of the memory’s command interface. The

data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable,

W, whichever occurs first.

2.6 Wr ite Pr otect (WP)

Write Protect is an input that gives an additional hardware protection for each block. When

Write Protect is at VIL, the lock-down is enabled and the protection status of the block

cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the block

can be locked or unlocked (refer to Table 7: Read Protection Register and Lock Register).

M28W640HCT, M28W640HCB Signal descriptions

13/72

2.7 Reset (RP)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the

memory is in reset mode: the outputs are high impedance and the current consumption is

minimized. After Reset all blocks are in the locked state. When Reset is at VIH, the device is

in normal operation. Exiting reset mode the device enters read array mode, but a negative

transition of Chip Enable or a change of the address is required to ensure valid data outputs.

2.8 VDD supply voltage

VDD provides the power supply to the internal core and the I/O pins of the memory device. It

is the main power supply for all operations (read, program and erase).

2.9 VPP program supply voltage

VPP is both a control input and a power supply pin. The two functions are selected by the

voltage range applied to the pin. The supply voltage, VDD, and the program supply voltage,

VPP

, can be applied in any order.

If VPP is kept in a low voltage range (0 V to 3.6 V) VPP is seen as a control input. In this case

a voltage lower than VPPLK gives an absolute protection against program or erase, while

VPP > VPP1 enables these functions (see Table 15: DC characteristics, for the relevant

values). VPP is only sampled at the beginning of a program or erase; a change in its value

after the operation has started does not have any effect on program or erase, however for

Double or Quadruple Word Program the results are uncertain.

If VPP is in the range 11.4 V to 12.6 V it acts as a power supply pin. In this condition VPP

must be stable until the Program/Erase algorithm is completed (see Table 17 and Ta bl e 18 ).

2.10 VSS ground

VSS is the reference for all voltage measurements.

Note: Each device in a system should have VDD and VPP decoupled with a 0.1 μF capacitor close

to the pin. See Figure 7: AC measurement load circuit. The PCB track widths should be

sufficient to carry the required VPP program and erase currents.

Bus o p eratio n s M2 8W64 0HCT, M 2 8W64 0HCB

14/72

3 Bus operations

There are six standard bus operations that control the device. These are Bus Read, Bus

Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2: Bus operations,

for a summary.

Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

3.1 Read

Read bus operations are used to output the contents of the memory array, the Electronic

Signature, the Status Register and the common Flash interface. Both Chip Enable and

Output Enable must be at VIL in order to perform a read operation. The Chip Enable input

should be used to enable the device. Output Enable should be used to gate data onto the

output. The data read depends on the previous command written to the memory (see

Section 4: Command interface). See Figure 8: Read AC waveforms, and Table 16: Read AC

characteristics, for details of when the output becomes valid.

Read operations of the memory array can be performed in asynchronous page mode, which

provides a fast access time. Data is internally read and stored in a page buffer. The page

has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the

electronic signature, the Status Register, the command Flash interface, the Block Protection

status, the Configuration Register status and the security code are performed as

asynchronous read cycles (Random Read). Both Chip Enable, E, and Output Enable, G,

must be at VIL in order to read the output of the memory (see Figure 9: Page Read AC

waveforms).

Read mode is the default state of the device when exiting reset or after power-up.

3.2 Write

Bus write operations write commands to the memory or latch input data to be programmed.

A write operation is initiated when Chip Enable and Write Enable are at VIL with Output

Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first.

See Figure 9 and Figure 11, Write AC waveforms, and Table 17 and Table 18, Write AC

characteristics, for details of the timing requirements.

3.3 Output Disable

The data outputs are high impedance when the Output Enable is at VIH.

3.4 Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current

consumption. The memory is in standby when Chip Enable is at VIH and the device is in

read mode. The power consumption is reduced to the standby level and the outputs are set

M28W640HCT, M28W640HCB Bus operations

15/72

to high impedance, independently from the Output Enable or Write Enable inputs. If Chip

Enable switches to VIH during a program or erase operation, the device enters Standby

mode when finished.

3.5 Automatic Standby

Automatic standby provides a low power consumption state during Read mode. Following a

read operation, the device enters automatic standby after 150 ns of bus inactivity even if

Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data inputs/outputs

will still output data if a bus read operation is in progress.

3.6 Reset

During Reset mode when Output Enable is Low, VIL, the memory is deselected and the

outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power

consumption is reduced to the standby level, independently from the Chip Enable, Output

Enable or Write Enable inputs. If Reset is pulled to VSS during a program or erase, this

operation is aborted and the memory content is no longer valid.

Table 2. Bus operations(1)

1. X = VIL or VIH, VPPH = 12 V ± 5%.

Operation E G W RP WP VPP DQ0-DQ15

Bus Read VIL VIL VIH VIH X Don't care Data output

Bus Write VIL VIH VIL VIH XV

DD or VPPH Data input

Output Disable VIL VIH VIH VIH X Don't care Hi-Z

Standby VIH XXV

IH X Don't care Hi-Z

Reset XXXV

IL X Don't care Hi-Z

Command interface M28W640HCT, M28W640HCB

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4 Command interface

All bus write operations to the memory are interpreted by the command interface.

Commands consist of one or more sequential bus write operations. An internal

Program/Erase controller handles all timings and verifies the correct execution of the

Program and Erase commands. The Program/Erase controller provides a Status Register

whose output may be read at any time to monitor the progress of the operation, or the

Program/Erase states. See Table 3: Command codes, for a summary of the commands and

see Appendix D, Table 31: Write state machine current/next, for a summary of the command

interface.

The command interface is reset to Read mode when power is first applied, when exiting

from reset or whenever VDD is lower than VLKO. Command sequences must be followed

exactly. Any invalid combination of commands will reset the device to Read mode. Refer to

Table 4: Commands, in conjunction with the text descriptions below.

4.1 Re ad Memory Array command

The Read command returns the memory to its Read mode. One Bus Write cycle is required

to issue the Read Memory Array command and return the memory to Read mode.

Subsequent read operations will read the addressed location and output the data. When a

device Reset occurs, the memory defaults to Read mode.

4.2 Read Status Register command

The Status Register indicates when a program or erase operation is complete and the

success or failure of the operation itself. Issue a Read Status Register command to read the

Status Register’s contents. Subsequent bus read operations read the Status Register at any

address, until another command is issued. See Table 11: Status Register bits, for details on

the definitions of the bits.

The Read Status Register command may be issued at any time, even during a

program/erase operation. Any read attempt during a program/erase operation will

automatically output the content of the Status Register.

4.3 Read Electro nic Signature command

The Read Electronic Signature command reads the manufacturer and device codes and the

Block Locking Status, or the Protection Register.

The Read Electronic Signature command consists of one write cycle, a subsequent read will

output the manufacturer code, the device code, the Block Lock and Lock-Down Status, or

the Protection and Lock Register. See Tables 5, 6 and 7 for the valid address.

M28W640HCT, M28W640HCB Command interface

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4.4 Read CFI Query command

The Read Query command is used to read data from the common Flash interface (CFI)

memory area, allowing programming equipment or applications to automatically match their

interface to the characteristics of the device. One Bus Write cycle is required to issue the

Read Query command. Once the command is issued subsequent bus read operations read

from the common Flash interface memory area. See Appendix B: Common Flash interface

(CFI), tables 25, 26, 27, 28, 29 and 30 for details on the information contained in the

common Flash interface memory area.

4.5 Block Erase command

The Block Erase command can be used to erase a block. It sets all the bits within the

selected block to ’1’. All previous data in the block is lost. If the block is protected then the

erase operation will abort, the data in the block will not be changed and the Status Register

will output the error.

Two Bus Write cycles are required to issue the command:

The first bus cycle sets up the Erase command

The second latches the block address in the internal state machine and starts the

Program/Erase controller.

If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are

set and the command aborts.

Table 3. Command codes

Hex code Comman d

01h Block Lock confirm

10h Program

20h Erase

2Fh Block Lock-down confirm

30h Double Word Program

40h Program

50h Clear Status Register

56h Quadruple Word Program

60h Block Lock, Block Unlock, Block Lock-down

70h Read Status Register

90h Read Electronic Signature

98h Read CFI Query

B0h Program/Erase Suspend

C0h Protection Register Program

D0h Program/Erase Resume, Block Unlock confirm

FFh Read Memory Array

Command interface M28W640HCT, M28W640HCB

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Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the erase

operation is aborted, the block must be erased again.

During erase operations the memory will accept the Read Status Register command and

the Program/Erase Suspend command, all other commands will be ignored. Typical Erase

times are given in Table 8: Program, Erase times and Program/Erase endurance cycles.

See Appendix C, Figure 19: Erase flowchart and pseudocode, for a suggested flowchart for

using the Erase command.

4.6 Program command

The memory array can be programmed word-by-word. Two bus write cycles are required to

issue the Program command:

The first bus cycle sets up the Program command.

The second latches the address and the data to be written and starts the

Program/Erase controller.

During program operations the memory will accept the Read Status Register command and

the Program/Erase Suspend command. Typical Program times are given in Table 8:

Program, Erase times and Program/Erase endurance cycles.

Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the

program operation is aborted, the block containing the memory location must be erased and

reprogrammed.

See Appendix C, Figure 15: Program flowchart and pseudocode, for the flowchart for using

the Program command.

4.7 Double Word Program command

This feature is offered to improve the programming throughput, writing a page of two

adjacent words in parallel.The two words must differ only for the address A0. Programming

should not be attempted when VPP is not at VPPH.

Three bus write cycles are necessary to issue the Double Word Program command:

The first bus cycle sets up the Double Word Program command

The second bus cycle latches the address and the data of the first word to be written

The third bus cycle latches the address and the data of the second word to be written

and starts the Program/Erase controller.

Read operations output the Status Register content after the programming has started.

Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the

program operation is aborted, the block containing the memory location must be erased and

reprogrammed.

See Appendix C, Figure 16: Double Word Program flowchart and pseudocode for the

flowchart for using the Double Word Program command.

M28W640HCT, M28W640HCB Command interface

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4.8 Quadruple Word Program command

This feature is offered to improve the programming throughput, writing a page of four

adjacent words in parallel.The four words must differ only for the addresses A0 and A1.

Programming should not be attempted when VPP is not at VPPH.

Five bus write cycles are necessary to issue the Quadruple Word Program command:

The first bus cycle sets up the Quadruple Word Program command.

The second bus cycle latches the address and the data of the first word to be written

The third bus cycle latches the address and the data of the second word to be written

The fourth bus cycle latches the address and the data of the third word to be written

The fifth bus cycle latches the address and the data of the fourth word to be written and

starts the Program/Erase controller.

Read operations output the Status Register content after the programming has started.

Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the

program operation is aborted, the block containing the memory location must be erased and

reprogrammed.

See Appendix C, Figure 17: Quadruple Word Program flowchart and pseudocode, for the

flowchart for using the Quadruple Word Program command.

4.9 Clear Status Register command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status

The bits in the Status Register do not automatically return to ‘0’ when a new Program or

Erase command is issued. The error bits in the Status Register should be cleared before

attempting a new Program or Erase command.

4.10 Program/Erase S uspe nd command

The Program/Erase Suspend command is used to pause a program or erase operation.

One bus write cycle is required to issue the Program/Erase command and pause the

Program/Erase controller.

During Program/Erase Suspend the command interface will accept the Program/Erase

Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI

Query commands. Additionally, if the suspend operation was Erase then the Program,

Double Word Program, Quadruple Word Program, Block Lock, Block Lock-down or

Protection Program commands will also be accepted. The block being erased may be

protected by issuing the Block Protect, Block Lock or Protection Program commands. When

the Program/Erase Resume command is issued the operation will complete. Only the blocks

not being erased may be read or programmed correctly.

During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by

taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL.

See Appendix C, Figure 18: Program Suspend & Resume flowchart and pseudocode, and

Figure 20: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using

the Program/Erase Suspend command.

Command interface M28W640HCT, M28W640HCB

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4.11 Program/Erase Resume command

The Program/Erase Resume command can be used to restart the Program/Erase controller

after a program/erase suspend operation has paused it. One Bus Write cycle is required to

issue the command. Once the command is issued subsequent bus read operations read the

Status Register.

See Appendix C, Figure 18: Program Suspend & Resume flowchart and pseudocode, and

Figure 20: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using

the Program/Erase Resume command.

4.12 Protection Register Program command

The Protection Register Program command is used to program the 128 bit user one-time-

programmable (OTP) segment of the Protection Register. The segment is programmed 16

bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program

the bits to ‘0’.

Two write cycles are required to issue the Protection Register Program command:

The first bus cycle sets up the Protection Register Program command

The second latches the address and the data to be written to the Protection Register

and starts the Program/Erase controller.

Read operations output the Status Register content after the programming has started.

The segment can be protected by programming bit 1 of the Protection Lock Register (see

Figure 5: Protection register memory map). Attempting to program a previously protected

Protection Register will result in a Status Register error. The protection of the Protection

The Protection Register Program cannot be suspended.

4.13 Block Lock command

The Block Lock command is used to lock a block and prevent program or erase operations

from changing the data in it. All blocks are locked at power-up or reset.

Two Bus Write cycles are required to issue the Block Lock command:

The first bus cycle sets up the Block Lock command

The second Bus Write cycle latches the block address.

The lock status can be monitored for each block using the Read Electronic Signature

command. Table 10 shows the protection status after issuing a Block Lock command.

The Block Lock bits are volatile, once set they remain set until a hardware reset or power-

down/power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block

Locking, for a detailed explanation.

M28W640HCT, M28W640HCB Command interface

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4.14 Block Unlock command

The Block Unlock command is used to unlock a block, allowing the block to be programmed

or erased. Two Bus Write cycles are required to issue the Block Unlock command:

The first bus cycle sets up the Block Unlock command

The second Bus Write cycle latches the block address.

The lock status can be monitored for each block using the Read Electronic Signature

command. Table 10 shows the protection status after issuing a Block Unlock command.

Refer to the Section 5: Block locking, for a detailed explanation.

4.15 Block Lock-down command

A locked block cannot be programmed or erased, or have its protection status changed

when WP is Low, VIL. When WP is High, VIH, the Lock-down function is disabled and the

locked blocks can be individually unlocked by the Block Unlock command.

Two Bus Write cycles are required to issue the Block Lock-down command:

The first bus cycle sets up the Block Lock command

The second Bus Write cycle latches the block address.

The lock status can be monitored for each block using the Read Electronic Signature

command. Locked-down blocks revert to the locked (and not locked-down) state when the

device is reset on power-down. Tab le 10 shows the protection status after issuing a Block

Lock-down command. Refer to the Section 5: Block locking for a detailed explanation.

Command interface M28W640HCT, M28W640HCB

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Table 4. Commands(1)

Commands

Cycles

Bus write operations

1st cycle 2n d c yc l e 3rd cycle 4th c ycle 5th cy cle

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

Read Memory

Array 1+ Write X FFh Read RA RD

Read Status

Read

Electronic

Signature

1+ Write X 90h Read SA(2) IDh

Read CFI

Query 1+ Write X 98h Read QA QD

Erase 2 Write X 20h Write BA D0h

Program 2 Write X 40h or

10h Write PA PD

Double Word

Program(3) 3 Write X 30h Write PA1 PD1 Write PA2 PD2

Quadruple

Word

Program(4)

5 Write X 56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

Clear Status

Program/Erase

Suspend 1Write X B0h

Program/Erase

Resume 1Write X D0h

Block Lock 2 Write X 60h Write BA 01h

Block Unlock 2 Write X 60h Write BA D0h

Block Lock-

down 2Write X 60h WriteBA 2Fh

Protection

Program

2 Write X C0h Write PRA PRD

1. X = Don't care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (manufacturer and device

code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data,

PRA=Protection Register Address, PRD=Protection Register Data.

2. The signature addresses are listed in Tables 5, 6 and 7.

3. Program addresses 1 and 2 must be consecutive addresses differing only for A0.

4. Program addresses 1,2,3 and 4 must be consecutive addresses differing only for A0 and A1.

M28W640HCT, M28W640HCB Command interface

23/72

Table 5. Read el e ctron i c si g n at ure(1)

1. RP = VIH.

Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-DQ15

Manufacturer

code VIL VIL VIH VIL VIL 0 Don't care 20h 00h

Device code

M28W640HCT VIL VIL VIH VIH VIL 0 Don't care 48h 88h

M28W640HCB VIL VIL VIH VIH VIL 0 Don't care 49h 88h

Table 6. Read block lock signature

Block status E G W A0 A1 A2-A7 A8-A11 A12-A21 DQ0 DQ1 DQ2-DQ15

Locked block VIL VIL VIH VIL VIH 0 Don't care Block address 1 0 00h

Unlocked block VIL VIL VIH VIL VIH 0 Don't care Block address 0 0 00h

Locked-down

block VIL VIL VIH VIL VIH 0 Don't care Block address X(1)

1. A locked-down block can be locked ‘DQ0 = 1’ or unlocked ‘DQ0 = 0’; see Section 5: Block locking.

100h

Table 7. Rea d Pro tection Regi ster and Lock Regi ster

Word E G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ3-

DQ7 DQ8-

DQ15

Lock VIL VIL VIH 80h Don't care 0 OTP Prot.

data 000h00h

Unique ID 0 VIL VIL VIH 81h Don't care ID data ID data ID data ID data ID data

Unique ID 1 VIL VIL VIH 82h Don't care ID data ID data ID data ID data ID data

Unique ID 2 VIL VIL VIH 83h Don't care ID data ID data ID data ID data ID data

Unique ID 3 VIL VIL VIH 84h Don't care ID data ID data ID data ID data ID data

OTP 0 VIL VIL VIH 85h Don't care OTP data OTP data OTP data OTP data OTP data

OTP 1 VIL VIL VIH 86h Don't care OTP data OTP data OTP data OTP data OTP data

OTP 2 VIL VIL VIH 87h Don't care OTP data OTP data OTP data OTP data OTP data

OTP 3 VIL VIL VIH 88h Don't care OTP data OTP data OTP data OTP data OTP data

OTP 4 VIL VIL VIH 89h Don't care OTP data OTP data OTP data OTP data OTP data

OTP 5 VIL VIL VIH 8Ah Don't care OTP data OTP data OTP data OTP data OTP data

OTP 6 VIL VIL VIH 8Bh Don't care OTP data OTP data OTP data OTP data OTP data

OTP 7 VIL VIL VIH 8Ch Don't care OTP data OTP data OTP data OTP data OTP data

Command interface M28W640HCT, M28W640HCB

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Table 8. Program, Erase times and Program/Erase endurance cycles

Parameter Test conditions M28W640HCT, M28W640HCB Unit

Min Typ Max

Word Program VPP =V

DD 10 200 μs

Double Word Program VPP = 12 V ± 5% 10 200 μs

Quadruple Word Program VPP = 12 V ± 5% 10 200 μs

Main Block Program

VPP = 12 V ± 5% 0.16/0.08(1) 5s

VPP = VDD 0.32 5 s

Parameter Block Program

VPP = 12 V ± 5% 0.02/0.01(1) 4s

VPP =V

DD 0.04 4 s

Main Block Erase

VPP =12V±5% 1 10 s

VPP =V

DD 110s

Parameter Block Erase

VPP =12V±5% 0.4 10 s

VPP =V

DD 0.4 10 s

Program/Erase cycles (per block) 100,000 cycles

1. Typical time to program a main or parameter block using the Double Word Program and the Quadruple Word Program

commands respectively.

M28W640HCT, M28W640HCB Block locking

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5 Block locking

The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme

that allows any block to be locked or unlocked with no latency. This locking scheme has

three levels of protection:

Lock/unlock - this first level allows software-only control of block locking

Lock-down - this second level requires hardware interaction before locking can be

changed

VPP ≤ VPPLK - the third level offers a complete hardware protection against program

and erase on all blocks.

The protection status of each block can be set to ‘Locked’, ‘Unlocked’, and ‘Lock-down’.

Table 10, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C,

Figure 21, shows a flowchart for the locking operations.

5.1 Reading a block’s lock stat us

The lock status of every block can be read in the Read Electronic Signature mode of the

device. To enter this mode write 90h to the device. Subsequent reads at the address

specified in Table 6, will output the protection status of that block. The lock status is

represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the

Lock command and cleared by the Unlock command. It is also automatically set when

entering Lock-down. DQ1 indicates the Lock-down status and is set by the Lock-down

command. It cannot be cleared by software, only by a hardware reset or power-down.

The following sections explain the operation of the locking system.

5.2 Locked state

The default status of all blocks on power-up or after a hardware reset is ‘Locked’ (states

(0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any

program or erase operations attempted on a locked block will return an error in the Status

the appropriate software commands. An unlocked block can be locked by issuing the Lock

command.

5.3 Unlocked state

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked

blocks return to the locked state after a hardware reset or when the device is powered-

down. The status of an unlocked block can be changed to ‘Locked’ or ‘Locked-down’ using

the appropriate software commands. A locked block can be unlocked by issuing the Unlock

command.

Block locking M28W640HCT, M28W640HCB

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5.4 Lock-down state

Blocks that are Locked-down (state (0,1,x)) are protected from program and erase

operations (as for locked blocks) but their protection status cannot be changed using

software commands alone. A Locked or Unlocked block can be Locked-down by issuing the

Lock-down command. Locked-down blocks revert to the locked state when the device is

reset or powered-down.

The Lock-down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in

the Lock-down state (0,1,x) are protected from program, erase and protection status

changes. When WP=1 (VIH) the Lock-down function is disabled (1,1,1) and Locked-down

blocks can be individually unlocked to the (1,1,0) state by issuing the software command,

where they can be erased and programmed. These blocks can then be relocked (1,1,1) and

unlocked (1,1,0) as desired while WP remains High. When WP is Low, blocks that were

previously Locked-down return to the Lock-down state (0,1,x) regardless of any changes

made while WP was High. Device reset or power-down resets all blocks, including those in

Lock-down or in a Locked state.

5.5 Locking operations during Erase Suspend

Changes to block lock status can be performed during an Erase Suspend by using the

standard locking command sequences to unlock, lock or lock-down a block. This is useful in

the case when another block needs to be updated while an erase operation is in progress.

To change block locking during an erase operation, first write the Erase Suspend command,

then check the Status Register until it indicates that the erase operation has been

suspended. Next write the desired Lock command sequence to a block and the Lock Status

will be changed. After completing any desired lock, read, or program operations, resume the

erase operation with the Erase Resume command.

If a block is Locked or Locked-down during an Erase Suspend of the same block, the

locking status bits will be changed immediately, but when the erase is resumed, the erase

operation will complete.

Locking operations cannot be performed during a Program Suspend. Refer to Appendix D,

command interface and Program/Erase controller state, for detailed information on which

commands are valid during Erase Suspend.

Table 9. Bloc k Lock status

Item Address Data

Block Lock configuration

xx002

LOCK

Block is Unlocked DQ0=0

Block is Locked DQ0=1

Block is Locked-down DQ1=1

M28W640HCT, M28W640HCB Block locking

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Tab le 10. Protect ion status

Current Protection status(1)

(WP, DQ1, DQ0)

1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for

a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

Next Protection status(1)

(WP, DQ1, DQ0)

Cur rent st at e Program/Erase

allowed

After Block

Lock

command

After Block

Unlock

command

After Block

Lock-down

command

After WP

transition

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1(2)

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1

1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1

0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1(2) no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)

3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Stat u s Regi ster M28W 640H CT , M28W640HCB

28/72

6 Status Register

The Status Register provides information on the current or previous program or erase

operation. The various bits convey information and errors on the operation. To read the

Status Register the Read Status Register command can be issued, refer to Section 4.2:

Read Status Register command. To output the contents, the Status Register is latched on

the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip

Enable or Output Enable returns to VIH. Either Chip Enable or Output Enable must be

toggled to update the latched data.

Bus read operations from any address always read the Status Register during program and

erase operations.

The bits in the Status Register are summarized in Table 11: Status Register bits. Refer to

Table 11 in conjunction with the following text descriptions.

6.1 Program/Erase controller st atus (bit 7)

The Program/Erase controller status bit indicates whether the Program/Erase controller is

active or inactive. When the Program/Erase controller status bit is Low (set to ‘0’), the

Program/Erase controller is active; when the bit is High (set to ‘1’), the Program/Erase

controller is inactive, and the device is ready to process a new command.

The Program/Erase controller Status is Low immediately after a Program/Erase Suspend

command is issued until the Program/Erase controller pauses. After the Program/Erase

controller pauses the bit is High.

During program, erase, operations the Program/Erase controller status bit can be polled to

find the end of the operation. Other bits in the Status Register should not be tested until the

Program/Erase controller completes the operation and the bit is High.

After the Program/Erase controller completes its operation the Erase Status, Program

Status, VPP Status and Block Lock Status bits should be tested for errors.

6.2 Erase Suspend status (bit 6)

The Erase Suspend status bit indicates that an erase operation has been suspended or is

going to be suspended. When the Erase Suspend status bit is High (set to ‘1’), a

Program/Erase Suspend command has been issued and the memory is waiting for a

Program/Erase Resume command.

The Erase Suspend Status should only be considered valid when the Program/Erase

controller status bit is High (Program/Erase controller inactive). Bit 7 is set within 30 μs of

the Program/Erase Suspend command being issued therefore the memory may still

complete the operation rather than entering the Suspend mode.

When a Program/Erase Resume command is issued the Erase Suspend Status bit returns

Low.

M28 W640H CT, M28W640 HCB Stat u s Register

29/72

6.3 Erase status (bit 5)

The Erase status bit can be used to identify if the memory has failed to verify that the block

has erased correctly. When the Erase status bit is High (set to ‘1’), the Program/Erase

controller has applied the maximum number of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Status bit should be read once the

Program/Erase controller status bit is High (Program/Erase controller inactive).

Once set High, the Erase Status bit can only be reset Low by a Clear Status Register

command or a hardware reset. If set High it should be reset before a new Program or Erase

command is issued, otherwise the new command will appear to fail.

6.4 Program status (bit 4)

The Program Status bit is used to identify a Program failure. When the Program Status bit is

High (set to ‘1’), the Program/Erase controller has applied the maximum number of pulses to

the byte and still failed to verify that it has programmed correctly. The Program Status bit

should be read once the Program/Erase controller status bit is High (Program/Erase

controller inactive).

Once set High, the Program status bit can only be reset Low by a Clear Status Register

command or a hardware reset. If set High it should be reset before a new command is

issued, otherwise the new command will appear to fail.

6.5 VPP status (bit 3)

The VPP status bit can be used to identify an invalid voltage on the VPP pin during program

and erase operations. The VPP pin is only sampled at the beginning of a program or erase

operation. Indeterminate results can occur if VPP becomes invalid during an operation.

When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid

voltage; when the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is below

the VPP Lockout voltage, VPPLK, the memory is protected and program and erase

operations cannot be performed.

Once set High, the VPP status bit can only be reset Low by a Clear Status Register

command or a hardware reset. If set High it should be reset before a new Program or Erase

command is issued, otherwise the new command will appear to fail.

6.6 Program Suspend status (bit 2)

The Program Suspend status bit indicates that a program operation has been suspended.

When the Program Suspend status bit is High (set to ‘1’), a Program/Erase Suspend

command has been issued and the memory is waiting for a Program/Erase Resume

command. The Program Suspend status should only be considered valid when the

Program/Erase controller status bit is High (Program/Erase controller inactive). Bit 2 is set

within 5 μs of the Program/Erase Suspend command being issued therefore the memory

may still complete the operation rather than entering the Suspend mode.

When a Program/Erase Resume command is issued the Program Suspend Status bit

returns Low.

Stat u s Regi ster M28W 640H CT , M28 W640H CB

30/72

6.7 Block Protection status (bit 1)

The Block Protection status bit can be used to identify if a program or erase operation has

tried to modify the contents of a locked block.

When the Block Protection status bit is High (set to ‘1’), a program or erase operation has

been attempted on a locked block.

Once set High, the Block Protection status bit can only be reset Low by a Clear Status

command is issued, otherwise the new command will appear to fail.

6.8 Reserved (bit 0)

Bit 0 of the Status Register is reserved. Its value must be masked.

Note: Refer to Appendix C: Flowcharts and pseudocodes, for using the Status Register.

Table 11. Status Re g i ster b i ts(1)

1. Logic level '1' is High, '0' is Low.

Bit Name Logic level Definition

7 P/E.controller status

'1' Ready

'0' Busy

6 Erase Suspend status

'1' Suspended

'0' In progress or completed

5 Erase status

'1' Erase error

'0' Erase success

4 Program status

'1' Program error

'0' Program success

PP status

'1' VPP invalid, abort

'0' VPP OK

2 Program Suspend status

'1' Suspended

'0' In progress or completed

1 Block Protection status

'1' Program/Erase on protected Block,

abort

'0' No operation to protected blocks

0 Reserved

M28W640HCT, M28W640HCB Maximum ratings

31/72

7 Maximum ratings

Stressing the device above the rating listed in Table 12: Absolute maximum ratings may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. Refer also to the Numonyx SURE Program

and other relevant quality documents.

Table 12. Abs ol ute maximu m ratings

Symbol Parameter Value Unit

Min Max

TAAmbient operating temperature – 40 85 °C

TBIAS Temperature under bias – 40 125 °C

TSTG Storage temperature – 55 155 °C

VIO Input or output voltage – 0.6 VDD+0.6 V

VDD Supply voltage – 0.6 4.1 V

VPP Program voltage – 0.6 13 V

DC and AC parameters M 28W 640H CT, M28W640HCB

32/72

8 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics tables that

follow, are derived from tests performed under the measurement conditions summarized in

Table 13: Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the measurement conditions when relying on the

quoted parameters.

Fig u re 6. AC measurem ent I/O waveform

Fig u re 7. AC measurem ent load ci rcuit

Table 13. Operating and AC measurem ent conditions

Parameter

M28W640HCT, M28W640HCB

70 ns Units

Min Max

VDD supply voltage 2.7 3.6 V

Ambient operating temperature –40 85 °C

Load capacitance (CL)50pF

Input rise and fall times 5 ns

Input pulse voltages 0 to VDD V

Input and output timing reference voltages VDD/2 V

AI00610b

VDD

0 V

VDD/2

AI00609d

VDD

CL includes JIG capacitance

25 kΩ

DEVICE

UNDER

TEST

0.1 µF

VDD

25 kΩ

M28W640HCT, M28W640HCB DC and AC parameters

33/72

Tab le 14. Capacitan ce(1)

1. Sampled only, not 100% tested.

Symbol Parameter Test condition Min Max Unit

CIN Input capacitance VIN = 0 V 6 pF

COUT Output capacitance VOUT = 0 V 12 pF

DC and AC parameters M 28W 640H CT, M28W640HCB

34/72

Table 15. DC cha r acter istics

Symbol Parameter Test condition Min Typ Max Unit

ILI Input Leakage current 0 V ≤VIN ≤VDD ±1 μA

ILO Output Leakage current 0 V ≤VOUT ≤VDD ±10 μA

IDD Supply current (Read) E=V

SS, G =V

IH,

f=5MHz 918mA

IDD1

Supply current (Standby or Automatic

Standby)

E=V

DD ±0.2V,

RP =V

DD ±0.2V 15 50 μA

IDD2 Supply current (Reset) RP =V

SS ±0.2V 15 50 μA

IDD3 Supply current (Program)

Program in progress

VPP =12V±5% 510mA

Program in progress

VPP =V

10 20 mA

IDD4 Supply current (Erase)

Erase in progress

VPP =12V±5% 10 20 mA

Erase in progress

VPP =V

10 20 mA

IDD5 Supply current (Program/Erase Suspend) E=V

DD ±0.2V,

Erase suspended 15 50 μA

IPP Program current (Read or Standby) VPP >V

DD 400 μA

IPP1 Program current (Read or Standby) VPP ≤VDD 15μA

IPP2 Program current (Reset) RP =V

SS ±0.2V 1 5 μA

IPP3 Program current (Program)

Program in progress

VPP =12V±5% 110mA

Program in progress

VPP =V

15μA

IPP4 Program Current (Erase)

Erase in progress

VPP = 12V ± 5% 310mA

Erase in progress

VPP = VDD

15μA

VIL Input Low voltage –0.5 0.4 V

VIH Input High voltage 0.7VDD VDD +0.4 V

VOL Output Low voltage IOL = 100 μA,

VDD = VDD min 0.1 V

VOH Output High voltage IOH = –100 μA,

VDD = VDD min VDD –0.1 V

VPP1

Program voltage (program or erase

operations) 2.7 3.6 V

VPPH

Program voltage (program or erase

operations) 11.4 12.6 V

VPPLK

Program voltage (program and erase

lock-out) 1V

VLKO

VDD supply voltage (Program and Erase

lock-out) 2V

M28W640HCT, M28W640HCB DC and AC parameters

35/72

Fig ur e 8. Read A C wavef or ms

Tab le 16. Read AC cha racte ristics

Symbol Alt Parameter

M28W640HCT,

M28W640HCB

70 ns Unit

tAVAV tRC Address valid to Next Address Valid Min 70 ns

tAVQV tACC Address valid to Random Output Valid Max 70 ns

tAXQX(1)

1. Sampled only, not 100% tested.

tOH Address Transition to Output Transition Min 0 ns

tEHQX(1) tOH Chip Enable High to Output Transition Min 0 ns

tEHQZ(1) tHZ Chip Enable High to Output Hi-Z Max 20 ns

tELQV(2)

2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.

tCE Chip Enable Low to Output Valid Max 70 ns

tELQX(1) tLZ Chip Enable Low to Output Transition Min 0 ns

tGHQX(1) tOH Output Enable High to Output Transition Min 0 ns

tGHQZ(1) tDF Output Enable High to Output Hi-Z Max 20 ns

tGLQV(2) tOE Output Enable Low to Output Valid Max 20 ns

tGLQX(1) tOLZ Output Enable Low to Output Transition Min 0 ns

tAVQV1 tPAGE Page address Valid to Page Output Valid Max 25 ns

tAXQX1 tOH Address Transition to Page Output Transition Min 0 ns

Q0-

Q15

AI04387

VALID

A0-A21

tAXQX

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

ADDR. VALID

CHIP ENABLE OUTPUTS

ENABLED DATA VALID STANDBY

tGHQX

tGHQZ

tEHQX

tEHQZ

DC and AC parameters M 28W 640H CT, M28W640HCB

36/72

Figure 9. Page Read AC waveforms

AI06191b

DQ0-DQ15

A2-A21 VALID

A0-A1 VALID

VALID

tEHQX

tGHQZ

tGHQX

tEHQZ

tELQV

tGLQV

tAVQV

VALIDVALID

VALID

VALID VALID VALID

tAVQV1

tAXQX1

M28W640HCT, M28W640HCB DC and AC parameters

37/72

Figu re 10. Write AC wavef o rm s, Write En ab le cont ro lled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A21

tAVAV

tQVVPL

tAVWH tWHAX

PROGRAM OR ERASE

tELWL tWHEH

tWHDX

tDVWH

tWLWH

tWHWL

tVPHWH

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tELQV

AI04388

tWPHWH

tWHGL

tQVWPL

tWHEL

DC and AC parameters M 28W 640H CT, M28W640HCB

38/72

Tab le 17. Write AC cha r acter istics, Write Enable co n trolled

Symbol Alt Parameter

M28W640HCT,

M28W640HCB

70 ns Unit

tAVAV tWC Write Cycle time Min 70 ns

tAVWH tAS Address Valid to Write Enable High Min 45 ns

tDVWH tDS Data Valid to Write Enable High Min 45 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns

tELQV Chip Enable Low to Output Valid Min 70 ns

tQVVPL(1)(2)

1. Sampled only, not 100% tested.

2. Applicable if VPP is seen as a logic input (VPP < 3.6 V).

Output Valid to VPP Low Min 0 ns

tQVWPL Output Valid to Write Protect Low Min 0 ns

tVPHWH(1) tVPS VPP High to Write Enable High Min 200 ns

tWHAX tAH Write Enable High to Address Transition Min 0 ns

tWHDX tDH Write Enable High to Data Transition Min 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 ns

tWHEL Write Enable High to Chip Enable Low Min 25 ns

tWHGL Write Enable High to Output Enable Low Min 20 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 25 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 ns

tWPHWH Write Protect High to Write Enable High Min 45 ns

M28W640HCT, M28W640HCB DC and AC parameters

39/72

Figure 11. Writ e AC waveforms, Chip Enable controlled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A21

tAVAV

tQVVPL

tAVEH tEHAX

PROGRAM OR ERASE

tWLEL tEHWH

tEHDX

tDVEH

tELEH

tEHEL

tVPHEH

POWER-UP AND

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tELQV

AI04389

tWPHEH

tEHGL

tQVWPL

DC and AC parameters M 28W 640H CT, M28W640HCB

40/72

Table 18. Write AC characteristics, Chip Enable controlled

Symbol Alt Parameter

M28W640HCT,

M28W640HCB

70 ns Unit

tAVAV tWC Write Cycle time Min 70 ns

tAVEH tAS Address Valid to Chip Enable High Min 45 ns

tDVEH tDS Data Valid to Chip Enable High Min 45 ns

tEHAX tAH Chip Enable High to Address Transition Min 0 ns

tEHDX tDH Chip Enable High to Data Transition Min 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 ns

tEHGL Chip Enable High to Output Enable Low Min 25 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 ns

tELQV Chip Enable Low to Output Valid Min 70 ns

tQVVPL (1)(2)

1. Sampled only, not 100% tested.

2. Applicable if VPP is seen as a logic input (VPP < 3.6 V).

Output Valid to VPP Low Min 0 ns

tQVWPL Data Valid to Write Protect Low Min 0 ns

tVPHEH (1) tVPS VPP High to Chip Enable High Min 200 ns

tWLEL tCS Write Enable Low to Chip Enable Low Min 0 ns

tWPHEH Write Protect High to Chip Enable High Min 45 ns

M28W640HCT, M28W640HCB DC and AC parameters

41/72

Figure 12. Power-up and Reset AC waveforms

Tab le 19. Power- u p and Reset AC chara cteristics

Symbol Parameter Test condition

M28W640HCT,

M28W640HCB

70 ns Unit

tPHWL

tPHEL

tPHGL

Reset High to Write Enable Low,

Chip Enable Low, Output Enable Low

During program and

erase Min 50 μs

others Min 30 ns

tPLPH(1)(2)

1. The device reset is possible but not guaranteed if tPLPH < 100 ns.

2. Sampled only, not 100% tested.

Reset Low to Reset High Min 100 ns

tVDHPH(3)

3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset.

Supply voltages High to Reset High Min 300 μs

AI03537c

tPHWL

tPHEL

tPHGL

W, E, G

tVDHPH

tPHWL

tPHEL

tPHGL

tPLPH

Power-up Reset

Package mechanical M28W640HCT, M28W640HCB

42/72

9 Package mechanical

In order to meet environmental requirements, Numonyx offers these devices in RoHS

compliant packages. RoHS compliant packages are lead-free. The category of second-level

interconnect is marked on the package and on the inner box label, in compliance with

JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label.

Fig ur e 13. TSOP 48 - 48 lead plastic th in smal l ou tline, 12 x 20 mm , package ou tl ine

1. Drawing is not to scale.

Table 20. TSOP48 - 48 lead plastic th in small outline, 12 x 20 mm, package

mechani cal data

Symbol millimeters inches

Typ Min Max Typ Min Max

A1.200.047

A1 0.10 0.05 0.15 0.004 0.002 0.006

A2 1.00 0.95 1.05 0.039 0.037 0.041

B 0.22 0.17 0.27 0.009 0.007 0.011

C 0.10 0.21 0.004 0.008

CP 0.10 0.004

D1 12.00 11.90 12.10 0.472 0.468 0.476

E 20.00 19.80 20.20 0.787 0.779 0.795

E1 18.40 18.30 18.50 0.724 0.720 0.728

e 0.50 – – 0.020 – –

L 0.60 0.50 0.70 0.024 0.020 0.028

L1 0.80 0.031

α3° 0° 5° 3° 0° 5°

TSOP-G

DIE

LA1 α

M28 W640H CT, M28W6 40HC B Package mechani cal

43/72

Figure 14. TFBGA48 6.39 x 10.5 m m - 8 x 6 ball array, 0.75 mm pitch, bottom view

package outline

1. Drawing is not to scale.

Tab le 21. TFB GA48 6.39 x 10.5 mm - 8 x 6 ball array, 0.75 mm pitch , packag e

mechani cal data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.26 0.010

A2 1.00 0.039

b 0.40 0.35 0.45 0.016 0.014 0.018

D 6.39 6.29 6.49 0.252 0.248 0.255

D1 5.250 – – 0.207 – –

ddd 0.10 0.004

E 10.50 10.40 10.60 0.413 0.409 0.417

E1 3.75 – – 0.148 – –

e 0.75 – – 0.029 – –

FD 0.57 – – 0.022 – –

FE 3.37 – – 0.133 – –

SD 0.37 – – 0.015 – –

SE 0.37 – – 0.015 – –

E1E

BGA-Z34

ddd

BALL "A1"

Ordering inform at ion M28W 64 0H CT, M28 W640H CB

44/72

10 Ordering information

Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of

available options (speed, package, etc.) or for further information on any aspect of this

device, please contact the Numonyx Sales Office nearest to you.

Table 22. Ordering informatio n sche me

Example: M28W640HCT 70 N 6 E

Device type

M28

O per a t in g vo l tag e

W = VDD = 2.7 V to 3.6 V

Device function

640HC = 64 Mbit (4 Mb x 16), boot block

Array matrix

T = top boot

B = bottom boot

Speed

70 = 70 ns

Package

N = TSOP48: 12 x 20 mm

ZB = TFBGA48: 6.39 x 10.5 mm, 0.75 mm pitch

Tem p e rat u re ran ge

6 = –40 to 85 °C

Option

E = RoHS compliant package, standard packing

F = RoHS compliant package, tape & reel packing

M28 W640H CT, M28W6 40HC B Block address tab les

45/72

Appendix A Block address tables

Table 23. Top b o ot block addresses, M2 8W640 HCT

# Size (Kword) Address range

0 4 3FF000-3FFFFF

1 4 3FE000-3FEFFF

2 4 3FD000-3FDFFF

3 4 3FC000-3FCFFF

4 4 3FB000-3FBFFF

5 4 3FA000-3FAFFF

6 4 3F9000-3F9FFF

7 4 3F8000-3F8FFF

8 32 3F0000-3F7FFF

9 32 3E8000-3EFFFF

10 32 3E0000-3E7FFF

11 32 3D8000-3DFFFF

12 32 3D0000-3D7FFF

13 32 3C8000-3CFFFF

14 32 3C0000-3C7FFF

15 32 3B8000-3BFFFF

16 32 3B0000-3B7FFF

17 32 3A8000-3AFFFF

18 32 3A0000-3A7FFF

19 32 398000-39FFFF

20 32 390000-397FFF

21 32 388000-38FFFF

22 32 380000-387FFF

23 32 378000-37FFFF

24 32 370000-377FFF

25 32 368000-36FFFF

26 32 360000-367FFF

27 32 358000-35FFFF

28 32 350000-357FFF

29 32 348000-34FFFF

30 32 340000-347FFF

31 32 338000-33FFFF

Block addr ess tab les M28W640HCT , M28W640HCB

46/72

32 32 330000-337FFF

33 32 328000-32FFFF

34 32 320000-327FFF

35 32 318000-31FFFF

36 32 310000-317FFF

37 32 308000-30FFFF

38 32 300000-307FFF

39 32 2F8000-2FFFFF

40 32 2F0000-2F7FFF

41 32 2E8000-2EFFFF

42 32 2E0000-2E7FFF

43 32 2D8000-2DFFFF

44 32 2D0000-2D7FFF

45 32 2C8000-2CFFFF

46 32 2C0000-2C7FFF

47 32 2B8000-2BFFFF

48 32 2B0000-2B7FFF

49 32 2A8000-2AFFFF

50 32 2A0000-2A7FFF

51 32 298000-29FFFF

52 32 290000-297FFF

53 32 288000-28FFFF

54 32 280000-287FFF

55 32 278000-27FFFF

56 32 270000-277FFF

57 32 268000-26FFFF

58 32 260000-267FFF

59 32 258000-25FFFF

60 32 250000-257FFF

61 32 248000-24FFFF

62 32 240000-247FFF

63 32 238000-23FFFF

64 32 230000-237FFF

65 32 228000-22FFFF

66 32 220000-227FFF

Table 23. Top b o ot block addresses, M2 8W640 HCT (conti n u ed)

# Size (Kword) Address range

M28 W640H CT, M28W6 40HC B Block address tab les

47/72

67 32 218000-21FFFF

68 32 210000-217FFF

69 32 208000-20FFFF

70 32 200000-207FFF

71 32 1F8000-1FFFFF

72 32 1F0000-1F7FFF

73 32 1E8000-1EFFFF

74 32 1E0000-1E7FFF

75 32 1D8000-1DFFFF

76 32 1D0000-1D7FFF

77 32 1C8000-1CFFFF

78 32 1C0000-1C7FFF

79 32 1B8000-1BFFFF

80 32 1B0000-1B7FFF

81 32 1A8000-1AFFFF

82 32 1A0000-1A7FFF

83 32 198000-19FFFF

84 32 190000-197FFF

85 32 188000-18FFFF

86 32 180000-187FFF

87 32 178000-17FFFF

88 32 170000-177FFF

89 32 168000-16FFFF

90 32 160000-167FFF

91 32 158000-15FFFF

92 32 150000-157FFF

93 32 148000-14FFFF

94 32 140000-147FFF

95 32 138000-13FFFF

96 32 130000-137FFF

97 32 128000-12FFFF

98 32 120000-127FFF

99 32 118000-11FFFF

100 32 110000-117FFF

101 32 108000-10FFFF

Table 23. Top b o ot block addresses, M2 8W640 HCT (conti n u ed)

# Size (Kword) Address range

Block addr ess tab les M28W640HCT , M28W640HCB

48/72

102 32 100000-107FFF

103 32 0F8000-0FFFFF

104 32 0F0000-0F7FFF

105 32 0E8000-0EFFFF

106 32 0E0000-0E7FFF

107 32 0D8000-0DFFFF

108 32 0D0000-0D7FFF

109 32 0C8000-0CFFFF

110 32 0C0000-0C7FFF

111 32 0B8000-0BFFFF

112 32 0B0000-0B7FFF

113 32 0A8000-0AFFFF

114 32 0A0000-0A7FFF

115 32 098000-09FFFF

116 32 090000-097FFF

117 32 088000-08FFFF

118 32 080000-087FFF

119 32 078000-07FFFF

120 32 070000-077FFF

121 32 068000-06FFFF

122 32 060000-067FFF

123 32 058000-05FFFF

124 32 050000-057FFF

125 32 048000-04FFFF

126 32 040000-047FFF

127 32 038000-03FFFF

128 32 030000-037FFF

129 32 028000-02FFFF

130 32 020000-027FFF

131 32 018000-01FFFF

132 32 010000-017FFF

133 32 008000-00FFFF

134 32 000000-007FFF

Table 23. Top b o ot block addresses, M2 8W640 HCT (conti n u ed)

# Size (Kword) Address range

M28 W640H CT, M28W6 40HC B Block address tab les

49/72

Table 24. Bottom boot block addresses, M28W640HC B

# Size (K word) Addres s rang e

134 32 3F8000-3FFFFF

133 32 3F0000-3F7FFF

132 32 3E8000-3EFFFF

131 32 3E0000-3E7FFF

130 32 3D8000-3DFFFF

129 32 3D0000-3D7FFF

128 32 3C8000-3CFFFF

127 32 3C0000-3C7FFF

126 32 3B8000-3BFFFF

125 32 3B0000-3B7FFF

124 32 3A8000-3AFFFF

123 32 3A0000-3A7FFF

122 32 398000-39FFFF

121 32 390000-397FFF

120 32 388000-38FFFF

119 32 380000-387FFF

118 32 378000-37FFFF

117 32 370000-377FFF

116 32 368000-36FFFF

115 32 360000-367FFF

114 32 358000-35FFFF

113 32 350000-357FFF

112 32 348000-34FFFF

111 32 340000-347FFF

110 32 338000-33FFFF

109 32 330000-337FFF

108 32 328000-32FFFF

107 32 320000-327FFF

106 32 318000-31FFFF

105 32 310000-317FFF

104 32 308000-30FFFF

103 32 300000-307FFF

102 32 2F8000-2FFFFF

101 32 2F0000-2F7FFF

100 32 2E8000-2EFFFF

Block addr ess tab les M28W640HCT , M28W640HCB

50/72

99 32 2E0000-2E7FFF

98 32 2D8000-2DFFFF

97 32 2D0000-2D7FFF

96 32 2C8000-2CFFFF

95 32 2C0000-2C7FFF

94 32 2B8000-2BFFFF

93 32 2B0000-2B7FFF

92 32 2A8000-2AFFFF

91 32 2A0000-2A7FFF

90 32 298000-29FFFF

89 32 290000-297FFF

88 32 288000-28FFFF

87 32 280000-287FFF

86 32 278000-27FFFF

85 32 270000-277FFF

84 32 268000-26FFFF

83 32 260000-267FFF

82 32 258000-25FFFF

81 32 250000-257FFF

80 32 248000-24FFFF

79 32 240000-247FFF

78 32 238000-23FFFF

77 32 230000-237FFF

76 32 228000-22FFFF

75 32 220000-227FFF

74 32 218000-21FFFF

73 32 210000-217FFF

72 32 208000-20FFFF

71 32 200000-207FFF

70 32 1F8000-1FFFFF

69 32 1F0000-1F7FFF

68 32 1E8000-1EFFFF

67 32 1E0000-1E7FFF

66 32 1D8000-1DFFFF

65 32 1D0000-1D7FFF

Table 24. Bottom boot block addresses, M28W640HC B (continue d)

# Size (K word) Addres s rang e

M28 W640H CT, M28W6 40HC B Block address tab les

51/72

64 32 1C8000-1CFFFF

63 32 1C0000-1C7FFF

62 32 1B8000-1BFFFF

61 32 1B0000-1B7FFF

60 32 1A8000-1AFFFF

59 32 1A0000-1A7FFF

58 32 198000-19FFFF

57 32 190000-197FFF

56 32 188000-18FFFF

55 32 180000-187FFF

54 32 178000-17FFFF

53 32 170000-177FFF

52 32 168000-16FFFF

51 32 160000-167FFF

50 32 158000-15FFFF

49 32 150000-157FFF

48 32 148000-14FFFF

47 32 140000-147FFF

46 32 138000-13FFFF

45 32 130000-137FFF

44 32 128000-12FFFF

43 32 120000-127FFF

42 32 118000-11FFFF

41 32 110000-117FFF

40 32 108000-10FFFF

39 32 100000-107FFF

38 32 0F8000-0FFFFF

37 32 0F0000-0F7FFF

36 32 0E8000-0EFFFF

35 32 0E0000-0E7FFF

34 32 0D8000-0DFFFF

33 32 0D0000-0D7FFF

32 32 0C8000-0CFFFF

31 32 0C0000-0C7FFF

30 32 0B8000-0BFFFF

Table 24. Bottom boot block addresses, M28W640HC B (continue d)

# Size (K word) Addres s rang e

Block addr ess tab les M28W640HCT , M28W640HCB

52/72

29 32 0B0000-0B7FFF

28 32 0A8000-0AFFFF

27 32 0A0000-0A7FFF

26 32 098000-09FFFF

25 32 090000-097FFF

24 32 088000-08FFFF

23 32 080000-087FFF

22 32 078000-07FFFF

21 32 070000-077FFF

20 32 068000-06FFFF

19 32 060000-067FFF

18 32 058000-05FFFF

17 32 050000-057FFF

16 32 048000-04FFFF

15 32 040000-047FFF

14 32 038000-03FFFF

13 32 030000-037FFF

12 32 028000-02FFFF

11 32 020000-027FFF

10 32 018000-01FFFF

9 32 010000-017FFF

8 32 008000-00FFFF

7 4 007000-007FFF

6 4 006000-006FFF

5 4 005000-005FFF

4 4 004000-004FFF

3 4 003000-003FFF

2 4 002000-002FFF

1 4 001000-001FFF

0 4 000000-000FFF

Table 24. Bottom boot block addresses, M28W640HC B (continue d)

# Size (K word) Addres s rang e

M28 W640H CT, M28W6 40HCB Common Flash interf ace (CF I)

53/72

Appendix B Common F lash int erface (CFI)

The Common Flash interface is a JEDEC approved, standardized data structure that can be

read from the Flash memory device. It allows a system software to query the device to

determine various electrical and timing parameters, density information and functions

supported by the memory. The system can interface easily with the device, enabling the

software to upgrade itself when necessary.

When the CFI Query command (RCFI) is issued the device enters CFI Query mode and the

data structure is read from the memory. Tables 25, 26, 27, 28, 29 and 30 show the

addresses used to retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number

is written (see Table 30: Security code area). This area can be accessed only in Read mode

by the final user. It is impossible to change the security number after it has been written by

Numonyx. Issue a Read command to return to Read mode.

Tab l e 25. Query structure overview (1)

1. Query data are always presented on the lowest order data outputs.

Offset Sub-section name Description

00h Reserved Reserved for algorithm-specific information

10h CFI Query identification string Command set ID and algorithm data offset

1Bh System interface information Device timing & voltage information

27h Device geometry definition Flash device layout

PPrimary algorithm-specific extended query

table

Additional information specific to the primary

algorithm (optional)

AAlternate algorithm-specific extended query

table

Additional information specific to the

alternate algorithm (optional)

Common Flash interface (CFI) M28W640HCT, M28W640HCB

54/72

Table 26. CFI que ry ident ificat ion string(1)

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Offset Data Description Value

00h 0020h Manufacturer code Numonyx

01h 8848h

8849h Device code To p

Bottom

02h-0Fh reserved Reserved

10h 0051h ‘Q’

11h 0052h Query unique ASCII string ‘QRY’ ‘R’

12h 0059h ‘Y’

13h 0003h Primary algorithm command set and control interface ID code 16

bit ID code defining a specific algorithm

Intel

compatible

14h 0000h

15h 0035h

Address for primary algorithm extended query table (see Table 28)P = 35h

16h 0000h

17h 0000h Alternate vendor command set and control interface ID code

second vendor - specified algorithm supported (0000h means

none exists)

18h 0000h

19h 0000h Address for Alternate algorithm extended query table

(0000h means none exists) NA

1Ah 0000h

M28 W640H CT, M28W6 40HCB Common Flash interf ace (CF I)

55/72

Tab l e 27. CFI query sy stem interface inf ormation

Offset Data Description Value

1Bh 0027h

VDD logic supply minimum program/erase or write voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

2.7 V

1Ch 0036h

VDD logic supply maximum Program/Erase or Write voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

3.6 V

1Dh 00B4h

VPP [programming] supply minimum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

11.4 V

1Eh 00C6h

VPP [programming] supply maximum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

12.6 V

1Fh 0004h Typical time-out per single word program = 2n μs16μs

20h 0004h Typical time-out for Double/Quadruple Word Program = 2n μs16μs

21h 000Ah Typical time-out per individual block erase = 2n ms 1 s

22h 0000h Typical time-out for full chip erase = 2n ms NA

23h 0005h Maximum time-out for Word program = 2n times typical 512 μs

24h 0005h Maximum time-out for Double/Quadruple Word Program = 2n times

typical 512 μs

25h 0003h Maximum time-out per individual block erase = 2n times typical 8 s

26h 0000h Maximum time-out for chip erase = 2n times typical NA

Common Flash interface (CFI) M28W640HCT, M28W640HCB

56/72

Table 28. Device geomet ry defi nitio n

Offset

Word

Mode Data Description Value

27h 0017h Device size = 2n in number of bytes 8 Mbyte

28h

29h

0001h

0000h Flash device interface code description x16

Async.

2Ah

2Bh

0003h

0000h Maximum number of bytes in multi-byte program or page = 2n 8

2Ch 0002h

Number of Erase block regions within the device.

It specifies the number of regions within the device containing

contiguous Erase blocks of the same size.

M28W640HCT

2Dh

2Eh

007Eh

0000h

Region 1 information

Number of identical-size erase block = 007Eh+1 127

2Fh

30h

0000h

0001h

Region 1 information

Block size in Region 1 = 0100h * 256 byte 64 Kbyte

31h

32h

0007h

0000h

Region 2 information

Number of identical-size erase block = 0007h+1 8

33h

34h

0020h

0000h

Region 2 information

Block size in region 2 = 0020h * 256 byte 8 Kbyte

M28W640HCB

2Dh

2Eh

0007h

0000h

Region 1 information

Number of identical-size erase block = 0007h+1 8

2Fh

30h

0020h

0000h

Region 1 information

Block size in region 1 = 0020h * 256 byte 8 Kbyte

31h

32h

007Eh

0000h

Region 2 information

Number of identical-size erase block = 007Eh=1 127

33h

34h

0000h

0001h

Region 2 information

Block size in region 2 = 0100h * 256 byte 64 Kbyte

M28 W640H CT, M28W6 40HCB Common Flash interf ace (CF I)

57/72

Table 29. P ri mary algor ithm -specific e xtended query table

Offset

P = 35h(1) Data Description Value

(P+0)h = 35h 0050h

Primary algorithm extended query table unique ASCII string ‘PRI’

‘P’

(P+1)h = 36h 0052h ‘R’

(P+2)h = 37h 0049h ‘I’

(P+3)h = 38h 0031h Major version number, ASCII ‘1’

(P+4)h = 39h 0030h Minor version number, ASCII ‘0’

(P+5)h = 3Ah 0066h Extended query table contents for primary algorithm. address

(P+5)h contains less significant byte.

bit 0Chip Erase supported(1 = Yes, 0 = No)

bit 1Suspend Erase supported(1 = Yes, 0 = No)

bit 2Suspend Program supported(1 = Yes, 0 = No)

bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No)

bit 4Queued Erase supported(1 = Yes, 0 = No)

bit 5Instant individual block locking supported(1 = Yes, 0 = No)

bit 6Protection bits supported(1 = Yes, 0 = No)

bit 7Page mode read supported(1 = Yes, 0 = No)

bit 8Synchronous read supported(1 = Yes, 0 = No)

bit 31 to 9Reserved; undefined bits are ‘0’

Yes

(P+6)h = 3Bh 0000h

(P+7)h = 3Ch 0000h

(P+8)h = 3Dh 0000h

(P+9)h = 3Eh 0001h

Supported functions after Suspend

Read Array, Read Status Register and CFI query are always

supported during erase or program operation

bit 0Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1Reserved; undefined bits are ‘0’ Yes

(P+A)h = 3Fh 0003h Block Lock status

Defines which bits in the block Status Register section of the

query are implemented.

Address (P+A)h contains less significant byte

bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0

= No)

bit 1Block Lock Status Register Lock-down bit active (1 = Yes, 0 =

No)

bit 15 to 2Reserved for future use; undefined bits are ‘0’

Yes

(P+B)h = 40h 0000h

(P+C)h = 41h 0030h

VDD logic supply optimum Program/Erase voltage (highest

performance)

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

(P+D)h = 42h 00C0h

VPP supply optimum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

12 V

(P+E)h = 43h 0001h Number of protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available 01

Common Flash interface (CFI) M28W640HCT, M28W640HCB

58/72

(P+F)h = 44h 0080h Protection field 1: protection description

This field describes user-available one-time-programmable

(OTP) protection register bytes. Some are pre-programmed with

device unique serial numbers. Others are user programmable.

bits 0–15 point to the Protection Register Lock byte, the section’s

first byte.

The following bytes are factory pre-programmed and user-

programmable.

bit 0 to 7 Lock/bytes JEDEC-plane physical low address

bit 8 to 15Lock/bytes JEDEC-plane physical high address

bit 16 to 23 "n" such that 2n = factory pre-programmed bytes

bit 24 to 31 "n" such that 2n = user programmable bytes

80h

(P+10)h = 45h 0000h 00h

(P+11)h = 46h 0003h 8 byte

(P+12)h = 47h 0004h 16 byte

(P+13)h = 48h Reserved

1. See Table 26, offset 15 for P pointer definition.

Tab l e 30. S ecurity co de area

Offset Data Description

80h 00XX Protection Register Lock

81h XXXX

64 bits: unique device number

82h XXXX

83h XXXX

84h XXXX

85h XXXX

128 bits: user programmable OTP

86h XXXX

87h XXXX

88h XXXX

89h XXXX

8Ah XXXX

8Bh XXXX

8Ch XXXX

Table 29. P ri mary algorithm -spe cific e xtended query table (continued)

Offset

P = 35h(1) Data Description Value

M28W640HCT, M28W640 HCB Flowchar ts and pseudo code s

59/72

Appendix C Flowcharts and ps eudocodes

Figure 15. Program flowchart and pseudocode

1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase controller operations.

Write 40h or 10h

AI03538b

Start

Write Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

/*or writeToFlash (any_address, 0x10) ; */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

Flowcharts and pseudoc odes M28W64 0H CT, M28W640H CB

60/72

Figure 16. Doubl e Word Progra m flowcha rt and pseudocode

1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and address 2 must be consecutive addresses differing only for bit A0.

Write 30h

AI03539b

Start

Write Address 1

& Data 1 (3)

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

Write Address 2

& Data 2 (3)

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

M28W640HCT, M28W640 HCB Flowchar ts and pseudo code s

61/72

Figure 17. Quadruple Word Program flowchart and pseudocode

1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to address 4 must be consecutive addresses differing only for bits A0 and A1.

Write 56h

AI06233

Start

Write Address 1

& Data 1 (3)

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

Write Address 2

& Data 2 (3)

quadruple_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

writeToFlash (any_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

Write Address 3

& Data 3 (3)

Write Address 4

& Data 4 (3)

Flowcharts and pseudoc odes M28W64 0H CT, M28W640H CB

62/72

Figure 18. Program Suspend & Resume flow cha rt and pseudocode

Write 70h

AI03540b

Read Status

YES

b7 = 1

YES

b2 = 1

Program Continues

Write D0h

Read data from

another address

Start

Write B0h

Program Complete

Write FFh

Read Data

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

}

Write FFh

M28W640HCT, M28W640 HCB Flowchar ts and pseudo code s

63/72

Figure 19. Erase flowchart and pseudocode

1. If an error is found, the Status Register must be cleared before further program/erase operations.

Write 20h

AI03541b

Start

Write Block

Address & D0h

Read Status

YES

b7 = 1

YES

b3 = 0

YES

b4, b5 = 1

VPP Invalid

Error (1)

Command

Sequence Error (1)

b5 = 0 Erase Error (1)

End

YES

b1 = 0 Erase to Protected

Block Error (1)

YES

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

} while (status_register.b7== 0) ;

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

error_handler ( ) ;

}

Flowcharts and pseudoc odes M28W64 0H CT, M28W640H CB

64/72

Figure 20. Erase Suspend & Resum e flowc hart and pseudocode

Write 70h

AI03542b

Read Status

YES

b7 = 1

YES

b6 = 1

Erase Continues

Write D0h

Read data from

another block

Program/Protection Program

Block Protect/Unprotect/Lock

Start

Write B0h

Erase Complete

Write FFh

Read Data

Write FFh

erase_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

M28W640HCT, M28W640 HCB Flowchar ts and pseudo code s

65/72

Figure 21. Loc king operations flowchart and pseudocode

Write

01h, D0h or 2Fh

AI04364

Read Block

Lock States

YES

Locking

change

confirmed?

Start

Write 60h locking_operation_command (address, lock_operation) {

writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

/*Check the locking state (see Read Block Signature table )*/

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

}

Write FFh

Write 90h

End

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

Flowcharts and pseudoc odes M28W64 0H CT, M28W640H CB

66/72

Figure 22. Prot ec tion Re giste r Program flowc hart and pseu docode

1. Status check of b1 (protected block), b3 (VPP invalid) and b4 (program error) can be made after each program operation or

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase controller operations.

Write C0h

AI04381

Start

Write Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0xC0) ;

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

M28W640HCT, M28W640HCB Command interface and Program/Erase controller state

67/72

Appendix D Command int erface and Program/Erase

controller state

Table 31. Wr ite st ate mac h i n e cu r rent/ n ext(1)

Current

state

bit

Dat a when

Read

Command input (and next state)

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

St atus

(70h)

Clear

Status

(50h)

Read Array ‘1’ Array Read

Array Prog.Setup Ers.

Setup Read Array Read

Sts.

Read

Array

Read

Status ‘1’ Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read

Elect.Sg. ‘1’ Electronic

signature

Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read CFI

Query ‘1’ CFI Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Lock Setup ‘1’ Status Lock Command Error Lock

(complete)

Lock Cmd

Error

Lock

(complete)

Lock Command

Error

Lock Cmd

Error ‘1’ Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Lock

(complete) ‘1’ Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Prot. Prog.

Setup ‘1’ Status Protection Register Program

Prot. Prog.

(continue) ‘0’ Status Protection Register Program continue

Prot. Prog.

(complete) ‘1’ Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Prog.

Setup ‘1’ Status Program

Program

(continue) ‘0’ Status Program (continue) Prog. Sus

Read Sts Program (continue)

Prog. Sus

Status ‘1’ Status

Prog.

Sus

Read

Array

Program Suspend to

Read Array

Program

(continue)

Prog. Sus

Read

Array

Program

(continue)

Prog.

Sus

Read

Sts

Prog.

Sus

Read

Array

Prog. Sus

Read Array ‘1’ Array

Prog.

Sus

Read

Array

Program Suspend to

Read Array

Program

(continue)

Prog. Sus

Read

Array

Program

(continue)

Prog.

Sus

Read

Sts

Prog.

Sus

Read

Array

Prog. Sus

Read

Elect.Sg.

‘1’ Electronic

signature

Prog.

Sus

Read

Array

Program Suspend to

Read Array

Program

(continue)

Prog. Sus

Read

Array

Program

(continue)

Prog.

Sus

Read

Sts

Prog.

Sus

Read

Array

Comm and interf ace and P ro g ram/E rase co n tro l ler state M 28W 640HCT, M28 W640H CB

68/72

Prog. Sus

Read CFI ‘1’ CFI

Prog.

Sus

Read

Array

Program Suspend to

Read Array

Program

(continue)

Prog. Sus

Read

Array

Program

(continue)

Prog.

Sus

Read

Sts

Prog.

Sus

Read

Array

Program

(complete) ‘1’ Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Erase

Setup ‘1’ Status Erase Command Error Erase

(continue)

Erase

CmdError

Erase

(continue)

Erase

Command Error

Erase

Cmd.Error ‘1’ Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Erase

(continue) ‘0’ Status Erase (continue) Erase Sus

Read Sts Erase (continue)

Erase Sus

Read Sts ‘1’ Status

Erase

Sus

Read

Array

Program

Setup

Erase

Sus

Read

Array

Erase

(continue)

Erase Sus

Read

Array

Erase

(continue)

Erase

Sus

Read

Sts

Erase

Sus

Read

Array

Erase Sus

Read Array ‘1’ Array

Erase

Sus

Read

Array

Program

Setup

Erase

Sus

Read

Array

Erase

(continue)

Erase Sus

Read

Array

Erase

(continue)

Erase

Sus

Read

Sts

Erase

Sus

Read

Array

Erase Sus

Read

Elect.Sg.

‘1’ Electronic

Signature

Erase

Sus

Read

Array

Program

Setup

Erase

Sus

Read

Array

Erase

(continue)

Erase Sus

Read

Array

Erase

(continue)

Erase

Sus

Read

Sts

Erase

Sus

Read

Array

Erase Sus

Read CFI ‘1’ CFI

Erase

Sus

Read

Array

Program

Setup

Erase

Sus

Read

Array

Erase

(continue)

Erase Sus

Read

Array

Erase

(continue)

Erase

Sus

Read

Sts

Erase

Sus

Read

Array

Erase

(complete) ‘1’ Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

1. Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

Table 31. Wr ite st ate mac h i n e cu r rent/ n ext(1) (continued)

Current

state

bit

Dat a when

Read

Command input (and next state)

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

St atus

(70h)

Clear

Status

(50h)

M28W640HCT, M28W640HCB Command interface and Program/Erase controller state

69/72

Table 32. Wr ite st ate mac h i n e cu r rent/ n ext(1)

Current

state

Command input (and next state)

Read

Elect.Sg.

(90h)

Read CFI

Query

(98h)

Lock Setup

(60h) Prot. Prog.

Setup (C0h)

Lock

Confirm

(01h)

Lock Down

Confirm

(2Fh)

Unlock

Confirm

(D0h)

Read Array Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Read Status Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Read

Elect.Sg.

Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Read CFI

Query

Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Lock Setup Lock Command Error Lock (complete)

Lock Cmd

Error

Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Lock

(complete)

Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Prot. Prog.

Setup Protection Register Program

Prot. Prog.

(continue) Protection Register Program (continue)

Prot. Prog.

(complete)

Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Prog. Setup Program

Program

(continue) Program (continue)

Prog.

Suspend

Read Status

Prog.

Suspend

Read

Elect.Sg.

Prog.

Suspend

Read CFI

Query

Program Suspend Read Array Program

(continue)

Prog.

Suspend

Read Array

Prog.

Suspend

Read

Elect.Sg.

Prog.

Suspend

Read CFI

Query

Program Suspend Read Array Program

(continue)

Prog.

Suspend

Read

Elect.Sg.

Prog.

Suspend

Read

Elect.Sg.

Prog.

Suspend

Read CFI

Query

Program Suspend Read Array Program

(continue)

Prog.

Suspend

Read CFI

Prog.

Suspend

Read

Elect.Sg.

Prog.

Suspend

Read CFI

Query

Program Suspend Read Array Program

(continue)

Program

(complete)

Read

Elect.Sg.

Read

CFIQuery Lock Setup Prot. Prog.

Setup Read Array

Comm and interf ace and P ro g ram/E rase co n tro l ler state M 28W 640HCT, M28 W640H CB

70/72

Erase Setup Erase Command Error Erase

(continue)

Erase

Cmd.Error

Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

Erase

(continue) Erase (continue)

Erase

Suspend

Read Ststus

Erase

Suspend

Read

Elect.Sg.

Erase

Suspend

Read CFI

Query

Lock Setup Erase Suspend Read Array Erase

(continue)

Erase

Suspend

Read Array

Erase

Suspend

Read

Elect.Sg.

Erase

Suspend

Read CFI

Query

Lock Setup Erase Suspend Read Array Erase

(continue)

Erase

Suspend

Read

Elect.Sg.

Erase

Suspend

Read

Elect.Sg.

Erase

Suspend

Read CFI

Query

Lock Setup Erase Suspend Read Array Erase

(continue)

Erase

Suspend

Read CFI

Query

Erase

Suspend

Read

Elect.Sg.

Erase

Suspend

Read CFI

Query

Lock Setup Erase Suspend Read Array Erase

(continue)

Erase

(complete)

Read

Elect.Sg.

Read CFI

Query Lock Setup Prot. Prog.

Setup Read Array

1. Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

Table 32. Wr ite st ate mac h i n e cu r rent/ n ext(1) (continued)

Current

state

Command input (and next state)

Read

Elect.Sg.

(90h)

Read CFI

Query

(98h)

Lock Setup

(60h) Prot. Prog.

Setup (C0h)

Lock

Confirm

(01h)

Lock Down

Confirm

(2Fh)

Unlock

Confirm

(D0h)

M28 W640H CT, M28W640HCB Revision h istory

71/72

11 Revision history

Table 33. Doc um ent revis ion history

Date Version Changes

29-Jan-2008 1 Initial release.

20-Mar-2008 2 Applied Numonyx branding.

06-Nov-2008 3 Changed title page to remove “preliminary” status.

Corrected minimum voltage for VIH in Table 15.: DC characteristics

M2 8W64 0HCT, M28W640H CB

72/72

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