MC68HC05B16FNE - Freescale Semiconductor / Motorola

freescale.com

Microcontrollers

M68HC05

MC68HC05B4

MC68HC705B5

MC68HC05B5

MC68HC05B6

MC68HC05B8

MC68HC05B16

MC68HC705B16

MC68HC705B16N

MC68HC05B32

MC68HC705B32

Technical Data

MC68HC05B6/D

Rev. 4.1

08/2005

INTRODUCTION

MODES OF OPERATION AND PIN DESCRIPTIONS

MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

TPG

INTRODUCTION

MODES OF OPERATION AND PIN DESCRIPTIONS

MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

TPG

CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05B6/D rev. 4)

Motorola wishes to continue to improve the qualit y of its documentation. We would w elcome your feedback on the publication you

have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer).

1. How would you rate the quality of the document? Check one box in each category.

Excellent Poor Excellent Poor

Organization ❏❏❏❏ Tables ❏❏❏❏

Readability ❏❏❏❏ Table of contents ❏❏❏❏

Understandability ❏❏❏❏ Index ❏❏❏❏

Accuracy ❏❏❏❏ Page size/binding ❏❏❏❏

Illustrations ❏❏❏❏ Over all impression ❏❏❏❏

Comments:

2. What is your intended use for this document ? If more than one option appli es, please rank them (1, 2, 3).

Selection of device for new application ❏Other ❏Please specify:

System design ❏

Training purposes ❏

3. How well does this manual enable y ou to perform the task(s) outlined in question 2?

Completely Not at all Comments:

❏❏❏❏

4. How easy is it to find the information you are looking for?

Easy Difficult Comments:

❏❏❏❏

5. Is the level of technical detail in the following sections sufficient to allo w you to understand how the device functions?

Too little detail Too much detail

Comments:

6. Have you found any errors? If so, please comment:

7. From your point of view, is anything missing from the document? If so , please say what:

❏❏❏❏❏

– Cut along this line to remove –

SECTION 1 INTRODUCTION

SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS

SECTION 3 MEMORY AND REGISTERS

SECTION 4 INPUT/OUTPUT PORTS

SECTION 5 PROGRAMMA BLE TIMER

SECTION 6 SERIAL COMMUNICATIONS INTERFACE

SECTION 7 PULSE LENGTH D/A CONVERTERS

SECTION 8 ANALOG TO DIGITAL CONVER TER

SECTION 9 RESETS AND INTERRUPTS

SECTION 10 CPU CORE AND INSTRUCTION SET

SECTION 11 ELECTRICAL SPECIFICATIONS

SECTION 12 MECHANICAL DATA

SECTION 13 ORDERING INFORMATION

SECTION 14 APPENDICES

SECTION 15 HIGH SPEED OPERATION

TPG

13. Currently there is some discussion in the semiconductor indu stry regarding a mov e towards p roviding data sh eets in electronic

for m. If you have any opinion on this subject, please comment.

14. We would be grateful if you would supply the followin g information (at your discretion), or attach you r card.

Name: Phone No:

Position: FAX No:

Department:

Company:

Address:

Thank you fo r helping us improve our documentation,

Graham Forbes, Technical Publications Manager, Motorola Ltd., Scotland.

– Cut along this line to remove –

– Third fold back along this line –

8. How could we improve this document?

9. How would you rate Motorola’s documentation?

Excellent Poor

– In general ❏❏❏❏

– Against other semiconductor suppliers ❏❏❏❏

10. Which semiconductor manufacturer provides the best technical documentation?

11. Which company (in any field) provides the best technical documentation?

12. How many years have you worked with microprocessors?

Less than 1 y ear ❏ 1–3 years

❏3–5 years ❏More than 5 years ❏

– Second f old back along this line –

– Finally, tuck this edge into opposite flap –

✂

By air mail

Par avion

NE PAS AFFRANCHIR

IBRS NUMBER PHQ-B/207/G

CCRI NUMERO PHQ-B/207/G

REPONSE PAYEE

GRANDE-BRETAGNE

Motorola Ltd.,

Colvilles Road,

Kelvin Industrial Estate,

EAST KILBRIDE,

G75 8BR.

GREAT BRITAIN.

F.A.O. Technical Publications Manager

(re: MC68HC05B6/D rev. 4)

NO STAMP REQUIRED

– First fold back along this line –

Semiconductor Products Sector

TPG

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume

any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liabilit y, including

without limitation consequential or incidental damages. “Typ ical” parameters which may be provided in Fre escale data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating

parameters, including “ Typicals”, must be valid ated for each customer appli cation by cust omer’s technica l experts. Freescale

does not convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended,

or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

support or sust ain life, or f or any o ther ap plication in which the failure of the Freescale product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly

or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Freescale was negligent regarding the design or manufacture of the part. Freescale, Inc. is an Equal

Opportunity/Aff irmative Action Employer.

All products are sold on Freescale’s Terms & Conditions of Supply. In ordering a product covered by this document the

Customer agrees to be b ound by those Te rms & Con ditions a nd noth ing con tai ned in t his d ocument const itute s or forms p art

of a contract (wi th the exception of the contents of this Notice). A copy of Freescale’s Terms & Conditions of Supply is available

on request.

The Customer should ensure that it has the most up to date version of the document by contacting its local Freescale office.

This document supersedes any earlier documentation relating to the products referred to herein. The information contained

in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.

 Freescale LTD., 2005

All Trade Marks recognized. This document contains information on new products. Specifications and information herein are

subject to change without notice .

MC68HC05B6

High-density Complementary

Metal Oxide Semiconductor

(HCMOS) Microcomputer Unit

TPG

Conventions

Where abbreviations are used in the text, an explanation can be found in the

glossary, at the back of this manual. Register and bit mnemonics are def ined in the

paragraphs describing the m .

An overbar is used to designate an active-low signal, eg: RESET.

Unless otherwise stated, shaded cells in a register diagram indicate that the bit is

either unused or reserved; ‘u’ is used to indicate an undefined state ( on reset).

Unless otherwise stated, pins labelled “NU” should be tied to VSS in an electrically

noisy en vironment. Pins labelled “NC” can be le ft floating, since the y are not bonded

to any part of the device.

TPG

MC68HC05B6

Rev. 4.1 Freescale

TABLE OF CONTENTS

Paragraph

Number Page

NumberTITLE

TA BLE OF CONTENTS

INTRODUCTION

1.1 Features.............................................................................................................1–2

1.2 Mask options for the MC68HC05B6..................................................................1–3

MODES OF OPERATION AND PIN DESCRIPTIONS

2.1 Modes of operation............................................................................................2–1

2.1.1 Single chip mode .........................................................................................2–1

2.2 Serial RAM loader .............. .................... .................................... .................... ...2–2

2.3 ‘Ju mp to any address’............................. .................................... .................... ...2–4

2.4 Low power modes..............................................................................................2–6

2.4.1 STOP ...........................................................................................................2–6

2.4.2 WAIT............................................................................................................2–8

2.4.2.1 Power consumption during WAIT mode.................................................2–8

2.4.3 SLOW mode.................................................................................................2–9

2.4.3.1 Miscellaneous register...........................................................................2–9

2.5 Pin descriptions ..............................................................................................2–10

2.5.1 VDD and VSS............................................................................................2–10

2.5.2 IRQ ............................................................................................................2–10

2.5.3 RESET.......................................................................................................2–10

2.5.4 TCAP1 .......................................................................................................2–10

2.5.5 TCAP2 .......................................................................................................2–11

2.5.6 TCMP1.......................................................................................................2–11

2.5.7 TCMP2.......................................................................................................2–11

2.5.8 OSC1, OSC2 .............................................................................................2–11

2.5.8.1 Crystal..................................................................................................2–11

2.5.8.2 Ceramic resonator................................................................................2–11

2.5.8.3 Extern al clock.......................................................................................2–12

2.5.9 RDI (Receive data in).................................................................................2–13

2.5.10 TDO (Transmit data out) ............................................................................2–13

2.5.11 SCLK..........................................................................................................2–13

2.5.12 PLMA.........................................................................................................2–13

Freescale

ii MC68HC05B6

Rev. 4.1

TABLE OF CONTENTS

Paragraph

Number Page

NumberTABLE OF CONTENTS

2.5.13 PLMB.........................................................................................................2–13

2.5.14 VPP1..........................................................................................................2–13

2.5.15 VRH...........................................................................................................2–13

2.5.16 VRL............................................................................................................2–13

2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7 ............................................................2–13

2.5.18 PD0/AN0–PD7/AN7...................................................................................2–13

MEMORY AND REGISTERS

3.1 Registers...........................................................................................................3–1

3.2 RAM ..................................................................................................................3–1

3.3 ROM..................................................................................................................3–1

3.4 Self-check ROM ................................................................................................3–2

3.5 EEPROM...........................................................................................................3–3

3.5.1 EEPROM control register ............................................................................3–3

3.5.2 EEPROM read operation.............................................................................3–5

3.5.3 EEPROM erase operation ...........................................................................3–5

3.5.4 EEPROM programming operation...............................................................3–6

3.5.5 Options register (OPTR)............ .................... .. .................... .................... ....3–6

3.6 EEPROM during STOP mode...........................................................................3–7

3.7 EEPROM during WAIT mode............................................................................3–7

3.8 Miscellaneous register......................................................................................3–9

INPUT/OUTPUT PORTS

4.1 Input/output programming .................................................................................4–1

4.2 Ports A and B ....................................................................................................4–2

4.3 Port C................................................................................................................4–3

4.4 Port D................................................................................................................4–3

4.5 Port registers.....................................................................................................4–4

4.5.1 Port data registers A and B (PORTA and POR T B).................... .. ................4–4

4.5.2 Port data register C (PORTC).......... .. .................... .................................... ..4–4

4.5.3 Port data register D (PORTD).......... .. .................... .................................... ..4–5

4.5.3.1 A/D status/control register......................................................................4–5

4.5.4 Data direction registe r s (DDRA, DDRB and DDRC)....................................4–5

4.6 Other port considerations..... ... .. ... ... ... ...............................................................4–6

MC68HC05B6
Rev. 4.1 Freescale
iii
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS

PROGRAMMABLE TIMER
1 Counter..............................................................................................................5–1
1.1 Counter register and alternate counter register............ ... ... ................... ... ...5–3
2 Timer control and status....................................................................................5–4
2.1 Timer control register (TCR)................... ................... .................... ..............5–4
2.2 Timer status register (TSR).......................................................................... 5–6
3 Input capture.... ... .. ...................................................................... .......................5–7
3.1 Input capture register 1 (ICR1) .................................................................... 5–7
3.2 Input capture register 2 (ICR2) .................................................................... 5–8
4 Output compare.................................................................................................5–9
4.1 Output compare register 1 (OCR1)..............................................................5–9
4.2 Output compare register 2 (OCR2)............................................................5–10
4.3 Software force compare.............................................................................5–11
5 Pulse Length Modulation (PLM) ......................................................................5–11
5.1 Pulse length modulation registe r s A and B (PLMA/PLMB)........................5–11
6 Timer during  STOP mode................................................................................5–12
7 Timer during WAIT mode.................................................................................5–12
8 Timer state diagrams.......................................................................................5–12

SERIAL COMMUNICATIONS INTERFACE
1 SCI two-wire system features............................................................................6–1
2 SCI receiver features.........................................................................................6–3
3 SCI transmitter features.....................................................................................6–3
4 Functional description........................................................................................6–3
5 Data format........................................................................................................6–5
6 Receive r wake-up oper ation...................... ................... ... .................... ... ...........6–5
6.1 Idle line wake-up..........................................................................................6–6
6.2 Address mark wake-up ................................................................................6–6
7 Receive data in (RDI) ........................................................................................6–6
8 Start bit detection...............................................................................................6–6
9 Transmit data out (TDO).............. ................... .................... .................... ...........6–8
10 SCI synchronous transmission..........................................................................6–9
11 SCI registers....................................................................................................6–10
11.1 Serial communications data register (SCDR)............................................6–10
11.2 Serial communications control register 1 (SCCR1) ...................................6–10
11.3 Serial communications control register 2 (SCCR2) ...................................6–14
11.4 Serial communications statu s  register (SCSR)..........................................6–16
11.5 Baud rate register (BAUD) .........................................................................6–18
12 Baud rate selection..........................................................................................6–19
13 SCI during STOP mode...................................................................................6–21
14 SCI during WAIT mode....................................................................................6–21

Freescale
iv MC68HC05B6
Rev. 4.1
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS

PULSE LENGTH D/A CONVERTERS
1 Miscellaneous register.......................................................................................7–3
2 PLM clock selection...........................................................................................7–4
3 PLM during STOP mode ...................................................................................7–4
4 PLM during WAIT mode....................................................................................7–4

ANALOG TO DIGITAL CONVERTER
1 A/D converter oper a tion......................... ................... .................... ................... ..8–1
2 A/D registers........... ... .. ................................................... ... .. ..............................8–3
2.1 Port D data register (PORTD).......... .. ... .................... ................... ................8–3
2.2 A/D result data register (ADDATA)...............................................................8–3
2.3 A/D status/control register (ADSTAT)...........................................................8–4
3 A/D converter during STOP mode.....................................................................8–6
4 A/D converter during WAIT mode......................................................................8–6
5 Port D analog input............................................................................................8–6

RESETS AND INTERRUPTS
1 Resets...............................................................................................................9–1
1.1 Power-on reset.............................................................................................9–2
1.2  Miscellaneous register................................................................................9–2
1.3 RESET pin................ ... ................. ... ................................. ... ........................9–3
1.4 Computer operating properly (COP) watchdog reset ..................................9–3
1.4.1 COP watchdog during STOP mode.......................................................9–4
1.4.2 COP watchdog during WAIT mode........................................................9–4
1.5 Functions aff ected by reset..........................................................................9–5
2 Interrupts...........................................................................................................9–6
2.1 Interrupt priorities.........................................................................................9–6
2.2 Nonmaskable software interrupt (SWI)........................................................9–6
2.3 Maskable hardware interrupts .....................................................................9–7
2.3.1 External interrupt (IRQ)..........................................................................9–7
2.3.2  Miscellaneous register ................ ... .................... ... ................... ... ..........9–9
2.3.3 Timer interrupts....................................................................................9–10
2.3.4 Serial communications interface (SCI) interrupts.................................9–10
2.4 Hardware controlled interrupt sequence....................................................9–11

MC68HC05B6
Rev. 4.1 Freescale
v
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS

CPU CORE AND INSTRUCTION SET
1 Registers .........................................................................................................10–1
1.1 Accumulator (A).........................................................................................10–2
1.2 Index register (X)........................................................................................10–2
1.3 Program counter (PC)................................................................................10–2
1.4 Stack pointer (SP)......................................................................................10–2
1.5 Condition code register (CCR)...................................................................10–2
2 Instr uction set..................................................................................................10–3
2.1 Register/memory Instructions....................................................................10–4
2.2 Branch instructions ....................................................................................10–4
2.3 Bit manipulation instructions......................................................................10–4
2.4 Read/modify/write instructions...................................................................10–4
2.5 Control instructions....................................................................................10–4
2.6 Tables.........................................................................................................10–4
3 Addressing modes.........................................................................................10–11
3.1 Inherent....................................................................................................10–11
3.2 Immediate................................................................................................10–11
3.3 Direct........................................................................................................10–11
3.4 Extended..................................................................................................10–12
3.5 Indexed, no offset.....................................................................................10–12
3.6 Indexed, 8-bit offset..................................................................................10–12
3.7 Indexed, 16-bit offset................................................................................10–12
3.8 Relative....................................................................................................10–13
3.9 Bit set/clear..............................................................................................10–13
3.10 Bit test and branch...................................................................................10–13

ELECTRICAL SPECIFICATIONS
1 Absolute maximum ratings ..............................................................................11–1
2 DC electrical characteri stics............................................................................11–2
2.1 IDD trends for 5V operation ........................................................................11–3
2.2 IDD trends for 3.3V operation .....................................................................11–6
3 A/D converter characteristics...........................................................................11–8
4 Control timing ................................................................................................11–10

MECHANICAL DATA
1 MC68HC05B family pin configurations............................................................12–1
1.1 52-pin plastic leaded chip carrier (PLCC)..................................................12–1
1.2 64-pin quad flat pa ck (QFP).......................................................................12–2

Freescale

vi MC68HC05B6

Rev. 4.1

TABLE OF CONTENTS

Paragraph

Number Page

NumberTABLE OF CONTENTS

12.1.3 56-pin shrink dual in line package (SDIP)............................................. ... ..12–3

12.2 MC68HC05B6 mechanical dimensions.......................... ... .. .................... ... ... ..12–4

12.2.1 52-pin plastic leaded chip carrier (PLCC)..................................................12–4

12.2.2 64-pin quad flat pack (QFP).......................................................................12–5

12.2.3 56-pin shrink dual in line package (SDIP)............................................. ... ..12–6

ORDERING INFORMATION

13.1 EPROMS.........................................................................................................13–2

13.2 Verification media............................................................................................13–2

13.3 ROM verification units (RVU)................... ... .................... ................... ... ...........13–2

MC68HC05B4

A.1 Features ........................................................................................................... A–1

A.2 Self-check mode............................................................................................... A–5

MC68HC05B8

B.1 Features ........................................................................................................... B–1

MC68HC705B5

C.1 Features ........................................................................................................... C–1

C.2 EPROM ............................................................................................................ C–5

C.2.1 EPROM pr ogramming operat ion........... ... ... ................... .................... .........C–5

C.3 EPROM registers.............................................................................................. C–6

C.3.1 EPROM cont rol register......................................... .................... .................C–6

C.4 Options register (OPTR)................................................................................... C –7

C.5 Boots trap mode........... ... ................. ... ... ...........................................................C–8

C.5.1 Erased EPROM verification......................................................................C–11

C.5.2 EPROM parallel bootstrap load ......... .................... .................... .. .............C–11

C.5.3 EPROM (RAM) serial bootstrap load and execute ...................................C–13

C.5.4 RAM parallel bootstrap load and execute.................................................C–14

C.5.5 Bootstrap loader timing diagrams............................................................. C–17

C.6 DC electrical characteristics........................................................................... C–19

C.7 Control timing.................................................................................................C–19

MC68HC05B6
Rev. 4.1 Freescale
vii
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS
D 
MC68HC05B16
D.1 Features............................................................................................................D–1
D.2 Self-check routines...........................................................................................D–2
D.3 External clock...................................................................................... .............D–4
E 
MC68HC705B16
E.1 Features............................................................................................................ E–2
E.2 External clock......................................... .......................................................... E–5
E.3 EPROM............................................................................................................. E–5
E.3.1 EPROM read operation...............................................................................E–5
E.3.2 EPROM program operation .........................................................................E–5
E.3.3 EPROM/EEPROM/ECLK control register................................................... E–6
E.3.4 Mask option register.... .. ... .................... ................... .................... ................E–8
E.3.5 EEPROM options register (OPTR) ............................................................. E–9
E.4 Bootstrap mode..............................................................................................E–10
E.4.1 Erased EPROM verification ......................................................................E–13
E.4.2 EPROM/EEPROM parallel bootstrap........................................................E–13
E.4.3 EEPROM/EPR OM/RAM serial bootstrap..................................................E–16
E.4.4 RAM parallel bootstrap .................. ... .................... ................... .................E–19
E.4.4.1 Jump to start of RAM ($0050)............................................................. E–20
E.5 Absolute maximum ratings .............................................................................E–21
E.6 DC electrical characteristics...........................................................................E–22
E.7 A/D converter characteristics..........................................................................E–24
E.8 Control timing ................................................................................................. E–26
E.9 EPROM electrical characteristics...................................................................E–28
F 
MC68HC705B16N
F.1 Features............................................................................................................ F–2
F.2 External clock............. .................... .................................................................. F–5
F.3 RESET pin........................................................................................................ F–5
F.4 EPROM............................................................................................................. F–5
F.4.1 EPROM read operation............................................................................... F–5
F.4.2 EPROM program operation......................................................................... F–6
F.4.3 EPROM/EEPROM/ECLK control register................................................... F–6
F.4.4 Mask option register.... .. ..................................... ................... ...................... F–8
F.4.5 EEPROM options register (OPTR) ............................................................. F–9
F.5 Bootstrap mode.............................................................................................. F–10
F.5.1 Erased EPROM verification ...................................................................... F–13

Freescale
viii MC68HC05B6
Rev. 4.1
TABLE OF CONTENTS
Paragraph
Number Page
NumberTABLE OF CONTENTS
F.5.2 EPROM/EEPROM parallel bootstrap.........................................................F–13
F.5.3 Serial RAM loader...................................................................................... F–16
F.5.3.1 Jump to start of RAM ($0051)..............................................................F–16
F.6 Absolute maximum ratings..............................................................................F–19
F.7 DC electrical characteristics............................................................................F–20
F.8 A/D converter characteristics ..................... ... ... ................... ... ... .................... ..F–22
F.9 Control timing..................................................................................................F–24
F.10 EPROM electrical characteristics....................................................................F–26
G 
MC68HC05B32
G.1 Features ...........................................................................................................G–1
G.2 External clock...................................................................................................G–2
H 
MC68HC705B32
H.1 Features ........................................................................................................... H–3
H.2 External clock...................................................................................................H–7
H.3 RESET pin......................... ... ... ................ ... ... ................. ... .. ................. ... ... ...... H–7
H.4 EPROM ............................................................................................................ H–7
H.4.1 EPROM read oper a tion.................... ................... ..................................... ... H–8
H.4.2 EPROM pr ogram opera tion ..................... .................... ................... ............H–8
H.4.3 EPROM/EEPR OM cont rol register............................................................. H–8
H.4.4 Mask option register .................................................................................H–11
H.4.5 Options register (OPTR)......... .................... ... ................... .................... .... H–12
H.5 Bootstrap mode.............. ... .............................................................................H–13
H.5.1 Erased EPROM verification......................................................................H–16
H.5.2 EPROM/EEPR OM parallel bootstrap........................................................ H–16
H.5.3 Serial RAM loader.....................................................................................H–19
H.5.3.1 Jump to start of RAM ($0051)............................................................. H–19
H.6 Absolute maximum ratings.............................................................................H–22
H.7 DC electrical characteristics...........................................................................H–23
H.8 A/D converter characteristics ..................... ... .................... .. .................... ... ... .H–25
H.9 Control timing.................................................................................................H–27
H.10 EPROM electrical characteristics...................................................................H–29
I 
HIGH SPEED OPERATION
I.1 DC electrical characteristics...............................................................................I–2
I.2 A/D converter char act eristics ..................... ... .................... .. .................... ... ........I–3
I.3 Control timing for 5V operation...........................................................................I–4

MC68HC05B6

Rev. 4.1 Freescale

LIST OF FIGURES

Figure

Number Page

NumberTITLE

LIST OF FIGURES

1-1 MC68HC05B6 block diagram.............................................................................1–3

2-1 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram............2–3

2-2 MC68HC05B6 ‘jump to any address’ schematic diagram..................................2–5

2-3 STOP and WAIT flowcharts................................................................................2–7

2-4 Slow mode divider block diagram.......................................................................2–9

2-5 Oscillator connections ......................................................................................2–12

3-1 Memory map of the MC68HC05B6....................................................................3–2

4-1 Standard I/O port structure.................................................................................4–2

4-2 ECLK timing diagram..........................................................................................4–3

4-3 Port logic levels...................................................................................................4–6

5-1 16-bit programmable timer block diagram ..........................................................5–2

5-2 Tim er state timing diagram for reset......... ................... .................... .................5–13

5-3 Timer state tim ing diagram f o r input capture........................ ... ................... ... ...5–13

5-4 Timer state tim ing diagram f o r output c om pare....................... .. ... ....................5–14

5-5 Timer state tim ing diagram f o r timer overflow....................... ................... ... ... ...5–14

6-1 Serial communications interface block diagram .................................................6–2

6-2 SCI rate generator division.................... .............................................................6–4

6-3 Data format.........................................................................................................6–5

6-4 SCI examples of start bit sampling technique ....................................................6–7

6-5 SCI sampling technique used on all bits.............................................................6–7

6-6 Artificial start following a framing error...............................................................6–8

6-7 SCI start bit following a break.............................................................................6–8

6-8 SCI e xample of synchronous and asynchronous tr ansmission.................. ... ... ..6–9

6-9 SCI data clock timing diagram (M=0) ........................................ .................... ...6–12

6-10 SCI dat a clock timing diagr am (M=1) ..................... ... .. ... .................... ..............6–13

7-1 PLM system block diagram.................................................................................7–1

7-2 PLM output waveform examples ........................................................................7–2

7-3 PLM clock selection................................................... .........................................7–4

8-1 A/D converter bloc k diagram .............. ... .................... .................................... .....8–2

8-2 Electrical model of an A/D input pin ...................................................................8–6

9-1 Reset timing diagram..........................................................................................9–1

9-2 Watchdog system block diagram........................................................................9–3

9-3 Interrupt flow char t..............................................................................................9–8

Freescale
xMC68HC05B6
Rev. 4.1
LIST OF FIGURES
Figure
Number Page
NumberTITLE
10-1 Programming model.........................................................................................10–1
10-2 Stacking order..................................................................................................10–1
11-1 Run IDD vs internal operating frequency (4.5V, 5.5V)......................................11–3
11-2 Run IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–3
11-3 Wait IDD vs internal operating frequency (4.5V, 5.5V) ......................................11–3
11-4 Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–4
11-5 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 5.5V...........11–4
11-6 IDD vs mode vs internal operating freque ncy, VDD = 5.5V ...............................11–4
11-7 Run IDD vs internal operating frequency (3V, 3.6V).........................................11–6
11-8 Run IDD (SM = 1) vs internal operating frequency (3V,3.6V)...........................11–6
11-9 Wait IDD vs internal operating frequency (3V, 3.6V).........................................11–6
11-10 Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V)..........................11–7
11-11 Increase in IDD vs frequency for A/D, SCI systems active, VDD = 3.6V............11–7
11-12 IDD vs mode vs internal operating frequency, VDD = 3.6V ...............................11–7
11-13 Timer relationship...........................................................................................11–12
12-1 52-pin PLCC pinout for the MC68HC05B6.......................................................12–1
12-2 64-pin QFP pinout for the MC68HC05B6.........................................................12–2
12-3 56-pin SDIP pinout for the MC68HC05B6........................................................12–3
12-4 52-pin PLCC mechanical dimensions ..............................................................12–4
12-5 64-pin QFP mechanical dimensions.................................................................12–5
12-6 56-pin SDIP mechanical dimensions................................................................12–6
A-1 MC68HC05B4 block diagram.............................................................................A–2
A-2 Memory map of the MC68HC05B4................. ... ................... ... .................... ......A–3
A-3 MC68HC05B4 self-chec k schematic diagram....................................................A–7
B-1 MC68HC05B8 block diagram.............................................................................B–2
B-2 Memory map of the MC68HC05B8................. ... ................... ... .................... ......B–3
C-1 MC68HC705B5 block diagram...........................................................................C–2
C-2 Memory map of the MC68HC705B 5.......................... ... ................... ..................C–3
C-3 Modes of operation flow chart (1 of 2)................................................................C–9
C-4 Modes of operation flow chart (2 of 2)..............................................................C–10
C-5 Timing diagram with handshake.......................................................................C–11
C-6 EPROM(RAM) parallel bootstrap schematic diagram.............. ... ... ..................C–12
C-7 EPROM (RAM) serial bootstrap schematic diagram........................................C–15
C-8 RAM parallel bootstrap schematic diagram......................................................C–16
C-9 EPROM parallel bootstrap loader timing diagram............................................C–17
C-10  RAM parallel loader timing diagram ................................................................C–18
D-1 MC68HC05B16 block diagram...........................................................................D–3
D-2 Oscillator connections........................................................................................D–4
D-3 Memory map of the MC68HC05B16......... ... ... ... ................... ... .................... .. ....D–5
E-1 MC68HC705B16 bloc k diagram........ ... .. ... .................... ... .. .................... ... ... ......E–2
E-2 Memory map of the MC68HC705B16.......... ... ... ................... .................... ... ......E–3
E-3 Modes of operation flow chart (1 of 2)..............................................................E–11

MC68HC05B6
Rev. 4.1 Freescale
xi
LIST OF FIGURES
Figure
Number Page
NumberTITLE
E-4 Modes of operation flow chart (2 of 2)..............................................................E–12
E-5 Timing diagram with handshake.......................................................................E–14
E-6 Parallel EPROM loader timing diagram............................................................E–14
E-7 EPROM Parallel bootstrap schematic diagram.................................................E–15
E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagr am..........................E–17
E-9 Parallel RAM loader timing diagram.................................................................E–19
E-10 RAM parallel bootstrap schematic diagram... .................... ... ... .. .................... ...E–20
E-11 Timer relationship...... .................... ................... .................... ................... .........E–28
F-1 MC68HC705B16N block diagram.......................................................................F–2
F-2 Memory map of the MC68HC705B16N..............................................................F–3
F-3 Modes of operation flow chart (1 of 2)..............................................................F–11
F-4 Modes of operation flow chart (2 of 2)..............................................................F–12
F-5 Timing diagram with handshake.......................................................................F–14
F-6 Parallel EPROM loader timing diagram............................................................F–14
F-7 EPROM parallel bootstrap schematic diagram.................................................F–15
F-8 RAM load and execute schematic diagram ......................................................F–17
F-9 Parallel RAM loader timing diagram.................................................................F–18
F-10 Timer relationship.............. ... ... .................................... .................... .................F–26
G-1 MC68HC05B32 block diagram.............. ... ... ................... ... ... ................... ... ... ....G–2
G-2 Memory map of the MC68HC05B32 .................................................................G–3
H-1 MC68HC705B32 block diagram........................................................................ H–4
H-2 Memory map of the MC68HC705B32 ............................................................... H–5
H-3 Modes of operation flow chart (1 of 2)............................................................. H–14
H-4 Modes of operation flow chart (2 of 2)............................................................. H–15
H-5 Timing diagram with handshake...................................................................... H–17
H-6 Parallel EPROM loader timing diagr am........................................................... H–17
H-7 EPROM parallel bootstrap schematic diagram................................................ H–18
H-8 RAM load and execute schematic diagram ..................................................... H–20
H-9 Parallel RAM loader timing diagram................................................................ H–21
H-10 Timer relationship......... .................................... .................... ........................... H–29
I-1 Timer relationship.......................... ......................................................................I–5

Freescale

xii MC68HC05B6

Rev. 4.1

LIST OF FIGURES

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6
Rev. 4.1 Freescale
xiii
LIST OF TABLES
Table
Number Page
NumberTITLE
LIST OF TABLES
1-1 Data sheet appendices.......................................................................................1–1
2-1 Mode of operation selection ...............................................................................2–1
3-1 EEPROM control bits description.......................................................................3–4
3-2 Register out line....... ................. ... ... .....................................................................3–8
3-3 IRQ sensitivity.....................................................................................................3–9
4-1 I/O pin stat es............. ... ................. .. ... ................. ... ... ................................. ... ... ..4–2
6-1 Method of receiver wake-up .............................................................................6–11
6-2 SCI clock on SCLK pin....................... ................................................... .. ... ......6–13
6-3 First prescaler stage.........................................................................................6–18
6-4 Second prescaler stage (transmitter) ...............................................................6–18
6-5 Second prescaler stage (receiver) ....................................................................6–19
6-6 SCI baud rat e selection.............. ... ................... ... .................... ................... ......6–20
8-1 A/D clock selection................................... ..........................................................8–4
8-2 A/D channel assignment....... .................... ................... ..................................... ..8–5
9-1 Effect of RESET, POR, ST O P  and WAIT..... .. .................... .................................9–5
9-2 Interrupt priorities ...............................................................................................9–7
9-3 IRQ sensitivity.....................................................................................................9–9
10-1 MUL instruction ................................................................................................10–5
10-2 Register/ memory instructions................ ... ... ................... ... .................... .. .........10–5
10-3 Branch instructions...........................................................................................10–6
10-4 Bit manipulation instructions....... ................... ... .................... ................... ... ......10–6
10-5 Read/modify/ write instructions ......................... .................... ... .. .................... ...10–7
10-6 Control inst ructions.... ... ... .................................... .................... .........................10–7
10-7 Instruction set (1 of 2) .......................................................................................10–8
10-8 Instruction set (2 of 2) .......................................................................................10–9
10-9 M68HC05 opcode map...................................................................................10–10
11-1 Absolute maximum ratings...............................................................................11–1
11-2 DC electrical characteristics for 5V operation...................................................11–2
11-3 DC electrical characteristics for 3.3V operation................................................11–5
11-4 A/D characteristics for 5V operation.................................................................11–8
11-5 A/D characteristics for 3.3V operation..............................................................11–9
11-6 Co ntrol timing for 5V oper ation.......................................................................11–10
11-7 Co ntrol timing for 3.3V operation....................................................................11–11

Freescale
xiv MC68HC05B6
Rev. 4.1
LIST OF TABLES
Table
Number Page
NumberTITLE
13-1 MC order numbers ...........................................................................................13–1
13-2 EPROMs for pattern generation.......................................................................13–2
A-1 Mode of operation selection...............................................................................A–1
A-2 Register outline ..................................................................................................A–4
A-3 MC68HC05B4 self-check results .......................................................................A–6
B-1 Register outline ..................................................................................................B–4
C-1 Register outline ..................................................................................................C–4
C-2 Mode of operation selection...............................................................................C–8
C-3 Bootstrap vector targets in RAM ......................................................................C–14
C-4 Additional DC electrical characteristics for MC68HC705B5......................... ....C–19
C-5 Additional control timing for MC68HC705B5....................................................C–19
D-1 Mode of operation selection...............................................................................D–2
D-2 Register outline ..................................................................................................D–6
E-1 Register outline ..................................................................................................E–4
E-2 EPROM control bits description ................... ... ................... ... ... .................... .. ....E–6
E-3 EEPROM control bits description.......................................................................E–7
E-4 Mode of operation selection.............................................................................E–10
E-5 Bootstrap vector targets in RAM ......................................................................E–18
E-6 Absolute maximum ratings...............................................................................E–21
E-7 DC electrical characteristics for 5V operation ..................................................E–22
E-8 DC electrical characteristics for 3.3V operation ...............................................E–23
E-9 A/D characteristics for 5V oper ation..................... ... ... ... ................... ... .............E–24
E-10 A/D characteristics for 3.3V  operation.................. ... ... ... ................... ... ... ..........E–25
E-11 Control timing for 5V operation.........................................................................E–26
E-12 Control timing for 3.3V operation......................................................................E–27
E-13 DC electrical characteri stics for 5V operation ..................................................E–28
E-14 Control timing for 5V operation.........................................................................E–28
E-15 Control timing for 3.3V operation......................................................................E–28
F-1 Register outline ..................................................................................................F–4
F-2 EPR OM cont rol bits description ................ .................... ... .. .................... ... ... ......F–7
F-3 EEPROM control bits description.......................................................................F–8
F-4 Mode of operation selection.............................................................................F–10
F-5 Bootstrap vector targets in RAM ......................................................................F–16
F-6 Absolute maximum ratings...............................................................................F–19
F-7 DC electrical  character istics for 5V operation ..................................................F–20
F-8 DC electrical characteristics for 3.3V operation ............... .. ... ....................... ....F–21
F-9 A/D characteristics for 5V operation............. .................... .. .................... ... .......F–22
F-10 A/D characteristics for 3. 3V operation................ .. ... .................... ... .. ................F–23
F-11 Control timing for 5V operation .........................................................................F–24
F-12 Control timing for 3.3V operation ......................................................................F–25
F-13 DC electrical characteri stics for 5V operation ..................................................F–26
F-14 Control timing for 5V operation .........................................................................F–26

MC68HC05B6
Rev. 4.1 Freescale
xv
LIST OF TABLES
Table
Number Page
NumberTITLE
F-15 Control timing for 3.3V operation......................................................................F–26
G-1 Register outline................................................................................ ..................G–4
H-1 Register outline........................... .................................... .................... ............... H–6
H-2 EPROM control bits description......................................................................... H–9
H-3 EEPROM control bits description.................................................................... H–10
H-4 Mode of operation selection ............................................................................ H–13
H-5 Bootstrap vector targets in RAM...................................................................... H–19
H-6 Absolute Maxim u m ratings.............. ... .................... ................... ...................... H–22
H-7 DC electrical characteristics for 5V operation.................................................. H–23
H-8 DC electrical characteristics for 3.3V operation............................................... H–24
H-9 A/D characteristics for 5V operation................................................................ H–25
H-10 A/D characteristics for 3.3V operation............................................................. H–26
H-11 Control ti ming for 5V op e ration........................................................................ H–27
H-12 Control timing for operation at 3.3V................................................................. H–28
H-13 DC electrical characteristics for 5V operation.................................................. H–29
H-14 Control ti ming for 5V op e ration........................................................................ H–29
H-15 Control ti ming for 3.3V operation..................................................................... H–29
I-1 Ordering info rmation............. ... .................... ................... .....................................I–1
I-2 DC electrical characteristics for 5V operation......................................................I–2
I-3 A/D characteristics for 5V operation....................................................................I–3

Freescale

xvi MC68HC05B6

Rev. 4.1

LIST OF TABLES

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6

Rev. 4.1 Freescale

1-1

INTRODUCTION

The MC68HC05B6 microcomputer (MCU) is a member of Freescale’s MC68HC05 family of

low-cost single chip microcomputers. This 8-bit MCU contains an o n-chip oscillator, CPU, RAM,

ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications

interface, programmable timer system and watchdog. The fully static design allows operation at

frequencies down to dc to further reduce the already low power consumption to a fe w micro-amps.

This data sheet is structured such that de vices similar to the MC68HC05B6 are described in a set

of appendices (see Table 1-1).

Table 1-1 Data sheet appendices

Device Appendix Differences from MC68HC05B6

MC68HC05B4 A 4K bytes ROM; no EEPROM

MC68HC05B8 B 7.25K bytes ROM

MC68HC705B5 C 6K bytes EPROM; self-check replaced by bootstrap

firmware; no EEPROM

MC68HC05B16 D 16K bytes ROM; increased RAM and self-check ROM

MC68HC705B16 E 16K bytes EPROM; increased RAM; self-check replaced

by bootstrap firmware; modified power-on reset routine

MC68HC705B16N F 16K bytes EPROM; increased RAM; self-check replaced

by bootstrap firmware; modified power-on reset routine

MC68HC05B32 G 32K bytes ROM; no page zero ROM; increased RAM

MC68HC705B32 H 32K bytes EPROM; no page zero ROM; increased RAM;

self-check mode replaced by bootstrap firmware

Freescale

1-2 MC68HC05B6

Rev. 4.1

INTRODUCTION

11.1 Features

Hardware features

• Fully sta tic design featuring the industry standard M68HC05 family CPU core

• On chip crystal oscillator with divide by 2 or a software selectable divide b y 32 option (SLO W

mode)

• 2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V

• High speed version available

• 176 bytes of RAM

• 5936 bytes of user ROM plus 14 bytes of user vectors

• 256 bytes of byte erasable EEPROM with internal charge pump and security bit

• Write/erase protect bit for 224 of the 256 bytes EEPROM

• Self te st/bootstrap mode

• Power saving STOP, WAIT and SLOW modes

• Thr ee 8-bit parallel I/O por ts and one 8-bit inp ut-only port

• Software option available to output the internal E-clock to port pin PC2

• 16-bit timer with 2 input captures and 2 output compares

• Computer operating properly (COP) watchdog timer

• Serial communications interf ace system (SCI) with independent tr ansmitter/receiv er baud rate

selection; receiver wake-up func tion for use in multi-receiver systems

• 8 channel A/D converter

• 2 pulse length modulation systems which can be used as D/A converters

• One interrupt request input plus 4 on-board hardware interrupt sources

• Av ailable in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat pac k (QFP) and 56-pin

shrink dual in line (SDIP) packages

• Complete de velopment system support available using the MMDS05 development station with

the M68HC05B32EM emulation module

• Extended operating temperature range of -40 to +125 °C

MC68HC05B6

Rev. 4.1 Freescale

1-3

INTRODUCTION

1.2 Mask options for the MC68HC05B6

The MC68HC05B6 has three mask options th at are programmed dur ing manufacture and must

be specified on the order form.

• Power-on-reset delay (tPORL) = 16 or 4064 cycles

• Automatic watchdog enable/disable following a power-on or external reset

• Watchdog enable/disable during WAIT mode

Warning: It is recommended that an e xternal clock is alwa ys used if tPORL is s et to 16 cycles. This

will prevent any problems arising with oscillator stability when the device is put into

STOP mode.

Figure 1-1 MC68HC05B6 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷ 32

PLMA D/A

PLMB D/A

8-bit

432 bytes

User ROM

5950 bytes

self check ROM

(including 14 bytes

User vectors)

Freescale

1-4 MC68HC05B6

Rev. 4.1

INTRODUCTION

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6

Rev. 4.1 Freescale

2-1

MODES OF OPERATION AND PIN DESCRIPTIONS

MODES OF OPERATION AND PIN

DESCRIPTIONS

2.1 Modes of operation

The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes.

Table 2-1 shows the conditions required to enter each mode on the rising edge of RESET.

2.1.1 Single chip mode

This is the nor mal operating mode of the MC68HC05B6. In this mode the device functions as a

self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O

ports and the 8-bit input-only port, av ailable to the user . All address and data activity occurs within

the MCU.

Table 2-1 Mode of operation selection

IRQ pin TCAP1 pin PD3 PD4 Mode

VSS to VDD VSS to VDD X X Single chip

2VDD VDD 1 0 Serial RAM loader

2VDD VDD 1 1 Jump to any address

Freescale

2-2 MC68HC05B6

Rev. 4.1

MODES OF OPERATION AND PIN DESCRIPTIONS

22.2 Serial RAM loader

The ‘load program in RAM and execute’ mode is entered if the following conditions are sati sfied

when the reset pin is released to VDD. The format used is identical to the format used for the

MC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to ‘1’.

–IRQ

at 2xVDD

– TCAP1 at VDD

–PD3 at V

DD for at least 30 machine cycles after reset

–PD4 at V

SS for at least 30 machine cycles after reset

In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via

the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until

the last byte is loaded. Program control is then transf erred to the RAM program starting at location

$0051. The first byte loaded is the count of the total number of bytes in the program plus the count

byte. The program star ts at th e second byte in RAM. Dur ing the fir mware initialization stage, the

SCI is configured for the NRZ data f ormat (idle line, start bit, eight data bits and stop bit). The baud

rate is 9600 with a 4 MHz crystal. A program to con v ert ASCII S-records to the f ormat required by

the RAM loader is available from Freescale.

If immediate execution is not desired after loading the RAM program, it is possible to hold off

e xecution. This is accomplished by setting the byte count to a v alue that is greater than the ov erall

length of the loaded data. When the last byte is loaded, the firmware will halt operation expecting

additional data to arrive. At this point, the reset switch is placed in the reset position which will reset

the MCU, but keep the RAM program intact. All routines can now be entered from this state,

including the one which will execute the program in RAM (see Section 2.3).

To load a program in the EEPROM, the ‘load prog ram in RAM and e xecute’ function is also used.

In this instance the p r ocess involves two distinct steps. Firstly, the RAM is loaded with a program

which will control the loading of the EEPROM, and when the RAM contents are ex ecuted, the MCU

is instructed to load the EEPROM.

The erased state of the EEPROM is $FF.

Figure 2-1 shows the schematic diagram of the circuit required for the ser ial RAM loader.

MC68HC05B6

Rev. 4.1 Freescale

2-3

MODES OF OPERATION AND PIN DESCRIPTIONS

Figure 2-1 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram

OSC1

OSC2

IRQ

TCAP2

TCMP2

TCAP1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

VSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

RESET

VDD

10 kΩ

0.01 µF

10 nF 47 µF

10 MΩ

4 MHz

22 pF 22 pF

P1 GND

+5V

2xVDD

RESET 10

VRH

VRL

VPP1

PLMA

PLMB

TCMP1

RDI

TDO

RS232 level translator

suggested:

MC145406 or MAX232

9600 Bd

RS232

SCLK

10 kΩ

Connect as required

for the application

Connect as required

for the application

MC68HC05B6 (52-pin package)

Freescale

2-4 MC68HC05B6

Rev. 4.1

MODES OF OPERATION AND PIN DESCRIPTIONS

22.3 ‘Ju mp to any address’

The ‘jump to any address’ mode is entered when the reset pin is released to VDD, if th e following

conditions are satisfied:

–IRQ

at 2xVDD

– TCAP1 at VDD

–PD3 at V

DD for at least 30 machine cycles after reset

–PD4 at V

DD for at least 30 machine cycles after reset

This function allows execution of programs previously loaded in RAM or EEPROM using the

methods outlined in Section 2.2.

To execute the ‘jump to any address’ function, data input at port A has to be $CC and data input at

port B and port C should represent the MSB and LSB respectively, of the address to jump to for

e x ecution of the user prog ram. A sch ematic d iagr am of the circuit required i s shown in Figure 2-2.

MC68HC05B6

Rev. 4.1 Freescale

2-5

MODES OF OPERATION AND PIN DESCRIPTIONS

Figure 2-2 MC68HC05B6 ‘jump to any address’ schematic diagram

OSC1

OSC2

IRQ

TCAP2

TCMP2

TCAP1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

VSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

RESET

VDD

10 kΩ

0.01 µF

10 nF 47 µF

10 MΩ

4 MHz

22 pF 22 pF

P1 GND

+5V

2xVDD

RESET 10

VRH

VRL

VPP1

PLMA

PLMB

TCMP1

RDI

TDO

SCLK

10 kΩ

52 Connect as required

for the application

8 x 10 kΩopti onal (see note)

8 x 10 kΩ

MSBLSB

Select required address

Note: These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7

are kept in input mode during application.

MC68HC05B6 (52-pin package)

Freescale
2-6 MC68HC05B6
Rev. 4.1
MODES OF OPERATION AND PIN DESCRIPTIONS
22.4 Low power modes
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.4.1 STOP
The ST OP instruction places the MCU in its lowest pow er consumption mode. In ST OP mode, the
internal oscillator is turned off, halting all internal processing including timer, serial
communications interface and the A/D conver ter (see flowchar t in Figure 2-3). The only way for
the MCU to wake-up from the ST OP mode is b y receipt of an external interrupt or by the detection
of a reset (logic low on RESET pin or a power-on reset). 
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
Section 10.1.5). The SM bit is cleared to allow nominal speed operation f or the 4064 cycles count
while exiting STOP mode (see Section 2.4.3). 
All other registers and memory remain unaltered and all input/output lines remain unchanged.
This continues until an external interrupt (IRQ) or reset is sensed, at which time the internal
oscillator is turned on. The external interrupt or reset causes the program counter to vector to the
corresponding locations ($1FFA, B and $1 FFE, F respectively).
When leaving STOP mode, a tPORL internal cycles delay is provided to give the oscillator time to
stabilise before releasing CPU operation. This del ay is selectable via a mask option to be e ither
16 or 4064 cycles. The CPU will resume operation by servicing the interr upt that wakes it up, or
by fetching the reset vector, if reset wakes it up. 
Warning: If tPORL is selected to be 16 cycles, it is recommended that an exter nal clock signal is
used to avoid problems with oscillator stability while the device is in ST OP mode.
Note: The stacking corresponding to an eventual interru pt to go out of  STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the individual modules of the
MC68HC05B6.
– The watchdog time r is reset; refer to Section 9.1.4.1
– The EEPR OM acts as read-only memory (ROM) ; refer to Section 3.6
– All SCI activity stopped; refer to Section 6.13
– The timer stops counting; refer to Section 5.6
– The PLM outputs remain at current level; refer to Section 7.3
– The A/D converter is disabled; refer to Section 8.3
– The I-bit in the CCR is cleared

MC68HC05B6

Rev. 4.1 Freescale

2-7

MODES OF OPERATION AND PIN DESCRIPTIONS

Figure 2-3 STOP and WAIT flowcharts

Timer interrupt?

IRQ

external

interrupt?

SCI interrupt?

Stop oscillator and all

clocks.

Clear I bit.

STOP WAIT

Reset?

IRQ

external

interrupt?

Generate

watchdog reset

Reset?

Watchdog active?

(1) Fetch reset vector or

(2) Service interrupt:

a. stack

b. set I-bit

c. vector to interrupt

routine

(1) Fetch reset vector or

(2) Service interrupt:

a. stack

b. set I-bit

c. vector to interrupt

routine

Turn on oscillator.

Wait for time delay to

stabilise

Restart processor clock

YES

Oscillator active. Timer, SCI,

A/D, EEPROM clocks active.

Processor clocks stopped

Clear I-bit

Freescale

2-8 MC68HC05B6

Rev. 4.1

MODES OF OPERATION AND PIN DESCRIPTIONS

22.4.2 WAIT

The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode

consumes more power than STOP mode. All CPU action is suspended and the watchdog is

disabled, but the timer, A/D and SCI systems remain active and operate as normal (see flowchart

in Figure 2-3). All other memory and registers remain unalte red an d all parallel input/output lin es

remain unchanged. The programming or erase mechanism of the EEPR OM is also unaffected, as

well as the charge pump high voltage generator.

During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the

miscellaneous register (Section 2.5) is not aff ected b y WAIT mode. When any interrupt or reset is

sensed, the program counter vectors to the locations containing the star t address of the interrupt

or reset service routine.

Any IRQ, timer (overflow, input captu re or output compare) or SCI interr upt (in additi on to a logic

low on the RESET pin) causes the processor to exit WAIT mode.

If a non-reset exit from WAIT mode is perf ormed (i.e. timer overflo w interrupt exit), the state of the

remaining systems will be unchanged.

If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state.

Note: The stacking corresponding to an eventual interrupt to leave WAIT mo de will only be

executed when leaving WAIT mode.

The following list summarizes the effect of WAIT mode on the modul es of the MC68HC05B6.

– The watchdog timer functions according to the mask option selected; refer

to Section 9.1.4.2

– The EEPROM is not affected; refer to Section 3.7

– The SCI is not affected; refer to Section 6.14

– The timer is not affected; refer to Section 5.7

– The PLM is not affected; refer to Section 7.4

– The A/D converter is not affected; refer to Section 8.4

– The I-bit in the CCR is cleared

2.4.2.1 Power consumption during WAIT mode

Power consumption during WAIT mode depends on how many systems are active. The power

consumption will be highest when all the systems (A/D, timer, EEPROM and SCI) are active, and

lowest when the EEPROM erase and programming mechanism, SCI and A/D are disabled. The

timer cannot be disabled in WAIT mode. It is important that before entering WAIT mode, the

programmer sets the relevant control bits for the individual modules to reflect the desired

functionality during WAIT mode.

Power consumption may be further reduced by the use of SLOW mode.

MC68HC05B6

Rev. 4.1 Freescale

2-9

MODES OF OPERATION AND PIN DESCRIPTIONS

2.4.3 SLOW mode

The SLOW mode function is controlled by the SM bit in the miscellaneous register at location

$000C. It allows the user to insert, under software control, an extra divide-by-16 between the

oscillator and the internal cloc k driver (see Figure 2-4). This f eature permits a slow do wn of all the

inter nal operations and thus reduces power consumption. Th e SLOW mode function should not

be enabled while using the A/D converter or while erasing/programming the EEPROM unless the

internal A/D RC oscillator is turned on.

2.4.3.1 Miscellaneous register

SM — Slow mode

1 (set) – The system runs at a bus speed 16 times lower than normal

(fOSC/32). SLOW mode affects all sections of the device, including

SCI, A/D and timer.

0 (clear) – The system runs at normal bus speed (fOSC/2).

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when

entering STOP mode.

Note: The bits shown shaded in the above representation are explained individually in the

relevant sections of this manual. The complete register plus an explanation of each bit

can be found in Section 3.8.

Figure 2-4 Slow mode divider block diagram

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?

OSC1

OSC2

Oscillator

fOSC

Control logicSM–bit

fOSC/2

÷ 2 ÷ 16

Main internal clock

fOSC/32

(bit 1, $000C)

Freescale

2-10 MC68HC05B6

Rev. 4.1

MODES OF OPERATION AND PIN DESCRIPTIONS

22.5 Pin descriptions

2.5.1 VDD and VSS

P o wer is supplied to the microcontroller using these two pins. VDD is the positiv e supply and VSS

is ground.

It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These

shor t r ise and fall times place very high short-duration current demands on the power supply. To

prevent noise problems, specia l care must be taken to provide good power supply by-passing at

the MCU . By-pass capacitors should hav e good high-frequency characteristics and be as close to

the MCU as possible . Bypassing requirements v ary, depending on how hea vily the MCU pins are

loaded.

2.5.2 IRQ

This is an input-only pin for external interr upt sources. Interrupt triggering is selected using the

INTP and INTN bits in the miscellaneou s register, to be one of four options detailed in Table 9-3.

In addition, the external interrupt facility (IRQ) can be disabled using the INTE bit in the

miscellaneous registe r (see Section 3.8). It is only po ssible to change the interr upt option bits i n

the miscellaneous register while the I-bit is set. Selecting a different interrupt option will

automatically clear any pending interrupts . Further details of the e xternal interrupt procedure can

be found in Section 9.2.3.1.

The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.

2.5.3 RESET

This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin f orces the device

to a known start-up state. An external RC-circuit can be connected to this pin to generate a

power-on-reset (POR) if required. In this case, the time constant must be great enough to allow

the oscillator circuit to stabilize. This input has an internal Schmitt trigger to improve noise

immunity. When a re set condition occurs inter nally, i.e. from the COP watchdog, the RESET pin

provides an active-low open drain output signal that may be used to reset external hardware.

2.5.4 TCAP1

The TCAP1 input controls the input capture 1 function of the on-chip progr ammable timer system.

MC68HC05B6

Rev. 4.1 Freescale

2-11

MODES OF OPERATION AND PIN DESCRIPTIONS

2.5.5 TCAP2

The TCAP2 input controls the input capture 2 function of the on-chip programmab le timer system.

2.5.6 TCMP1

The TCMP1 pin is the output of the output compare 1 function of the timer system.

2.5.7 TCMP2

The TCMP2 pin is the output of the output compare 2 function of the timer system.

2.5.8 OSC1, OSC2

These pins provide control input for an on-chip oscillator ci rcuit. A crystal, ceramic reson ator or

external clock signal connected to these pins supplies the oscillator clock. The oscillator frequency

(fOSC) is divided by two to give the internal bus frequency (fOP). There is also a software option

which introduces an additional divide by 16 into the oscillator clock, giving an internal bus

frequency of fOSC/32.

2.5.8.1 Crystal

The circuit shown in Figure 2-5(a) is recommended when using either a crystal or a ceramic

resonator. Figure 2-5(d) lists the recommended capacitance and f eedback resistance values. The

internal oscillator is designed to interf ace with an AT-cut par allel-resonant quartz crystal resonator

in the frequency range specified for fOSC (see Section 11.4). Use of an exter nal CMOS o sci llator

is recommended when crystals outside the specified ranges are to be used. The crystal and

associated components should be mounted as close as possible to the input pins to minimise

output distor tion and star t-up stabilisatio n time. The manufacturer of the par ticular crystal being

considered should be consulted f or specific information.

2.5.8.2 Ceramic resonator

A ceramic resonator ma y be used instead of a crystal in cost sensitive applications. The circuit shown

in Figure 2-5(a) is recommended when using either a cr ystal or a ceramic re sonator. Figure 2-5(d)

lists the recommended capacitance and feedback resistance values. The manufacturer of the

particular ceramic resonator being considered should be consulted for specific inf ormation.

Freescale

2-12 MC68HC05B6

Rev. 4.1

MODES OF OPERATION AND PIN DESCRIPTIONS

22.5.8.3 External clock

An external clock should be applied to the OSC1 input, with the OSC2 pin le ft unconnected, as

shown in Figure 2-5(c). The tOXOV or tILCH specifications (see Section 11.4) do not apply when

using an external clock input. The equivalent specification of the external clock source should be

used in lieu of tOXOV or tILCH.

Figure 2-5 Oscillator connections

Ceramic resonator

2 – 4MHz Unit

RS(typ) 10 Ω

C040 pF

C14.3 pF

COSC1 30 pF

COSC2 30 pF

RP1 – 10 MΩ

Q 1250 —

Crystal

2MHz 4MHz Unit

RS(max) 400 75 Ω

C057pF

C1812ƒF

COSC1 15 – 40 15 – 30 pF

COSC2 15 – 30 15 – 25 pF

RP10 10 MΩ

Q 30 000 40 000 —

OSC1 OSC2

MCU

COSC2

COSC1

OSC1 OSC2

MCU

NCExternal

clock

OSC1 OSC2

(d) Typical crystal and ceramic resonator parameters

(b) Crystal equivalent circuit

(a) Crystal/ceramic resonator

oscillator connections

MC68HC05B6

Rev. 4.1 Freescale

2-13

MODES OF OPERATION AND PIN DESCRIPTIONS

2.5.9 RDI (Receive data in)

The RDI pin is the input pin of the SCI receiver.

2.5.10 TDO (Tr ansmit data out)

The TDO pin is the output pin of the SCI transmitter.

2.5.11 SCLK

The SCLK pin is the clock output pin of the SCI transmitter.

2.5.12 PLMA

The PLMA pin is the output of pulse length modula tion converter A.

2.5.13 PLMB

The PLMB pin is the output of pulse length modula tion converter B.

2.5.14 VPP1

The VPP1 pin is the output of the charge pump for the EEPROM1 array.

2.5.15 VRH

The VRH pin is the positive reference voltage for the A/D conv erter .

2.5.16 VRL

The VRL pin is the negative reference voltage for the A/D converter.

2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7

These 24 I/O lines comprise ports A, B and C . The state of an y pin is software programmable, and

all the pins are configured as inputs during power-on or reset.

Under software control the PC2 pin can output the inter nal E-clock (see Section 4.2).

2.5.18 PD0/AN0–PD7/AN7

This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D

converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is

disabled which forces the port D pins to be input only port pins (see Section 8.5).

Freescale

2-14 MC68HC05B6

Rev. 4.1

MODES OF OPERATION AND PIN DESCRIPTIONS

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6

Rev. 4.1 Freescale

3-1

MEMORY AND REGISTERS

The MC68HC05B6 MCU is capable of addressing 8192 bytes of memory and registers with its

program counter. The memory map includes 5950 bytes of User ROM (including User vectors),

432 bytes of self check ROM, 176 bytes of RAM and 256 bytes of EEPROM.

3.1 Registers

All the I/O, control and status registers of the MC68HC05B6 are contained within the first 32-byte

block of the memory map, as shown in Figure 3-1. The miscellaneous register is shown in

Section 3.8 as this register contains bits which are relevant to several modules.

3.2 RAM

The user RAM comprises 1 76 bytes of memor y, from $0050 to $00FF. This is shared with a 64

byte stack area. The stack begins at $00FF and may extend down to $00C0.

Note: Using the stack area for data storage or temporary work locations requires care to prev ent

the data from being overwritten due to stacking from an interrupt or subroutine call.

3.3 ROM

The User ROM consists of 5950 bytes of ROM mapped as follows:

• 4 8 bytes of page zero ROM from $0020 to $004F

• 5888 bytes of User ROM from $0800 to $1EFF

• 14 bytes of User vectors from $1FF2 to $1FFF

Freescale

3-2 MC68HC05B6

Rev. 4.1

MEMORY AND REGISTERS

3.4 Self-check ROM

There are two areas of self-check ROM (ROMI and ROMII) located from $0200 to $02BF (192

bytes) and $1F00 to $1FEF (240 bytes) respectively.

Figure 3-1 Memory map of the MC68HC05B6

$1FFE–F

$1FF6–7

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

User vectors

(14 bytes)

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$02C0

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

Self-check ROM I

(192 bytes)

User ROM

(5888 bytes)

Self-check ROM II

(240 bytes)

$0800

$1FF2–3

OPTR (1 byte)

Non protected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B6 Registers

SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$1FF4–5

$1FF8–9

$1FFA–B

$1FFC–D

MC68HC05B6

Rev. 4.1 Freescale

3-3

MEMORY AND REGISTERS

3.5 EEPROM

The user EEPROM consists of 256 bytes of memor y located from address $0100 to $01FF. 255

bytes are general purpose and 1 b yte is used b y the option register. The non-volatile EEPROM is

byte erasable.

An internal charge pump provides the EEPROM voltage (VPP1), which remov es the need to supply

a high voltage for erase and progr amming functions. The charge pump is a capacitor/diode ladder

network which will give a very high impedance output of around 20-30 MΩ. The voltage of the

charge pump is visible at the VPP1 pin. During normal operation of the device, where

programming/erasing of the EEPR OM arra y will occur, VPP1 should ne v er be connected to either

VDD or VSS as this could prev ent the charge pump reaching the necessary prog ramming voltage .

Where it is considered dangerous to leave VPP1 unconnected for reasons of excessive noise in

a system, it may be tied to VDD; this will protect the EEPROM data but will also increase power

consumption, and therefore it is recommended that the protect bit function is used for regular

protection of EEPROM data (see Section 3.5.5).

In order to achiev e a higher deg ree of security f or stored data, there is no capability for b ulk or row

erase operations.

The EEPROM control register ($0007) provides control of the EEPROM programming and erase

operations.

Warning: The VPP1 pin should never be connected to VSS, as this could cause permanent

damage to the device.

3.5.1 EEPROM control register

ECLK

See Section 4.3 for a description of this bit.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An erase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been sele cted, E1ERA cannot be changed.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000

Freescale

3-4 MC68HC05B6

Rev. 4.1

MEMORY AND REGISTERS

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for furt her

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note: After the tERA1 erase time or tPROG1 programming time, the E1LAT bit ha s to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Internal charge pump generator switched off.

When the charge pump generator is on, the resulting high v oltage is applied to the EEPROM array.

This bit cannot be set before the data is selected, and once this bit has been set it can onl y be

cleared by clearing the E1 LAT bit.

A summary of the eff ects of setting/clearing bits 0, 1 and 2 of the control register are give in Table 3-1.

Note: All combinations are not sh own in the above table, since the E1PGM and E1ERA bits

are cleared when the E1LAT bit is at zero, and will result in a read condition.

Table 3-1 EEPROM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

MC68HC05B6

Rev. 4.1 Freescale

3-5

MEMORY AND REGISTERS

3.5.2 EEPROM read operation

To be able to read from EEPROM, the E1LAT bit has to be at logic zero, as shown in Table 3-1.

While this bit is at logic zero , the E1PGM bit and the E1ERA bit are permanently reset to z ero and

the 256 bytes of EEPROM ma y be read as if it were a normal R OM area. The internal charge pump

generator is automatically switched off since the E1PGM bit is reset.

If a read operation is executed while the E1LAT bit is set (erase or prog ramming sequence), data

resulting from the operation will be $FF.

Note: When not performing any programming or erase operation, it is recommended that

EEPROM should remain in the read mode (E1LAT = 0)

3.5.3 EEPROM erase operation

To erase the contents of a byte of the EEPROM, the following steps should be taken:

1 Se t th e E1 LAT bit.

1) Set the E1ERA bit (1& 2 may be done simultaneously with the same

instruction).

2) Write address/data to the EEPROM address to be erased.

3) Set the E1PGM bit.

4) Wait for a time tERA1.

5) Reset the E1LAT bit (to logic zero).

While an erase operation is being performed, any access of the EEPROM array will not be

successful.

The erased state of the EEPROM is $FF and the programmed state is $00.

Note: Data written to the address to be erased is not used, therefore its value is not

significant.

If a second word is to be erased, it is impor tant that the E1LAT bit be reset be fore restarting the

erasing sequence otherwise any write to a new address will have no effect. This condition provides

a higher degree of security for the stored data.

User programs must be running from the RAM or R OM as the EEPROM will hav e its address and

data buses latched.

Freescale

3-6 MC68HC05B6

Rev. 4.1

MEMORY AND REGISTERS

3.5.4 EEPROM programming operation

To program a b yte of EEPROM, the following steps should be taken:

1 Set the E1LAT bit.

2 Write address/data to the EEPROM address to be programmed.

3 Set the E1PGM bit.

4 Wait for time tPROG1.

5 Reset the E1LAT bit (to logic zero).

While a programming operation is being performed, any access of the EEPR OM array will not be

successful.

Warning: To program a byte correctly, it has to ha ve been previously erased. It is advised that this

is done only for 0→1 transitions, as this saves excessive o verwriting of EEPROM.

If a second word is to be programmed, it is important that the E1LAT bit be reset bef ore restarting

the programming sequence otherwise any write to a new address will have no effect. This

condition provides a higher degree of security for the stored data.

User programs m ust be running from the RAM or R OM as the EEPROM will hav e its address and

data buses latched.

Note: 224 bytes of EEPR OM (address $0120 to $01FF) can be program and erase protected

under the control of bit 1 of the OPTR register detailed in Section 3.5.5.

3.5.5 Options register (OPTR)

This register (OPTR), located at $0100, contains the secure and protect functions for the

EEPROM and allows the user to select options in a non-volatile manner. The contents of the

OPTR register are loaded into data latches with each power-on or external reset.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1)

(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

$0100 EE1P SEC Not affected

MC68HC05B6

Rev. 4.1 Freescale

3-7

MEMORY AND REGISTERS

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Par t 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit

of the options register.

1 (set) – P art 2 of the EEPROM arr ay is not protected; all 256 bytes of EEPR OM

can be accessed for an y read, erase or progr amming operations

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the ELAT bit in the EEPROM control register is set.

SEC – Security bit

This high security bit allows the user to secure the EEPROM data from e xternal accesses. When

the SEC bit is at ‘0’, the EEPR OM contents are secured by pre v enting any entry to test mode. The

only wa y to erase the SEC bit to ‘1’ externally is to enter self-chec k mode, at which time the entire

EEPROM contents will be erased. When the SEC bit is changed, its ne w value will have no eff ect

until the next external or power-on reset.

3.6 EEPROM during STOP mode

When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1

high voltage charge pump generator is automatically disabled.

3.7 EEPROM during WAIT mode

The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in

norm al operating mode. The charge pump is not affected by WAIT mode, therefore it is possible

to wait the tERA1 erase time or tPROG1 programming time in WAIT mode.

Under normal operating conditions, the charge pump generator is driven by the internal CPU

clocks. When the operating frequency is low , e .g. during W AIT mode, the cloc king should be done

by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D

status/control register at $0009.

Freescale

3-8 MC68HC05B6

Rev. 4.1

MEMORY AND REGISTERS

Table 3-2 R e gister outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(3) $0100 EE1P SEC Not affected

(1) The POR bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

MC68HC05B6

Rev. 4.1 Freescale

3-9

MEMORY AND REGISTERS

3.8 Miscellaneous register

POR — Power-on reset bit (see Section 9.1)

This bit is set each ti me the device is powered on. Therefore, the state of the POR bit all ows the

user to make a software distinction between a power-on and an external reset. This bit cannot be

set by software and is cleared by writing it to zero.

1 (set) – A power-on reset has occurred.

0 (clear) – No power-on reset has occurred.

INTP, INTN — External interrupt sensitivity options (see Section 9.2)

These two bits allow the user to select which edge the IRQ pin will be sensitive to (see Table 3-3).

Both bits can be written to only while the I-bit is set, and are cleared by po wer-on or e xternal reset,

thus the device is initialised with negative edge and low level sensitivity.

INTE — External interrupt enab le (see Section 9.2)

1 (set) – External interrupt function (IRQ) enabled.

0 (clear) – External interrupt function (IRQ) disabled.

The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,

thus enabling the external interrupt function.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR(1)

(1) The POR bit is set each time there is a power-on reset.

INTP INTN INTE SFA SFB SM WDOG(2)

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

?001 000?

Table 3-3 IRQ sensitivity

INTP INTN IRQ sensitivity

0 0 Negative edge and low level sensitive

0 1 Negative edge only

1 0 Positive edge only

1 1 Positive and negative edge sensitive

Freescale

3-10 MC68HC05B6

Rev. 4.1

MEMORY AND REGISTERS

SFA — Slow or fast mode selection for PLMA (see Section 7.1)

This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation

output.

1 (set) – Slow mode PLMA (4096 x timer clock period).

0 (clear) – Fast mode PLMA (256 x timer clock period).

SFB — Slow or fast mode selection for PLMB (see Section 7.1)

This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation

output.

1 (set) – Slow mode PLMB (4096 x timer clock period).

0 (clear) – Fast mode PLMB (256 x timer clock period).

Note: The highest speed of the PLM system corresponds to the frequency of the TOF bit

being set, multiplied by 256. The lowest speed of the PLM system corresponds to the

frequency of the TOF bit being set, multiplied by 16.

Warning: Because the SF A bit and SFB bit are not doub le b uffered, it is mandatory to set the SFA

bit and SFB bit to the desired values before writing to the PLM registers; not doing so

could temporarily give incorrect values at the PLM outputs.

SM — Slow mode (see Section 2.4.3)

1 (set) – The system runs at a bus speed 16 times lower than normal

(fOSC/32). SLOW mode affects all sections of the device, including

SCI, A/D and timer.

0 (clear) – The system runs at normal bus speed (fOSC/2).

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when

entering STOP mode.

WDOG — Watchdog enable/disable (see Section 9.1.4)

The WDOG bit can be used to enable the watchdog time r previously disabled by a mask option.

F ollowing a watchdog reset the state of the WDOG bit is as defined b y the mask option specified.

Once the watchdog is enabled, the WDOG bit acts as a reset mechanism for the watchdog

counter. Writing a’1’ to this bit clears the counter to its initial value and prevents a watchdog

timeout.

1 (set) – Watchdog counter cleared and enabled.

0 (clear) – The watchdog cannot be disabled by software; writing a zero to this

bit has no effect.

MC68HC05B6

Rev. 4.1 Freescale

4-1

INPUT/OUTPUT PORTS

In single-chip mode, the MC68HC05B6 has a total o f 24 I/O lines, arranged as three 8-bit por ts

(A, B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually

programmable as either input or output, under the software control of the data direction registers.

The 8-bit input-only port (D) shares its pins with the A/D converter, when the A/D converter is

enabled. To avoid glitches on the outpu t pins, data shou ld be wr itten to the I/O port data register

before writing ones to the corresponding data direction register bits to set the pins to output mode.

4.1 Input/output pr ogramming

The bidirectional port lines may be programmed as inputs or outputs under software control. The

direction of each pin is determined by the state of the corresponding bit in the port data direction

its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding

DDR bit is cleared to a logic zero.

At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data

direction registers can b e wr itten to or read by the MCU. During the programmed output state, a

read of the data register actually reads the value of the output data latch and not the I/O pin. The

operation of the standard port hardware is shown schematically in Figure 4-1.

Freescale

4-2 MC68HC05B6

Rev. 4.1

INPUT/OUTPUT PORTS

Table 4-1 shows the effect of reading from or writing to an I/O pin in vario us circumstance s. Note

that the read/write signal shown is internal and not available to the user.

4.2 Ports A and B

These por ts are standard M68HC 05 bidirectional I/O por ts, each compr ising a data register an d

a data direction register.

Reset does not affect the state of the data register, but clears the data direction register, thereby

retur ning all port pins to input mode. Wr iting a ‘1’ to any DDR bit sets the corresponding port pin

to output mode.

Figure 4-1 Standard I/O port structure

Table 4-1 I/O pin stat es

R/W DDRn Action of MCU write to/read of data bit

0 0 The I/O pin is in input mode. Data is written into the output data latch.

0 1 Data is written into the output data latch, and output to the I/O pin.

1 0 The state of the I/O pin is read.

1 1 The I/O pin is in output mode. The output data latch is read.

Latched data

DDRn

DATA

Input

buffer

Output

buffer

O/P

data

buffer

M68HC05 internal connections

DDRn DATA I/O Pin

100

111

0 0 tristate

0 1 tristate

I/O

Output





Input

Data direction









MC68HC05B6

Rev. 4.1 Freescale

4-3

INPUT/OUTPUT PORTS

4.3 Port C

In addition to the standard port functions described for port A and B, port C pin 2 can be

configured, using the ECLK bit of the EEPR OM/ECLK control register, to output the CPU clock. If

this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read

the output data latch. The other port C pins are not affected by this feature.

ECLK — External clock output bit

1 (set) – ECLK CPU clock is output on PC2.

0 (clear) – ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.

The ECLK bit is cleared by power-on or e xternal reset. It is not affected b y the ex ecution of a STOP

or WAIT instruction.

The timing diagram of the clock output is shown in Figure 4-2.

4.4 Port D

This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D

conv erter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D conv erter . Port D can

be read at any time, however, if it is read during an A/D conversion sequence noise, may be

injected on the analog inputs, resulting in redu ced accuracy of the A/D. Furthermore, performing

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000

Figure 4-2 ECLK timing diagram

Internal clock (PHI2)

External clock (ECLK/PC2)

Output port (if write to output port)

Freescale

4-4 MC68HC05B6

Rev. 4.1

INPUT/OUTPUT PORTS

a digital read of por t D with levels other than VDD or VSS on the por t D pins will result in greater

power dissipation during the read cycle.

As por t D is an input-on ly por t there is no DDR associated with it. Also, at power up or external

reset, the A/D converter is disabled, thus the port is configured as a standard inp ut-only port.

Note: It is recommended that all unused input por ts and I/O por ts be tied to an appropriate

logic level (i.e. either VDD or VSS).

4.5 Port registers

The following sections explain in detail the individual bits in the data and control registers

associated with the ports.

4.5.1 Port data registers A and B (PORTA and PORTB)

Each bit can be configured as input or output via th e corresponding data di rection bit in the por t

data direction register (DDRx).

The state of the port data registers following reset is not defined.

4.5.2 Port data register C (PORTC)

Each bit can be configured as input or output via th e corresponding data di rection bit in the por t

data direction register (DDRx).

In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM

CTL/ECLK regi st er is set (see Section 4.3).

The state of the port data registers following reset is not defined.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port C data (PORTC) $0002 PC2/

ECLK Undefined

MC68HC05B6

Rev. 4.1 Freescale

4-5

INPUT/OUTPUT PORTS

4.5.3 Port data register D (PORTD)

All the port D bits are input-only and are shared with the A/D converter . The function of each bit is

determined by the ADON bit in the A/D status/contro l register.

The state of the port data registers following reset is not defined.

4.5.3.1 A/D status/control register

ADON — A/D converter on

1 (set) – A/D converter is switched on; all port D pins act as analog inputs for

the A/D conv erter.

0 (clear) – A/D converter is switched off; all port D pins act as input only pins.

Reset clears the ADON bit, thus configuring port D as an input only port.

4.5.4 Data direction registers (DDRA, DDRB and DDRC)

Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing an y

bit to ‘0’ configures the corresponding port pin as an input.

Reset clears these registers, thus configuring all ports as inputs.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

A/D status/control $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

Freescale

4-6 MC68HC05B6

Rev. 4.1

INPUT/OUTPUT PORTS

4.6 Other port considerations

All output ports can emulate ‘open-dr ain’ outputs . This is achie ved b y writing a zero to the relev ant

output por t latch. By toggling the corresponding data direction bit, the port pin will either be an

output zero or tri-state (an input). This is shown diagrammat i c al l y in Figure 4-3.

When using a por t pin as an ‘open-drain’ output, certain precautions must be taken in the user

software. If a read-modify-write instruction is used on a por t where the ‘open-drain’ is assigned

and the pin at this time is progr ammed as an input, it will read it as a ‘one’. The read-modify-write

instruction will then write this ‘one’ into the output data latch on the next cycle. This would cause

the ‘open-drain’ pin not to output a ‘zero’ when desired.

Note: ‘Open-drain’ outputs should not be pulled above VDD.

Figure 4- 3 Port logic le vels

DDRn A Y

(b)

100

Normal operation – tri state

111

00tri state

01tri state

10low

‘Open-drain’

11—

0 0 high

0 1 high

















Read buffer output

Data direction register bit DDRn

Px0

VDD

DDRx, bit 0 = 0

Portx, bit 0 = 0

DDRx, bit 0 = 0

Portx, bit 0 = 0

(c)

(a)

‘Open-drain’ output

MC68HC05B6

Rev. 4.1 Freescale

5-1

PROGRAMMABLE TIMER

The programmable timer on the MC68HC05B6 consists of a 16-bit read-only free-running counter,

with a fixed divide-by-f our prescaler , plus the input capture/output compare circuitry. The timer can

be used for many purposes including measuring pulse length of two input signals and generating

two output signals. Pulse lengths for both input and output signals can vary from several

microseconds to many seconds. In addition, it works in conjunction with the pulse length

modulation (PLM) system, which can also be referred to as the pulse width modulation system, to

exe cute two 8-bit D/A PLM (pulse length modulati on) conversions, with a choice of two repetition

rates. The timer is also capable of generating periodic interrupts or indicating passage of an

arbitrary multiple of four CPU cycles . A bloc k diagram is shown in Figure 5-1, and timing diagrams

are shown in Figure 5-2, Figure 5-3, Figure 5-4 and Figure 5-5.

The timer has a 16-bit architecture, hence each specific functional segment is represented by two

8-bit registers (e xcept the PLMA and PLMB which use one 8-bit register for each). These registers

contain the high and low byte of that functional segment. Accessing the low b yte of a specific timer

function allows full control of that function; howe ver , an access of the high byte inhibits that specific

timer function until the low byte is also accessed.

The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full

details of which are contained in this section.

Note: A problem may arise if an interr upt occurs in the time between the high and low bytes

being accessed. To prevent this, the I-bit in the condition code register (CCR) should be

set while manipulating both the high and low byte register of a sp ecific timer funct ion,

ensuring that an interrupt does not occur.

5.1 Counter

The key element in the p rogrammable timer is a 16-b it, free-running counter or counter register,

preceded by a prescaler that divides the internal processor clock by f our. The prescaler gives the

timer a resolution of 2µs if the internal bus clock is 2 MHz. The counter is incremented during the

low por tion of the internal bus clock. Software can read th e counter at any time without affecting

its value.

Freescale

5-2 MC68HC05B6

Rev. 4.1

PROGRAMMABLE TIMER

Figure 5-1 16-bit programmable timer block diagram

Internal

Internal bus

Output

compare

processor

clock

8-bit

buffer

÷4

High Low

16-bit

free-running

counter

Counter

alternate

Input capture

Internal timer bus

Overflow

detect

circuit

Edge

detect

TCAP1

TCMP2

TCMP1

Latch

compare

Output

Input capture

byte byte

High

byte

Low

byte

High

byte

Low

byte

High

byte

Low

byte

Low

byte

High

byte

circuit 1

compare

Output

circuit 2

compare

Output

circuit 1

Edge

detect

circuit 2

TCAP2

Latch

76543Timer status

Timer control

$0013

$0012

$0018

$0019

$001A

$001B

$001C

$0016

$0017

$0014

$0015

$001E

$001F $001D

To PLM

ICF1 OCF1 TOF ICF2 OCF2

ICIE OCIE TOIE FOLV2 OLVL2 IEDG1 OLVL1FOLV1

Interrupt circuit

Input capture

interrupt

$1FF8,9

Output compare

interrupt

$1FF6,7

Overflow interrupt

$1FF4,5

COP watchdog

counter input

MC68HC05B6

Rev. 4.1 Freescale

5-3

PROGRAMMABLE TIMER

5.1.1 Counter register and alternate counter register

The double-b yte, free-running counter can be read from either of two locations, $18-$19 (counter

of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read

of the free-run ning counter or alter n ate counter register first addresses the more significant byte

(MSB) ($18 or $1A), the LSB is tr ansfe rred to a buff er . This b uffer v alue remains fix ed after the first

MSB read, even if the user reads the MSB several times. This buffer is accessed when reading

the free-running cou nter or alternate co unter register LSB and thus completes a read sequence

of the total counter value. In reading either the free-running counter or al ternate counter register,

if the MSB is read, the LSB must also be read to complete the sequence. If the timer o v erflow flag

(TOF) is set when the counter regi ster LSB is read then a read of the timer status reg ister (TSR)

will clear the flag.

The alternate counter register differs from the counter register only in that a read of the LSB does

not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow

interr upts due to clearing of TOF, the alternate counter register should be used.

The free-running counter is set to $FFFC during power-on and external reset and is always a

read-only register. During a power-on reset, the counter begins running after the oscillator start-up

delay. Because the free-r unning counter is 16 bits preceded by a fixed divide-by-4 prescaler, the

value in the free-running counter repeats ev ery 262,144 internal b us clock cycles. T OF is set when

the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.

In some par ticular timing control applicati ons it may be desirable to reset the 16-bit free running

counter under software control. When the low byte of the counter ($19 or $1B) i s written to, the

counter is configured to its reset value ($FFFC).

The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of

the flags and enable bits remain unaltered by this oper ation. If access has pre viously been made

to the high byte of the free-running counter ($18 or $1A), then the reset counter operation

ter minates the access sequence.

Warning: This operation may aff ect the function of the watchdog system (see Section 9.1.4). The

PLM results will also be affected while resetting the counter.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Freescale

5-4 MC68HC05B6

Rev. 4.1

PROGRAMMABLE TIMER

5.2 Timer control and status

The various functions of the timer are monitored and controlled using the timer control and status

registers described below.

5.2.1 Timer control register (TCR)

The timer control register ($0012) is used to enable the input captures (ICIE), output compares

(OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and

FOLV2), selectin g input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).

ICIE — Input captures interrupt enable

If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the timer

status register) is set.

1 (set) – Interrupt enabled.

0 (clear) – Interrupt disabled.

OCIE — Output compares interrupt enable

If this bit is set, a timer interrupt is enabled whenev er the OCF1 or OCF2 status flag (in the timer

status register) is set.

1 (set) – Interrupt enabled.

0 (clear) – Interrupt disabled.

TOIE — Timer overflow interrupt enable

If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status

1 (set) – Interrupt enabled.

0 (clear) – Interrupt disabled.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

MC68HC05B6

Rev. 4.1 Freescale

5-5

PROGRAMMABLE TIMER

FOLV2 — Force output compare 2

This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position

will force the OLV2 bit to the corresponding output le vel latch, thus appearing at the TCMP2 pin. Note

that this bit does not affect the OCF2 bit of the status register (see Section 5.4.3).

1 (set) – OLV2 bit forced to output level latch.

0 (clear) – No effect.

FOLV1 — Force output compare 1

This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position

will force the OLV1 bit to the corresponding output le vel latch, thus appearing at the TCMP1 pin. Note

that this bit does not affect the OCF1 bit of the status register (see Section 5.4.3).

1 (set) – OLV1 bit forced to output level latch.

0 (clear) – No effect.

OLV2 — Output level 2

When OLV2 is set a high output level will be clocked into the output level register by the next

successful output compare, and will a ppear on the TCMP2 p in. When clear, it will be a low level

which will appear on the TCMP2 pin.

1 (set) – A high output level will appear on the TCMP2 pin.

0 (clear) – A low output level will appear on the TCMP2 pin.

IEDG1 — Input edg e 1

When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the

free-running counter value to the input capture register 1. When clear, a negative-going edge

triggers the transf er.

1 (set) – TCAP1 is positive-going edge sensitive.

0 (clear) – TCAP1 is negative-going edge sensitive.

Note: There is no need for an equivalent bit for the input capture register 2 as TCAP2 is

negative-going edge sensitive only.

OLV1 — Output level 1

When OLV1 is set a high output level will be clocked into the output level register by the next

successful output compare, and will a ppear on the TCMP1 p in. When clear, it will be a low level

which will appear on the TCMP1 pin.

1 (set) – A high output level will appear on the TCMP1 pin.

0 (clear) – A low output level will appear on the TCMP1 pin.

Freescale

5-6 MC68HC05B6

Rev. 4.1

PROGRAMMABLE TIMER

5.2.2 Timer status register (TSR)

The timer sta tus register ($13) is a read only re gister an d contains the status bits correspon ding

to the four timer interrupt conditions – ICF1,OCF1, TOF, ICF2 and OCF2.

Accessing the timer status register satisfies the first condition required to clear the status bits. The

remaining step is to access the register corresponding to the status bit.

ICF1 — Input capture flag 1

This bit is set when the selected polarity of edge is detected by the input capture edge detector 1

at TCAP1; an input capture in terrupt will be generated, if ICIE is set. ICF1 is cl eared by reading

the TSR and then the input capture low register 1 ($15).

1 (set) – A valid input capture has occurred.

0 (clear) – No input capture has occurred.

OCF1 — Output compare flag 1

This bit is set when the output compare 1 register contents match those of the free-running

counter; an output compare interrupt will be gener ated if OCIE is set. OCF1 is cleared b y reading

the TSR and then reading or writing the output compare 1 low register ($17).

1 (set) – A valid output compare has occurred.

0 (clear) – No output compare has occurred.

TOF — Timer overflow status flag

This bit is set when the free-running counter ov erflows from $FFFF to $0000; a timer ov erflow interrupt

will occur if TOIE is set. TOF is cleared b y reading the TSR and the counter low register ($19).

1 (set) – Timer overflow has occurred.

0 (clear) – No timer overflow has occurred.

When using the time r overflow function and reading the free -r unning counter at rand om times to

measure an elapsed time , a problem ma y occur whereby the timer ov erflow flag is unintentionally

cleared if:

1 The timer status register is read or written when TOF is set, and

1) The LSB of the free-running counter is read, but not for the pur pose of

servicing the flag.

Reading the alternate counter register instead of the counter register will avoid this potential

problem.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

MC68HC05B6

Rev. 4.1 Freescale

5-7

PROGRAMMABLE TIMER

ICF2 — Input capture flag 2

This bit is set when a negative edge is detected by the input capture e dge detector 2 at TC AP2;

an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and

then the input capture low register 2 ($1D).

1 (set) – A valid (negative) input capture has occurred.

0 (clear) – No input capture has occurred.

OCF2 — Output compare flag 2

This bit is set when the output compare 2 register contents match those of the free-running

counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading

the TSR and then reading or wr iting the output compare 2 low register ($1F).

1 (set) – A valid output compare has occurred.

0 (clear) – No output compare has occurred.

5.3 Input capture

‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free

running coun ter. In this way it is possible to relate the timing of an external signal to the i nternal

counter value, and hence to elapsed time .

There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).

The same input capture interrupt enable bit (ICIE) is used for the two input captures.

5.3.1 Input capture register 1 (ICR1)

The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used

to latch the value of the free-running counter after the input capture edge detector circuit 1 senses

a valid transition at TCAP1. The lev el tr ansition that triggers the counter transfer is defined by the

input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag ICF1 in TSR is

set. An interrupt can also accompa ny an input capture 1 provided the ICIE bit in TCR is set. The

8 most significant bits are stored in the input capture high 1 register at $14, the 8 least significant

bits in the input capture low 1 register at $15.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Freescale

5-8 MC68HC05B6

Rev. 4.1

PROGRAMMABLE TIMER

The result obtained from an input capture will be one greater than the value of the free-running

counter on the rising edge of the internal bus clock preceding the e xternal transition. This delay is

required for internal synchronization. Resolution is one count of the free-running counter , which is

four internal bus clock cycles. The free-running counter contents are transferred to the input

capture register 1 on each valid signal transition whether the input cap ture 1 flag (ICF1) is set or

clear. The input capture register 1 always contains the free-running counter value that

corresponds to the most recent input capture 1. After a read of the inp ut capture 1 register MSB

($14), the counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes

the time used in the input capture software routine and its interaction with the main program to

deter mine the minimum pulse per iod. A read of the input capture 1 registe r LSB ($15) does not

inhibit the free-running counter transfer since the two actions occur on opposite edges of the

internal bus clock.

Reset does not affect the contents of the input capture 1 register , except when e xiting STOP mode

(see Section 5.6).

5.3.2 Input capture register 2 (ICR2)

The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used

to latch the value of the free-running counter after the input capture edge detector circuit 2 senses

a negative tr ansition at pin TCAP2. When an input capture 2 occurs, the corresponding flag ICF2

in TSR is set. An interrupt can also accompan y an input capture 2 provided the ICIE bit in TCR is

set.The 8 most significant bits are stor ed in the input capture 2 high regi ster at $1C, the 8 least

significant bits in the input capture 2 low register at $1D.

The result obtained from an input capture will be one greater than the value of the free-running

counter on the rising edge of the internal bus clock preceding the e xternal transition. This delay is

required for internal synchronization. Resolution is one count of the free-running counter , which is

four internal bus clock cycles. The free-running counter contents are transferred to the input

capture register 2 on each negative signal transition whether the input capture 2 flag (IC2F ) is set

or clear. The input capture register 2 always contains the free-running counter value that

corresponds to the most recent input capture 2. After a read of the inp ut capture register 2 MSB

($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes

the time used in the input capture software routine and its interaction with the main program to

deter mine the minimum pulse period. A read of the in put capture register 2 LSB ($1C) does not

inhibit the free-running counter transfer since the two actions occur on opposite edges of the

internal bus clock.

Reset does not affect the contents of the input capture 2 register , except when e xiting STOP mode

(see Section 5.6).

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

MC68HC05B6

Rev. 4.1 Freescale

5-9

PROGRAMMABLE TIMER

5.4 Output compare

‘Output compare’ is a technique which may be used, for example, to generate an output w avef orm,

or to signal when a specific time period has elapsed, by presetting the output compare register to

the appropriate value.

There are two output compare registers: output compare register 1 (OCR1) and output compare

Note: The same output compare interrupt enable bit (OCIE) is used for the two output

compares.

5.4.1 Output compare register 1 (OCR1)

The 16-bit output compare register 1 is made up of two 8-bit registers at locations $16 (MSB) and

$17 (LSB). The contents of the output comp are register 1 a re compared w ith the contents of the

free-running cou nter continually and, if a match is found, the corresponding output compare flag

(OCF1) in th e timer status re gister is set and the output leve l (OLVL1) is transf erred to pin TCMP1.

The output compare register 1 values and the output level bit should be changed after each

successful comparison to establish a new elapsed timeout. An interrupt can also accompany a

successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The

free-running counter is upda ted every four interna l bus clock cycles.)

After a processor write cycle to the output compare register 1 containing the MSB ($16), the output

compare function is inhi bited until the LSB ($17) is also written. Th e user must write both bytes

(locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare

1 function. The processor can write to either b yte of the output compare register 1 without affecting

the other byte . The output le v el (OLVL1) bit is cloc ked to the output lev el register and hence to the

TCMP1 pin whether the output compare flag 1 (OCF1) is set or clear. The minimum time required

to update the output compare register 1 is a function of the program rather than the internal

hardware. Because the output compare flag 1 and the ou tp ut compare regi ster 1 a re not defin ed

at power on, and not affected by reset, care must be taken when initializing output compare

functions with software. The f ollowing procedure is recommended:

– Write to output compare high 1 to inhibit further compares;

– Read the timer status register to clear OCF1 (if set);

– Write to output compare low 1 to enab le the output compare 1 function.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Freescale

5-10 MC68HC05B6

Rev. 4.1

PROGRAMMABLE TIMER

The purpose of this procedure is to prev ent the OCF1 bit from being set between the time it is read

and the write to the corresponding output compare register.

All bits of the o utput compare re gister are re adable and wr itable and are n ot altere d by the timer

hardware or reset. If the compare function is not needed, the two bytes of the output compare

5.4.2 Output compare register 2 (OCR2)

The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and

$1F (LSB). The contents of the output compare regi ster 2 are compar ed with the contents of the

free-runn ing counter continually and , if a match is found, the corresponding output co mpare flag

(OCF2) in the timer status register is set and the output lev el (OLVL2) is transferred to pin TCMP2.

The output compare register 2 values and the output level bit should be changed after each

successful comparison to establish a new elapsed timeout. An interrupt can also accompany a

successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The

free-running counter is updated every four internal bus clock cycles .)

After a processor write cycle to the output compare register 2 containing the MSB ($1E), the

output compare function is inhibited until the LSB ($1F) is also written . The user must write both

bytes (locations) if the MSB is written first. A wr ite made only to the LSB ($1F) will not inhi bit the

compare 2 function. The processor can write to either byte of the output compare register 2 without

affecting the other byte. The output level (OLVL2) bit is clocked to the output level register and

hence to the TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear . The minimum

time required to update the output compare register 2 is a function of the program rather than the

inter nal hardware. Because the output compare flag 2 and the output co mpare registe r 2 are not

defined at power on, and not affected by reset, care must be taken when initializing output

compare functions with software. The follo wing procedure is recommended:

– Write to output compare high 2 to inhibit further compares;

– Read the timer status register to clear OCF2 (if set);

– Write to output compare low 2 to enable the output compare 2 function.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

MC68HC05B6

Rev. 4.1 Freescale

5-11

PROGRAMMABLE TIMER

The purpose of this procedure is to pre vent the OCF1 bit from being set between the time it is read

and the wr ite to the corresponding output compare register.

All bits of the output compare register are readable and writable and are not altered by the timer

hardware or reset. If the compare function is not needed, the two bytes of the output compare

5.4.3 Software force compare

A software f orce compare is required in many applications. To achieve this, bit 3 (FOLV1 for OCR1)

and bit 4 (FOLV2 f or OCR2) in the timer control register are used. These bits alwa ys read as ‘zero’,

but a write to ‘one’ causes th e respective OLVL1 or OLVL2 values to be copied to the respective

output level (TCMP1 and TCMP2 pins).

Inter nal logic is arranged such that in a single instruction, o ne can change OLVL1 and/or OLVL2,

at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In

conjunction with normal compare, this function allows a wide range of applications including fixed

frequency generation.

Note: A software force compare will affect the corresponding output pin TCMP1 and/or

TCMP2, but will not affect the compare flag, thus it will not generate an interrupt.

5.5 Pulse Length Modulation (PLM)

The programmable timer w orks in conjunction with the PLM system to execute two 8-bit D/A PLM

conversions, with a choice of two repetition rates (see Section 7).

5.5.1 Pulse length modulation registers A and B (PLMA/PLMB)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Pulse length modulation A (PLMA) $000A 0000 0000

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Pulse length modulation B (PLMB) $000B 0000 0000

Freescale

5-12 MC68HC05B6

Rev. 4.1

PROGRAMMABLE TIMER

5.6 Timer during STOP mode

When the MCU enters STOP mode, the timer counter stops counting and remains at that

particular count value until STOP mode is exited by an interrupt. If STOP mode is exited by

power-on or external reset, the cou nter is forced to $FFFC but if it is exited by exter nal interr upt

(IRQ) then the counter resumes from its stopped value.

Another feature of the programmable timer is that if at least one valid input capture e dge occurs

at one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is

armed. This action does not wake the MCU or set any timer flags, but when the MCU does

wake-up there will be an active input capture flag (and data) from that first valid edge which

occurred during STOP mode.

If STOP mode is exited by an exter nal reset then no such in put capture flag or data action takes

place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.

5.7 Timer during WAIT mode

The timer system is not affected by WAIT mode and continues nor mal operation. Any valid timer

interrupt will wake-up the system.

5.8 Timer state diagrams

The relationships be tween the inte rnal clock signals, the counter contents and the sta tus of the

flag bits are sh own in the following figures. It should be noted that the signals labelled ‘inter nal’

(processor clock, timer clocks and reset) are not available to the user.

MC68HC05B6

Rev. 4.1 Freescale

5-13

PROGRAMMABLE TIMER

Figure 5-2 Timer state timing diagram for reset

Figure 5-3 Timer state timing diagram for input capture

Internal

processor clock

Internal

reset

16-bit

counter

External reset

or end of POR

Internal

timer clocks











$FFFC $FFFD $FFFE $FFFF

Note: The counter and timer control registers are the only ones affected by power-on or external reset.

T00

T01

T11

T10

Internal

processor clock

16-bit

counter $F123 $F124 $F125 $F126

Internal

timer clocks











T00

T01

T11

T10

Internal

capture latch

$F124$????

Input capture

flag

Input

edge

}

Note: If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then

the input capture flag will be set during the next T11 state.

Freescale

5-14 MC68HC05B6

Rev. 4.1

PROGRAMMABLE TIMER

Figure 5-4 Timer state timing diagram for output compare

Figure 5-5 Timer state timing diagram for timer overflow

Internal

processor clock

16-bit

counter $F456 $F457 $F458 $F459

Internal

timer clocks











T00

T01

T11

T10

$F457CPU writes $F457

Output compare

flag and TCMP1,2

Note: 1 The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state

T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.

1) The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this example).

Output compare

Compare register

latch

(Note 2)

(Note 1)

Internal

processor clock

16-bit

counter $FFFF $0000 $0001 $0002

Internal

timer clocks











T00

T01

T11

T10

Note: The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared

by a read of the timer status register during the internal processor clock high time, followed by a read of the

counter low register.

Timer overflow

flag

MC68HC05B6

Rev. 4.1 Freescale

6-1

SERIAL COMMUNICATIONS INTERFACE

A full-duplex asynchronous serial communications interface (SCI) is provided with a standard

non-return-to-zero (NRZ) f ormat and a variety of baud rates. The SCI transmitter and receiver are

functionally independent and have their o wn baud rate generator; however the y share a common

baud rate prescaler and data format.

The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data

bits, and one stop bit.

The SCLK pin is the output of the transmitter clock. It outputs the transmitter data clock for

synchronous transmission (no clocks on start bit and stop bit, and a softw are option to send clock

on last data bit). This allows control of peripherals containing shift registers (e.g. LCD drivers).

Phase and polarity of these clocks are software programmable.

Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and

transmit data out (TDO).

‘Baud’ and ‘bit rate’ are used synonymously in the following descripti on.

6.1 SCI two-wire system features

• Standard NRZ (mark/space) format

• Advanced error detection method with noise detection for noise duration of up to 1/16th bit time

• Full-duplex operation (simultaneous transmit and receive)

• 32 software selectable baud rates

• D ifferent baud rates for transmit and receive; for each transmit baud rate, 8 possible receive

baud rates

• So ftware selectable word length (eight or nine bits)

• Separate transmitter and receiver enable bits

• Capable of being interrupt driven

• Transmitter clocks available without altering the regular transmitte r or recei ver functions

• Four separate enable bits for interrupt control

Freescale

6-2 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

Figure 6-1 Serial communications interface block diagram

& & & &

Internal bus

SCI interrupt

Transmit Receive

TDO

RDI

Transmitter

control

Receiver

control

clock

Clock extraction

phase and

polarity control

Receiver

clock

Transmitter

Flag

control

data register data register

TIE

TCIE

RIE

ILIE

SBK

RWU

$000F

SCCR2

SCSR

$0010

SCCR1

$000E

TRDE TC RDRF IDLE OR NF FE

TE SBK

$0011

(See note) (See note)

R8 T8 M WAKE CPOL CPHA LBCL

012

765 2

SCLK

Wake up

unit

Receive

data shift

Transmit

data shift

$0011

Note: The serial communications data register (SCI SCDR) is controlled by the internal

R/W signal. It is the transmit data register when written to and the receive data

MC68HC05B6

Rev. 4.1 Freescale

6-3

SERIAL COMMUNICATIONS INTERFACE

6.2 SCI receiver features

• R eceiver wake-up function (idle line or address bit)

• Idle line detection

• Framing error detection

• Noise detection

• Overrun detection

• Receiver data register full flag

6.3 SCI transmitter features

• Transmit data register empty flag

• Transmit complete flag

• Send break

6.4 Functional description

A bloc k diagram of the SCI is shown in Figure 6-1. Option bits in serial control register1 (SCCR1)

select the ‘wake-up’ method (W AKE bit) and data word length (M-bit) of the SCI. SCCR2 provides

control bits that individually enable the transmitter and receiver, enable system interrupts and

provide the wak e-up enable bit (R WU) and the send break code bit (SBK). Control bits in the baud

rate register (BA UD) allo w the user to select one of 32 different baud rates f or the tr ansmitter and

receiver (see Section 6.11.5).

Data transmission is initiated by writing to the serial communications data register (SCDR).

Provided the transmitter is enabled, data stored in th e SCDR is transferred to the transmit data

shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI

status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The

transfer of data to the transmit data shift register is synchronized with the bit rate clock (see

Figure 6-2). All data is transmitted least significant bit first. Upon completion of data transmission,

the transmission complete flag (TC) in the SCSR is set (provided no pending data , preamble or

break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enab led). If

the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has

been sent, the TC bit will also be set. This will also generate an interrupt if the transmission

complete interrupt enable bit (TCI E) is set. If the tr ansmitter is disabl ed during a transmission, the

character being transmitted will be completed before the transmitter gives up control of the

TDO pin.

Freescale

6-4 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

When SCDR is read, it contains the last data byte received, pro vided that the receiver is enab led.

The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has

been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the

receiver interrupt is enabled. The data transfer from the input ser ial shift register to the SCDR is

synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error

flags in the SCSR may be set if data reception errors occurred.

An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects

idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to

detect the end of a message or the preamble of a new message, or to resynchronize with the

transmitter . A v alid character must be received before the idle line condition or the IDLE bit will not

be set and idle line interrupt will not be generated.

The SCP0 and SCP1 bits function as a prescaler for SCR0–SCR2 to generate the receiver baud rate

and for SCT0–SCT2 to generate the transmitter baud rate. Together , these eight bits provide multiple

transmitter/receiver rate combinations for a given crystal frequency (see Figure 6-2). This register

should only be written to while both the transmitter and receiv er are disab led (TE=0, RE=0).

Figure 6-2 SCI rate generator division

SCP1 SPC0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

Internal processor clock

SCP0 – SCP1

prescaler

rate control

(÷ NP)

SCR0 – SCR2

receiver

(÷ NR)

SCT0 – SCT2

transmitter

rate control

(÷ NT)

÷16

Transmitter clock Receiver clock

rate control

76543210

$000D

Baud rate register

Note: There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling).

This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can

be obtained.

MC68HC05B6

Rev. 4.1 Freescale

6-5

SERIAL COMMUNICATIONS INTERFACE

6.5 Data format

Receive data or transmit data is the serial data that is transf erred to the internal data b us from the

receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The

non-return-to-zero (NRZ) data format shown in Figure 6-3 is used and must meet the following

criteria:

– The idle line is brought to a logic one state prior to transmission/reception of

a character.

– A start bit (logic zero) is used to in dicate the start of a frame.

– The data is transmitted and received least significant bit first.

– A stop bit (logic one) is used to indicate the end of a frame. A frame consists

of a start bit, a character of eight or nine data bits, and a stop bit.

– A break is defined as the transmission or reception of a low (logic zero) for at

least one complete frame time (10 zeros for 8-bit f ormat, 11 z eros for 9-bit).

6.6 Receiver wake-up operation

The receiver logic hardware also supports a receiver wake-up function which is intended for

systems having more than one receiver . With this function a tr ansmitting de vice directs messages

to an individual receiver or group of receivers by passing addressing information as the initial

byte(s) of each message. The wake-up function allows receivers not addressed to remain in a

dorm ant state for the remainder of the unwanted message. This eliminates any furth er software

overhead to service the remaining characters of the unwanted message and thus improves

system perf ormance.

The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2

are inhibited (cannot become set). Note that the idle line detect function is inhibited while the R WU

bit is set. Although RWU ma y be cleared by a softw are write to SCCR2, it would be unusual to do

so. Normally RWU is set by software and is cleared automatically in hardware by one of the two

methods described below.

Figure 6-3 Data form at

StartStop

Control bit M selects

8 or 9 bit data

Start

Idle line 012345678







Freescale

6-6 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

6.6.1 Idle line wake-up

In idle line wake-up mode, a dor mant receiver wakes up as soon as the RDI lin e becomes idle.

Idle is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times.

Systems using this type of wake-up must provide at least one character time of idle between

messages to wake up sleeping receivers, but must not allow any idle time between characters

within a message.

6.6.2 Address mark wake-up

In address mark wak e-up , the most significant bit (MSB) in a character is used to indicate whether

it is an address (1 ) or data (0) character. Slee ping receivers will wake up whenever an address

character is received. Systems using this method for wake-up would set the MSB of the first

character of each message and leave it clear f or all other characters in the message. Idle periods

may be present within messages and no idle time is required between messages f or this wak e-up

method.

6.7 Receive data in (RDI)

Receive data is the serial data that is applied through the input line and the SCI to the internal bus.

The receiver circuitry cloc ks the input at a rate equal to 16 times the baud rate. This time is referred

to as the RT rate in Figure 6-4 and as the receiver clock in Figure 6-2.

The receiver clock generator is controlled by the baud rate register, as shown in Figure 6-1 and

Figure 6-2; however, the SCI is synchronized by the start bit, independent of the transmitter.

Once a valid star t bit is detected, the star t bit, each data bit and the stop bit are samp led three

times at RT intervals 8 RT, 9 RT and 10 R T (1 RT is the position where the bit is expected to start),

as shown in Figure 6-5. The value of the bit is determined by voting logic which takes the v alue of

the majority of the sa mp les. A noise flag is set w hen all th re e samples on a valid start bit or data

bit or the stop bit do not agree.

6.8 Start bit detection

When the input (idle) l ine is detected low, it is tested for three more sample time s (referred to as

the start edge verification samples in Figure 6-4). If at least two of these three verification samples

detect a logic zero, a v alid start bit has been detected, otherwise the line is assumed to be idle. A

noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit

could be assumed with a set noise flag present.

MC68HC05B6

Rev. 4.1 Freescale

6-7

SERIAL COMMUNICATIONS INTERFACE

If there has been a framing error without detection of a break (10 zeros f or 8 bit f ormat or 11 zeros

for 9 bit format), the circuit continues to operate as if there actually was a stop bi t, and the star t

edge will be placed artificially. The last bit received in the data shift register is inverted to a logic

one, and the three logic one start qualifiers (shown in Figure 6-4) are forced into the sample shift

the start bit will be accepted no sooner than it is anticipated.

Figure 6-4 SCI examples of start bit sampling technique

Figure 6-5 SCI sampling technique used on all bits

111 111 111110000

1RT 2RT 3RT 5RT 7RT4RT 6RT 8RT

Start

qualifiers

Idle

Start edge

verification samples

16X internal sampling clock

RT clock edges for all three examples

Noise

Start

111 111 1110 1 0000

111 111 1111 1 0010

Start

Noise

RDI

SamplesPresent bit Next bitPrevious bit

16RT 1RT 8RT 9RT 10RT 16RT 1RT

RDI

Freescale

6-8 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced

the framing error, the start bit will not be artificially induced and the receiver must actually detect

a logic one before the start bit can be recognised (see Figure 6-7).

6.9 Transmit data out (TDO)

Transmit data is the seria l data from the inter nal data bus that is applied through the SCI to the

output line. Data format is as discussed in Section 6.5 and shown in Figure 6-3. The transmitter

generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal

to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the

receiver and transmitter).

Figure 6-6 Artificial start following a framing error

Figure 6-7 SCI start bit following a break

Data Expected stop

Data samples

Artificial edge

Start bit

Data

RDI

Data Expected stop

Data samples

Start edge

Start bit

Data

RDI

a) Case 1: receive line low during artificial edge

b) Case 2: receive line high during expected start edge

Expected stop

Data samples

Detected as valid start edge

Start bit

RDI

Break









Start

qualifiers Start edge

verification

samples

MC68HC05B6

Rev. 4.1 Freescale

6-9

SERIAL COMMUNICATIONS INTERFACE

6.10 SCI synchronous transmission

The SCI transmitter allows the user to control a one way synchronous serial transmission. The

SCLK pin is the clock output of th e SCI transmitter. No clocks are sent to that pin during start bit

and stop bit. Dependin g on the state of the LBCL bit (bit 0 of SCC R1), clocks will or will not be

activated during the last valid data bit (address mark ). The CPOL b it (bit 2 of SCCR1) all ows the

user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the

phase of the external clock (see Figure 6-8, Figure 6-9 and Figure 6-10).

During idle, preamble and send break, the external SCLK clock is not activated.

These options allow the user to serially control peripherals which consist of shift registers , without

losing any functions of the SCI transmitter which can still talk to other SCI receivers . These options

do not affect the SCI receiver which is independent of the transmitter.

The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled

(TE = 0), the SCLK and TDO pins go to the high impedance state.

Note: The LBCL, CPOL an d CPHA bits have to be selected before enabling the transmitter

to ensure that the clocks function correctly. These bits should not be changed while the

transmitter is enabled.

Figure 6-8 SCI example of synchronous and asynchronous transmission

RDI

TDO

SCLK

Output port

Data out

Data in

Clock

Enable

Asynchronous

MC68HC05B6

(e.g. Modem)

Synchronous

(e.g. shift register,

display driver, etc.)

Freescale

6-10 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

6.11 SCI registers

The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR,

and BAUD.

6.11.1 Serial communications data register (SCDR)

The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts

as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it

is written. Figure 6-1 shows this register as two separate registers, RDR and TDR. The RDR

provides the interf ace from the receive shift register to the internal data bus and the TDR provides

the parallel interface from the internal data bus to the transmit shift register.

The receive data register is a read-only register containing the last b yte of data receiv ed from the

shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status

SCDR. The transfer is synchroni zed with the receiver bit rate clock (from the receiver control) as

shown in Figure 6-1. All data is received with the least significant bit first.

The transmit data register (TDR) is a write-only register containing the next byte of data to be

applied to the transmit shift register from the internal data bus. As long as the transmitter is

enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte

in the shift register has been transmitted).

The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as

shown in Figure 6-1. All data is received with the least significant bit first.

6.11.2 Serial communications control register 1 (SCCR1)

The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character

format, the receiver wake-up feature and the options to output the transmitter clocks for

synchronous transmissions.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI data (SCDR) $0011 0000 0000

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

MC68HC05B6

Rev. 4.1 Freescale

6-11

SERIAL COMMUNICATIONS INTERFACE

R8 — Receive data bit 8

This read-only bit is the ninth serial data bit received when the SCI system is configured for nine

data bit operation (M = 1). The most signi ficant bit (bit 8) of the received character is transferred

into this bit at th e same time as the re maining eight b its (bits 0–7 ) are transferred from the serial

receive shifter to the SCI receive data register.

T8 — Transmit data bit 8

This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine

data bit operation (M = 1). When the eight low order bits (bits 0–7) of a transmit character are

transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is

transferred to the ninth bit position of the shifter.

M — Mode (select character format)

The read/write M-bit controls the character length for both the transmitter and receiver at the same

time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity

bit (see Table 6-1).

1 (set) – Start bit, 9 data bits, 1 stop bit.

0 (clear) – Start bit, 8 data bi ts, 1 stop bit.

WAKE — Wake-up mode select

This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or

written to any time. See Table 6-1.

1 (set) – W ak e-up on address mark; if RWU is set, SCI will wak e-up if the 8th

(if M=0) or 9th (if M=1) bit received on the Rx line is set.

0 (clear) – W ake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M=0)

or 12 (if M=1) consecutive ‘1’s on the Rx line.

Table 6-1 Method of receiver wake-up

WAKE M Method of receiver wake-up

Detection of an idle line allows the next data type received to cause the receive

data register to fill and produce an RDRF flag.

Detection of a received one in the eighth data bit allows an RDRF flag and

associated error flags.

Detection of a received one in the ninth data bit allows an RDRF flag and

associated error flags.

x = Don’t care

Freescale

6-12 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

CPOL – Clock polarity

This bit allows the user to select the polar ity of the clocks to be sen t to the SCL K pin. It works in

conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-9 and

Figure 6-10).

1 (set) – Steady high value at SCLK pin outside transmission window.

0 (clear) – Steady low value at SCLK pin outside transmission window.

This bit should not be manipulated while the transmitter is enabled.

CPHA – Clock phase

This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works

in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 6-9 and

Figure 6-10).

1 (set) – SCLK clock line activated at beginning of data bit.

0 (clear) – SCLK clock line activated in middle of data bit.

This bit should not be manipulated while the transmitter is enabled.

Figure 6-9 SC I da t a clo ck timing diagram (M=0)

Idle or preceding

transmission

clock

Stop

Start

LSB

data

M = 0 (8 data bits)

Idle or next

LBCL bit controls last data clock

transmission

clock

Start Stop

0123456

MSB

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

MC68HC05B6

Rev. 4.1 Freescale

6-13

SERIAL COMMUNICATIONS INTERFACE

LBCL – Last bit clock

This bit allows the user to select whether the clock associated with the last data bit transmitted

(MSB) has to be output to the SCLK pin. The cloc k of the last data bit is output to the SCLK pin if

the LBCL bit is a logic one, and is not output if it is a logic zero.

The last bit is the 8th or 9th d ata bit transmitted depending on th e 8 or 9 bit form at selected by

M-bit (seeTable 6-2).

This bit should not be manipulated while the transmitter is enabled.

Figure 6-10 SCI data clock timing diag r a m (M= 1)

Table 6 - 2 SCI clock on SCLK pin

Data format M-bit LBCL bit Number of clocks on

SCLK pin

8 bit 0 0 7

8 bit 0 1 8

9 bit 1 0 8

9 bit 1 1 9

Idle or preceding

transmission

clock

StopStart

LSB

data

M = 1 (9 data bits)

Idle or next

LBCL bit controls last data clock

transmission

clock

Start Stop

0123456

MSB

(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)

(CPOL = 1, CPHA = 0)

(CPOL = 1, CPHA = 1)

Freescale

6-14 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

6.11.3 Serial communications control register 2 (SCCR2)

The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI

functions.

TIE — Tr ansmit interrupt enable

1 (set) – TDRE interrupts enabled.

0 (clear) – TDRE interrupts disabled.

TCIE — Transmit complete interrupt enable

1 (set) – TC interr upts enabled.

0 (clear) – TC interrupts disabled.

RIE — Receiver interrupt enable

1 (set) – RDRF and OR interrupts enabled.

0 (clear) – RDR F and OR interrupts disabled.

ILIE — Idle line interrupt enable

1 (set) – IDLE interrupts enabled.

0 (clear) – IDLE interrupts disabled.

TE — Transmitter enable

When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and

the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M

(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) con secutive ones is transmitted when software

sets the TE bit from a cleared state.

If a transmission is in progress and a zero is writte n to TE, the transmitter will wait unti l after the

present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high

impedance state.

If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,

the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new

preamble. After this latest transmission, and provided the TDRE bit is set (no new data to

transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs.

This function allows the user to neatly terminate a transmission sequence.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI control (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

MC68HC05B6

Rev. 4.1 Freescale

6-15

SERIAL COMMUNICATIONS INTERFACE

After loading the last byte in the serial communications data register and receiving the TDRE flag,

the user should clear TE. Transmission of the last byte will then be completed and the line will go

idle.

1 (set) – Transmitter enabled.

0 (clear) – Transmitter disabled.

RE — Receiver enable

1 (set) – Receiver enabled.

0 (clear) – Receiver disabled.

When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,

OR, NF and FE) are inhibited.

RWU — Receiver wake-up

When the receiver wak e-up bit is set b y the user software, it puts the receiver to sleep and enables

the wake-up function. The typ e of wake-up mode for the receiver is determined by the WAKE bit

discussed above (in the SCCR1). When the R WU bit is set, no status flags will be set. Flags which

were set pre viously will not be cleared when RWU is set.

If the W A KE bit is cleared, R WU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)

consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is

set, R WU is cleared after receiving an address bit. The RDRF flag will then be set and the address

byte stored in the receiver data register.

SBK — Send break

If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1)

zeros and then reverts to idle sending data. If SBK remains set, the transmitter will continually

send whole blocks of zeros (sets of 10 or 11) until cleared. At the comp letion of the break code,

the transmitter sends at least one high bit to guarantee recognition of a valid start bit.

Freescale

6-16 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

6.11.4 Serial communications status register (SCSR)

The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for

generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also

contained in the SCSR.

TDRE — Transmit data register empty flag

This bit is set when the contents of the transmit data register are transferred to the serial shift

transmit data register to clear the TDRE flag.

If the TDRE bit is clear , this indicates that the transfer has not y et occurred and a write to the serial

communications data register will overwrite the previous value. The TDRE bit is cleared by

accessing the serial communications status register (with TDRE set) followed by writing to the

serial communications data register.

TC — Transmit complete flag

This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no

data in shifter, no preamble, no break). When TC is set the serial line will go idle (continuous

MARK). The TC bit is cleared by accessing the serial communications status register (with TC set)

followed by writing to the serial communications data register. It does not inhibit the transmitter

function in any way.

RDRF — Receive data register full flag

This bit is set when the contents of the receiver serial shift register are transferred to the receiver

data register.

If multiple errors are detected in any one received word, the NF and RDRF bits will be aff ected as

appropriate during the same cloc k cycle. The RDRF bit is cleared when the serial communications

status register is accessed (with RDRF set) followed by a read of the serial communications data

IDLE — Idle line detected flag

This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven

consecutive “1”s). This bit will not be set by the idle line condition when the RWU bit is set. This

allows a receiver that is not in the wake-up mode to detect the end of a message, detect the

preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by

accessing the serial communications status register (with IDLE set) followed by a read of the serial

communications data register . Once cleared, IDLE will not be set again until after RDRF has been

set, (i.e. until after the line has been active and becomes idle again).

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

MC68HC05B6

Rev. 4.1 Freescale

6-17

SERIAL COMMUNICATIONS INTERFACE

OR — Overrun error flag

This bit is set when a new byte is ready to be transferred from the receiver shift register to the

receiver data register and the receive data register is already full (RDRF bit is set). Data transfer

is inhibited until the RDRF bit is cleared. Data in the se rial communications data register is valid

in this case, but additional data received during an overr un condition (including the byte causing

the overrun) will be lost.

The OR bit is cleared when the ser ial communications status registe r is accessed (with OR set)

followed by a read of the serial communications data register.

NF — Noise error flag

This bit is set if there is noise on a ‘valid’ start bit, any of the data bits or on the stop b it. The NF

bit is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set

until the RDRF flag is set. Each data bit is sampled three times as described in Section 6.7.

The NF bit represents the status of the byte in the serial communications data register. For the

byte being received (shifted in) there will be also a ‘wor king ’ noise flag, the value of which will be

transferred to the NF bit when the serial data is loaded into the serial communications data

can be used to generate the interrupt.

The NF bit is cleared when th e serial communications status register is accessed (with NF set)

followed by a read of the serial communications data register.

FE — Framing err or fla g

This bit is set when the word boundar ie s in the b it stream are not synchronized with the receiver

bit counter (generated by the reception of a logic z ero bit wher e a sto p b it w a s expected). The FE

bit reflects the status of the byte in the receive data register and the transfer from the receive shifter

to the receive data register is inhibited by an overrun. The FE bit is set during the same cycle as

the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag inhibits

further transfer of data into the receive data register until it is cleared.

The FE bit is cleared when the serial communications status register is accessed (with FE set)

followed by a read of the serial communications data register.

Freescale

6-18 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

6.11.5 Baud rate register (BAUD)

The baud rate register provides the means to select two different or equivalent baud rates for the

transmitter and receiver.

SCP1, SCP0 — Serial prescaler select bits

These read/wr ite bits deter mine the prescale factor, NP, by which the internal processor clock is

divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This

common prescaled output is used as the i nput to a divider that is contro lled by the SCR0–SCR2

bits for the SCI receiver, and by the SCT0–SCT2 bits for the transmitter.

SCT2, SCT1,SCT0 — SCI rate sele ct bi ts (transmitter)

These three read/write bits select the baud rates f or the transmitter. The prescaler output is divided

by the factors shown in Table 6-4.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

SCI baud rate (BAUD) $000D SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 00uu uuuu

Table 6-3 First prescaler stage

SCP1 SCP0 Prescaler

division ratio (NP)

00 1

01 3

10 4

11 13

Table 6-4 Second prescaler stage (transmitter)

SCT2 SCT1 SCT0 Transmitter

division ratio (NT)

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

MC68HC05B6

Rev. 4.1 Freescale

6-19

SERIAL COMMUNICATIONS INTERFACE

SCR2, SCR1, SCR0 — SCI rate select bits (receiver)

These three read/write bits select the baud rates for the receiver. The prescaler output described

above is divided by the factors shown in Table 6-5.

The following equations are used to calculate the receiver and transmitter baud rates:

where:

NP = prescaler divide ratio

NT = transmitter baud rate divide ratio

NR = receiver baud rate divide ratio

baudTx = transmitter baud ra te

baudRx = receiver baud rate

fOSC = oscillator frequency

6.12 Baud rate selection

The flexibility of the baud rate generator allows many different baud rates to be selected. A

particular baud rate may be generated in se v er al w ays b y manipulating the various prescaler and

division ratio bits. Table 6-6 shows the baud rates that can be achieved, for five typical crystal

frequencies. These are effectively the highest baud rates which can be achieved using a given

crystal.

Table 6-5 Second prescaler stage (receiver)

SCR2 SCR1 SCR0 Receiver

division ratio (NR)

000 1

001 2

010 4

011 8

100 16

101 32

110 64

1 1 1 128

baudTx fop

16 NP NT••

-----------------------------------

baudRx fop

16 NP NR••

-----------------------------------

Freescale

6-20 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

Note: The examples sho wn abov e do not apply when the part is operating in slow mode (see

Section 2.4.3).

Table 6-6 SCI baud rate selection

Crystal frequency – fOSC (MHz)

SCP1 SCP0 SCT/R2 SCT/R1 SCT/R0 NP NT/NR 4.194304 4.00 2.4576 2.00 1.8432

0 0 0 0 0 1 1 131072 125000 76800 62500 57600

0 0 0 0 1 1 2 65536 62500 38400 31250 28800

0 0 0 1 0 1 4 32768 31250 19200 15625 14400

0 0 0 1 1 1 8 16384 15625 9600 7813 7200

0 0 1 0 0 1 16 8192 7813 4800 3906 3600

0 0 1 0 1 1 32 4096 3906 2400 1953 1800

0 0 1 1 0 1 64 2048 1953 1200 977 900

0 0 1 1 1 1 128 1024 977 600 488 450

0 1 0 0 0 3 1 43691 41667 25600 20833 19200

0 1 0 0 1 3 2 21845 20833 12800 10417 9600

0 1 0 1 0 3 4 10923 10417 6400 5208 4800

0 1 0 1 1 3 8 5461 5208 3200 2604 2400

0 1 1 0 0 3 16 2731 2604 1600 1302 1200

0 1 1 0 1 3 32 1365 1302 800 651 600

0 1 1 1 0 3 64 683 651 400 326 300

0 1 1 1 1 3 128 341 326 200 163 150

1 0 0 0 0 4 1 32768 31250 19200 15625 14400

1 0 0 0 1 4 2 16384 15625 9600 7813 7200

1 0 0 1 0 4 4 8192 7813 4800 3906 3600

1 0 0 1 1 4 8 4096 3906 2400 1953 1800

1 0 1 0 0 4 16 2048 1953 1200 977 900

1 0 1 0 1 4 32 1024 977 600 488 450

1 0 1 1 0 4 64 512 488 300 244 225

1 0 1 1 1 4 128 256 244 150 122 113

1 1 0 0 0 13 1 10082 9615 5908 4808 4431

1 1 0 0 1 13 2 5041 4808 2954 2404 2215

1 1 0 1 0 13 4 2521 2404 1477 1202 1108

1 1 0 1 1 13 8 1260 1202 738 601 554

1 1 1 0 0 13 16 630 601 369 300 277

1 1 1 0 1 13 32 315 300 185 150 138

1 1 1 1 0 13 64 158 150 92 75 69

111111312879 75 46 38 35

MC68HC05B6

Rev. 4.1 Freescale

6-21

SERIAL COMMUNICATIONS INTERFACE

6.13 SCI during STOP mode

When the MCU ente rs STOP mode, the bau d rate generator dr iving the rece iver and transmitter

is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to

operate.

If the STOP instruction is executed during a transmitter transfer, that transfer is halted. When

STOP mode is exited as a result of an external interrupt, that particular transmission resumes.

If the receiver is receiving data when the STOP instruction is ex ecuted, receiv ed data sampling is

stopped (baud generator stops) and the rest of the data is lost.

Warning: For the abo ve reasons, all SCI transactions should be in the idle state when the STOP

instruction is executed.

6.14 SCI during WAIT mode

The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI

interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering

WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial

communication control register 2 at $000F. This action will result in a reduction of power

consumption dur ing WAIT mode.

Freescale

6-22 MC68HC05B6

Rev. 4.1

SERIAL COMMUNICATIONS INTERFA CE

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6

Rev. 4.1 Freescale

7-1

PULSE LENGTH D/A CONVERTERS

The pulse length D/A conver ter (PLM) system works in conjunction with the time r to execute two

8-bit D/A conversions, with a choice of two repetition rates. (See Figure 7-1.)

Figure 7-1 PLM system block diagram

PLMA

PLMB

‘A’ register

buffer

‘B’ register

‘A’

comparator

‘B’

Latch

Zero detector

SFA

bit

SFB

D/A

Timer bus From timer

multiplexer

‘A’ ‘B’

buffer

comparator

multiplexer

PLMA

PLMB

D/A

bit

Zero detector

Latch

Freescale

7-2 MC68HC05B6

Rev. 4.1

PULSE LENGTH D/A CONVERTERS

The D/A conv erter has two data r eg isters associated with it, PLMA and PLMB.

This is a dual 8- bit resolution D/A converter associated with two output pins (PLMA and PL MB).

The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These

signals can be used directly as PLMs, or the filtered average may be used as general purpose

analog outputs.

The longest repetition period is 4096 times the programmable timer clock period (CPU clock

multiplied by four), and the sho r test repetition per iod is 256 times the programmable timer clock

period (the repetiti on rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).

Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two

counters. A value of $00 loaded into these registers results in a continuously low output on the

corresponding D/A output pin. A va lue of $80 results in a 50% duty cycle output, and so on, to the

maximum v alue $FF corresponding to an output which is at ‘1’ f or 255/256 of the cycle. When the

MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A

conv erters at the end of a complete cycle of con version. This results in a monotonic change of the

DC component at the output without overshoots or vicious starts (a vicious start is an output which

gives totally erroneous PLM during the period immediately following an update of the PLM D/A

registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of

PWM output waveforms are shown in Figure 7-2.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Figure 7-2 PLM output wavef orm examples

256 T

255 T

128 T

$80

$FF

T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode

128 T

$00

$01

255 T

MC68HC05B6

Rev. 4.1 Freescale

7-3

PULSE LENGTH D/A CONVERTERS

Note: Since the PLM system uses the timer counter , PLM results will be affected while resetting

the timer counter. Both D/A registers are reset to $00 dur ing power-on or external reset.

WAIT mode does not affe ct the output wa v eform of the D/A conv erters .

7.1 Miscellaneous register

SFA — Slow or fast mode selection for PLMA

This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation

output.

1 (set) – Slow mode PLMA (4096 x timer clock period).

0 (clear) – Fast mode PLMA (256 x timer clock period).

SFB — Slow or fast mode selection for PLMB

This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation

output.

1 (set) – Slow mode PLMB (4096 x timer clock period).

0 (clear) – Fast mode PLMB (256 x timer clock period).

The highest speed of the PLM system corresponds to the frequency of the TOF bit being set,

multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF

bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is

mandatory to set them to the desired v alues before writing to the PLM registers; not doing so could

temporarily give incorrect values at the PLM outputs.

SM — Slow mode

1 (set) – The system runs at a bus speed 16 times lower than normal

(fOSC/32). SLOW mode affects all sections of the device, including

SCI, A/D and timer.

0 (clear) – The system runs at normal bus speed (fOSC/2).

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?

Freescale

7-4 MC68HC05B6

Rev. 4.1

PULSE LENGTH D/A CONVERTERS

The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when

entering STOP mode.

Note: The bits that are shown shaded in th e a b ove representation are explained individual ly

in the relevant sections of this manual. The complete register plus an explanation of

each bit can be found in Section 3.8

7.2 PLM clock selection

The slow/f ast mode of the PLM D/A conv erters is selected by bits 1, 2, and 3 of the miscellaneous

effect on the D/A conver ters’ 8-bit resolution (see Figure 7-3).

7.3 PLM during STOP mode

On enter ing STOP mode, the PLM outputs remain at their par ticular level. When STOP mode is

exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by

power-on or external reset the registers values are forced to $00.

7.4 PLM during WAIT mode

The PLM system is not affected by WAIT mode and continues normal operation.

Figure 7-3 PLM clock selection

fOSC ÷2

÷32

SM bit = 0

SM bit = 1

÷4x4096

x256

SF bit = 1

SF bit = 0

Timer

clock PLM

clock

Bus

frequency (fOP)

MC68HC05B6

Rev. 4.1 Freescale

8-1

ANALOG TO DIGITAL CONVERTER

The analog to digital converter system consists of a single 8-bit successive approximation

converter and a sixteen channel multiplexer. Eight of the channels are connected to the

PD0/AN0 – PD7/AN7 pins of the MC68HC05B6 and the other eight channels are dedicated to

internal ref erence points f or test functions. The channel input pins do not hav e an y internal output

driver circuitry connected to them because such circuitry would load the analog input signals due

to output buff er leakage current. There is one 8-bit result data register (address $08) and one 8-bit

status/control register (address $09).

The A/D conver ter is ratiometric and two dedi cated pins, VRH and VRL, a re used to supply the

reference voltage levels for all analog inputs. These pins are used in preference to the system

power supply lines because any voltage drops in the bonding wires of th e heavily loaded supply

pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than

VRH converts to $FF (full scale) with no overflow indication and an input voltage equal to VRL

converts to $00.

The A/D converter can operate from either the bus clock or an internal RC type oscillator. The

internal RC type oscilla tor is activated by the ADRC bit in the A/D status/control register (ADSTAT)

and can be used to give a sufficiently high clock r ate to the A/D conv erter when the bus speed is too

low to provide accurate results. When the A/D converter is not being used it can be disconnected,

by clearing the ADON bit in the ADSTAT register, in order to sa ve power (see Section 8.2.3).

For further information on A/D converter operation please refer to the M68HC11 Reference

Manual — M68HC11RM/AD.

8.1 A/D converter operation

The A/D converter consists of an analog multiple xer, an 8-bit digital to analog converter capacitor

array, a comparator and a successive approximation register (SAR) (see Figure 8-1).

There are eleven options that can be selected by the multiplexer; AN0–AN7, VRH, (VRH+VRL)/2

or VRL. Selection is done via th e CHx bi ts in the ADSTAT re gister (see Section 8.2.3). AN0–AN7

are the only input points for A/D conversion operations; the others are reference points that can

be used for test purposes.

Freescale

8-2 MC68HC05B6

Rev. 4.1

ANALOG TO DIGITAL CONVERTER

The A/D reference input (AN0–AN7) is applied to a precision internal D/A conv erter . Control logic

drives this D/A conver ter and the analog output is successively compared with the analog input

sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.

The result of each successive comparison is stored in the SAR and, when the conversion is

complete, the contents of the SAR are transferred to the read-only result data register ($08), and

the conversion complete flag, COCO, is set in the A/D status/control register ($09).

Warning: Any write to the A/D status/control register will abor t the current conversion, reset the

conversion complete flag and start a new conversion on the selected channel.

At power-on or e xternal reset, both the ADRC and ADON bits are cleared; thus the A/D is disab led.

Figure 8-1 A/D converter block diagram

AN0

VRH

(VRH+VRL)/2

VRL

Analog MUX

A/D result register (ADDATA) $08

8-bit capacitive DAC

with sample and hold

VRH

VRL

Result

A/D status/control register (ADSTAT)$09

(Channel assignment)

COCO

ADRCADON0CH3CH2CH1CH0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Successive approximation

MC68HC05B6

Rev. 4.1 Freescale

8-3

ANALOG TO DIGITAL CONVERTER

8.2 A/D registers

8.2.1 Port D data register (PORTD)

Por t D is an input-only por t which routes the eight analog inputs to the A/D conver ter. When the

A/D conver ter is di sa bled, the pins are configured as standard inp ut-only port pins, which can be

read via the port D data register.

Note: When the A/D function is enabled, pins PD0–PD7 will act as analog inputs. Using a pin

or pins as A/D inputs does not aff ect the ability to read port D as static inputs; ho we v er ,

reading port D during an A/D conversion sequence may inject noise on the analog

inputs and result in reduced accuracy of the A/D result.

Performing a digital read of por t D with levels other than VDD or VSS on the pins will

result in greater power dissipation during the read cycle, and may give unpredictable

results on the corresponding port D pins.

8.2.2 A/D result data register (ADDATA)

ADDATA is a read-only register which is used to store the results of A/D conv ersions. Each result

is loaded into the register from the SAR and the conv ersion complete flag, COCO, in the ADSTAT

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

A/D data (ADDATA) $0008 0000 0000

Freescale

8-4 MC68HC05B6

Rev. 4.1

ANALOG TO DIGITAL CONVERTER

8.2.3 A/D status/control register (ADSTAT)

COCO — Conversion complete flag

1 (set) – COCO is set each time a conversion is complete, allowing the new

result to be read from the A/D result data register ($08). The

converter then starts a new conversion.

0 (clear) – COCO is cleared by reading the result data register or writing to the

status/control register.

Reset clears the COCO flag.

ADRC — A/D RC oscillator control

The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a

sufficiently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds.

1 (set) – When the ADRC bit is set, the A/D RC oscillator is turned on and, if

ADON is set, the A/D runs from the RC oscillator c loc k. See Table 8-1.

0 (clear) – Wh en the ADRC bit is cleared, the A/D RC oscillator is turned-off

and, if ADON is set, the A/D runs from the CPU clock.

When the A/D RC oscillator is turned on, it takes a time tADRC to stabilize (see Table 11-6 and

Table 11-7). During this time A/D conversion results ma y be inaccurate.

Note: If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on.

Power-on or external reset clears the ADRC bi t .

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Table 8-1 A/D clock selection

ADRC ADON RC

oscillator

A/D

converter Comments

0 0 OFF OFF A/D switched off.

0 1 OFF ON A/D using CPU clock.

1 0 ON OFF Allows the RC oscillator to stabilize.

1 1 ON ON A/D using RC oscillator clock.

MC68HC05B6

Rev. 4.1 Freescale

8-5

ANALOG TO DIGITAL CONVERTER

ADON — A/D converter on

The ADON bit allows the user to enable/disable the A/D converter.

1 (set) – A/D converter is switched on.

0 (clear) – A/D converter is switched off.

When the A/D converter is switched on, it takes a time tADON for the current sources to stabilize

(see Table 11-6 and Table 11-7). Using the A/D converter before this time has elapsed may result

in the incorrect operation of the A/D , e v en after tADON has elapsed. In this case AD ON would ha v e

to be cleared and set again.

Power-on or external reset will clear the ADON bit, thus disabling the A/D converter.

CH3–CH0 — A/D channels 3, 2, 1 and 0

The CH3–CH0 bits allow the user to determine which channel of the A/D conver ter multiplexer is

selected. See Table 8-2 for channel selection.

Reset clears the CH0–CH3 bits.

Table 8-2 A/D channel assignment

CH3 CH2 CH1 CH0 Channel selected

0000 AN0

0001 AN1

0010 AN2

0011 AN3

0100 AN4

0101 AN5

0110 AN6

0111 AN7

1 0 0 0 VRH pin (high)

1001 (VRH + VRL) / 2

1 0 1 0 VRL pin (low)

1 0 1 1 VRL pin (low)

1 1 0 0 VRL pin (low)

1 1 0 1 VRL pin (low)

1 1 1 0 VRL pin (low)

1 1 1 1 VRL pin (low)

Freescale

8-6 MC68HC05B6

Rev. 4.1

ANALOG TO DIGITAL CONVERTER

8.3 A/D converter during STOP mode

When the MCU ent ers STOP mode with the A/D co n verter turned on, th e A/D clocks are stop ped

and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles

star t-up time. If the A/D RC oscillator is in operation it will also be disabled.

8.4 A/D converter during WAIT mode

The A/D converter is not affected by WAIT mode and continues normal operation.

In order to reduce power consumption the A/D converter can be disconnected, under software

control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before

entering WAIT mode.

8.5 Port D analog input

The e xternal analog v oltage value to be processed b y the A/D conv erter is sampled on an internal

capacitor through a resistive path, provided by input-selection switches and a sampling aper tu re

time switch, as shown in Figure 8-2. Sampling time is limited to 12 bus clock cycles. After

sampling, the analog value is stored on the capacitor and held until the end of conv ersion. During

this hold time, the analog input is disconnected from the internal A/D system and the external

voltage source sees a high impedance input.

The equivalent analog input dur ing sampling is a n RC low-pass filter with a mini mum resistance

of 50 kΩ and a capacitance of at least 10pF. It should be noted that these are typical values

measured at room temperatur e.

Figure 8-2 Electrical model of an A/D input pin

Analog

input

Input protection device

VRL

< 2pF

+∼20V

-∼0.7V

1 µA

junction

leakage

≥50kΩ

≥10pF

DAC

capacitance

Note: The analog switch is closed during the 12 cycle sample time only.

MC68HC05B6

Rev. 4.1 Freescale

9-1

RESETS AND INTERRUPTS

9.1 Resets

The MC68HC05B6 can be reset in three wa ys: b y the initial power-on reset function, by an active

low input to the RESET pin or by a computer operating properly (COP) watchdog reset. Any of

these resets will cause the program to go to its starting address, specified by the contents of

memory locations $1FFE and $1FFF, and cause the interrupt mask bit in the condition code

Figure 9-1 Reset timing diagram

VDD

RESET

1FFF1FFE

1FFE

New

1FFF1FFE1FFE1FFE PC

OSC1

New

Internal

processor clock

1FFE

code

New

PCL

New

PCH

tVDDR

code

New

PCL

New

PCH

address bus

Internal

data bus

tOXOV

tCYC

tPORL

1FFE

Program

execution

begins

Program

execution

begins

tRL(or tDOGL)

(Internal power-on reset) (External hardware reset)

VDD threshold (1-2V typical)

Reset sequence Reset sequence

Freescale

9-2 MC68HC05B6

Rev. 4.1

RESETS AND INTERRUPTS

9.1.1 Power-on reset

A power-on reset occurs when a positive transition is detected on VDD. The power-on reset

function is strictly for power turn-on conditions and should not be used to detect drops in the power

supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the

oscillator becomes active. If the external RESET pin is low at the end of this delay then the

processor remains in the reset state until RESET goes high. The user must ensure that the voltage

on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.

If there is doubt, the e xternal RESET pin should remain low until the voltage on VDD has reached

the specified minimum operating voltage. This may be accomplished by connecting an external

RC circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be

great enough to allow the oscillator circuit to stabilize.

During power-on reset, the RESET pin is driven low during a tPORL delay start-up sequence . tPORL is

defined by a user specified mask option to be either 16 cycles or 4064 cycles (see Section 1.2).

A software distinction between a power-on reset and an external reset can be made using the

POR bit in the miscellaneous register (see Section 9.1.2).

9.1.2 Miscellaneous register

POR — P ower-on reset bit

This bit is set each time the device is powered on. Therefore, the state of the POR bit a llows the

user to make a software distinction between a power-on and an external reset. This bit cannot be

set by software and is cleared by writing it to zero.

1 (set) – A power-on reset has occurred.

0 (clear) – No power-on reset has occurred.

Note: The bits shown shaded in the above representation are explained individually in the

relevant sections of this manual. The complete register plus an e xplanation of each bit

can be found in Section 3.8.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR(1)

(1) The POR bit is set each time there is a power-on reset.

INTP INTN INTE SFA SFB SM WDOG(2)

(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

?001 000?

MC68HC05B6

Rev. 4.1 Freescale

9-3

RESETS AND INTERRUPTS

9.1.3 RESET pin

When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied

to the RESET input f or a minimum period of 1.5 machine cycles (tCYC). An internal Schmitt Trigger

is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will

resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR

or the COP watchdog, the RESET pin pro vides an active -lo w open drain output signal which may

be used to reset external hardware. Current limitation to protect the pull-down device is provided

in case an RC type external reset circuit is used.

9.1.4 Computer operating properl y (COP) watchdog reset

The watchdog counter system consists of a divide-by-8 counter, preceded by a fixed divide-by-4

and a fixed divide-by-256 prescaler, plus control logic as shown in Figure 9-2. The divide-by-8

counter can be reset by software.

Warning: The input to the watchdog system is derived from the carr y output of bit 7 of th e free

running timer counter. Therefore, a reset of the timer may affect the period of the

watchdog timeout.

The watchdog system can be automatically enabled, f ollowing power-on or external reset, via a

mask option (see Section 1.2), or it can be enabled by software by writing a ‘1’ to the WDOG bit

in the miscellaneous register at $000C (see Section 9.1.2). Once enabled, the watchdog system

Figure 9-2 Watchdog system block diagram

÷ 256

(Bit 7 of free

fOSC/2

fOSC/32

Main CPU

÷ 8 watchdog

counter

WDOG bit Control logic

Latch

Reset

Schmitt Input

protectiontrigger

Power-on

Enable

Reset

clock

÷ 4

prescaler running counter)

Freescale

9-4 MC68HC05B6

Rev. 4.1

RESETS AND INTERRUPTS

cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In

addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this

bit clears the counter to its ini tial value and prevents a watchdog timeout.

WDOG — Watchdog enable/d isable

The WDOG bit can be used to enable the watchdog time r previously disabled by a mask option.

F ollowing a watchdog reset the state of the WDOG bit is as defined b y the mask option specified.

1 (set) – Watchdog enabled and counter cleared.

0 (clear) – The watchdog cannot be disabled by software; writing a zero to this

bit has no effect.

The divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its final

state; seven clocks are necessary to bring the watchdog counter from its clear state to its final

state. This reset appears after time t DOG since the last clear or since the enable of the watchdog

counter system. The watchdog counter , therefore, has to be cleared periodically, by softw are, with

a period less th an tDOG.

The reset generated b y the w atchdog system is apparent at the RESET pin (see Figure 9-2). The

RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’

for a minimum of tDOGL, the RESET pin is released.

9.1.4.1 COP watchdog during STOP mode

The STOP instruction is in hibite d wh en the watchdog system is e nabled. If a STOP instruction is

e x ecuted while the wa tchdog system is enabled, then a watchdog reset will occur as if there were

a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will

not be affected, thus there will be no tPORL cycles start-up delay. On start-up, the watchdog will be

configured according to the user specified mask option.

9.1.4.2 COP watchdog during WAIT mode

The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to

be one of the options below:

Watchdog enabled — the watchdog counter will continue to operate during WAIT mode and a

reset will occur after time tDOG.

Watchdog disabled — on entering WAIT mode, the watchdog counter system is reset and

disabled. On exiting WAIT mode the counter resumes normal operation.

MC68HC05B6

Rev. 4.1 Freescale

9-5

RESETS AND INTERRUPTS

9.1.5 Functions affected by reset

When processing stops with in the MCU f or any reason, i.e . power-on reset, e xternal reset or the

execution of a STOP or WAIT instruction, various internal functions of the MCU are affected.

Table 9-1 shows the resu lting action of an y type of system reset, but not necessa rily in the order

in which they occur.

Table 9-1 Effect of RESET, POR, STOP and WAIT

Function/effect RESET POR WAIT STOP

Timer prescaler set to zero x x – –

Timer counter set to $FFFC x x – –

All timer enable bits cleared (disable) x x – –

Data direction registers cleared (inputs) x x – –

Stack pointer set to $00FF x x – –

Force internal address bus to restart x x – –

Vector $1FFE, $1FFF x x – –

Interrupt mask bit (I-bit CCR) set to 1 x x – –

Interrupt mask bit (I-bit CCR) cleared – – x x

Set interrupt enable bit (INTE) x x – –

Set POR bit in miscellaneous register – x – –

Reset STOP latch x x – –

Reset IRQ latch x x – –

Reset WAIT latch x x – –

SCI disabled x x – –

SCI status bits cleared (except TDRE and TC) x x – –

SCI interrupt enable bits cleared x x – –

SCI status bits TDRE and TC set x x – –

Oscillator disabled for 4064 cycles – x – x

Timer clock cleared – x – x

SCI clock cleared – x – x

A/D disabled x x – x

SM bit in the miscellaneous register cleared x x – x

Watchdog counter reset x x x x

WDOG bit in the miscellaneous register reset x x – x

EEPROM control bits (see Section 3.5.1)xx–x

x = Described action takes place

– = Described action does not take place

Freescale

9-6 MC68HC05B6

Rev. 4.1

RESETS AND INTERRUPTS

9.2 Interrupts

The MCU can be interrupted by four different sources: three maskable hardware interrupts and

one non maskable software interrupt:

• External signal on the IRQ pin

• Serial communications interface (SCI)

• Programmable timer

• Software in te rrupt instructio n (SW I)

Interr upts cause the processor to save the regist er contents on the sta ck and to set the interrupt

mask (I-bit) to prev ent additional interrupts . The RTI instruction (ReTurn from Interrupt) causes the

e x ecuting the R TI instruction, the value of the I-bit is replaced by the corresponding I-bit stored on

the stack.

Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but

are considered pending until the current instruction is complete. The current instruction is the one

already fetched and being operated on. When the cu rrent instruction is comp lete, the processor

checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the

corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;

otherwise, the next instruction is fetched and executed.

Note: Power-on and external reset clear all interr upt enable bits, but set the INTE bit in the

miscellaneous register, thus preventing interrupts during the reset sequence.

9.2.1 Interrupt priorities

Each potential interrupt source is assigned a priority level, which means that if more than one

interrupt is pending at th e same time, the processor wi ll ser vice the o ne with the highest pr iority

first. F or example, if both an e xternal interrupt and a timer interrupt are pending after an instruction

execution, the external interrupt is ser v iced first.

Table 9-2 shows the relative priority of all the possible interrupt sources. Figure 9-3 shows

the interrupt processing flow.

9.2.2 Nonmaskable software interrupt (SWI)

The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is

e xecuted regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI

is executed after interrupts that were pending when the SWI was fetched, but before interrupts

MC68HC05B6

Rev. 4.1 Freescale

9-7

RESETS AND INTERRUPTS

generated after the SW I was fetched. The SWI interrupt service routine address is specified by

the contents of memory locations $1FFC and $1FFD.

9.2.3 Maskable hardware interrupts

If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are

masked. Clearing the I-bit allows interrupt processing to occur .

Note: The internal interrupt latch is cleared in the first part of the interrupt service routine;

therefore, one external interrupt pulse could be latched and serviced as soon as the

I-bit is cleared.

9.2.3.1 External interrupt (IRQ)

If the interr upt mask in the condition code register has been cleared and the interr upt enable bit

(INTE) is set and the signal on the extern al interrupt pin (IRQ) satisfies the condition sele cte d by

the option control bits (INTP and INTN), then the e xternal interrupt is recognized. INTE, INTP and

INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is

recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks

further interrupts until the present one is serviced. The external interrup t service routine address

is specified by the content of memory loca tions $1FFA and $1FFB.

Table 9 - 2 Interrupt priorities

Source Register Flags Vector address Priority

Reset — — $1FFE, $1FFF highest

Software interrupt (SWI) — — $1FFC, $1FFD

External interrupt (IRQ) — — $1FFA, $1FFB

Timer input captures TSR ICF1, ICF2 $1FF8, $1FF9

Timer output compares TSR OCF1, OCF2 $1FF6, $1FF7

Timer overflow TSR TOF $1FF4, $1FF5

Serial communications

interface (SCI) SCSR TDRE, TC, OR,

RDRF, IDLE $1FF2, $1FF3 lowest

Freescale

9-8 MC68HC05B6

Rev. 4.1

RESETS AND INTERRUPTS

Figure 9-3 Interrupt flow chart

Reset

Is I-bit set?

IRQ

external interrupt?

Timer

internal interrupt?

SCI

internal interrupt?

Fetch next

instruction

Execute instruction

Clear IRQ request

latch

Stack

PC, X, A, CC

Set I-bit

Load PC from:

IRQ: $1FFA-$1FFB

Timer IC: $1FF8-$1FF9

Timer OC: $1FF6-$1FF7

Timer OVF:$1FF4-$1FF5

SCI: $1FF2-$1FF3

Complete interrupt routine

and execute RTI

MC68HC05B6

Rev. 4.1 Freescale

9-9

RESETS AND INTERRUPTS

9.2.3.2 Miscellaneous register

Note: The bits shown shaded in the above representation are explained individually in the

relevant sections of this manual. The complete register plus an explanation of each bit

can be found in Section 3.8.

INTP, INTN — External interrupt sensitivity options

These two bits allow the user to select which edge the IRQ pin is sensitive to as shown in

Table 9-3. Both bits can be wr itten to only while the I-bit is set, and are cleared by power-on or

external reset. Therefore the device is initialised with negative edge and low level sensitivity.

INTE — External interrupt enable

1 (set) – External interrupt function (IRQ) enabled.

0 (clear) – External interrupt function (IRQ) disabled.

The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,

thus enabling the external interrupt function.

Table 9-3 describes the v arious triggering options availab le for the IRQ pin, howe v er it is important

to re-emphasize here that in order to avoid any conflict and spurious in terrupt, it is o nly possible

to change the external interr upt options while the I-b it is set. Any attempt to change the external

interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is pending, it will

automatically be cleared when selecting a different interrupt option.

Note: If the external interrupt function is disabled by the INTE bit and an external inte rrupt is

sensed by the edge detector circuitry, then the interrupt request is latched and the

interrupt stays pending until the INTE bit is set. The internal latch of the external

interrupt is cleared in the first part of the service routine (except for the low level

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG ?001 000?

Table 9-3 IRQ sensitivity

INTP INTN IRQ sensitivity

0 0 Negative edge and low level sensitive

0 1 Negative edge only

1 0 Positive edge only

1 1 Positive and negative edge sensitive

Freescale

9-10 MC68HC05B6

Rev. 4.1

RESETS AND INTERRUPTS

interrupt which is not latched); therefore, only one external interrupt pulse can be

latched during tILIL and serviced as soon as the I-bit is cleared.

9.2.3.3 Timer interrupts

There are five diff erent timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a

timer interrupt whenever they are set and enabled. These five interrupt flags are found in the five

most significant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will v ector

to the service routine defined by $1FF8-$1FF9, OCF1 and OCF2 will v ector to the service routine

defined by $1FF6–$1FF7 and TOF will vector to the service routine defined by $1FF4–$1FF5 as

shown in Figure 5.1.

There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,

and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address

$0012. See Section 5.2.1 and Section 5.2.2 for further information.

9.2.3.4 Serial communications interface (SCI) interrupts

There are five different interrupt flags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts

whene ver they are set and enab led. These five interrupt flags are found in the fiv e most significant

bits of the SCI status register (SCSR) at location $0010.

There are four corresponding enable bits: TIE f or TDRE, TCIE f or TC , RIE f or OR and RDRF, and

ILIE for IDLE. These enable bits are located in the serial communications control register 2

(SCCR2) at address $000F. See Section 6.11.3 and Section 6.11.4.

The SCI interrupt causes the program counter to vector to the address pointed to by memory

locations $1FF2 and $1FF3 which contain the starting address of the interrupt service routine.

Software in the SCI interrupt service routine must determine the priority and cause of the interrupt

by examining the interrupt flags and the status bits located in the serial communications status

The general sequence for clearing an interrupt is a software sequence of accessing the serial

communications status register while the flag is set followed by a read or write of an associated

MC68HC05B6

Rev. 4.1 Freescale

9-11

RESETS AND INTERRUPTS

9.2.4 Hardware controlled interrupt sequence

The following three functions: reset, STOP and W AIT, are not in the strictest sense interrupts. Howe ver ,

they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Figure 2.4.

RESET: A reset condition causes the program to vector to its starting address, which is

contained in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the

condition code register is also set, to disable interrupts.

ST OP: The ST OP instruction causes the oscillator to be turned off and the processor to ‘sleep’

until an external interrupt (IRQ) or occurs or the device is reset.

WAIT: The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks

running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt

(IRQ), a timer interrupt or an SCI interrupt. There are no special W AIT v ectors f or these

individual interr upts.

Freescale

9-12 MC68HC05B6

Rev. 4.1

RESETS AND INTERRUPTS

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6

Rev. 4.1 Freescale

10-1

CPU CORE AND INSTRUCTION SET

This section provides a description of the CPU core registers, the instruction set and the

addressing modes of the MC68HC05B6.

10.1 Registers

The MCU contains five registers, as shown in the programming model of Figure 10-1. The interrupt

stacking order is shown in Figure 10-2.

Figure 10-1 Programming model

Figure 10-2 Stacking order

Accumulator

Index register

Program counter

Stack pointer

Condition code register

Carry / borrow

Zero

Negative

Interrupt mask

Half carry

15 7 0

000000011

11 1 H I N Z C

Condition code register

Accumulator

Index register

Program counter high

Program counter low

Stack

Unstack

Decreasing

memory

address

Increasing

memory

address

Interrupt

Return

115

Freescale

10-2 MC68HC05B6

Rev. 4.1

CPU CORE AND INSTRUCTION SET

10.1.1 Accumulator (A)

The accumulator is a general purpose 8-bit register used to hold operands and results of

arithmetic calculations or data manipulations.

10.1.2 Index register (X)

The index register is an 8-bit register, which can contain the indexed addressing value used to

create an effective address. The index register may also be used as a te mporary storage area.

10.1.3 Program counter (PC)

The program counter is a 16-bit register , which contains the address of the ne xt byte to be f etched.

10.1.4 Stack pointer (SP)

The stack pointer is a 16-bit register, which contains the address of the next free location on the

stac k. During an MCU reset or th e reset stac k po inter (RSP) instruction, the stack pointer is set to

location $00FF. The stack pointer is then decremented as data is pushed onto the stack and

incremented as data is pulled from the stack.

When accessing memory, the ten most significant bits are permanently set to 0000000011. These

ten bits are appended to the six least significant register bits to produce an address within the

range of $00C0 to $00FF. Subroutines and i nterr upts may use up to 64 (decimal) locations. If 64

locations are exceeded, the stack pointer wraps around and overwrites the previously stored

inf ormation. A subroutine call occupies two locations on the stack; an interrupt uses fiv e locations.

10.1.5 Condition code register (CCR)

The CCR is a 5-bit register in which f our bits are used to indicate the results of the instruction just

e xecuted, and the fifth bit indicates whether interrupts are masked. These bits can be individually

tested by a program, and specific actions can be taken as a result of their state. Each bit is

explained in the following paragraphs.

115

MC68HC05B6

Rev. 4.1 Freescale

10-3

CPU CORE AND INSTRUCTION SET

Half carry (H)

This bit is set during ADD and ADC oper ations to indicate that a carry occurred between bits 3 and 4.

Interrupt (I)

When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set,

the interr upt is latched and remains pending until the interrupt bit is cleared .

Negative (N)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was

negative.

Zero (Z)

When set, this bit indicates that the result of the last arithmetic , logical, or data manipulation was zero .

Carry/borrow (C)

When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred

during the last arithmetic operation. This bit is also affected during bit test and branch instructions

and during shifts and rotates.

10.2 I nstruction set

The MCU has a set of 62 basic instructions. They can be grouped into five different types as

follows:

– Register/memory

– Read/modify/write

–Branch

– Bit manipulation

– Control

The following paragraphs briefly explain each type. All the instructions within a given type are

presented in individual tables.

This MCU uses all the instructions available in the M146805 CMOS family plus one more: the

unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents

of the accumulator (A) and the index register (X). The high-order product is then stored in the index

instruction is shown in Table 10-1.

115

Freescale

10-4 MC68HC05B6

Rev. 4.1

CPU CORE AND INSTRUCTION SET

10.2.1 Register/memory Instructions

Most of these instr uctions use two operands. The first operand is either the accumulator or the

index register. The second oper and is obtained from memory using one of the addressing modes .

The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register

operand. Refer to Table 10-2 for a complete list of register/memory instructions.

10.2.2 Branch instructions

These instructions cause the program to branch if a particular condition is met; otherwise, no

operation is performed. Branch instructions are two-byte instructions. Refer to Table 10-3.

10.2.3 Bit manipulation instructions

The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space

(page 0). All port data and data direction registers, timer and serial interface registers,

control/status registers and a po r tion of the on-ch ip RAM reside in page 0. An addition al feature

allows the software to test and branch on the state of an y bit within thes e locations. The bit set, bit

clear, bit test and branch functions ar e all implemented with single instr uctions. For the test and

branch instructions, the value of the bit tested is also place d in the carry bit of the condition code

10.2.4 Read/modify/write instructions

These instructions read a memory location or a register, modify or test its contents, and write the

modified value bac k to memory or to the register. The test for negativ e or zero (TST) instruction is

an exception to this sequence of reading, modifying and writing, since it does not modify the value.

Refer to Table 10-5 for a complete list of read/modify/write instructions.

10.2.5 Control instructions

These instructions are re gister ref erence i nstructions and are used to control processor operation

during program execution. Refer to Table 10-6 for a complete list of control instructions.

10.2.6 Tables

Tables for all the instru ction types listed above follow. In addition ther e is a complete alphabetical

listing of all the instructions (see Table 10-7 and Table 10-8), and an opcode map for the

instruction set of the M68HC05 MCU family (see Table 10-9).

115

MC68HC05B6

Rev. 4.1 Freescale

10-5

CPU CORE AND INSTRUCTION SET

Table 10-1 MUL instruction

Operation X:A ← X*A

Description

Multiplies the eight bits in the index register by the eight

bits in the accumulator and places the 16-bit result in the

concatenated accumulator and index register.

Condition

codes

H : Cleared

I : Not affected

N : Not affected

Z : Not affected

C : Cleared

Source MUL

Form Addressing mode Cycles Bytes Opcode

Inherent 11 1 $42

Table 10-2 Register/memory instructions

Addressing modes

Immediate Direct Extended

Indexed

(no

offset)

Indexed

(8-bit

offset)

Indexed

(16-bit

offset)

Function

Mnemonic

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Load A from memory LDA A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 D6 3 5

Load X from memory LDX AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5

Store A in memory STA B724C735F714E725D736

Store X in memory STX BF24CF35FF14EF25DF36

Add memory to A ADDAB22BB23CB34FB13EB24DB35

Add memory and carry to A ADCA922B923C934F913E924D935

Subtract memory SUBA02 2B02 3C03 4F01 3E02 4D03 5

Subtract memory from A

with borrow SBCA22 2B22 3C23 4F21 3E22 4D23 5

AND memory with A ANDA422B423C434F413E424D435

OR memory with A ORAAA22BA23CA34FA13EA24DA35

Exclusive OR memory with A EORA822B823C834F813E824D835

Arithmetic compare A

with memory CMPA12 2B12 3C13 4F11 3E12 4D13 5

Arithmetic compare X

with memory CPXA32 2B32 3C33 4F31 3E32 4D33 5

Bit test memory with A

(logical compare) BIT A52 2B52 3C53 4F51 3E52 4D53 5

Jump unconditional JMP BC22CC33FC12EC23DC34

Jump to subroutine JSR BD25CD36FD15ED26DD37

115

Freescale

10-6 MC68HC05B6

Rev. 4.1

CPU CORE AND INSTRUCTION SET

Table 10-3 Branch instructions

Relative addressing mode

Function Mnemonic Opcode # Bytes # Cycles

Branch always BRA 20 2 3

Branch never BRN 21 2 3

Branch if higher BHI 22 2 3

Branch if lower or same BLS 23 2 3

Branch if carry clear BCC 24 2 3

(Branch if higher or same) (BHS) 24 2 3

Branch if carry set BCS 25 2 3

(Branch if lower) (BLO) 25 2 3

Branch if not equal BNE 26 2 3

Branch if equal BEQ 27 2 3

Branch if half carry clear BHCC 28 2 3

Branch if half carry set BHCS 29 2 3

Branch if plus BPL 2A 2 3

Branch if minus BMI 2B 2 3

Branch if interrupt mask bit is clear BMC 2C 2 3

Branch if interrupt mask bit is set BMS 2D 2 3

Branch if interrupt line is low BIL 2E 2 3

Branch if interrupt line is high BIH 2F 2 3

Branch to subroutine BSR AD 2 6

Table 10-4 Bit manipulation instructions

Addressing Modes

Bit set/clear Bit test and branch

Function Mnemonic Opcode # Bytes # Cycles Opcode # Bytes # Cycles

Branch if bit n is set BRSET n (n=0–7) 2•n 3 5

Branch if bit n is clear BRCLR n (n=0–7) 01+2•n 3 5

Set bit n BSET n (n=0–7) 10+2•n 2 5

Clear bit n BCLR n (n=0–7) 11+2•n 2 5

115

MC68HC05B6

Rev. 4.1 Freescale

10-7

CPU CORE AND INSTRUCTION SET

Table 10-5 Read/modify/write instructions

Addressing modes

Inherent

(A)

Inherent

(X) Direct

Indexed

(no

offset)

Indexed

(8-bit

offset)

Function

Mnemonic

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Increment INC 4C1 35C1 33C2 57C1 56C2 6

Decrement DEC4A1 35A1 33A2 57A1 56A2 6

Clear CLR4F1 35F1 33F2 57F1 56F2 6

Complement COM431 3531 3332 5731 5632 6

Negate (two’s complement) NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6

Rotate left through carry ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6

Rotate right through carry ROR461 3561 3362 5761 5662 6

Logical shift left LSL481 3581 3382 5781 5682 6

Logical shift right LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6

Arithmetic shift right ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6

Test for negative or zero TST4D1 35D1 33D2 47D1 46D2 5

Multiply MUL 42 1 11

Table 10-6 Control instructions

Inherent addressing mode

Function Mnemonic Opcode # Bytes # Cycles

Transfer A to X TAX 97 1 2

Transfer X to A TXA 9F 1 2

Set carry bit SEC 99 1 2

Clear carry bit CLC 98 1 2

Set interrupt mask bit SEI 9B 1 2

Clear interrupt mask bit CLI 9A 1 2

Software interrupt SWI 83 1 10

Return from subroutine RTS 81 1 6

Return from interrupt RTI 80 1 9

Reset stack pointer RSP 9C 1 2

No-operation NOP 9D 1 2

Stop STOP 8E 1 2

Wait WAIT 8F 1 2

115

Freescale

10-8 MC68HC05B6

Rev. 4.1

CPU CORE AND INSTRUCTION SET

Table 10-7 Instruction set (1 of 2)

Mnemonic Addressing modes Condition codes

INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C

ADC Þ • ÞÞÞ

ADD Þ • ÞÞÞ

AND ••ÞÞ•

ASL • • ÞÞÞ

ASR • • ÞÞÞ

BCC •••••

BCLR •••••

BCS •••••

BEQ •••••

BHCC •••••

BHCS •••••

BHI •••••

BHS •••••

BIH •••••

BIL •••••

BIT ••ÞÞ•

BLO •••••

BLS •••••

BMC •••••

BMI •••••

BMS •••••

BNE •••••

BPL •••••

BRA •••••

BRN •••••

BRCLR ••••Þ

BRSET ••••Þ

BSET •••••

BSR •••••

CLC ••••0

CLI •0•••

CLR ••01•

CMP • • ÞÞÞ

Condition code symbols

H Half carry (from bit 3) Þ Tested and set if true,

cleared otherwise

I Interrupt mask • Not affected

N Negate (sign bit) ? Load CCR from stack

Z Zero 0 Cleared

C Carry/borrow 1 Set

Not implemented

Address mode abbreviations

BSC Bit set/clear IMM Immediate

BTB Bit test & branch IX Indexed (no offset)

DIR Direct IX1 Indexed, 1 byte offset

EXT Extended IX2 Indexed, 2 byte offset

INH Inherent REL Relative

115

MC68HC05B6

Rev. 4.1 Freescale

10-9

CPU CORE AND INSTRUCTION SET

Table 10-8 In struction set (2 of 2)

Mnemonic Addressing modes Condition codes

INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C

COM ••ÞÞ1

CPX ••ÞÞÞ

DEC ••ÞÞ•

EOR ••ÞÞ•

INC ••ÞÞ•

JMP •••••

JSR •••••

LDA ••ÞÞ•

LDX ••ÞÞ•

LSL ••ÞÞÞ

LSR ••0ÞÞ

MUL 0•••0

NEG ••ÞÞÞ

NOP •••••

ORA ••ÞÞ•

ROL ••ÞÞÞ

ROR ••ÞÞÞ

RSP •••••

RTI ?????

RTS •••••

SBC ••ÞÞÞ

SEC ••••1

SEI •1•••

STA ••ÞÞ•

STOP •0•••

STX ••ÞÞ•

SUB ••ÞÞÞ

SWI •1•••

TAX •••••

TST ••ÞÞ•

TXA •••••

WAIT •0•••

Condition code symbols

H Half carry (from bit 3) Þ Tested and set if true,

cleared otherwise

I Interrupt mask • Not affected

N Negate (sign bit) ? Load CCR from stack

Z Zero 0 Cleared

C Carry/borrow 1 Set

Not implemented

Address mode abbreviations

BSC Bit set/clear IMM Immediate

BTB Bit test & branch IX Indexed (no offset)

DIR Direct IX1 Indexed, 1 byte offset

EXT Extended IX2 Indexed, 2 byte offset

INH Inherent REL Relative

115

Freescale

10-10 MC68HC05B6

Rev. 4.1

CPU CORE AND INSTRUCTION SET

Table 10-9 M68HC05 opcode map

Bit manipulation Branch Read/modify/write Control Register/memory

BTB BSC REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX

High 0123456789ABCDEF

High

Low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Low

0000

553533659 234543

0000

BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI SUB SUB SUB SUB SUB SUB

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX1INH 2IMM2 DIR3EXT3 IX22 IX11 IX

0001

553 6234543

0001

BRCLR0 BCLR0 BRN RTS CMPCMPCMPCMPCMPCMP

3BTB2BSC2REL 1INH 2IMM2 DIR3EXT3 IX22 IX11 IX

0010

553 11 234543

0010

BRSET1 BSET1 BHI MUL SBC SBC SBC SBC SBC SBC

3BTB2BSC2REL 1INH 2IMM2 DIR3EXT3 IX22 IX11 IX

0011

5535336510 234543

0011

BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI CPXCPXCPXCPXCPXCPX

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX1INH 2IMM2 DIR3EXT3 IX22 IX11 IX

0100

55353365 234543

0100

BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR AND AND AND AND AND AND

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 2IMM2 DIR3EXT3 IX22 IX11 IX

0101

553 234543

0101

BRCLR2 BCLR2 BCS BITBITBITBITBITBIT

3BTB2BSC2REL 2IMM2 DIR3EXT3 IX22 IX11 IX

0110

55353365 234543

0110

BRSET3 BSET3 BNE ROR RORA RORX ROR ROR LDA LDA LDA LDA LDA LDA

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 2IMM2 DIR3EXT3 IX22 IX11 IX

0111

55353365 245654

0111

BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR TAX STA STA STA STA STA

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 1INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1000

55353365 2234543

1000

BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL CLC EOR EOR EOR EOR EOR EOR

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 1 INH2IMM2 DIR3EXT3 IX22 IX11 IX

1001

55353365 2234543

1001

BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 1 INH2IMM2 DIR3EXT3 IX22 IX11 IX

1010

55353365 2234543

1010

BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA ORA ORA ORA

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 1 INH2IMM2 DIR3EXT3 IX22 IX11 IX

1011

553 2234543

1011

BRCLR5 BCLR5 BMI SEI ADD ADD ADD ADD ADD ADD

3BTB2BSC2REL 1 INH2IMM2 DIR3EXT3 IX22 IX11 IX

1100

55353365 223432

1100

BRSET6 BSET6 BMC INC INCA INCX INC INC RSP JMP JMP JMP JMP JMP

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 1INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1101

55343354 2656765

1101

BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1110

553 2234543

1110

BRSET7 BSET7 BIL STOP LDX LDX LDX LDX LDX LDX

3BTB2BSC2REL 1INH 2IMM2 DIR3EXT3 IX22 IX11 IX

1111

5535336522 45654

1111

BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX STX STX STX STX

3BTB2BSC2REL2DIR1INH1INH2 IX11 IX1INH1INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

1111

0000

SUB

1IX

Opcode in hexadecimal

Opcode in binary

Address mode

Cycles

Bytes

Mnemonic

Legend

Abbreviations for address modes and registers

BSC

BTB

DIR

EXT

INH

IMM

IX1

IX2

REL

Bit set/clear

Bit test and branch

Direct

Extended

Inherent

Immediate

Indexed (no offset)

Indexed, 1 byte (8-bit) offset

Indexed, 2 byte (16-bit) offset

Relative

Accumulator

Index register Not implemented

115

MC68HC05B6

Rev. 4.1 Freescale

10-11

CPU CORE AND INSTRUCTION SET

10.3 Addressing modes

Ten different addressing modes provide programmers with the flexibility to optimize their code for

all situations. The various inde xed addressing modes make it possible to locate data tab les , code

conv ersion tables and scaling tables anywhere in the memory space. Short inde x ed accesses are

single byte instructions; the l ongest instructions (three bytes) enable access to tables throughout

memory. Short absolute (direct) and long absolute (extended) addressing are also included. One

or two byte direct addressing instructions access all data bytes in most applications. Extended

addressing permits jump instructions to reach all memory locations.

The term ‘effective address’ (EA) is used in describing the various addressing modes. The

effective address is defined as the address from which the argu ment for an instruction is fetched

or stored. The ten addressing modes of the processor are described below . P arentheses are used

to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the

contents of the location poi nted to by the PC (p rogram counter). An arrow indicates ‘is replaced

by’ and a colon indicates concatenation of two bytes. For additional details and graphical

illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/

Microprocessor User's Manual or to the M68HC05 Applications Guid e.

10.3.1 Inherent

In the inherent addressing mode, all the information necessary to execute the instruction is

contained in the opcode. Operations specifying only the index register or accumulator, as well as

the control instruction, with no other arguments are included in this mode. These instructions are

one byte long.

10.3.2 Immediate

In the immediate addressing mode , the operand is contained in the byte immediately following the

opcode. The immediate addressing mode is used to access consta nts that do not change during

program execution (e .g. a constant used to initialize a loop counter).

EA = PC+1; PC ← PC+2

10.3.3 Direct

In the direct addressing mode , the effectiv e address of the argument is contained in a single byte

following the opcode byte. Direct addressing allows the user to directly address the lowest 256

bytes in memory with a single two-byte instruction.

EA = (PC+1); PC ← PC+2

Address bus high ← 0; Address bus low ← (PC+1)

115

Freescale

10-12 MC68HC05B6

Rev. 4.1

CPU CORE AND INSTRUCTION SET

10.3.4 Extended

In the extended addressing mod e, the effective address of the argument is contained in the two

bytes following the opcode byte. Instructions with extended addressing mode are capable of

referencing argu me nts anywhere in memory with a single three-byte instruction. When using the

Freescale assembler, the user need not specify whether an instruction uses direct or extended

addressing. The assembler automatically selects the short form of the instruction.

EA = (PC+1):(PC+2); PC ← PC+3

Address bus high ← (PC+1); Address bus low ← (PC+2)

10.3.5 Indexed, no offset

In the indexed, no offset addressing mo de, the effective address of the argument i s contained in

the 8-bit index register. This addressing mode can access the first 256 memory locations. These

instructions are only on e byte long. This mode is often used to move a pointer through a table or

to hold the address of a frequently referenced RAM or I/O location.

EA = X; PC ← PC+1

Address bus high ← 0; Address bus low ← X

10.3.6 Indexed, 8-bit offset

In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of

the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the

operand can be located anywhere within the lowest 511 memory locations. This addressing mode

is useful for selecting the mth element in an n element table.

EA = X+(PC+1); PC ← PC+2

Address bus high ← K; Address bus low ← X+(PC+1)

where K = the carry from the addition of X and (PC+1)

10.3.7 Indexed, 16-bit offset

In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of

the unsigned 8-bit in dex register and the two unsigned bytes following the opcode. This address

mode can be used in a manner similar to index ed, 8-bit offset e xcept that this three-byte instruction

allows tables to be anywhere in memory. As with direct and extended addressing, the Fr eescale

assembler determines the shortest form of index ed addressing.

EA = X+[(PC+1):(PC+2)]; PC ← PC+3

Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)

where K = the carry from the addition of X and (PC+2)

115

MC68HC05B6

Rev. 4.1 Freescale

10-13

CPU CORE AND INSTRUCTION SET

10.3.8 Relative

The relative addressing mode is only used in branch instructions. In relative addressing, the

contents of the 8-bit signed b yte (the offset) f ollowing the opcode are added to the PC if , and only

if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of

relative addressing is from –126 to +129 from the opcode address. The programmer need not

calculate the offset when using the Freescale assembler, since it calculates the proper offset and

checks to see that it is within the span of the branch.

EA = PC+2+(PC+1); PC ← EA if branch taken;

otherwise EA = PC ← PC+2

10.3.9 Bit set/clear

In the bit set/clear addressing mode, the bit to be set or cleared is par t of the opcode. The byte

following the opcode specifies the address of the byte in which the specified bit is to be set or

cleared. Any read/write bit in the first 256 locations of memory, including I/O , can be selectiv ely set

or cleared with a single two-byte instruction.

EA = (PC+1); PC ← PC+2

Address bus high ← 0; Address bus low ← (PC+1)

10.3.10 Bit test and branch

The bit test and branch addressing mode is a combination of direct addressing and relative

addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The

address of the byte to be tested is in the single byte immediately f ollowing the opcode byte (EA1).

The signed relative 8-bit offset in the third byte (EA2) is added to th e PC if the specified bit is se t

or cleared in the specified memory location. This single three-byte instruction allows the program

to branch based on the condition of any readable bit in the first 256 locations of memory. The span

of branch is from –125 to +130 from the opcode address. The state of the tested bit is also

transferred to the carry bit of the condition code register.

EA1 = (PC+1); PC ← PC+2

Address bus high ← 0; Address bus low ← (PC+1)

EA2 = PC+3+(PC+2 ); PC ← EA2 if branch taken;

otherwise PC ← PC+3

115

Freescale

10-14 MC68HC05B6

Rev. 4.1

CPU CORE AND INSTRUCTION SET

THIS PAGE LEFT BLANK INTENTIONALLY

115

MC68HC05B6

Rev. 4.1 Freescale

11-1

ELECTRICAL SPECIFICAT IONS

ELECTRICAL SPECIFICATIONS

This section contains the electrical specifications and associated timing information for the

MC68HC05B6.

11.1 Absolute maximum ratings

Note: This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric fields. However, it is recommended that normal

precautions be taken to avoid the application of any voltages higher than those given

in the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inputs should be tied to either VSS or VDD.

Table 11-1 Absolute maximum ratings

Rating Symbol Value Unit

Supply voltage(1)

(1) All voltages are with respect to VSS.

VDD – 0.5 to +7.0 V

Input voltage (Except VPP1)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC05B6)

– Extended (MC68HC05B6C)

– Automotive (MC68HC05B6M)

TATL to TH

0 to +70

–40 to +85

–40 to +125

°C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

129

130

131

132

133

Freescale

11-2 MC68HC05B6

Rev. 4.1

ELECTRICAL SPECIFICATIONS

11.2 DC electrical characteristics

Table 11-2 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient

switching currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

VDD – 0.4

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—0.1

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,

RESET,TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (extended)

– 40 to 125 (automotive)

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from

rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

IDD

—

3.5

0.5

0.35

—

1.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2

±0.2

±1

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI, IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

134

135

136

137

138

MC68HC05B6

Rev. 4.1 Freescale

11-3

ELECTRICAL SPECIFICAT IONS

11.2.1 IDD trends for 5V operation

For the examples below, typical values are at the mid-point of the voltage range and at a

temperature of 25°C only.

Figure 11-1 Run IDD vs internal operating frequency (4.5V, 5.5V)

Figure 11-2 Run IDD (SM = 1) vs inter nal operating frequency (4.5V, 5.5V)

Figure 11-3 Wait IDD vs internal operating frequency (4.5V, 5.5V)

00.511.522.533.54

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

1.2

00.511.522.533.54

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

0.8

0.6

0.4

0.2

2.5

00.511.522.533.54

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

1.5

0.5

139

140

Freescale

11-4 MC68HC05B6

Rev. 4.1

ELECTRICAL SPECIFICATIONS

Figure 11-4 Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V)

Figure 11-5 Increase in IDD vs frequency for A/D, SCI systems activ e, VDD = 5.5V

Figure 11-6 IDD vs mode vs internal operating frequency, VDD = 5.5V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00.511.522.533.54

IDD (mA)

Internal operating frequency (MHz)

5.5V

4.5V

0.9

1.4

1.2

0.8

0.6

0.4

0.2

00.511.522.53

IDD (mA)

Internal operating frequency (MHz)

A/D + SCI

A/D

1.6

SCI

000.511.522.533.54

IDD (mA)

Internal operating frequency (MHz)

Wait IDD (SM = 1)

Run IDD

Wait IDD

Run IDD (SM = 1)

MC68HC05B6

Rev. 4.1 Freescale

11-5

ELECTRICAL SPECIFICAT IONS

Table 11-3 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ(2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.2mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 0.4mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

Output low voltage (ILOAD = 0.4mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 0.4mA)

RESET

VOL

—0.1

0.2

0.3

0.6

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,

RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (extended)

– 40 to 125 (automotive)

IDD

—

1.2

0.2

0.4

0.15

—

1.5

0.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2

±0.2

±1

µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI, IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO,

SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V

from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

Freescale

11-6 MC68HC05B6

Rev. 4.1

ELECTRICAL SPECIFICATIONS

11.2.2 IDD trends fo r 3.3V operation

For the examples below, typical values are at the mid-point of the voltage range and at a

temperature of 25°C on ly.

Figure 11-7 Run IDD vs internal operating frequency (3V, 3.6V)

Figure 11-8 Run IDD (SM = 1) vs internal operating frequency (3V,3.6V)

Figure 11-9 Wait IDD vs internal operating frequency (3V, 3.6V)

2.5

00.511.522.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

1.5

0.5

0.6

00.511.522.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

0.5

0.4

0.3

0.2

0.1

1.2

00.511.522.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

0.8

0.6

0.4

0.2

MC68HC05B6

Rev. 4.1 Freescale

11-7

ELECTRICAL SPECIFICAT IONS

Figure 11-10 Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V)

Figure 11-11 Increase in IDD vs frequency f or A/D , SCI systems active, VDD = 3.6V

Figure 11-12 IDD vs mode vs internal operating frequency, VDD = 3.6V

0.5

00.511.522.5

IDD (mA)

Internal operating frequency (MHz)

3.6V

3.0V

0.4

0.3

0.2

0.1

0.7

0.6

0.5

0.4

0.3

0.2

0.1

000.511.522.5

IDD (mA)

Internal operating frequency (MHz)

A/D

SCI

A/D + SCI

2.5

1.5

0.5

000.511.522.5

IDD (mA)

Internal operating frequency (MHz)

Run IDD

Wait IDD

Run IDD (SM=1)

Wait IDD (SM=1)

Freescale

11-8 MC68HC05B6

Rev. 4.1

ELECTRICAL SPECIFICATIONS

11.3 A/D con verter characteristics

Table 11-4 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 1LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1)

(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

Minimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator

—

tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2)

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

—

tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3)

(3) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

MC68HC05B6

Rev. 4.1 Freescale

11-9

ELECTRICAL SPECIFICAT IONS

Table 11-5 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 1LSB

Quantization error Uncertainty due to converter resolution — ± 1LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 2LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Freescale

11-10 MC68HC05B6

Rev. 4.1

ELECTRICAL SPECIFICATIONS

11.4 Control timing

Table 11-6 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

4.2

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

2.1

MHz

Cycle time (see Figure 9-1)t

CYC 476 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV —100ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

tPROG

—

Timer (see Figure 11-13)

Resolution(2)

Input capture pulse width

Input capture pulse period

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

tRESL

tTH, tTL

tTLTL

125

—(3)

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute

the capture interrupt service routine plus 24 tCYC.

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 125 — ns

Interrupt pulse period tILIL —(4)

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 tCYC.

—t

CYC

OSC1 pulse width(5)

(5) tOH and tOL should not total less than 238ns.

tOH, tOL 90 — ns

Write/Erase endurance(6)(7)

(6) At a temperature of 85°C

— 10000 cycles

Data retention(6)(7)

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

—10years

MC68HC05B6

Rev. 4.1 Freescale

11-11

ELECTRICAL SPECIFICAT IONS

Table 11-7 Control timing for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

2.0

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

—

1.0

MHz

Cycle time (see Figure 9-1)t

CYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure 11-13)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 200 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 tCYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 tCYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Freescale

11-12 MC68HC05B6

Rev. 4.1

ELECTRICAL SPECIFICATIONS

Figure 11-13 Timer relationship

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

MC68HC05B6

Rev. 4.1 Freescale

12-1

MECHANICAL DATA

12.1 M C68HC05B family pin configurations

12.1.1 52-pin plastic leaded chip carrier (PLCC)

Figure 12-1 52-pin PLCC pinout for the MC68HC05B6

PC3

PC4

PC5

PC6

PC7

VSS

VPP1/NU

PB0

PB1

PB2

PB3

PB4

PB5

VRH

PD4/AN4

VDD

PD3/AN3

PD2/AN2

PD1/AN1

PD0/AN0

NC/VPP6

OSC1

OSC2

RESET

IRQ

PLMA

PLMB

TCAP1

TCAP2

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB7

PB6

VRL

NC/NU

PD5/AN5

PD6/AN6

PD7/AN7

TCMP1

TCMP2

TDO

SCLK

RDI

PC0

PC1

PC2/ECLK

Device Pin 6 Pin 15 Pin 40

MC68HC05B4 NC NC NU

MC68HC05B6 NC NC VPP1

MC68HC05B8 NC NC VPP1

MC68HC05B16 NC NC VPP1

MC68HC05B32 NC NC VPP1

MC68HC705B5 NC VPP6 NU

MC68HC705B16 NU VPP6 VPP1

MC68HC705B16N NU VPP6 VPP1

MC68HC705B32 NU VPP6 VPP1

NC = Not connected

NU = Non-user pin (Should be tied to VSS

in an electrically noisy environment)

TPG

141

Freescale

12-2 MC68HC05B6

Rev. 4.1

MECHANICAL DATA

12.1.2 64-pin quad flat pack (QFP)

Figure 12-2 64-pin QFP pinout for the MC68HC05B6

PB0

NC/NU

VPP1/NC

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

TCAP2

TCAP1

PLMB D/A

PC1

PC0

RDI

SCLK

TDO

TCMP2

TCMP1

PD7/AN7

PD6/AN6

PD5/AN5

VRL

VRH

VDD

PD3/AN3

PD2/AN2

PD1/AN1

NC/VPP6

OSC1

OSC2

RESET

IRQ

PLMA D/A

PD4/AN4

PC2/ECLK

PC3

PC5

PC6

PC7

VSS

PB1

PB2

PB3

PB4

PB5

PC4

PD0/AN0

Device Pin 27 Pin 55 Pin 57

MC68HC05B4 NC NC NC

MC68HC05B6

MC68HC05B8

MC68HC05B16

MC68HC05B32

NC NC VPP1

MC68HC705B5 Not available in this package

MC68HC705B16 VPP6 NU VPP1

MC68HC705B16N VPP6 NU VPP1

MC68HC705B32 VPP6 NC VPP1

NC = Not connected

NU = Non-user pin (Should be tied to VSS in an electrically noisy environment)

TPG

142

MC68HC05B6

Rev. 4.1 Freescale

12-3

MECHANICAL DATA

12.1.3 56-pin shrink dual in line package (SDIP)

Figure 12-3 56-pin SDIP pinout for the MC68HC05B6

TCMP1

PD7

PD6

PD5

NC/NU

VRL

VRH

PD4

VDD

PD3

PD2

PD1

PD0

NC/VPP6

OSC1

OSC2

RESET

IRQ

PLMA

56 TCMP2

TDO

SCLK

RDI

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

VSS

VPP1/NC

PB0

PB1

PB2

PB3

PB4

PB5

PLMB

TCAP1

TCAP2

PA7

PA6

PA5

PA4

PB6

PB7

PA0

PA1

PA2

PA3

Device Pin 6 Pin 16 Pin 42

MC68HC05B4 NC NC NC

MC68HC05B6 NC NC VPP1

MC68HC05B8 NC NC VPP1

MC68HC05B16 NC NC VPP1

MC68HC05B32 NC NC VPP1

MC68HC705B5 NC VPP6 NC

MC68HC705B16 Not available in this package

MC68HC705B16N Contact Sales

MC68HC705B32 NU VPP6 VPP1

NC = Not connected

NU = Non-user pin (Should be tied to VSS in an electrically noisy environment)

TPG

143

Freescale

12-4 MC68HC05B6

Rev. 4.1

MECHANICAL DATA

12.2 MC68HC05B6 mechanical dimensions

12.2.1 52-pin plastic leaded chip carrier (PLCC)

Figure 12-4 52-pin PLCC mechanical dimensions

–L– –M–

–P–

–N–

pin 1

pin 52

Y BRK

J E

0.10

–T– SEATING PLANE

0.18 T N –P L –M

S S S

Case No. 778-02

52 Lead PLCC

w/o pedestal

Dim. Min. Max. Notes Dim. Min. Max.

A 19.94 20.19

1. Datums –L–, –M–, –N– and –P– are determined where top of lead

shoulder exits plastic body at mould parting line.

2. Dimension G1, true position to be measured at datum –T– (seating

plane).

3. Dimensions R and U do not include mould protrusion. Allowable

mould protrusion is 0.25mm per side.

4. Dimensions and tolerancing per ANSI Y 14.5M, 1982.

5. All dimensions in mm.

U 19.05 19.20

B 19.94 20.19 V 1.07 1.21

C 4.20 4.57 W 1.07 1.21

E 2.29 2.79 X 1.07 1.42

F 0.33 0.48 Y — 0.50

G1.27 BSC Z2°10°

H 0.66 0.81 G1 18.04 18.54

J0.51— K11.02—

K0.64— Z12°10°

R 19.05 19.20

0.18 T L –M N –P

S S S

0.18 T L –M N –P

S S S

0.18 T N –P L –M

S S S

0.25 T L –M N –P

S S S

TPG

144

MC68HC05B6

Rev. 4.1 Freescale

12-5

MECHANICAL DATA

12.2.2 64-pin quad flat pack (QFP)

Figure 12-5 64-pin QFP mechanical dimensions

64 lead QFP

0.20 MCA – B SDS

3348

161

- B -

B V

0.05 A – B

- D -

0.20 MHA – B SDS

- A -

Detail “A”

- A, B, D -

Detail “A”

Section B–B

Base

Metal

-C-

Detail “C”

-H- Datum

Plane

Seating

Plane

Dim. Min. Max. Notes Dim. Min. Max.

A 13.90 14.10 1. Datum Plane –H– is located at bottom of lead and is coincident with

the lead where the lead exits the plastic body at the bottom of the

parting line.

2. Datums A–B and –D to be determined at Datum Plane –H–.

3. Dimensions S and V to be determined at seating plane –C–.

4. Dimensions A and B do not include mould protrusion. Allowable

mould protrusion is 0.25mm per side. Dimensions A and B do

include mould mismatch and are determined at Datum Plane –H–.

5. Dimension D does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08 total in excess of the D dimension

at maximum material condition. Dambar cannot be located on the

lower radius or the foot.

6. Dimensions and tolerancing per ANSI Y 14.5M, 1982.

7. All dimensions in mm.

M5°10°

B 13.90 14.10 N 0.130 0.170

C 2.067 2.457 P 0.40 BSC

D0.300.45 Q 2°8°

E 2.00 2.40 R 0.13 0.30

F 0.30 — S 16.20 16.60

G 0.80 BSC T 0.20 REF

H 0.067 0.250 U 9°15°

J 0.130 0.230 V 16.20 16.60

K 0.50 0.66 W 0.042 NOM

L 12.00 REF X 1.10 1.30

0.20 MCA – B SDS

0.05 A – B

0.20 MHA – B SDS

0.20 MCA – B SDS

Case No. 840C

TPG

145

Freescale

12-6 MC68HC05B6

Rev. 4.1

MECHANICAL DATA

12.2.3 56-pin shrink dual in line package (SDIP)

Figure 12-6 56-pin SDIP mechanical dimensions

128

56 29

- A -

Plane

Seating

Dim. Min. Max. Notes Dim. Min. Max.

A 51.69 52.45

1. Due to space limitations, this case shall be represented by a

general case outline, rather than one showing all the leads.

2. Dimensions and tolerancing per ANSI Y 14.5 1982.

3. All dimensions in mm.

4. Dimension L to centre of lead when formed parallel.

5. Dimensions A and B do not include mould flash. Allowable mould

flash is 0.25 mm.

H 7.62 BSC

B 13.72 14.22 J 0.20 0.38

C 3.94 5.08 K 2.92 3.43

D 0.36 0.56 L 15.24 BSC

E0.89 BSC M0°15°

F 0.81 1.17 N 0.51 1.02

G 1.778 BSC

Case No. 859-01

56 lead SDIP - B -

- T -

0.25 T A

0.25 T B

TPG

146

MC68HC05B6

Rev. 4.1 Freescale

13-1

ORDERING INFORMATION

This section describes the inf ormation needed to order the MC68HC05B6 and other family members .

To initiate a ROM pattern f or the MCU, it is necessary to contact your local field service office, local

sales person or Freescale representativ e. Please note that you will need to supply details such as:

mask option selections; temperature range; oscillator frequency; package type; electrical test

requirements; and device marking details so that an order can be processed, and a customer

specific part number allocated. Refer to Table 13-1 f or appropriate part numbers. The part number

consists of the device title plus the appropr iate suffix. For example, the MC68HC05B6 in 52-pin

PLCC package at –40 to +85°C would be ordered as: MC68HC05B6CFN.

Table 13-1 MC order numbers

Device Title Package Type Suffix

0 to 70°C

Suffix

-40 to +85°C

Suffix

-40 to +105°C

Suffix

-40 to +125°C

MC68HC05B6

52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B4

52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B8

52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B16

52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP B CB VB MB

MC68HC05B32

52-pin PLCC FN CFN N/A N/A

64-pin QFP FU CFU N/A N/A

56-pin SDIP B Contact Sales N/A N/A

MC68HC705B5 52-pin PLCC FN CFN VFN MFN

56-pin SDIP B CB VB MB

MC68HC705B16 52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

MC68HC705B16N

52-pin PLCC FN CFN VFN MFN

64-pin QFP FU CFU VFU MFU

56-pin SDIP Contact Sales

MC68HC705B32

52-pin PLCC FN CFN N/A N/A

64-pin QFP FU CFU N/A N/A

56-pin SDIP B CB N/A N/A

147

148

Freescale

13-2 MC68HC05B6

Rev. 4.1

ORDERING INFORMATION

13.1 EPROMS

For the MC68HC05B6, an 8 kbyte EPROM programmed with the customer’s software (positive

logic for address and data) should be submitted for patter n generation. All unused bytes should

be programmed to $00. The size of EPR OM which should be used for all other f amily members is

listed in Table 13-2.

The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.

13.2 Verification media

All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A

computer listing of the ROM code will be generated and retur ned with a li sting ver ification form.

The listing should be thoroughly check ed and the verification form completed, signed and returned

to F reescale. The signed verification f orm constitutes the contractual agreement for creation of the

custom mask. If desired, Freescale will program blank EPROMs (supplied by the customer) from

the data file used to create the custo m mask, to aid in the verification process.

13.3 ROM verification units (RVU)

Ten MCUs containing the customer’ s ROM pattern will be provided f or program v erification. These

units will have been made using the custom mask but are for ROM verification only. For

expediency, they are usually unmarked and are tested only at room temperature (25°C) and at

5 Volts. These RVUs are included in the mask charge and are not production parts. They are

neither backed nor guaranteed by Freescale Quality Assurance.

Table 13-2 EPR OMs for pattern gener ation

Device Size of EPROM

MC68HC05B4 8 kbyte

MC68HC05B8 8 kbyte

MC68HC05B16 16 kbyte

MC68HC05B32 32 kbyte

MC68HC05B6

Rev. 4.1 Freescale

A-1

MC68HC05B4

The MC68HC05B4 is a device similar to the MC68HC05B6, but without EEPROM and having a

reduced ROM size of 4 kb ytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B4,

with the exceptions outlined in this appendix.

A.1 Features

• 4158 bytes User ROM (including 14 bytes User vectors)

• No EEPROM

• High speed version not available

Section 3.5, ‘EEPROM’, therefore, does not apply to the MC68HC05B4, and the register at

address $07 only allows the user to select whether or not the ECLK should appear at PC2, using

bit 3 of $07. All other bits of this register read as ‘0’.

Table A-1 Mode of operation selection

IRQ pin TCAP1 pin PD3 PD4 Mode

VSS to VDD VSS to VDD X X Single chip

2VDD VDD 0 X Self check

2VDD VDD 1 0 Serial RAM loader

2VDD VDD 1 1 Jump to any address

149

150

151

152

153

Freescale

A-2 MC68HC05B6

Rev. 4.1

MC68HC05B4

Figure A-1 MC68HC05B4 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

432 bytes

User ROM

4158 bytes

self check ROM

(including 14 bytes

User vectors)

154

155

156

MC68HC05B6

Rev. 4.1 Freescale

A-3

MC68HC05B4

Figure A-2 Memory map of th e MC68HC05B4

User vectors

(14 bytes)

$1FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$02C0

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

Self-check ROM I

(192 bytes)

User ROM

(4096 bytes)

Self-check ROM II

(240 bytes)

$0F00

Reserved

MC68HC05B4 Registers

$1FF4–5

$1FF6–7

$1FF8–9

$1FFA–B

$1FFC–D

$1FFE–F

Freescale

A-4 MC68HC05B6

Rev. 4.1

MC68HC05B4

Table A-2 Register outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7/

AN7

PD6/

AN6

PD5/

AN5

PD4/

AN4

PD3/

AN3

PD2/

AN2

PD1/

AN1

PD0/

AN0

Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

ECLK control $0007 0 0 0 0 ECLK 0 0 0 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG

(2)

?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL uuuu uuuu

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 uuuu uuuu

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

MC68HC05B6

Rev. 4.1 Freescale

A-5

MC68HC05B4

A.2 Self-check mode

The self-check function available on the MC68HC05B4 provides an internal capability to

determine if the de vice is functional. Self-chec k is performed using the circuit shown in Figure A-3.

P ort C pins PC0–PC3 are monitored f or the self-check results (light emitting diodes are shown but

other devices could be used), and are interpreted as described in Table A-3. The self-check mode

is entered by applying 2 x VDD dc (via a 4.7kΩ resistor) to the IRQ pin and 5V dc input (via a 4.7kΩ

resistor) to the TCAP1 pin and then depressing the reset s witch to e x ecute a reset. After reset, the

following tests are performed automati cally and once completed they continually repeat. A good

device will exhibit flashing LEDs; a bad device will be indicated by the LEDs holding at one v alue .

Note: Self-check code can be obtained from your local Freescale representative.

I/0 — Functionally exercises ports A, B, C and D

RAM — Counter test for each RAM byte

ROM — Exclusive OR with odd ones parity result

Timer — Tracks counter registers and checks ICF1, ICF2, OCF1, OCF2 and TOF

flags

SCI — Transmission test; check for RDRF, TDRE, TC and FE flags

A/D — Check A/D functionality on internal channels: VRL, VRH and (VRL +

VRH)/2

PLM — Checks the PLM basic functio nality

Interrupts — Tests external timer and SCI interrupts

Watchdog— Tests the watchdog

Caution: This document includes descriptions of the various self-check and bootstrap

mechanisms that are currently implemented as firmware in the non-user R OM areas of

the MC68HC05B6 and related devices.

As these firmware routines are intended primarily to help F reescale’ s engineers test the

devices, they may be changed or removed at any time.

For this reas on, Freescale recommends the self-check and bootstrap routine s are not

called from the user software. Customers who do call these routines from the user

software do so at their own risk.

Freescale

A-6 MC68HC05B6

Rev. 4.1

MC68HC05B4

Table A-3 MC68HC05B4 self-check results

PC3 PC2 PC1 PC0 Remarks

1 0 0 1 Bad port

0 1 1 0 Bad port

1010Bad RAM

1011Bad ROM

1100Bad Timer

1101Bad SCI

1110Bad A/D

0001Bad PLM

0 0 1 0 Bad interrupts

0 0 1 1 Bad watchdog

Flashing Good device

All others Bad device, bad port etc.

‘0’ indicates LED on; ‘1’ indicates LED off

MC68HC05B6

Rev. 4.1 Freescale

A-7

MC68HC05B4

Figure A-3 MC68HC05B4 self-check schematic diagram

OSC1

OSC2

IRQ

TCAP2

TCMP2

TCAP1

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

VRLVSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

TCMP1

SCLK

PLMB

PLMA

TDO

RDI

VPP1

RESET

NC VRH VDD

41 7

0.01 µF

10 nF 47 µF

10 MΩ

4 MHz

22 pF 4k7 Ω

4k7 Ω

680 Ω

22 pF

4k7 Ω

680 Ω

BC239

P1 GND

+5V

2xVDD

RESET

EEPROM tested

EEPROM not tested

15 8 10

Note: For the MC68HC05B4, switches on PB5 and PB6 have no effect

All resistors are 10 kΩ, unless otherwise stated.

MC68HC05B4 (52-pin package)

Freescale

A-8 MC68HC05B6

Rev. 4.1

MC68HC05B4

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6

Rev. 4.1 Freescale

B-1

MC68HC05B8

The MC68HC05B8 is a d evice similar to the MC68HC05B6, but with an increased ROM size of

7.25 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B8, with the

exceptions outlined in this appe ndix.

B.1 Features

• 7230 bytes User ROM (including 14 bytes User vectors)

• H igh speed version available

TPG

157

Freescale

B-2 MC68HC05B6

Rev. 4.1

MC68HC05B8

Figure B-1 MC68HC05B8 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

432 bytes

User ROM

7230 bytes

self check ROM

(including 14 bytes

User vectors)

TPG

158

MC68HC05B6

Rev. 4.1 Freescale

B-3

MC68HC05B8

Figure B-2 Memory map of th e MC68HC05B8

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$02C0

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

Self-check ROM I

(192 bytes)

User ROM

(7168 bytes)

Self-check ROM II

(240 bytes)

$0300

OPTR (1 byte)

Non protected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B8 Registers

User vectors

(14 bytes)

$1FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$1FF4–5

$1FF6–7

$1FF8–9

$1FFA–B

$1FFC–D

$1FFE–F

TPG

159

Freescale

B-4 MC68HC05B6

Rev. 4.1

MC68HC05B8

Table B-1 Register outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(3) $0100 EE1P SEC Not affected

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

TPG

160

MC68HC05B6

Rev. 4.1 Freescale

C-1

MC68HC705B5

The MC68HC705B5 is a device similar to the MC68HC05B6, but with the 6 kb ytes ROM and 256

bytes EEPROM replaced by a single EPROM array. In addition, the self-check routines available

on the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B5 is intended to

operate as a one time programmab le (O TP) version of the MC68HC05B6 without EEPROM or the

MC68HC05B4, meaning that the application program can never be erased once it has been

loaded into the EPR OM. The entire MC68HC05B6 data sheet applies to the MC68HC705B5, with

the exceptions outlined in this appendix.

C.1 Features

• 6206 bytes EPROM (including 14 bytes User vectors)

• No EEPROM

• Bootstrap firmware

• Simultaneous programming of up to 4 bytes

• D ata protection for program code

• Optional pull-down resistors on port B and port C

• MC6 8HC05B6 mask options are programmable using control bits held in the options register

• 52-pin PLCC and 56-pin SDIP packages

• High speed version not available

161

162

163

164

165

Freescale

C-2 MC68HC05B6

Rev. 4.1

MC68HC705B5

Figure C-1 MC68HC705B5 block diagr am

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

programmable

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

176 bytes

RAM

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP6

256 bytes

EPROM1

6206 bytes

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

496 bytes

bootstrap ROM

EPROM

(including 14 bytes

User vectors)

166

167

168

169

170

MC68HC05B6

Rev. 4.1 Freescale

C-3

MC68HC705B5

Figure C-2 Memory map of the MC68HC705B5

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$1FF0

Stack

RAM

(176 bytes)

$0300

$0200

$1F00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

EPROM

(48 bytes)

Bootstrap ROMI

(256 bytes)

User EPROM

(5888 bytes)

Bootstrap ROMII

(240 bytes)

$0800

User EPROM1

(256 bytes)

$1EFEOptions register

Reserved

MC68HC705B5 Registers

Options register

$1EFE

User vectors

(14 bytes)

$1FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$1FF2–3

171

172

173

174

175

Freescale

C-4 MC68HC05B6

Rev. 4.1

MC68HC705B5

Table C-1 Register outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/ECLK control $0007 EPPT(1) ELAT EPGM ECLK u?00 0uuu

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(2) INTP INTN INTE SFA SFB SM WDOG(3) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL uuuu

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 uuuu

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(4) $1EFE EPP 0 RTIM RWAT WWAT PBPD PCPD Not affected

(1) This bit reflects the state of the EPP bit in the options register ($1EFE) at reset.

(2) This bit is set each time the device is powered-on.

(3) The state of the WDOG bit after reset depends on the mask option selected; ‘1’ = watchdog enabled and ‘0’ = watchdog disabled.

(4) Because this register is implemented in EPROM, reset has no effect on the state of the individual bits.

176

177

178

MC68HC05B6

Rev. 4.1 Freescale

C-5

MC68HC705B5

C.2 EPROM

The MC68HC705B5 has a total of 6206 bytes of EPROM, 256 bytes being reserved for the

EPROM 1 a rray (see Figure C-2). The EPP bit (EPROM protect) is not operative on the EPR OM1

array, making it possible to program it after the main EPROM has been programmed and

protected. The reset and interr upt vectors are located at $1FF2-$1 FFF and the EPROM control

The EPROM array is supplied by the VPP6 pin in bo th read and programming modes. Typically

the user’ s softw are will be loaded in a programming board where VPP6 is controlled by one of the

bootstrap loader routines (bootloader mode). It will then be placed in an application where no

programming occurs (user mode). In this case the VPP6 pin should be hardwired to VDD.

An erased EPROM byte reads as $00.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on, as a lower voltage could damage the device. Unless otherwise stated,

EPROM programming is guaranteed at ambient (25°C) temperature only

C.2.1 EPROM programming operation

The User program can be used to program some EPROM locations, provided the proper

procedure is followed. In par ticular, the programming sequence must be running in RAM, as the

EPROM will not be availab le for code ex ecution while the ELAT bit is set. The VPP6 switching must

occur externally, after the EPGM bit is set, f or e xample, under the control of a signal generated on

a pin by the programming routine.

Note: Unless the part has a window for reprogramming, only the cumulative programming of

bits to logic 1 is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to 4 bytes, they must be in the same group of addresses

which share the same most significant address bits; only the two LSBs can change.

Freescale

C-6 MC68HC05B6

Rev. 4.1

MC68HC705B5

C.3 EPROM registers

C.3.1 EPR OM control register

Bit 7 — Factory use only

This bit is strictly for factory use only and will always read zero.

EPPT — EPROM protect test bit

This bit is a copy of the EPROM protect bit (EPP) located in the option register . When ELAT is set,

the EPPT bit can be tested by the software to check if the EPROM arra y is protected or not, since

the EPROM content is not available when ELAT is set.

POR or external reset modifies this bit to reflect the state of the EPP bit in the options register.

ELAT — EPROM pr og rammin g latch enable bit

1 (set) – When set, this bit allows latching of th e address and up to 4 data

bytes for further programming, provided EPGM is zero.

0 (clear) – When cleared, program and interrupt routines can be executed and

data can be read in the EPROM or firmware ROM.

STOP, power-on and external reset clear this bit.

EPGM — EPROM programming bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

ELAT is set and at least one byte is written to the EPROM. It is not possible to clear EPGM by

software, but clearing ELAT will always clear EPGM.

ECLK — External clock option bit

See Section 4.3.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/ECLK control $0007 EPPT(1)

(1) This bit is a copy of the EPP bit in the options register at $1EFE and therefore its state on reset will be the same as that for the

EPP bit.

ELAT EPGM ECLK u?00 0uuu

MC68HC05B6

Rev. 4.1 Freescale

C-7

MC68HC705B5

C.4 Options register (OPTR)

Note: This register can only be written to while the device is in bootloader mode.

Bit 7 — Factory use only

Warning: This bit is strictly for factory use only and will always read zero to avoid accidental

damage to the device. Any attempt to write to this bit could result in physical damage.

EPP — EPROM protect

This bit protects the contents of the main EPR OM against accidental modification; it has no effect

on reading or executing code in the EPROM.

1 (set) – EPROM contents are protected.

0 (clear) – EPROM contents are not protected.

RTIM — Reset time

This bit can modify tPORL, i.e. the time that the RESET pin is k ept low following a pow er-on reset.

This feature is handled in the ROM part via a mask option.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT — Watchdog after reset

This bit can modify the status of the watchdog counter after reset.

1 (set) – The watchdog will be active immediately following power-on or

external reset (except in bootstrap mode).

0 (clear) – The watchdog system will be disabled after power-on or external

reset.

WWAT — Wa tchdog during WAIT mode

This bit can modify the status of the watchdog counter during WAIT mode.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1)

(1) This register is implemented in EPROM, therefore reset has no effect on the state of the individual bits.

$1EFE EPP 0 RTIM RWAT WWAT PBPD PCPD Not affected

Freescale

C-8 MC68HC05B6

Rev. 4.1

MC68HC705B5

1 (set) – The watchdog will be active during WAIT mode.

0 (clear) – The watchdog system will be disabled during WAIT mode.

PBPD – Port B pull-down resistor s

1 (set) – Pull-down resistors are connected to all 8 pins of port B; the

pull-down, RPD, is active only while the pin is an input.

0 (clear) – No pull-down resistors are connected.

PCPD — Port C pull-down resistors

1 (set) – Pull-down resistors are connected to all 8 pins of port C; the

pull-down, RPD, is active only while the pin is an input.

0 (clear) – No pull-down resistors are connected.

The combination of bit 0 and bit 1 allows the option of pull-down resistors on 0, 8 or 16 inputs. This

feature is not available on the MC68HC05B6.

C.5 Bootstrap mode

The 432 bytes of self-check firmware on the MC68HC05B6 are replaced with 496 bytes of

bootstrap firmware. The bootstrap firmware located from $0200 to $02FF and $1F00 to $1FEF

can be used to program the EPROM, to check if the EPROM is erased and to load and execute

data in RAM.

When the MC68HC705B5 is placed in the bootstrap mode, the bootstrap reset vector is fetched

and the bootstrap firmware starts to execute. Table C-2 shows the conditions required to enter

each level of bootstrap mode on the rising edge of RESET. The hold time on the IRQ and TCAP1

pins after the e xternal RESET pin is brought high is two clock cycles.

Table C-2 Mode of operation selection

IRQ pin TCAP1 pin PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD x x x Single chip

+ 9 Volts VDD 0 1 0 Erased EPROM verification

+ 9 Volts VDD x 0 0 EPROM parallel bootstrap load

+ 9 Volts VDD x 1 1 EPROM (RAM) serial bootstrap load and execute

+ 9 Volts VDD x 0 1 RAM parallel bootstrap load and execute

x = Don’t care

MC68HC05B6

Rev. 4.1 Freescale

C-9

MC68HC705B5

The bootstrap program first copies part of itself into RAM, as the program cannot be executed in

ROM during verification/programming of the EPROM. It then sets the TCMP1 output to a logic high

level.

Figure C-3 Modes of operation flow chart (1 of 2)

TCAP1 set?

IRQ at 9V?

EPROM

erased?

PD2 set?PD3 set?

PD4 set?

Reset

Program EPROM;

parallel load;

green LED flashes

Programming OK?

User mode

Red LED on

Green LED on

Non-user mode

Red LED on Green LED on

Non-user mode

Bootstrap mode

EPROM not erased

EPROM verified

Parallel EPROM bootstrap

Bad EPROM programming

Freescale

C-10 MC68HC05B6

Rev. 4.1

MC68HC705B5

Figure C-4 Modes of operation flow chart (2 of 2)

Programming OK?

Negative

address?

PD4 set?

PD3 set?

Transmit last four

programmed locations

Red LED off

Receive address

Receive four data

Execute RAM

program at $0083

Green LED on

Load next RAM

byte

RAM full?

Execute RAM

program at $0050

Program EPROM data

at address; green LED

flashes

Red LED on

Serial EPROM (RAM) bootstrap

Bad EPROM

Bootstrap RAM

programming

MC68HC05B6

Rev. 4.1 Freescale

C-11

MC68HC705B5

C.5.1 Erased EPROM verification

The flowchart in Figure C-3 and Figure C-4 shows that the on-chip bootstrap routines can be used

to check if the EPROM is erased (all $00s). If a non $00 byte is detected, the red LED stays on

and the routine will stay in a loop. Only when the whole EPROM content is verified as erased will

the green LED be turned on.

C.5.2 EPROM parallel bootstrap load

When this mode is selected, the EPROM is loaded in increasing address order with non EPROM

segments being skipped by the loader. Simultaneous programming is perfor med by reading four

bytes of data bef ore actual programming is perf ormed, thus dividing the loading time of the internal

EPROM by four.

When PD2=0, the programming time is set to 5 milliseconds and the program/v erify routine takes

approximately 15 seconds.

Parallel data is entere d through Port A, whil e the 13-bit address is output on por t B and PC0 to

PC4. If the data comes from an external EPROM, the handshake can be disabled by connecting

together PC5 and PC6. If the data is supplied via a parallel interf ace, handshaking will be pro vided

by PC5 and PC6 according to the timing diagram of Figure C-5.

During programming, the green LED fl ashes at about 3 Hz.

Upon completion of the programming operation, the EPROM content is checked against the

external data source. If programming is v erified the g reen LED stays on, while an error causes the

red LED to be turned on. Figure C-6 shows a circuit that can be used to program the EPROM (or

to load and execute data in the RAM).

Note: The entire EPROM can be loaded from the externa l source; if it is desired to leave a

segment undisturbed, the data for this segment should be all zeros.

Figure C-5 Timing diagram with handshake

Data read Data read

Address

HDSK out

(PC5)

DATA

HDSK in

(PC6)

F29

Freescale

C-12 MC68HC05B6

Rev. 4.1

MC68HC705B5

14 Figure C-6 EPROM(RAM) parallel bootstrap schematic diagram

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

VCCPGMVPP

14 22

1262728

+5V

P1 GND

+5V

100µF

22pF 4.0 MHz

1N914

1kΩ

1.0µF

22pF

10MΩ

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10 kΩ

27C64

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

RAM

EPROM

47µF+

MC68HC705B5

Note: This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C . If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

MC68HC05B6

Rev. 4.1 Freescale

C-13

MC68HC705B5

C.5.3 EPROM (RAM) serial bootstrap load and execute

The serial routine communicates through the SCI with an external host, typically a PC, by means

of an RS232 link at 9600 baud, 8-bit, no parity and full duplex.

Data format is not ASCII, but 8-bit binar y, so a compleme ntar y program must be run by the host

to supply the required format. Such a program is available for the IBM PC from Freescale.

The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed

of programming, four bytes are programmed in parallel while the data is simultaneously

transmitted and received in full duple x. This implies that while 4 bytes are being progr ammed, the

next 4 b ytes are receiv ed and the preceding 4 bytes are echoed. The format accepted by the serial

loader is as follows:

[address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)]

Address n must have the two LSBs at zero so that n, n+1, n+2 and n+3 have identical MSBs.

These bloc ks of four b ytes do not need to be contiguous, as a ne w address is transmitted f or each

new group.

The protocol is as follows:

1 The MC68HC705B5 sends the last two bytes progr ammed to the host as a

prompt; this allows verification by the host of proper programming.

1) In response to the first byte prompt, the host sends the first address byte.

2) After receiving the first addre ss byte, the MC68HC705B5 sends the next

byte programmed.

3) The exchange of data continues until the MC68HC705B5 has sent the four

data bytes and the host has sent the 2 address data b ytes and 4 data bytes.

4) If the data is non zero, it is programmed at the address provided, while th e

next address and bytes are received and the previous data is echoed.

5) Loop to 1.

After reset, the MC68HC705B5 serial bootstrap routine will first e cho two blocks of four bytes at

$0000, as no data is programmed yet.

If the data sent in is $00, no programming in the EPROM takes place, and the contents of the

accessed location are returned as a prompt. The entire EPROM memory can be read in this

fashion (serial dump). The red LED will be on if the data read from the EPROM is not $00.

Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if

the address sent by the host in the serial protocol points to the RAM.

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table C-3). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s

service-routine address.

Freescale

C-14 MC68HC05B6

Rev. 4.1

MC68HC705B5

A 10-byte stac k is also reserved at the top of the RAM allowing, for e xample, one interrupt and two

sub-routine levels.

Program execution is triggered by sending a negative (bit 7 set) high address; execution starts at

address XADR ($0083).

The RAM addresses between $0050 and $0082 are used by the loader and are therefore not

available to the user during ser ial loading/executing.

Refer to Figure C-7 shows a suitable circuit. Figure C-9 shows address and data bus timing.

C.5.4 RAM parallel bootstrap load and execute

The RAM bootstrap program will star t loading the RAM with external data (e.g. from a 2564 or

2764 EPROM). Bef ore loading a ne w byte, the state of the PD4/AN4 pin is checked; if this pin goes

to level ‘0’, or if the RAM is full, then control is given to the loaded program at address $0050.

If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6

according to Figure C-10. If the data comes from an external EPROM, the handshake can be

disabled b y connecting together PC5 and PC6.

Figure C-8 shows a circuit that can be used to load the RAM with shor t test programs. Up to 8

programs can be loaded in turn from the EPROM. Selection is accomplished by means of the

switches connected to the EPROM higher address lines (A8 through A10). If the user program sets

PC0 to level ‘1’, the exter nal EPROM will be disabled, rendering both por t A outputs and por t B

inputs available.

The EPROM parallel bootstrap loader circuit (Figure C-6) can also be used, provided VPP is tied

to VDD. The high order address lines will be at zero. The LEDs will stay off.

Table C-3 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $00E4

Timer overflow $00E7

Timer output compare $00EA

Timer input capture $00ED

IRQ $00F0

SWI $00F3

MC68HC05B6

Rev. 4.1 Freescale

C-15

MC68HC705B5

Figure C-7 EPROM (RAM) serial bootstrap schematic diagram

Red — programming error

Green — programming OK

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

Connector MAX

232

+5V

9600 BD

8-bit

no par ity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

10MΩ

4k7Ω

12 kΩ

BC239C

BC309C

10 kΩ

1nF

1N5819

1 kΩ

Serial boot

Erase check

47µF+

PD3

RDI

TDO

Erase check

Red — EPROM not erased

Green — EPROM erased

Serial boot

MC68HC705B5

Note: A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

Freescale

C-16 MC68HC05B6

Rev. 4.1

MC68HC705B5

14 Figure C-8 RAM parallel bootstrap schematic diagram

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

TCAP2

TCMP2

TCMP1

PLMB

PLMA

SCLK

TDO

RDI

VRH

VRL

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

OSC1

OSC2

TCAP1

IRQ

RESET

PD4

VPP6

VSS

GND OE

A10

A11

A12

VCCPGMVPP

14 22

1262728

+5V

3 x 4.7kΩ

+5V+5V

16 x 100kΩ

P1 GND

+5V

100µF

22pF 4.0 MHz

1N914

1kΩ

1.0µF

22pF

10MΩ

100kΩ

1N914

RESET RUN

0.01µF

2764

+5V 18 x 100 k Ω

MC68HC705B5

MC68HC05B6

Rev. 4.1 Freescale

C-17

MC68HC705B5

C.5.5 Bootstrap loader timing diagrams

Figure C-9 EPROM parallel bootstrap loader timing diagram

tCOOE

tADE

tDHE

Address

Data

tADE

tDHE

tADE

tDHE

tADE

tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (5ms nominal)

1 machine cycle = 1/(2f0(Xtal))

Freescale

C-18 MC68HC05B6

Rev. 4.1

MC68HC705B5

Figure C-10 RAM parallel loader timing diagram

tADR tDHR

Address

Data

tCR

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be

recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

MC68HC05B6

Rev. 4.1 Freescale

C-19

MC68HC705B5

C.6 DC electrical characteristics

Note: The complete table of DC electrical characteristics can be found in Section 1 1.2. The

values contained in the following tab le should be used in conjunction with those quoted

in that section.

C.7 Control timing

Note: The complete table of control timing can be found in Section 11.4. The values

contained in the following table should be used in conjunction with those quoted in that

section.

Table C-4 Additional DC electrical characteristics for MC68HC705B5

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Typ Max Unit

Input current

Port B and port C pull-down (VIN=VIH)IRPD 80 µA

EPROM absolute maximum voltage VPP6 max VDD —18V

EPROM programming voltage VPP6 15.0 15.5 16 V

EPROM programming current IPP6 ——18mA

EPROM read voltage VPP6R VDD VDD VDD V

Table C-5 Additional control timing for MC68HC705B5

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25° C)

Characteristic Symbol Min Typ Max Unit

EPROM programming time tPROG 5—20ms

Freescale

C-20 MC68HC05B6

Rev. 4.1

MC68HC705B5

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6

Rev. 4.1 Freescale

D-1

MC68HC05B16

The MC68HC05B16 is a device similar to the MC68HC05B6, but with increased RAM, ROM and

self-check ROM sizes. The entire MC68HC05B6 data sheet, including the electrical

characteristics, applies to the MC68HC05B16, with the exceptions outlined in this appendix.

D.1 Features

• 15 kbytes User ROM

• 352 bytes of RAM

• 496 bytes self-check ROM

• 52-pin PLCC, 56-pin SDIP and 64-pin QFP packages

• H igh speed version available

Maskset errata

This errata section outlines the differences between previously available masksets

(D20J, F62J and G28F) and all other masksets. Unless otherwise stated, the main

body of Appendix D refers to all these other masksets with any diff erences being noted

in this errata section.

• Certain MC68HC05B16 masksets contain the same oscillator circuitry as the

MC68HC05B6 (see Section 2.5.8.3). These are denoted by D20J , F62J and G28F.

179

180

181

182

183

Freescale

D-2 MC68HC05B6

Rev. 4.1

MC68HC05B16

D.2 Self-check routines

The self-check routines for the MC68HC05B16 are identical to those of the MC68HC05B4 with the

f ollowing exception.

The count byte on the MC68HC05B1 6 can be a ny value up to 256 ($00). The first 176 bytes are

loaded into RAM I and the remainder is loaded into RAM II startin g at $0250.

Table D-1 Mode of operation selection

IRQ pin TCAP1 pin PD3 PD4 Mode

VSS to VDD VSS to VDD X X Single chip

2VDD VDD 0XSelf check

2VDD VDD 1 0 Serial RAM loader

2VDD VDD 1 1 Jump to any address

184

MC68HC05B6

Rev. 4.1 Freescale

D-3

MC68HC05B16

Figure D-1 MC68HC05B16 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

15120 bytes

ROM

352 bytes

static RAM

496 bytes

self-check ROM

Freescale

D-4 MC68HC05B6

Rev. 4.1

MC68HC05B16

D.3 External clock

When using an e x ternal clock th e OSC1 and OSC2 pins shoul d be driv en in an tiphase , as sho wn

in Figure D-2. The tOXOV or tILCH specifications (see Section 11.4) do not apply when using an

exter nal clock input. The equivalent specification of th e exter nal clock source should be used in

lieu of tOXOV or tILCH.

Figure D-2 Oscillator connections

Ceramic resonator

2 – 4MHz Unit

RS(typ) 10 Ω

C040 pF

C14.3 pF

COSC1 30 pF

COSC2 30 pF

RP1 – 10 MΩ

Q 1250 —

Crystal

2MHz 4MHz Unit

RS(max) 400 75 Ω

C057pF

C1812ƒF

COSC1 15 – 40 15 – 30 pF

COSC2 15 – 30 15 – 25 pF

RP10 10 MΩ

Q 30 000 40 000 —

OSC1 OSC2

MCU

COSC2

COSC1

OSC1 OSC2

MCU

NCExternal

clock

OSC1 OSC2

(d) Typical crystal and ceramic resonator parameters

(b) Crystal equivalent circuit

(a) Crystal/ceramic resonator

oscillator connections

MC68HC05B6

Rev. 4.1 Freescale

D-5

MC68HC05B16

Figure D-3 Memory map of the MC68HC05B16

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$3FF0

Stack

RAM1

(176 bytes)

$0250

$0200

$3E00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

ROM

(48 bytes)

User ROM

(15104 bytes)

Self-check ROM

(496 bytes)

$0300

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B16 Registers

RAM11

(176 bytes)

$3DFE

User vectors

(14 bytes)

$3FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$3FF4–5

$3FF6–7

$3FF8–9

$3FFA–B

$3FFC–D

$3FFE–F

Freescale

D-6 MC68HC05B6

Rev. 4.1

MC68HC05B16

Table D-2 Register outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(3) $0100 EE1P SEC Not affected

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

MC68HC05B6

Rev. 4.1 Freescale

E-1

MC68HC705B16

The MC68HC705B16 is a device similar to the MC68HC05B6, but with increased RAM and

15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in

the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B16 is an OTPROM

(one-time progr ammab le R OM) v ersion of the MC 68HC05B16, meaning that once the application

program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data

sheet applies to the MC68HC705B16, with the exceptions outlined in this appendix.

To ensure correct operation of the MC 68HC705B16 after power-on, the device must

be reset a second time after power-on. This can be done in software using the

MC68HC705B16 watchdog.

The following software sub-routine should be used:

RESET2 BSET 0, $0C Start watchdog

STOP STOP causes immediate watchdog

system reset

The interrupt vector at $3FF0 and $3FF1 must be initialised with the RESET2

address value.

185

186

187

188

189

Freescale

E-2 MC68HC05B6

Rev. 4.1

MC68HC705B16

E.1 Features

• 15 k bytes EPROM

• 352 bytes of RAM

• 576 bytes bootstrap ROM

• Simultaneous programming of up to 8 bytes of EPROM

• Optional pull-down resistors available on all port B and port C pins

• 52-pin PLCC and 64-pin QFP packages

• Hig h speed version not available

Note: The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not

apply to the MC68HC705B16. Data specific to the MC68HC705B16 can be found in

this appendix.

Figure E-1 MC68HC705B16 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷ 32

PLMA D/A

PLMB D/A

8-bit

15168 bytes

EPROM

352 bytes

static RAM

576 bytes

VPP6

bootstrap ROM

190

191

192

193

194

MC68HC05B6

Rev. 4.1 Freescale

E-3

MC68HC705B16

Figure E-2 Memory map of the MC68HC705B16

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$3FF0–1

Stack

RAM1

(176 bytes)

$0250

$0200

$3E00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

E/EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

EPROM

(48 bytes)

User EPROM

(15104 bytes)

Bootstrap ROM11

(496 bytes)

$0300

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC705B16 Registers

RAM11

(176 bytes)

$3DFE

$3DFF Mask option register

Mask option register $3DFE

Bootstrap ROM1

(80 bytes)

User vectors

(14 bytes)

$3FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$3FF4–5

$3FF6–7

$3FF8–9

$3FFA–B

$3FFC–D

$3FFE–F

195

196

197

198

199

Freescale

E-4 MC68HC05B6

Rev. 4.1

MC68HC705B16

Table E-1 Register outlin e

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $3DFE RTIM RWAT WWAT PBPD PCPD Not affected

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

200

201

202

203

204

MC68HC05B6

Rev. 4.1 Freescale

E-5

MC68HC705B16

E.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH specifications (see Section E.8) do not apply when using an

external clock input. The equivalent specification of the external clock source should be used in

lieu of tOXOV or tILCH.

E.3 EPROM

The MC68HC705B16 memory map is given in Figure E-2. The device has a total of 15168 bytes

of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM.

The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the

user’ s software would be loaded into a programming board where VPP6 is controlled b y one of the

bootstrap loader routines. It would then be placed in an application where no programming occurs.

In this case the VPP6 pin should be hardwired to VDD.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on. Failure to do so could result in permanent damage to the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C) tempe rature

only.

E.3.1 EPROM read operation

The execution of a program in the EPROM address range or a load from the EPROM are both

read operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0’

which automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM.

Reading the EPROM with the E6LAT bit set will give data that does not correspond to the actual

memor y content. As interr upt vectors are in EPROM, they will not be loaded when E6LAT is set.

Similarly, the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the

VPP6 pin must be at the VDD level. When entering the STOP mode, the EPROM is automatically

set to the read mode.

Note: An erased byte reads as $00.

E.3.2 EPROM program operation

Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.

However, the user program can be used to program some EPROM locations if the proper

procedure is followed. In par ticular, the programming sequence must be running in RAM, as the

205

206

207

208

209

Freescale

E-6 MC68HC05B6

Rev. 4.1

MC68HC705B16

EPROM will not be available for code execution while the E6LAT bit is set. The VPP6 switching

must occur externally after the E6PGM bit is set, for example under control of a signal generated

on a pin by the programming routine.

Note: When the part becomes a PROM, only the cumulative programming of bits to logic ‘1’

is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to eight bytes, these bytes must be in the same group

of addresses which share the same most sign ificant addre ss bits; only the three lea st significant

bits can change.

E.3.3 EPROM/EEPROM/ECLK control register

E6LAT — EPROM programming latch enable bit

1 (set) – Address and up to eight data bytes can be latched into the EPROM

for further programming providing the E6PGM bit is cleared.

0 (clear) – Data can be read from the EPROM or firmware R OM; the E6PGM bit

is reset to zero when E6LAT is ‘0’.

STOP, power-on and external reset clear the E6LAT bit.

Note: After the tERA1 erase time or tPROG1 programming time, the E6LAT bit ha s to be reset

to zero in order to clear the E6PGM bit.

E6PGM — EPROM program enable bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

E6LAT is set and at least one byte is written to the EPROM. It is not possib le to clear this bit using

software but clearing E6LAT will always clear E6PGM.

Note: The E6PGM bit can never be set while the E6LAT bit is at zero.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

Table E-2 EPROM control bits description

E6LAT E6PGM Description

0 0 Read/execute in EPROM

1 0 Ready to write address/data to EPROM

1 1 programming in progress

210

211

212

MC68HC05B6

Rev. 4.1 Freescale

E-7

MC68HC705B16

ECLK

See Section 4.3.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An er ase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been sele cted, E1ERA cannot be changed.

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for further

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note: After the tERA1 erase time or tPROG1 programming ti me, the E1LAT bit has to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Interna l charge pump generator switched off.

When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.

This bit cannot be set before the data is selected, and once this bit has been set it can only be

cleared by clearing the E1LAT bit.

A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table E-3.

Note: The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.

Table E-3 EEPROM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

Freescale

E-8 MC68HC05B6

Rev. 4.1

MC68HC705B16

E.3.4 Mask option register

RTIM — Reset time

This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT — Watchdog after reset

This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system

is disabled after power-on or extern al reset but when this b it is set, it will be active immediately

after the following resets (except in bootstrap mode).

WWAT — Watchdog during WAIT mode

This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog

system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT

mode.

PBPD — P o rt B pull-down

This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down,

RPD, is active on a given pin only while it is an input.

PCPD — P o rt C pull-down

This bit, when programmed, connects a resistive pull-down on each pin of port C . This pull-down,

RPD, is active on a given pin only while it is an input.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Mask option register (MOR)(1)

(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

$3DFE RTIM RWAT WWAT PBPD PCPD Not affected

MC68HC05B6

Rev. 4.1 Freescale

E-9

MC68HC705B16

E.3.5 EEPROM options register (OPTR)

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Par t 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit

in the options register.

1 (set) – Part 2 of the EEPROM array is not protected; all 256 bytes of

EEPROM can be accessed for any read, erase or programming

operations.

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful.

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.

Note: The EEPROM1 protect function is disabled while in bootstrap mode.

SEC — Secure bit

This bit allows the EPROM and EEPROM1 to be secured from exter nal access. When this bit is

in the erased state (set), the EPROM and EEPROM1 content is not secured and the d evice may

be used in non user mode. When the SEC bit is programmed to ‘z ero’, the EPROM and EEPROM1

content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the

EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be

entered into th e EPROM erase verification mode with PD1 set. When the SEC bit is changed, its

new value will have no effect until the next power-on or external reset.

1 (set) – EEPR OM/EPROM not protected.

0 (clear) – EEPROM/EPROM protected.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1)

(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

$0100 EE1P SEC Not affected

Freescale

E-10 MC68HC05B6

Rev. 4.1

MC68HC705B16

E.4 Bootstrap mode

The 432 b ytes of self-check firmwa re on the MC68HC05B6 are repl aced by 576 b ytes of bootstrap

fir m ware. A detailed description of the modes of operation within bootstrap mode is given below.

The bootstrap program in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can

be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load

and execute data in RAM.

After reset, while going to the bootstrap mode, the vector located at address $ 3FEE and $3FEF

(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap

mode, the IRQ pin should be at + 9V with the TCAP1 pin ‘high’ during transition of the RESET pin

from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external

RESET pin is brought high.

When the MC68HC705B16 is placed in the bootstrap mode, the bootstrap reset vector is fetched

and the bootstrap firmware starts to execute. Table E-4 shows the conditions required to enter

each level of bootstrap mode on the rising edge of RESET.

The bootstrap program first copies part of itself in RAM (except ‘RAM parallel load’), as the

program cannot be e xecuted in ROM during verification/programming of the EPROM. It then sets

the TCMP1 output to a logic hi gh level.

Table E-4 Mode of operation selection

IRQ pin TCAP1 pin PD1 PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD x x x x Single chip

+ 9 Volts VDD 0 0 x 0 Erased EPROM verification (EEV)

+ 9 Volts VDD 1000

Erased EPROM verification; erase EEPROM; EPROM/EEPROM

parallel program/verify

+ 9 Volts VDD 1010

Erased EPROM verification; erase EEPROM;

EPROM/EEPROM/ RAM serial bootstrap load and execute

+ 9 Volts VDD x x 0 1 RAM parallel bootstrap load and execute (if SEC bit = 1)

+ 9 Volts VDD x x 1 1 Serial EPROM/EEPROM/RAM bootloader (if SEC = 1)

x = Don’t care

MC68HC05B6

Rev. 4.1 Freescale

E-11

MC68HC705B16

Figure E-3 Modes of operation flow chart (1 of 2)

PD3 set?

EEPROM1 erased?

TCAP1 set?

IRQ at 9V?

PD2 set?PD4 set?

Reset

Program EPROM;

parallel load; green LED

flashes

User mode

Green LED on

Red LED on

Non-user mode

Red LED on Green LED on

Non-user mode

Bootstrap mode

EPROM not erased

EPROM verified

Parallel E/EEPROM bootstrap

Bad EPROM programming

PD1 set?

Bulk erase EEPROM1

Red LED on

Red LED off

Erased EPROM verification

SEC bit active?

EPROM

erased?

Programming OK?

Freescale

E-12 MC68HC05B6

Rev. 4.1

MC68HC705B16

14 Figure E-4 Modes of operation flow chart (2 of 2)

Negative

address?

PD4 set?

PD3 set?

Transmit last four

programmed locations

Receive address

Receive four data

Execute RAM

program at $008B

Green LED on

Load next RAM

byte

RAM1 full?

Execute RAM

program at $0050

Program E/EEPROM

data at address; green

LED flashes

Serial E/EEPROM (RAM) bootstrap

Parallel bootstrap RAM

SEC bit set?

Red LED flashes

MC68HC05B6

Rev. 4.1 Freescale

E-13

MC68HC705B16

E.4.1 Erased EPROM verification

If a non $00 byte is detected, the red LED is turned on and the routine stops (see Figure E-3 and

Figure E-4). Only when the entire EPROM content is verified as erased does the green LED switch

on. PD1 is then check ed. If PD1=0, the bootstrap program stops here and no programming occurs

until such time as a high level is sensed on PD1. If PD1=1, the bootstrap program proceeds to

erase the EEPROM1 for a nominal 100 ms (4.0 MHz crystal). It is then checked for complete

erasure; if a non $FF byte is detected, the red LED is turned on, and erase is performed a second

time, and so on until total erasure is verified. At this point, both EPROM and EEPROM1 are

completely erased and the security bit is cleared. The programming operation can then be

performed. A schematic diagram of the circuit required f or erased EPROM v erification is shown in

Figure E-7.

E.4.2 EPROM/EEPROM parallel bootstrap

Before the parallel bootstrap routines begin, the erased EPROM verification program is executed

as described in Section E.4.1. When PD2=0, the pro gramming time is set to 5 milliseconds with

the bootstrap program and verify for the EPROM taking approximately 15 seconds. The EPROM

is loaded in increasing address order with non EPROM segments being skipped by the loader.

Simultaneous programming is performed by reading eight bytes of data before actual

programming is perform ed, thus the loading time of the internal EPROM is divided by eight.

Parallel data is entered throug h Port A, while the 14-bit addre ss is o utput on port B, PC0 to PC4

and TCMP2. If the data comes from an external EPROM, the handshake can be disabled by

connecting together PC5 and PC6. If the data is supplied b y a parallel interface , handshaking will

be provided by PC5 and PC6 according to the timing diagram of Figure E-5 (see also Figure E-6).

During programming, the green LED will flash at about 3 Hz.

Upon completion of the programming ope ration, the contents of the EPROM and EEPROM1 are

check ed against the e xternal data source. If programming is verified the green LED stays on, while

an error will cause the red LED to be turned on. Figure E-7 is a schematic diagram of a circuit that

can be used to program the EPROM or to load and execute data in the RAM.

Note: The entire EPROM and EEPROM1 can be loaded from the external source; if it is

desired to leave a segment undisturbed, the data for this segment should b e all zeros

for EPROM data and all $FFs for EEPROM1 data.

Freescale

E-14 MC68HC05B6

Rev. 4.1

MC68HC705B16

Figure E-5 Timing diagram with handshake

Figure E-6 Parallel EPROM loader timing dia gram

Data read Data read

Address

HDSK out

(PC5)

Data

HDSK in

(PC6)

F29

tCOOE

tADE

tDHE

Address

Data

tADE

tDHE

tADE

tDHE

tADE

tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (5ms nominal for EPROM; 10ms for EEPROM1))

1 machine cycle = 1/(2f0(Xtal))

MC68HC05B6

Rev. 4.1 Freescale

E-15

MC68HC705B16

Figure E-7 EPROM Parallel bootstrap schematic diagram

VCC

281

VPP PGM

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

14 22

+5V

P1 GND

+5V

100µF

22pF

4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

27C128

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

RAM

EPROM

green LED — EPROM erased

47µF+

Erase check & boot

EPROM erase

check

VPP1

red LED — EPROM not erased

Boot

Erase check

A13

MC68HC705B16

MCU

Note: This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C . If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

Freescale

E-16 MC68HC05B6

Rev. 4.1

MC68HC705B16

E.4.3 EEPROM/EPROM/RAM serial bootstrap

For erased EPROM verification, PD4 must be at ‘0’. In this case, erased EPROM verification

executes as described in Section E.4.1 before control is given to the serial routine.

If PD4 is at ‘1’, the program initially checks the state of the security bit. If the security bit is active

(‘0’), the program will not enter serial bootstrap and the red LED will flash. Otherwise the ser ial

bootstrap program will be executed according to Figure E-3 and Figure E-4.

The serial routine comm unicates through the SCI with an e xternal host, typically a PC, by means

of an RS232 link at 9600 baud, 8-bit, no parity and full duple x. Ref er to Figure E-8 f or a schematic

diagram of a suitable circuit.

Note: Data format is not ASCII, but 8-bit binary, so a complementary program must be run b y

the host to supply the required f ormat. Such a program is av ailable fo r the IBM PC from

Freescale.

The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed

of programming the 15 kbytes, four bytes are programmed while the data is simultaneously

transmitted back and f orward in full duplex. This implies that while 4 bytes are being programmed

the next 4 bytes are received and the preceding 4 bytes are echoed. The format accepted by the

serial loader is as f o llo ws:

1) EPROM locations

[address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)]

Address n must hav e the tw o least significant bits at zero so that n, n+1, n+2 and n+3

have identical most significant bits. These blocks of four bytes do not need to be

contiguous, as a new address is transmitted for each new group.

2) EEPROM1 locations

[address n high] [address n lo w] [data(n)] [dummy data 1] [dummy data 2] [dummy data 3]

The same four byte protocol of data exchange is used, but only the first data value is

programmed at address n. The three follo wing dummy data v alues must be sent to be

in agre ement with the protocol, b u t a r e no t significant.

The protocol is as follows:

1) The MC68HC705B16 sends the last two bytes programmed to the host as a

prompt; this also allows the host to verify that programming has been carried

out correctly.

2) In response to the first byte prompt, the host sends the first address byte.

3) After receiving the first address byte, the MC68HC705B16 sends the next

byte programmed.

MC68HC05B6

Rev. 4.1 Freescale

E-17

MC68HC705B16

Figure E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram

Green LED — programming ended

Flashing green LED — programming

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

connector MAX

232

+5V

9600 BD

8-bit

no par ity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

1nF

1N5819

1 kΩ

Serial boot

Erase check

47µF+

PD3

RDI

TDO

Erase check

Red LED — EPROM not erased

Green LED — EPROM erased

Serial boot &

serial boot

Erase check and serial boot

EPROM erase check

VPP1

U2 MC68HC705B16

MCU (socket)

Note: A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

Freescale

E-18 MC68HC05B6

Rev. 4.1

MC68HC705B16

4) The exchange of data continues until the MC68HC705B16 has sent the four

data bytes and the host has sent the 2 address data bytes and 4 data bytes.

5) If the data is different from $00 for EPROM or $FF for EEPROM, it is

programmed at the address provided, while the next address and bytes are

received and the previous data is echoed.

6) Loop to 1.

After reset, the MC68HC705B16 serial bootstrap routine will first echo two blocks of four bytes at

$00, as no data is programmed yet.

If the data received is $00 for EPROM locations or $FF for EEPROM locations, no programming

in the EPROM and EEPR OM1 tak es place, and the contents of the accessed location are returned

as a prompt. The entire EPROM/EEPROM memory can be read in this fashion (serial dump).

Warning: When using this function with a programmed device, the device must be placed into

RAM/EPR OM/EEPR OM serial bootstrap mode without EPR OM er ase chec k (PD4 = 1).

Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if

the address sent by the host in the serial protocol points to the RAM.

RAM bytes $008B–$00E3 and $0250–$02ED are available for user test programs. A 10-byte stack

resides at the top of RAMI, allowing, for example, one interr upt and two sub-routine levels. The

RAM addresses between $0050 and $008A are used by the loader and are therefore not a vailab le

to the user during serial loading/executing.

If the SEC bit is at ‘1’, program execution is triggered by sending a negative (bit 7 set) high

address; execution starts at address XADR ($008B).

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table E-5). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s service

routine address.

Table E-5 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $02EE

Timer overflow $02F1

Timer output compare $02F4

Timer input capture $02F7

IRQ $02FA

SWI $02FD

MC68HC05B6

Rev. 4.1 Freescale

E-19

MC68HC705B16

E.4.4 RAM parallel bootstrap

The program first checks the state of the security bit. If th e SEC b it is active, i.e. ‘0’, the program

will not enter the RAM bootstrap mode and the red LED will flash. Otherwi se the RAM b ootstrap

program will start loading the RAM with external data (e .g. from a 2564 or 2764 EPROM). Before

loading a new byte the state of the PD4/AN4 pi n is checked. If this pin goes to level ‘0’, or if the

RAM is full, then control is given to the loaded program at address $0050. See Figure E-3 and

Figure E-4.

If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6

according to Figure E-9. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6.

Figure E-10 provides a schematic diagram of a circuit that can be used to load the RAM with short

test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is

accomplished by means of the switches connected to the EPROM higher address lines (A8

through A10). If the user program sets PC0 to le vel ‘1’, this will disable the e xternal EPROM, thus

rendering both port A output and port B input available. The EPROM parallel bootstrap loader

schematic can also be used (Figure E-7), provided VPP is at VDD level. The high order address

lines will be at zero. The LEDs will stay off.

Figure E-9 Parallel RAM loader timing diagram

tADR tDHR

Address

Data

tCR

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

Freescale

E-20 MC68HC05B6

Rev. 4.1

MC68HC705B16

E.4.4.1 Jump to start of RAM ($0050)

PD4 must be high during the first 49 program cycles and pulled low before the 68th cycle for

immediate jump execution at address $0050.

Figure E-10 RAM parallel bootstrap schematic diagram

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

TCAP2

TCMP2

TCMP1

PLMB

PLMA

SCLK

TDO

RDI

VRH

VRL

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

OSC1

OSC2

TCAP1

IRQ

RESET

PD4

VPP6

VSS

GND OE

A10

A11

A12

VCCPGMVPP

14 22

1262728

+5V

3 x 4.7kΩ

+5V

16 x 100kΩ

P1 GND

+5V

100µF

22pF 4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

2764

+5V 18 x 100 k Ω

VPP1

U2 MC68HC705B16

MCU (socket)

MC68HC05B6

Rev. 4.1 Freescale

E-21

MC68HC705B16

E.5 Absolute maximum ratings

Note: This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric fields. However, it is recommended that normal

precautions be taken to avoid the application of any voltages higher than those given

in the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inputs should be tied to either VSS or VDD.

Table E-6 Absolute maximum ratings

Rating Symbol Value Unit

Supply voltage(1)

(1) All voltages are with respect to VSS.

VDD – 0.5 to +7.0 V

Input voltage (Except VPP1 and VPP6)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC705B16)

– Extended (MC68HC705B16C)

– Industrial (MC68HC705B16V)

– Automotive (MC68HC705B16M)

TATL to TH

0 to +70

–40 to +85

–40 to +105

–40 to +125

°C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

Freescale

E-22 MC68HC05B6

Rev. 4.1

MC68HC705B16

E.6 DC electrical characteristics

Table E-7 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching

currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

VDD – 0.4

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—0.1

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

IDD

—

5.0

1.0

1.5

0.9

—

1.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

MC68HC05B6

Rev. 4.1 Freescale

E-23

MC68HC705B16

Table E-8 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ(2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—0.1

0.2

0.4

0.6

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,

RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

IDD

—

2.0

0.8

1.0

0.4

—

1.5

0.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO,

SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching

currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

Freescale

E-24 MC68HC05B6

Rev. 4.1

MC68HC705B16

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

MC68HC05B6

Rev. 4.1 Freescale

E-25

MC68HC705B16

E.7 A/D converter characteristics

Table E-9 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 1LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1)

(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

Minimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator

—

tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2)

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

—

tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3)

(3) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

Freescale

E-26 MC68HC05B6

Rev. 4.1

MC68HC705B16

Table E-10 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 1LSB

Quantization error Uncertainty due to converter resolution — ± 1LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 2LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

MC68HC05B6

Rev. 4.1 Freescale

E-27

MC68HC705B16

E.8 Control timing

Table E-11 Control timing for 5V opera tion

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

4.2

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

2.1

MHz

Cycle time (see Figure 9-1)t

CYC 480 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

tPROG

—

Timer (see Figure E-11)

Resolution(2)

Input capture pulse width

Input capture pulse period

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

tRESL

tTH, tTL

tTLTL

125

—(3)

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 tCYC.

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 125 — ns

Interrupt pulse period tILIL —(4)

(4) The minimum period tILIL should not be less than the number of cycle times it takes to

execute the interrupt service routine plus 21 tCYC.

—t

CYC

OSC1 pulse width(5)

(5) tOH and tOL should not total less than 238ns.

tOH, tOL 90 — ns

Write/Erase endurance(6)(7)

(6) At a temperature of 85°C

— 10000 cycles

Data retention(6)(7)

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

— 10 years

Freescale

E-28 MC68HC05B6

Rev. 4.1

MC68HC705B16

Table E-12 Control timing for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

2.0

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

—

1.0

MHz

Cycle time (see Figure 9-1)t

CYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV —100ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure E-11)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 200 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) —10years

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 tCYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 tCYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

MC68HC05B6

Rev. 4.1 Freescale

E-29

MC68HC705B16

E.9 EPROM electrical characteristics

Figure E-11 Timer relationship

Table E-13 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

EPROM

Absolute maximum voltage

Programming voltage

Programming current

Read voltage

VPP6 max

VPP6

IPP6

VPP6R

VDD

—

VDD

—

15.5

VDD

Table E-14 Control timing for 5V opera tion

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time tPROG 520ms

Table E-15 Control timing for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time tPROG 520ms

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

Freescale

E-30 MC68HC05B6

Rev. 4.1

MC68HC705B16

MC68HC05B6

Rev. 4.1 Freescale

F-1

MC68HC705B16N

The MC68HC705B16N is a device similar to the MC68HC05B6, but with increased RAM and

15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in

the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B16N is an OTPROM

(one-time progr ammab le R OM) v ersion of the MC 68HC05B16, meaning that once the application

program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data

sheet applies to the MC68HC705B16N, with the exceptions outlined in this appendix.

The MC68HC705B16N is a new device identical to the MC68HC705B16 in its memory

map and functionality, except for the following:

• Bootloader

• Reset pulse width

• Reset twice issue

• Electrical characteristics

On the MC68HC705B16 there was a requirement to reset the device a second time

after power-on. On the MC68HC705B16N this reset twice action is now not required.

The interrupt service routine for the vector at address $3FF0–$3FF1 is no longer

required, as the vector will nev er be f etched. Howev er, the interrupt service routine and

vector contents required for the MC68HC705B16 (see Section E, page E–1) can also

be kept on the MC68HC705B16N with no detrimen tal effect, although they will never

be used.

213

214

215

216

217

Freescale

F-2 MC68HC05B6

Rev. 4.1

MC68HC705B16N

F.1 Features

• 15 kbytes EPROM

• 352 bytes of RAM

• 576 bytes bootstrap ROM

• Simultaneous programming of up to 8 bytes of EPROM

• Optional pull-down resistors available on all port B and port C pins

• 52-pin PLCC and 64-pin QFP packages

Note: The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not

apply to the MC68HC705B16N. Data specifi c to the MC68HC705B16N ca n be found

in this appendix.

Figure F-1 MC68HC705B16N block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷ 32

PLMA D/A

PLMB D/A

8-bit

15168 bytes

EPROM

352 bytes

static RAM

576 bytes

VPP6

bootstrap ROM

218

219

220

221

222

MC68HC05B6

Rev. 4.1 Freescale

F-3

MC68HC705B16N

Figure F-2 Memory map of the MC68HC705B16N

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$3FF0–1

Stack

RAM1

(176 bytes)

$0250

$0200

$3E00

$0050

Port A data direction register

Port B data direction register

Port C data direction register

E/EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Page 0 User

EPROM

(48 bytes)

User EPROM

(15104 bytes)

Bootstrap ROM11

(496 bytes)

$0300

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC705B16 Registers

RAM11

(176 bytes)

$3DFE

$3DFF Mask option register

Mask option register $3DFE

Bootstrap ROM1

(80 bytes)

User vectors

(14 bytes)

$3FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$3FF4–5

$3FF6–7

$3FF8–9

$3FFA–B

$3FFC–D

$3FFE–F

223

224

225

226

227

Freescale

F-4 MC68HC05B6

Rev. 4.1

MC68HC705B16N

Table F-1 Register outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $3DFE RTIM RWAT WWAT PBPD PCPD Not affected

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

228

229

230

231

232

MC68HC05B6

Rev. 4.1 Freescale

F-5

MC68HC705B16N

F.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH specifications (see Section F.9) do not apply when using an

external clock input. The equivalent specification of the external clock source should be used in

lieu of tOXOV or tILCH.

F.3 RESET pin

When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied

to the RESET input f or a minimum period of 3.0 machine cycles (tCYC). For more information see

Section 9.1.3.

F.4 EPROM

The MC68HC705B16N memory map is given in Figure F-2. The device has a total of 15168 bytes

of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM.

The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the

user’ s software would be loaded into a programming board where VPP6 is controlled b y one of the

bootstrap loader routines. It would then be placed in an application where no programming occurs.

In this case the VPP6 pin should be hardwired to VDD.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on. Failure to do so could result in permanent damage to the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C) tempe rature

only.

F.4.1 EPROM read operation

The execution of a program in the EPROM address range or a load from the EPROM are both

read operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0’

which automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM.

Reading the EPROM with the E6LAT bit set will give data that does not correspond to the actual

memor y content. As interr upt vectors are in EPROM, they will not be loaded when E6LAT is set.

Similarly, the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the

VPP6 pin must be at the VDD level. When entering the STOP mode, the EPROM is automatically

set to the read mode.

Note: An erased byte reads as $00.

233

234

235

236

237

Freescale

F-6 MC68HC05B6

Rev. 4.1

MC68HC705B16N

F.4.2 EPROM program operation

Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.

However, the user program can be used to program some EPROM locations if the proper

procedure is followed. In par ticula r, the programming sequence must be r unning in RAM, as th e

EPROM will not be available for code execution while the E6LAT bit is set. The VPP6 switching

must occur externally after the E6PGM bit is set, for example under control of a signal generated

on a pin by the programming routine.

Note: When the part becomes a PROM, only the cumulative programming of bits to logic ‘1’

is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to eight bytes, these bytes must be in the same group

of addresses which share the same most sign ificant addre ss bits; only the three lea st significant

bits can change.

F.4.3 EPROM/EEPROM/ECLK control register

E6LAT — EPROM programming latch enable bit

1 (set) – Address and up to eight data bytes can be latched into the EPROM

for further programming providing the E6PGM bit is cleared.

0 (clear) – Data can be read from the EPROM or firmware R OM; the E6PGM bit

is reset to zero when E6LAT is ‘0’.

STOP, power-on and external reset clear the E6LAT bit.

Note: After the tERA1 erase time or tPROG1 programming time, the E6LAT bit ha s to be reset

to zero in order to clear the E6PGM bit.

E6PGM — EPROM program enable bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

E6LAT is set and at least one byte is written to the EPROM. It is not possib le to clear this bit using

software but clearing E6LAT will always clear E6PGM.

Note: The E6PGM bit can never be set while the E6LAT bit is at zero.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/EEPROM/ECLK control $0007 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000

238

MC68HC05B6

Rev. 4.1 Freescale

F-7

MC68HC705B16N

ECLK

See Section 4.3.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An er ase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been sele cted, E1ERA cannot be changed.

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for further

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note: After the tERA1 erase time or tPROG1 programming ti me, the E1LAT bit has to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Interna l charge pump generator switched off.

When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.

This bit cannot be set before the data is selected, and once this bit has been set it can only be

cleared by clearing the E1LAT bit.

A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table F-3.

Note: The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.

Table F-2 EPROM control bits description

E6LAT E6PGM Description

0 0 Read/execute in EPROM

1 0 Ready to write address/data to EPROM

1 1 programming in progress

Freescale

F-8 MC68HC05B6

Rev. 4.1

MC68HC705B16N

F.4.4 Mask option register

RTIM — Reset time

This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT — Watchdog after reset

This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system

is disabled after power-on or extern al reset but when this b it is set, it will be active immediately

after the following resets (except in bootstrap mode).

WWAT — Watchdog during WAIT mode

This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog

system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT

mode.

PBPD — P o rt B pull-down

This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down,

RPD, is active on a given pin only while it is an input.

Table F-3 EEPROM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Mask option register (MOR)(1)

(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

$3DFE RTIM RWAT WWAT PBPD PCPD Not affected

MC68HC05B6

Rev. 4.1 Freescale

F-9

MC68HC705B16N

PCPD — Port C pull-down

This bit, when programmed, connects a resistive pull-down on each pin of port C . This pull-down,

RPD, is active on a given pin only while it is an input.

F.4.5 EEPR OM options register (OPTR)

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Par t 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit

in the options register.

1 (set) – Part 2 of the EEPROM array is not protected; all 256 bytes of

EEPROM can be accessed for any read, erase or programming

operations.

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful.

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.

Note: The EEPROM1 protect function is disabled while in bootstrap mode.

SEC — Secure bit

This bit allows the EPROM and EEPROM1 to be secured from exter nal access. When this bit is

in the erased state (set), the EPROM and EEPROM1 content is not secured and the d evice may

be used in non user mode. When the SEC bit is programmed to ‘z ero’, the EPROM and EEPROM1

content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the

EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be

entered into th e EPROM erase verification mode with PD1 set. When the SEC bit is changed, its

new value will have no effect until the next power-on or external reset.

1 (set) – EEPR OM/EPROM not protected.

0 (clear) – EEPROM/EPROM protected.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1)

(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

$0100 EE1P SEC Not affected

Freescale

F-10 MC68HC05B6

Rev. 4.1

MC68HC705B16N

F.5 Bootstrap mode

Oscillator divide-by-two is forced in bootstrap mode.

The 432 b ytes of self-chec k firmwa re on the MC68HC05B6 are repl aced by 576 b ytes of bootstrap

fir m ware. A detailed description of the modes of operation within bootstrap mode is given below.

The bootstrap program in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can

be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load

and execute data in RAM.

After reset, while going to the bootstrap mode, the vector located at address $ 3FEE and $3FEF

(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap

mode, the IRQ pin should be at 2xVDD with the TCAP1 p in ‘high’ dur ing transition of the R ESET

pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the

external RESET pin is brought high.

When the MC68HC705B16N is pl aced in the bootstrap mode, the bootstrap reset vector will be

fetched and the bootstrap firmware will star t to execute. Table F-4 shows the conditions re quired

to enter each level of bootstrap mode on the rising edge of RESET.

The bootstrap program will first copy part of itself in RAM (except ‘RAM parallel load’), as the

program cannot be executed in ROM during verification/programming of the EPROM. It will then

set the TCMP1 output to a logic high le vel, unlike the MC68HC05B6 which keeps TCMP1 low . This

can be used to distinguish between the two circuits and, in particular , for selection of the VPP le vel

and current capability.

Table F-4 Mode of operation selection

IRQ pin TCAP1 pin PD1 PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD x x x x Single chip

2xVDD VDD 0 0 0 0 Erased EPROM verification

2xVDD VDD 0010EPROM verification;

2xVDD VDD 1000

EPROM verification; erase EEPROM;

EPROM/EEPROM parallel program/verify

2xVDD VDD 1010

Erased EPROM verification; erase EEPROM;

EPROM parallel program/verify (no E2)

2xVDD VDD 1 0 0 1 Jump to start of RAM ($0051); SEC bit = NON ACTIVE

2xVDD VDD x011

Serial RAM load/execute – similar to MC68HC05B6 but can fill RAM I

and II

x = Don’t care

MC68HC05B6

Rev. 4.1 Freescale

F-11

MC68HC705B16N

Figure F-3 Modes of operation flow chart (1 of 2)

IRQ at 2xVDD?

Red LED on

TCAP1=VDD?

SEC bit active?

PD3 set?

User mode

Non-user mode

PD4 set?

Jump to RAM

($0051)

PD1 set?

Red LED on

EPROM erased?

Green LED on

Verify EPROM

SEC bit active?

PD3 set? Y

SEC bit active?

EPROM

verified?

Red LED on

Serial RAM

load/execute

Red LED on

Erased EPROM

verification

Green LED on

Reset

Erased EPROM verification

EPROM verify

PD2 set?

Non-user mode

PD2 set? Non-user mode

Freescale

F-12 MC68HC05B6

Rev. 4.1

MC68HC705B16N

14 Figure F-4 Modes of operation flow chart (2 of 2)

Go to $300

(EPROM only)

PD3 set?

Red LED on

Go to $100

(EPROM and EEPROM)

Green LED on

EEPROM erased?

EEPROM byte

erase and verify

Data verified?

Parallel program

and verify

Parallel program

MC68HC05B6

Rev. 4.1 Freescale

F-13

MC68HC705B16N

F.5.1 Erased EPROM verification

If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see Figure F-3

and Figure F-4). Only when the whole EPR OM content is verified as erased will the green LED be

turned on. PD1 is then check ed. If PD1=0, the bootstrap program stops here and no programming

occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap program

proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then checked

f or compl ete er as ure; if an y EEPR O M b yte i s not er ased , the p rog ram w ill stop before er asing the

SEC byte. When both EPROM and EEPROM1 are completely erased and the security bit is

cleared the programming operation can be perf ormed. A schematic diagr am of the circuit required

f or erased EPROM verification is shown in Figure F-8.

F.5.2 EPROM/EEPROM parallel bootstrap

Within this mode there are variou s su bsection s wh ich ca n be utilised by correctly configur i ng the

port pins shown in Table F-4.

The erased EPROM verification program will be executed first as described in Section F.5.1. The

EPROM programming time is set to 10 milliseconds with the bootstrap program and verify for the

EPROM taking approximately 15 seconds. The EPR OM will be loaded in increasing address order

with non EPROM segments being skipped by the loader . Simultaneous programming is perf ormed

by reading eight bytes of data before actual programming is perfor med, thus divid ing the load ing

time of the internal EPROM by 8. If any block of 8 EPROM bytes or 1 EEPROM byte of data is in

the erased state, no programming takes place, thus speeding up the execution time.

Parallel data is entered throug h Port A, while the 15-bit addre ss is o utput on port B, PC0 to PC4

and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,

handshake will be provided by PC5 and PC6 according to the timing diagram of Figure F-6 (see

also Figure F-7).

During programming, the green LED will flash at about 3 Hz.

Upon completion of the programming operation, the EPROM and EEPROM1 content will be

checked against the external data source. If programming is ver ified the green LED will stay on,

while an error will cause the red LED to be turned on. Figure F-7 is a schematic diagram of a circuit

which can be used to program the EPROM or to load and execute data in the RAM.

Note: The entire EPROM and EEPROM1 can be loaded from the external source; if it is

desired to leave a segment undisturbed, the data for this segment sh ould be all $00s

for EPROM data and all $FFs for EEPROM1 data.

Freescale

F-14 MC68HC05B6

Rev. 4.1

MC68HC705B16N

Figure F-5 Timing diagram with handshake

Figure F-6 P arallel EPRO M loader timing diagram

Data read Data read

Address

HDSK out

(PC5)

Data

HDSK in

(PC6)

F29

tCOOE

tADE

tDHE

Address

Data

tADE

tDHE

tADE

tDHE

tADE

tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (10 ms nominal for EPROM; 10ms for EEPROM1))

1 machine cycle = 1/(2f0(Xtal))

MC68HC05B6

Rev. 4.1 Freescale

F-15

MC68HC705B16N

Figure F-7 EPROM parallel bootstrap schematic diagram

VCC

281

VPP PGM

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

14 22

+5V

P1 GND

+5V

100µF

22pF

4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

27C256

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

EPROM

green LED — EPROM erased

47µF+

Erase verify & boot

EPROM

check

VPP1

red LED — EPROM not erased

Boot

Erase check

A13

MC68HC705B16N

MCU

A14

Note: This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C . If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

EPROM verify

Erase check

& boot

(EPROM only)

Erase check &

boot (EPROM

& EEPROM)

Freescale

F-16 MC68HC05B6

Rev. 4.1

MC68HC705B16N

F.5.3 Serial RAM loader

This mode is similar to the RAM load/execute program for the MC68HC05B6 described in

Section 2.2, with the additional features listed below. Table F-4 shows the entry conditions

required for this mode.

If the first byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count

byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes)

then the code continues to fill RAM II. In this case the count byte is ignored and the program

execution begins at $0051 once the total RAM area is filled or if no data is received for 5

milliseconds.

The user must take care when using branches or jumps as his code will be relocated in RAM I and

II. If the user intends to use the stac k in his program, he should send NOP’s to fill the desired stack

area.

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table F-5). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an explicit jump (JMP) opcode is needed to cause the desired jump to the users

ser vice-routine address.

F.5.3.1 Jump to start of RAM ($0051)

The Jump to start of RAM program will be executed when the device is brought out of reset with

PD1 and PD4 at ‘1’ and PD2 and PD3 at ‘0’.

Table F-5 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $0063

Timer overflow $0060

Timer output compare $005D

Timer input capture $005A

IRQ $0057

SWI $0054

MC68HC05B6

Rev. 4.1 Freescale

F-17

MC68HC705B16N

Figure F-8 RAM load and execute schematic diagram

Green LED — programming ended

Flashing green LED — programming

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

Connector MAX

232

+5V

9600 BD

8-bit

no par ity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

1nF

1N5819

1 kΩ

Serial boot

47µF+

PD3

RDI

TDO

Erase check

Red LED — EPROM not erased

Green LED — EPROM erased

Serial boot

Serial RAM

VPP1

MC68HC705B16N

MCU (socket)

Jump to $51

RAM load

& ex ecute

load & execute

Note: A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

Freescale

F-18 MC68HC05B6

Rev. 4.1

MC68HC705B16N

Figure F-9 Parallel RAM loader ti ming diagram

tADR tDHR

Address

Data

tCR

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

MC68HC05B6

Rev. 4.1 Freescale

F-19

MC68HC705B16N

F.6 Absolute maximum ratings

Note: This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric fields. However, it is recommended that normal

precautions be taken to avoid the application of any voltages higher than those given

in the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inputs should be tied to either VSS or VDD.

Table F-6 Absolute maximum ratings

Rating Symbol Value Unit

Supply voltage(1)

(1) All voltages are with respect to VSS.

VDD – 0.5 to +7.0 V

Input voltage (Except VPP1 and VPP6)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC705B16N)

– Extended (MC68HC705B16NC)

– Industrial (MC68HC705B16NV)

– Automotive (MC68HC705B16NM)

TATL to TH

0 to +70

–40 to +85

–40 to +105

–40 to +125

°C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

Freescale

F-20 MC68HC05B6

Rev. 4.1

MC68HC705B16N

F.7 DC electrical characteristics

Table F-7 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching

currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

VDD – 0.4

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—0.1

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11.2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

IDD

—

5.0

1.0

1.5

0.9

—

1.5

100

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

MC68HC05B6

Rev. 4.1 Freescale

F-21

MC68HC705B16N

Table F-8 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = TL to TH)

Characteristic(1) Symbol Min Typ(2) Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—0.1

0.2

0.4

0.6

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,

RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

IDD

—

2.0

0.8

1.0

0.4

—

1.5

0.5

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO,

SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching

currents inherent in CMOS designs (see Section 2).

(2) Typical values are at mid point of voltage range and at 25°C only.

Freescale

F-22 MC68HC05B6

Rev. 4.1

MC68HC705B16N

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

MC68HC05B6

Rev. 4.1 Freescale

F-23

MC68HC705B16N

F.8 A/D converter characteristics

Table F-9 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 1LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1)

(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

Minimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator

—

tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2)

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

—

tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3)

(3) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

Freescale

F-24 MC68HC05B6

Rev. 4.1

MC68HC705B16N

Table F-10 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 1LSB

Quantization error Uncertainty due to converter resolution — ± 1LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 2LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

MC68HC05B6

Rev. 4.1 Freescale

F-25

MC68HC705B16N

F.9 Control timing

Table F-11 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

4.2

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

2.1

MHz

Cycle time (see Figure 9-1)t

CYC 480 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

tPROG

—

Timer (see Figure F-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

tRESL

tTH, tTL

tTLTL

125

—(3)

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 tCYC.

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 125 — ns

Interrupt pulse period tILIL —(4)

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 tCYC.

—t

CYC

OSC1 pulse width(5)

(5) tOH and tOL should not total less than 238ns.

tOH, tOL 90 — ns

Write/Erase endurance(6)

(6) At a temperature of 85°C

— 10000 cycles

Data retention(6)(7)

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

— 10 years

Freescale

F-26 MC68HC05B6

Rev. 4.1

MC68HC705B16N

Table F-12 Cont rol timing for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

2.0

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

—

1.0

MHz

Cycle time (see Figure 9-1)t

CYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

– 40 to 105 (industrial)

– 40 to 125 (automotive)

tPROG

—

Timer (see Figure F-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 200 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) —10years

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 tCYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 tCYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

MC68HC05B6

Rev. 4.1 Freescale

F-27

MC68HC705B16N

F.10 EPROM electrical characteristics

Figure F-10 Timer relationship

Table F-13 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

EPROM

Absolute maximum voltage

Programming voltage

Programming current

Read voltage

VPP6 max

VPP6

IPP6

VPP6R

VDD

—

VDD

—

15.5

VDD

Table F-14 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time tPROG 520ms

Table F-15 Control timing for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time tPROG 520ms

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

Freescale

F-28 MC68HC05B6

Rev. 4.1

MC68HC705B16N

MC68HC05B6

Rev. 4.1 Freescale

G-1

MC68HC05B32

The MC68HC05B32 is a device similar to the MC68HC05B6, but with increased RAM and ROM

sizes. The entire MC68HC05B6 data sheet applies to the MC68HC05B32, with the exceptions

outlined in this appendix.

G.1 Features

• 3 1248 bytes User ROM

• No page zero ROM

• 528 bytes of RAM

• 52-pin PLCC and 64-pin QFP packages for -40 to +85°C operating temperature range

(extended)

• 56-pin SDIP package for 0 to 70°C operating temperature range

• High speed version not available

Note: Preliminar y electrical specifications for the MC68HC05B32 should be taken as being

similar to those for the MC68HC705B32. When silicon is fully availab le , the part will be

re-characterised and new data made available.

G.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH specifications (see Section H.9) do not apply when using an

external clock input. The equivalent specification of the external clock source should be used in

lieu of tOXOV or tILCH.

239

240

241

242

Freescale

G-2 MC68HC05B6

Rev. 4.1

MC68HC05B32

Figure G-1 MC68HC05B32 block diag ram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

32 kbytes

ROM

528 bytes

static RAM

638 bytes

VPP6

self-check ROM

MC68HC05B6

Rev. 4.1 Freescale

G-3

MC68HC05B32

Figure G-2 Memory map of the MC68HC05B32

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$7FF0

Stack

RAMI

(176 bytes)

$0250

$0200

$0050

Port A data direction register

Port B data direction register

Port C data direction register

EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

User ROM

(31232 bytes)

Bootloader ROMIII

(478 bytes)

$03B0

$7FE0

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC05B32 Registers

RAMII

(352 bytes)

$0400

Bootloader ROMI

(80 bytes)

Bootloader ROM vectors

(16 bytes)

Bootloader ROMII

(80 bytes)

$7E00

$7FDE

User vectors

(14 bytes)

$7FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$7FF4–5

$7FF6–7

$7FF8–9

$7FFA–B

$7FFC–D

$7FFE–F

Freescale

G-4 MC68HC05B6

Rev. 4.1

MC68HC05B32

Table G-1 Register outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $7FDE RTIM RWAT WWAT PBPD PCPD Not affected

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in ROM; therefore reset has no effect on the individual bits.

MC68HC05B6

Rev. 4.1 Freescale

H-1

MC68HC705B32

Preliminary

MC68HC705B32

Maskset errata

This errata section outlines the diff erences between two pre viously availab le masksets

(D59J and D40J) and all other masksets. Unless otherwise stated, the main body of

Appendix G refers to all these other masksets with any differences being noted in this

errata section.

• For the D59J and D40J masksets, the MCU only requires that a logic zero is

applied to the RESET input for 1.5 tCYC.

• For D59J, 16 cycle POR delay option (tPORL) is not available

• For the D59J maskset, oscillator divide ratio DIV10 is forced in Bootstrap mode.

On all other revisions DIV2 is forced.

For the D59J:

The STOP Idd is greater than the expected value of 120µA at 5 volts Vdd at a

temperature of 20°C with the CAN module enabled and in SLEEP mode. Typically the

STOP Idd is in the region of 2.0 milliamps at 20°C.

The fault lies with the design of the EPROM array. When the STOP instruction is

executed, the ne xt opcode in memory is present on the data bus. A f ault in the EPR OM

write data latch circuitry causes a latch to be driven to logic 0 on both sides when the

data bus for that bit is logic 1. This results in increasing STOP Idd of 450µA per data

bus bit set to a logic 1. If all data bus bits are set to logic 1 (i.e. next opcode is $FF,

STX 0,X) the STOP Idd shall be in the region of 3.6mA.

The minimum ST OP Idd is achiev ed by ensuring the opcode immediately f ollowing the

ST OP instruction is data $00. This corresponds to BRSET 0,ADDRESS,LABEL. If the

label points to the next sequential instruction in memory then this has the effect of a 5

cycle NOP but note that the carry bit in the condition code register may be altered by

the BRSET instruction.

243

244

245

246

247

Freescale

H-2 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

Example

STOP

BRSET 0,$00,NEXT

NEXT any CPU instruction

The address compared may be any address in the page zero memory and the only

restriction is that it should not be a re gister with flags cleared by reading the register.

The example shows the address compared to be por t A data register and this should

not cause any problems in any applications.

High STOP Idd will be variable dependant upon the opcode following the STOP

instruction. The more bits set in the following opcode, the higher the STOP Idd. The

work around described abov e may be used on any 68HC05B32 or corrected version of

the 68HC705B32 wi thout p roblem. It simp ly adds a 5 cycle delay to the recovery from

ST OP and 3 bytes of additional code per STOP instruction but ma y alter the state of the

carr y bit in the CCR.

Also for the D59J:

The EEPROM programming circuit only fully supports 16-byte simultaneous

programming mode and does not support single byte programming correctly.

The f ault lies with the design of the EPR OM array. A fault in the EPR OM write data latch

circuitry causes a latch to be driven to logic 0 on both sides when the data bus for that

bit is logic 1. When the ELAT signal is remo ved, there is a race condition with the EPBS

signal which results in the data bus value being copied to all the EPR OM latches.

Since 16-byte simultaneous programming functions correctly, it is a relatively simple

matter to emulate single byte programming by first initialising all 16 data latches to $00

and then writing the data to be written to the appropria te address.

This problem does not affect user application software in normally circumstances since

it only applies to programming the EPROM array. The serial programming software

should always simulate 16-byte programming. The Freescale software for

programming the 705B32 from an IBM compatible PC functions in 16 byte

programming mode. This program therefore correctly programs the EPROM.

In normal circumstances this errata does not affect the user application software. This

only affects software that programs the EPROM array. The parallel programming

bootloader software within the 705B32 ROM performs 16-byte programming and so

functions correctly.

248

249

250

251

252

MC68HC05B6

Rev. 4.1 Freescale

H-3

MC68HC705B32

Preliminary

The MC68HC705B32 is an EPROM version of the MC68HC05B32, with the ROM replaced by a

similar amount of EPROM. The entire MC68HC05B6 data sheet applies to the MC68HC705B32,

with the exceptions outlined in this appendix.

H.1 Features

• 31246 bytes user EPROM

• No page zero EPROM at $20–$4F

• 528 bytes of RAM

• 638 bytes bootstrap ROM instead of 432 bytes of self-check ROM

• Simultaneous programming of EPROM with up to 16 bytes of different data

• -40 to +85°C oper ating temperature range (extended)

• 52-pin PLCC, 56-pin SDIP and 64-pin QFP packages

• High speed version not available

Note: The electrical characteristics from the MC68HC05B6 data sheet should not be used f or

the MC68HC705B32. Data specific to this device can be found in Section H.7 and

Section H.9.

253

254

255

256

257

Freescale

H-4 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

Figure H-1 MC68HC705B32 block diagram

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

Port B

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Port C

PC0

PC1

PC2/ECLK

PC3

PC4

PC5

PC6

PC7

16-bit

timer

Port D

PD0/AN0

PD1/AN1

PD2/AN2

PD3/AN3

PD4/AN4

PD5/AN5

PD6/AN6

PD7/AN7

Oscillator

COP watchdog

RESET

IRQ

VDD

VSS

OSC1

OSC2

M68HC05

CPU

SCI

A/D converter

PLM

TCAP1

TCAP2

TCMP1

TCMP2

VRH

VRL

RDI

SCLK

TDO

VPP1

256 bytes

EEPROM

Charge pump

÷ 2 / ÷32

PLMA D/A

PLMB D/A

8-bit

32 kbytes

EPROM

528 bytes

static RAM

638 bytes

VPP6

bootstrap ROM

258

259

260

261

262

MC68HC05B6

Rev. 4.1 Freescale

H-5

MC68HC705B32

Preliminary

Figure H-2 Memory map of the MC68HC705B32

Bootstrap ROM vectors

(16 bytes)

Port B data register

Port C data register

Port D input data register

Port A data register $0000

Compare low register 2

A/D data register

$0000

I/O

(32 bytes)

$0020

$00C0

$0100

$7FDE

$7FF0–1

Stack

RAM1

(176 bytes)

$0250

$0200

$0050

Port A data direction register

Port B data direction register

Port C data direction register

E/EEPROM/ECLK control register

A/D status/control register

Pulse length modulation A

Pulse length modulation B

Miscellaneous register

SCI baud rate register

SCI control register 1

SCI control register 2

SCI status register

SCI data register

Timer control register

Timer status register

Capture high register 1

Capture low register 1

Compare high register 1

Compare low register 1

Counter high register

Counter low register

Alternate counter high register

Alternate counter low register

Capture high register 2

Capture low register 2

Compare high register 2

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

$0010

$0011

$0012

$0013

$0014

$0015

$0016

$0017

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

Bootstrap ROMII

(80 bytes)

$03B0

$7FE0

Options register

Unprotected (31 bytes)

Protected (224 bytes)

EEPROM

(256 bytes)

$0101

$0120

$0100Options register

Reserved

MC68HC705B32 Registers

RAM11

(352 bytes)

$0400

Mask option register

Mask option register $7FDE

Bootstrap ROMI

(80 bytes)

User EPROM

(31232 bytes)

Bootstrap ROMIII

(478 bytes)

$7E00

User vectors

(14 bytes)

$7FF2–3 SCI

Timer overflow

Timer output compare 1& 2

Timer input capture 1 & 2

External IRQ

SWI

Reset/power-on reset

$7FDF

$7FF4–5

$7FF6–7

$7FF8–9

$7FFA–B

$7FFC–D

$7FFE–F

263

264

265

266

267

Freescale

H-6 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

Table H-1 Register outline

reset

Port A data (PORTA) $0000 Undefined

Port B data (PORTB) $0001 Undefined

Port C data (PORTC) $0002 PC2/

ECLK

Undefined

Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined

Port A data direction (DDRA) $0004 0000 0000

Port B data direction (DDRB) $0005 0000 0000

Port C data direction (DDRC) $0006 0000 0000

EPROM/EEPROM/ECLK control $0007 0 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000

A/D data (ADDATA) $0008 0000 0000

A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000

Pulse length modulation A (PLMA) $000A 0000 0000

Pulse length modulation B (PLMB) $000B 0000 0000

Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) ?001 000?

SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu

SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined

SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000

SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u

SCI data (SCDR) $0011 0000 0000

Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0

Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined

Input capture high 1 $0014 Undefined

Input capture low 1 $0015 Undefined

Output compare high 1 $0016 Undefined

Output compare low 1 $0017 Undefined

Timer counter high $0018 1111 1111

Timer counter low $0019 1111 1100

Alternate counter high $001A 1111 1111

Alternate counter low $001B 1111 1100

Input capture high 2 $001C Undefined

Input capture low 2 $001D Undefined

Output compare high 2 $001E Undefined

Output compare low 2 $001F Undefined

Options (OPTR)(3) $0100 EE1P SEC Not affected

Mask option register (MOR)(4) $7FDE RTIM RWAT WWAT PBPD PCPD Not affected

(1) This bit is set each time there is a power-on reset.

(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.

(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.

(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.

268

269

270

MC68HC05B6

Rev. 4.1 Freescale

H-7

MC68HC705B32

Preliminary

H.2 External clock

When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see

Figure D-2). The tOXOV or tILCH specifications (see Section H.9) do not apply when using an

external clock input. The equivalent specification of the external clock source should be used in

lieu of tOXOV or tILCH.

H.3 RESET pin

When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied

to the RESET input f or a minimum period of 3.0 machine cycles (tCYC). This diff ers from the 05B6,

05B4, 705B5, 05B8, 05B16, 705B16 and the 05B32, which require 1.5 tCYC. For more inf ormation

see Section 9.1.3.

H.4 EPROM

The MC68HC705B32 memory map is given in Figure H-2. The device has a total of 31246 bytes

of EPROM. 14 bytes are used for the reset and interr upt vectors from address $7FF2 to $7FFF.

The main EPROM block of 31232 bytes is located from $0400 to $7DFF. One byte of EPROM is

used as an options register and is located at address $7FDE.

The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the

user’s software will be loaded into a programming board where VPP6 is contro lled by one of the

bootstrap loader routines. It will then be placed in an a pplication where no programming occurs.

In this case the VPP6 pin should be hardwired to VDD.

Warning: A minimum VDD voltage must be applied to the VPP6 pin at all times, including

power-on. Failure to do so could result in permanent damage to the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C) tempe rature

only.

Freescale

H-8 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

H.4.1 EPROM read operation

The execution of a program in the EPROM address range or a load from the EPROM are both

read operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0 ’

which automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM.

Reading the EPROM with the E6LAT bit set will give data that does not correspond to the actual

memor y content. As interrup t vectors are in EPROM, they will not be loaded when E6LAT is set.

Similarly, the bootstrap ROM routines cannot be executed when E6LAT is set. In re ad mode, the

VPP6 pin must be at the VDD level. When entering the STOP mode, the EPROM is automatically

set to the read mode.

Note: An erased byte reads as $00.

H.4.2 EPROM program operation

Typically, the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.

However, the user program can be used to program some EPROM locations if the proper

procedure is followed. In par ticula r, the programming sequence must be r unning in RAM, as th e

EPROM will not be available for code execution while the E6LAT bit is set. The VPP6 switching

must occur externally after EPGM is set, for e xample under control of a signal gener ated on a pin

by t h e pro gramming ro utine.

Note: Unless the part has a window for reprogr amming, only the cumulative programming of

bits to logic ‘1’ is possible if multiple programming is made on the same byte.

To allow simultaneous programming of up to sixteen b ytes, these bytes m ust be in the same group

of addresses which share the same most significant address bits; only the f our LSBs can change.

H.4.3 EPROM/EEPROM control register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

EPROM/EEPROM/ECLK control $0007 0 E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000

MC68HC05B6

Rev. 4.1 Freescale

H-9

MC68HC705B32

Preliminary

E6LAT — EPROM programming latch enable bit

1 (set) – Address and up to sixteen data bytes can be latched into the EPROM

for further programming providing the E6PGM bit is cleared. When

programming the EPR OM, all other 15 addresses must be latched

with the erased state ($00) or corruption may occur.

0 (clear) – Data can be read from the EPROM or firmware ROM; the E6PGM bit

is reset to zero when E6LAT is ‘0’.

STOP, power-on and external reset clear the E6LAT bit.

Note: After the tERA1 erase time or tPROG1 programming ti me, the E6LAT bit has to be reset

to zero in order to clear the E6PGM bit.

E6PGM — EPROM program enable bit

This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after

E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using

software but cleari ng E6LAT will always clear E6PGM.

Note: All combinations are not shown in the above table, since the E6PGM bit is cleared when

the E6LAT bit is at zero, and will result in a read condition.

ECLK

See Section 4.3.

E1ERA — EEPROM erase/programming bit

Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the

EEPROM is for erasing or programming purposes.

1 (set) – An er ase operation will take place.

0 (clear) – A programming operation will take place.

Once the program/erase EEPROM address has been sele cted, E1ERA cannot be changed.

Table H-2 EPROM control bits description

E6LAT E6PGM Description

0 0 Read/execute in EPROM

1 0 Ready to write address/data to EPROM

1 1 programming in progress

Freescale

H-10 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

E1LAT — EEPROM programming latch enable bit

1 (set) – Address and data can be latched into the EEPROM for furt her

program or erase operations, providing the E1PGM bit is cleared.

0 (clear) – Data can be read from the EEPROM. The E1ERA bit and the E1PGM

bit are reset to zero when E1LAT is ‘0’.

STOP, power-on and external reset clear the E1LAT bit.

Note: After the tERA1 erase time or tPROG1 programming time, the E1LAT bit ha s to be reset

to zero in order to clear the E1ERA bit and the E1PGM bit.

E1PGM — EEPROM charge pump enable/disable

1 (set) – Internal charge pump generator switched on.

0 (clear) – Internal charge pump generator switched off.

When the charge pump generator is on, the resulting high v oltage is applied to the EEPROM array.

This bit cannot be set before the data is selected, and once this bit has been set it can onl y be

cleared by clearing the E1 LAT bit.

A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table H-3.

Note: The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.

Table H - 3 EEPR OM control bits description

E1ERA E1LAT E1PGM Description

0 0 0 Read condition

0 1 0 Ready to load address/data for program/erase

0 1 1 Byte programming in progress

1 1 0 Ready for byte erase (load address)

1 1 1 Byte erase in progress

MC68HC05B6

Rev. 4.1 Freescale

H-11

MC68HC705B32

Preliminary

H.4.4 Mask option register

RTIM

This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset.

1 (set) – tPORL = 16 cycles.

0 (clear) – tPORL = 4064 cycles.

RWAT

This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system

is disabled after power-on or external reset but when this bit is set, it will be active immediately

after the following resets (except in bootstrap mode).

WWAT

This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog

system is disabled in WAIT mode but when this bit is set, the watchdog will be active in WAIT

mode.

PBPD

This bit, when programmed, connects a resistive pull-down on all 8 pins of port B. This pull-down,

RPD, is active on a given pin only while it is an input.

PCPD

This bit, when programmed, connects a resistiv e pull-down on all 8 pins of port C. This pull-down,

RPD, is active on a given pin only while it is an input.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Mask option register (MOR)(1)

(1) Because this register is implemented in EPROM, reset has no effect on the individual bits.

$7FDE RTIM RWAT WWAT PBPD PCPD Not affected

Freescale

H-12 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

H.4.5 Options register (OPTR)

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two par ts,

both working from the VPP1 charge pump. Par t 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 b ytes from $0120 to $01FF) is protected by the EE1P bit

of the options register.

1 (set) – Part 2 of the EEPROM array is not protected; all 256 bytes of

EEPROM can be accessed for any read, erase or programming

operations.

0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful.

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.

Note: The EEPROM1 protect function is disabled while in bootstrap mode.

SEC — Secure bit

This bit allows the EPROM and EEPROM1 to be secured from external access. When this bit is

in the erased state (set), the EPROM and EEPROM1 content is not secured and the device may

be used in non user mode. When the SEC bit is programmed to ‘z ero’, the EPR OM and EEPROM1

content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the

EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be

entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its

new value will have no effect until the next power-on or external reset.

1 (set) – EEPROM/EPROM not protected.

0 (clear) – EEPROM/EPROM protected.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State

on reset

Options (OPTR)(1)

(1) Because this register is implemented in EEPROM, reset has no effect on the individual bits.

$0100 EE1P SEC Not affected

MC68HC05B6

Rev. 4.1 Freescale

H-13

MC68HC705B32

Preliminary

H.5 Bootstrap mode

Oscillator divide-by-two is forced in bootstrap mode.

The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 654 bytes of bootstrap

fir mware. A detailed description of the modes of operation within bootstrap mode is given below.

The bootstrap program in mask ROM address locations $0200 to $024F, $03B0 to $3FFF, $7E00

to $7FDD and $7FE0 to $7FEF can be used to program the EPROM and the EEPROM, to check

if the EPROM is erased or to load and execute data in RAM.

After reset, while going to the bootstrap mode, the vector located at address $7FEE and $7FEF

(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap

mode, the IRQ pin should be at 2xVDD with the TCAP1 pin ‘high’ during transition of the RESET

pin from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the

e xternal RESET pin is brought high.

When the MC68HC705B32 is placed in the bootstrap mode, the bootstrap reset vector will be

fetched and th e bo otstrap firmware will start to execute. Table H-4 shows the co nditio ns requ ired

to enter each level of bootstrap mode on the rising edge of RESET.

The bootstrap program will first copy part of itself in RAM (except ‘RAM parallel load’), as the

program cannot be executed in ROM during ver ification/programming of the EPROM. It will then

set the TCMP1 output to a logic high level, unlike the MC68HC05B6 which keeps TCMP1 low . This

can be used to distinguish betw een the tw o circuits and, in particular , f or selection of the VPP le vel

and current capability.

Table H-4 Mode of operation selection

IRQ pin TCAP1 pin PD1 PD2 PD3 PD4 Mode

VSS to VDD VSS to VDD xxxxSingle chip

2xVDD VDD 0 0 0 x Erased EPROM verification

2xVDD VDD 1000

EPROM verification; erase EEPROM;

EPROM/EEPROM parallel program/verify

2xVDD VDD 0100

Erased EPROM verification;

no EEPROM erase if SEC is zero (parallel mode)

2xVDD VDD 1100

Erased EPROM verification; erase EEPROM;

EPROM parallel program/verify (no E2)

2xVDD VDD x 1 1 0 Jump to start of RAM ($0051); SEC bit = ACTIVE

2xVDD VDD 0101EPROM and EEPROM verification; SEC bit = ACTIVE (parallel mode)

2xVDD VDD xx11

Serial RAM load/execute – similar to MC68HC05B6 but can fill RAM I,

II and III

x = Don’t care

Freescale

H-14 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

Figure H-3 Modes of operation flow chart (1 of 2)

Red LED on

TCAP1=VDD?

SEC bit active?PD3 set?

Reset

User mode

Red LED on

Non-user mode

Bootstrap mode Parallel E/EEPROM bootstrap

PD4 set?

Erased EPROM verification

Serial RAM

load/execute

PD2 set?

Jump to RAM

($0051)

PD2 set?

PD1 set?

SEC bit active? Red LED on

PD4 set? Y

EPROM erased?

Green LED on

PD1 set?

Erase EEPROM1

Red LED off

SEC bit active?

IRQ at 2xVDD?

MC68HC05B6

Rev. 4.1 Freescale

H-15

MC68HC705B32

Preliminary

Figure H-4 Modes of operation flow chart (2 of 2)

Data verified?

PD2 set?

Red LED on

ABase address = $400

(EPROM only)

Base address = $100

(EPROM and EEPROM)

Green LED on

PD2 set? NY

Base address = $400

(EPROM only)

Base address = $400

(EPROM only)

Freescale

H-16 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

H.5.1 Erased EPROM verification

If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see

Figure H-3 and Figure H-4). Only when the whole EPROM content is verified as erased will th e

green LED be tur ned on. PD1 is then che cked. If PD1=0, the bootstrap p rogram stops here and

no programming occurs until such time as a high le vel is sensed on PD1. If PD1 = 1, the bootstrap

program proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then

checked for complete erasure; if any EEPROM byte is not erased, the program will stop before

erasing the SEC byte . When both EPROM and EEPR OM1 are completely erased and the security

bit is cleared the programming operation can be performed. A schematic diagram of the circuit

required for erased EPROM veri fication is shown in Figure H-7.

H.5.2 EPROM/EEPROM parallel bootstrap

Within this mode there are various subse cti ons wh ich can be util ised by correctly configuring the

port pins shown in Table H-4.

The erased EPROM verification program will be executed first as described in Section H.5.1.

When PD2=0, the programming time is set to 5 milliseconds with the bootstrap program and v erify

for the EPROM taking approximately 15 seconds. The EPROM will be loaded in increasing

address order with non EPROM segments being skipped by the loader. Simultaneous

programming is performed by reading sixteen bytes of data before actual programming is

perf ormed, thus dividing the loading time of the internal EPROM b y 16. If any b loc k of 16 EPROM

bytes or 1 EEPROM byte of data is in the erased state, no programming takes place, thus

speeding up the execution time.

Parallel data is entered through Port A, while the 15 -bit address i s output o n port B, PC0 to PC4

and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be

disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,

handshake will be provided by PC5 and PC6 according to the timing diagram of Figure H-5 (see

also Figure H-6).

During programming, the green LED will flash at about 3 Hz.

Upon completion of the programming operation, the EPROM and EEPROM1 content will be

checked against the external data source. If programming is verified the green LED will stay on,

while an error will cause the red LED to be turned on. Figure H-7 is a schematic diagram of a

circuit which can be used to program the EPROM or to load and execute data in the RAM.

Note: The entire EPROM and EEPROM1 can be loaded from the external source; if it is

desired to leave a segment undisturbed, the data for this segment should be all $00s

for EPROM data and all $FFs for EEPROM1 data.

MC68HC05B6

Rev. 4.1 Freescale

H-17

MC68HC705B32

Preliminary

Figure H-5 Timing diagram with handshake

Figure H-6 Parallel EPROM loader timing diagram

Data read Data read

Address

HDSK out

(PC5)

Data

HDSK in

(PC6)

F29

tCOOE

tADE

tDHE

Address

Data

tADE

tDHE

tADE

tDHE

tADE

tDHE

tCOOE tCOOE tCDDE

tADE max (address to data delay) 5 machine cycles

tDHA min (data hold time) 14 machine cycles

tCOOE (load cycle time) 117 machine cycles < tCOOE < 150 machine cycles

tCDDE (programming cycle time) tCOOE + tPROG (5ms nominal for EPROM; 10ms for EEPROM1))

1 machine cycle = 1/(2f0(Xtal))

Freescale

H-18 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

Figure H-7 EPROM parallel bootstrap schematic diagram

VCC

281

VPP PGM

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

GND OE

14 22

+5V

P1 GND

+5V

100µF

22pF

4.0 MHz

1N914

1kΩ

1.0µF

22pF

100kΩ

1N914

RESET RUN

0.01µF

TDO

SCLK

RDI

VRL

TCAP2

PD7

PD6

PD5

PD3

PD2

PD1

PD0

PD4

+5V

3VPP

VPP6

PC7

PC5

PC4

PC3

PC2

PC1

PC0

PC6

A10

A12

A11

A12

A11

A10

HDSK out

HDSK in

Short circuit if

handshake not used

100 kΩ

TCMP1

TCMP2

PLMA

PLMB

470Ω

red LED

green LED

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

27C256

VRH

red LED — programming failed

green LED — programming OK

1nF

1N5819

1 kΩ

RAM

EPROM

green LED — EPROM erased

47µF+

Erase check & boot

EPROM erase

check

VPP1

red LED — EPROM not erased

Boot

Erase check

A13

MC68HC705B32

MCU

A14

Verify

Program

EPROM

Note: This circuit is recommended for programming only at 25°C and not for use in the

end application, or at temperatures other than 25°C. If used in the end application,

VPP6 should be tied to VDD to avoid damaging the device.

MC68HC05B6

Rev. 4.1 Freescale

H-19

MC68HC705B32

Preliminary

H.5.3 Serial RAM loader

This mode is similar to the RAM load/execute program for the MC68HC05B6 described in

Section 2.2, with the additional features listed below. Table H-4 shows the entry conditions

required f or this mode .

If the first byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count

byte follow ed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes)

then the code continues to fill RAM II then RAM III. In this case the count byte is ignored and the

program execution begins at $0051 once the total RAM area is filled or if no data is received for 5

milliseconds.

The user must take care when using branches or jumps as his code will be relocated in RAM I, II

and III. If the user intends to use the stac k in his program, he should send NOP’ s to fill the desired

stack area.

In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see

Table H-5). This allows programmers to use their own service-routine addresses. Each

pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,

because an explicit jump (JMP) opcode is needed to cause the desired jump to the users

service-routine address.

H.5.3.1 Jump to start of RAM ($0051)

The Jump to start of RAM program will be executed wh en br ing the d evice out of reset with PD2

and PD3 at ‘1’ and PD4 at ‘0’.

Table H-5 Bootstrap vector targets in RAM

Vector targets in RAM

SCI interrupt $0063

Timer overflow $0060

Timer output compare $005D

Timer input capture $005A

IRQ $0057

SWI $0054

Freescale

H-20 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

Figure H-8 RAM load and execute schematic diagram

Green LED — programming ended

Flashing green LED — programming

VPP6

PC7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

VDD

OSC1

OSC2

TCAP1

IRQ

RESET

VSS

P1 GND

+5V

1N914

1kΩ

1.0µF

100kΩ

1N914

RESET RUN

0.01µF

3VPP

PC5

PC4

PC3

PC2

PC1

PC0

PC6

PLMA

PLMB

470Ω

Red LED

Green LED

VRH

22µF

2 x 3KΩ1

1213

22µF

RS232

Connector MAX

232

+5V

9600 BD

8-bit

no par ity

22 8 10

41 7

VRL

TCAP2

TCMP1

TCMP2

SCLK

10nF 47µF

PD0

PD4

PD1

PD2

PD5

PD6

PD7

22pF 4.0 MHz

22pF

4k7Ω

12 kΩ

BC239C

BC309C

10k Ω

1nF

1N5819

1 kΩ

Serial boot

Erase check

47µF+

PD3

RDI

TDO

Erase check

Red LED — EPROM not erased

Green LED — EPROM erased

Serial boot &

serial boot

Erase check and serial boot

EPROM erase check

VPP1

MC68HC705B32

MCU (socket)

Note: A minimum VDD voltage must be applied to the VPP6 pin at all times,

including power-on, as a lower voltage could damage the device. Unless

otherwise stated, EPROM programming is guaranteed at ambient (25°C)

temperature only

MC68HC05B6

Rev. 4.1 Freescale

H-21

MC68HC705B32

Preliminary

Figure H-9 Parallel RAM loader timing diagram

tADR tDHR

Address

Data

tCR

PD4 tEXR max

tHO

tHI max

PC5 out

PC6 in

tADR max (address to data delay; PC6=PC5) 16 machine cycles

tDHR min (data hold time) 4 machine cycles

tCR (load cycle time; PC6=PC5) 49 machine cycles

tHO (PC5 handshake out delay) 5 machine cycles

tHI max (PC6 handshake in, data hold time) 10 machine cycles

tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5 30 machine cycles

1 machine cycle = 1/(2f0(Xtal))

Freescale

H-22 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

H.6 Absolute maximu m ratings

Note: This device contains circuitry designed to protect against damage due to high

electrostatic voltages or electric fields. However, it is recommended that normal

precautions be taken to avoid the a pplication of any voltages higher th an those given

in the maximum ratings table to this high impedance circuit. For maximum reliability all

unused inpu ts should be tied to eith er V SS or VDD.

Table H-6 Absolute Maximum ratings

Rating Symbol Value Unit

Supply voltage(1)

(1) All voltages are with respect to VSS.

VDD – 0.5 to +7.0 V

Input voltage (Except VPP1 and VPP6)V

IN VSS – 0.5 to VDD + 0.5 V

Input voltage

– Self-check mode (IRQ pin only) VIN VSS – 0.5 to 2VDD + 0.5 V

Operating temperature range

– Standard (MC68HC705B32)

– Extended (MC68HC705B32C)

TATL to TH

0 to +70

–40 to +85

°C

Storage temperature range TSTG – 65 to +150 °C

Current drain per pin (excluding VDD and VSS)(2)

– Source

– Sink

(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.

MC68HC05B6

Rev. 4.1 Freescale

H-23

MC68HC705B32

Preliminary

H.7 DC electrical characteristics

Table H-7 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, –40 to +85°C)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching

currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

Output high voltage (ILOAD = -300µA)

OSC2

VOH

VDD – 0.8

VDD – 0.4

VDD – 0.3

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

Output low voltage (ILOAD = -100µA)

OSC2

VOL

—

0.1

0.4

TBD

0.4

—

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7,OSC1, IRQ,

RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3) (For Guidance Only)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

IDD

—

1.5

TBD

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current

Port B and port C pull-down (VIN=VIH)I

RPD 80 µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2 ±1µA

Input current (– 40 to 85)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO,

SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

Freescale

H-24 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail; no

DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

MC68HC05B6

Rev. 4.1 Freescale

H-25

MC68HC705B32

Preliminary

Table H - 8 DC electrical characteristics for 3.3V operation

(VDD = 3.3Vdc ± 10%, VSS = 0Vdc, TA = –40 to +85°C)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.3

VDD – 0.1

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—0.1

0.2

0.3

0.6

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,

RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3) (For Guidance Only)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0 MHz); all inputs

0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

IDD

—

1.5

0.5

TBD

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL —±0.2 ±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN —±0.2 ±1µA

Input current (– 40 to 125)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN ——±5µA

Capacitance

Ports (as input or output), RESET, TDO,

SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

Freescale

H-26 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

H.8 A/D converter characteristics

Table H-9 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 1LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator

—

tCYC

µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(1)

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

—

tCYC

µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2)

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

MC68HC05B6

Rev. 4.1 Freescale

H-27

MC68HC705B32

Preliminary

Table H-10 A/D characteristics for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity Max deviation from the best straight line through the A/D

transfer characteristics

(VRH = VDD and VRL = 0V)

—± 1LSB

Quantization error Uncertainty due to converter resolution — ± 1LSB

Absolute accuracy Difference between the actual input voltage and the

full-scale equivalent of the binary code output code for all

errors

—± 2LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VRMinimum difference between VRH and VRL 3—V

Conversion time Total time to perform a single analog to digital conversion

Internal RC oscillator — 32 µs

Monotonicity Conversion result never decreases with an increase in

input voltage and has no missing codes GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition time Analog input acquisition sampling

Internal RC oscillator(1) —12µs

Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(2) Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH — 1 µA

(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

(2) The external system error caused by input leakage current is approximately equal to the product of R source and input

current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).

Freescale

H-28 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

H.9 Control timing

Table H-11 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

4.2

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

—

2.1

MHz

Cycle time (see Figure 9-1)t

CYC 476 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

tPROG

—

Timer (see Figure H-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor

in determining the timer resolution.

tRESL

tTH, tTL

tTLTL

125

—(3)

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute

the capture interrupt service routine plus 24 tCYC.

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 125 — ns

Interrupt pulse period tILIL —(4)

(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute

the interrupt service routine plus 21 tCYC.

—t

CYC

OSC1 pulse width(5)

(5) tOH and tOL should not total less than 238ns.

tOH, tOL 90 — ns

Write/Erase endurance(6)(7)

(6) At a temperature of 85°C

— 10000 cycles

Data retention(6)(7)

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

— 10 years

MC68HC05B6

Rev. 4.1 Freescale

H-29

MC68HC705B32

Preliminary

Table H-12 Control timing for operation at 3.3V

(VDD = 3.3Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

2.0

MHz

Internal operating frequency (fOSC/2)

Using crystal

Using external clock

fOP

—

1.0

MHz

Cycle time (see Figure 9-1)t

CYC 1000 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV — 100 ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

RC oscillator stabilization time tADRC 5µs

A/D converter stabilization time tADON 500 µs

External RESET input pulse width tRL 3.0 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

tPROG

—

Timer (see Figure H-10)

Resolution(2)

Input capture pulse width

Input capture pulse period

tRESL

tTH, tTL

tTLTL

250

—(3)

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 250 — ns

Interrupt pulse period tILIL —(4) —t

CYC

OSC1 pulse width(5) tOH, tOL 100 — ns

Write/Erase endurance(6)(7) — 10000 cycles

Data retention(6)(7) — 10 years

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 tCYC.

(4) The minimum period tILIL should not be less than the number of cycle times it takes to

execute the interrupt service routine plus 21 tCYC.

(5) tOH and tOL should not total less than 500ns.

(6) At a temperature of 85°C

(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.

Freescale

H-30 MC68HC05B6

Rev. 4.1

MC68HC705B32

Preliminary

THIS PAGE LEFT BLANK INTENTIONALLY

H.10 EPROM electrical characteristics

Figure H-10 Timer relationship

Table H-13 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the

transient switching currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

EPROM

Absolute maximum voltage

Programming voltage

Programming current

Read voltage

VPP6 max

VPP6

IPP6

VPP6R

VDD

—

VDD

—

15.5

VDD

Table H-14 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time tPROG 520ms

Table H-15 Control timing for 3.3V operation

(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 25°C)

Characteristic Symbol Min Max Unit

EPROM programming time tPROG 520ms

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

MC68HC05B6

Rev. 4.1 Freescale

I-1

HIGH SPEED OPERATION 15271

272

273

274

275

HIGH SPEED OPERATION

This section contains the electrical specifications and associated timing information for high speed

versions of the MC68HC05B6, MC68HC05B8 and MC68HC05B16 (fOSC max = 8 MHz). The

ordering information for these devices is contained in Table I-1.

Note: The high speed version has the same device title as the standard version. High speed

operation is selected via a check-box on the order form and will be confirmed on the

listing verification form.

Table I-1 Ordering information

Device title Package Suffix

0 to 70°C

Suffix

-40 to +85°C

MC68HC05B6

52-pin PLCC FN CFN

64-pin QFP FU CFU

56-pin SDIP B CB

MC68HC05B8

52-pin PLCC FN CFN

64-pin QFP FU CFU

56-pin SDIP B CB

MC68HC05B16

52-pin PLCC FN CFN

64-pin QFP FU CFU

56-pin SDIP B CB

Freescale

I-2 MC68HC05B6

Rev. 4.1

HIGH SPEED OPERATION

I.1 DC electrical characteristics

Table I-2 DC electrical characteristics for 5V operation

(VDD = 5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic(1)

(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient

switching currents inherent in CMOS designs (see Section 2).

Symbol Min Typ(2)

(2) Typical values are at mid point of voltage range and at 25°C only.

Max Unit

Output voltage

ILOAD = – 10 µA

ILOAD = +10 µA

VOH

VOL

VDD – 0.1

—

0.1

Output high voltage (ILOAD = 0.8mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2

Output high voltage (ILOAD = 1.6mA)

TDO, SCLK, PLMA, PLMB

VOH

VDD – 0.8

—

Output low voltage (ILOAD = 1.6mA)

PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,

TDO, SCLK, PLMA, PLMB

Output low voltage (ILOAD = 1.6mA)

RESET

VOL

—

0.4

Input high voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1,

IRQ, RESET, TCAP1, TCAP2, RDI

VIH 0.7VDD —V

DD V

Input low voltage

PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,

RESET, TCAP1, TCAP2, RDI

VIL VSS —0.2V

DD V

Supply current(3)

RUN (SM = 0) (See Figure 11-1)

RUN (SM = 1) (See Figure 11-2)

WAIT (SM = 0) (See Figure 11-3)

WAIT (SM = 1) (See Figure 11-4)

STOP

0 to 70 (standard)

– 40 to 85 (extended)

(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 8.0MHz); all inputs 0.2 V from

rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).

STOP /WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH =V

DD – 0.2 V: STOP IDD measured with

OSC1 = VDD.

WAIT IDD is affected linearly by the OSC2 capacitance.

IDD

—

µA

High-Z leakage current

PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK IIL ——±1µA

Input current (0 to 70)

IRQ, OSC1, TCAP1, TCAP2, RDI,

PD0/AN0-PD7/AN7 (channel not selected)

IIN ——

—

±5

±1

µA

Capacitance

Ports (as input or output), RESET, TDO, SCLK

IRQ, TCAP1, TCAP2, OSC1, RDI

PD0/AN0–PD7/AN7 (A/D off)

PD0/AN0–PD7/AN7 (A/D on)

COUT

CIN

—

276

MC68HC05B6

Rev. 4.1 Freescale

I-3

HIGH SPEED OPERATION 15

I.2 A/D converter characteristics

Table I-3 A/D characteristics for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Parameter Min Max Unit

Resolution Number of bits resolved by the A/D 8 — Bit

Non-linearity

Max deviation from the best straight line through

the A/D transfer characteristics

(VRH = VDD and VRL = 0V)

—± 0.5 LSB

Quantization error Uncertainty due to converter resolution — ± 0.5 LSB

Absolute accuracy

Difference between the actual input voltage and

the full-scale equivalent of the binary code

output code for all errors

—± 1LSB

Conversion range Analog input voltage range VRL VRH V

VRH Maximum analog reference voltage VRL VDD + 0.1 V

VRL Minimum analog reference voltage VSS – 0.1 VRH V

∆VR(1)

(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.

Minimum difference between VRH and VRL 3—V

Conversion time

Total time to perform a single analog to digital

conversion

a. External clock (OSC1, OSC2)

b. Internal RC oscillator

—

tCYC

µs

Monotonicity

Conversion result never decreases with an

increase in input voltage and has no missing

codes

GUARANTEED

Zero input reading Conversion result when VIN = VRL 00 — Hex

Full scale reading Conversion result when VIN = VRH —FFHex

Sample acquisition

time

Analog input acquisition sampling

a. External clock (OSC1, OSC2)

b. Internal RC oscillator(2)

(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.

—

tCYC

µs

Sample/hold

capacitance Input capacitance on PD0/AN0–PD7/AN7 — 12 pF

Input leakage(3)

(3) The external system error caused by input leakage current is approximately equal to the product of R

source and input current. Input current to A/D channel will be dependent on external source impedance

(see Figure 8-2).

Input leakage on A/D pins PD0/AN0–PD7/AN7

VRL, VRH

—

µA

Freescale

I-4 MC68HC05B6

Rev. 4.1

HIGH SPEED OPERATION

I.3 Control timing for 5V operation

(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 to +85°C)

Characteristic Symbol Min Max Unit

Frequency of operation

Crystal option

External clock option

fOSC

—

8.0

MHz

Internal operating frequency (fOSC/2)

Crystal

External clock

fOP

—

4.0

MHz

Cycle time (see Figure 9-1)t

CYC 250 — ns

Crystal oscillator start-up time (see Figure 9-1)t

OXOV —100ms

Stop recovery start-up time (crystal oscillator) tILCH 100 ms

External RESET input pulse width tRL 1.5 — tCYC

Power-on RESET output pulse width

4064 cycle

16 cycle

tPORL

4064

—

tCYC

Watchdog RESET output pulse width tDOGL 1.5 — tCYC

Watchdog time-out tDOG 6144 7168 tCYC

EEPROM byte erase time

0 to 70 (standard)

– 40 to 85 (extended)

tERA

—

EEPROM byte program time(1)

0 to 70 (standard)

– 40 to 85 (extended)

(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when

programming the EEPROM.

tPROG

—

Timer (see Figure I-1)

Resolution(2)

Input capture pulse width

Input capture pulse period

(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting

factor in determining the timer resolution.

tRESL

tTH, tTL

tTLTL

125

—(3)

(3) The minimum period tTLTL should not be less than the number of cycle times it takes to

execute the capture interrupt service routine plus 24 tCYC.

—

tCYC

Interrupt pulse width (edge-triggered) tILIH 125 — ns

Interrupt pulse period tILIL —(4)

(4) The minimum period tILIL should not be less than the number of cycle times it takes to

execute the interrupt service routine plus 21 tCYC.

—t

CYC

OSC1 pulse width tOH, tOL 90 — ns

Write/Erase endurance(5)(6)

(5) At a temperature of 85°C

— 10000 cycles

Data retention(5)(6)

(6) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate

information.

—10years

MC68HC05B6

Rev. 4.1 Freescale

I-5

HIGH SPEED OPERATION 15

Figure I-1 Timer relationship

External

signal

(TCAP1,

TCAP2)

tTLTL tTH tTL

Freescale

I-6 MC68HC05B6

Rev. 4.1

HIGH SPEED OPERATION

THIS PAGE LEFT BLANK INTENTIONALLY

MC68HC05B6 Freescale

GLOSSARY

This section contains abbreviations and specialist words used in this data

sheet and throughout the industry . Further information on many of the terms

may be gleaned from Freescale’s M68HC11 Reference Manual,

M68HC11RM/AD, or from a variety of standard electronics text books.

$xxxx The digits following the ‘$’ are in hexadecimal format.

%xxxx The digits following the ‘%’ are in binary format.

A/D, ADC Analog-to-digital (converter).

Bootstrap mode In this mode the device automati cally loads its internal memory from an

external source on reset and then allows this program to be e xecuted.

Byte Eight bits.

CCR Condition codes register; an integral part of the CPU.

CERQUAD A ceramic pac kage type, principally used for EPROM and high temperature

devices.

Clear ‘0’ — the logic zero state; the opposite of ‘set’.

CMOS Complementary metal oxide semiconductor. A semiconductor technology

chosen for its low power consumption and good noise immunity.

COP Computer operating properly. aka ‘watchdog’. This circuit is used to detect

device runaway and provide a means for restorin g correct operation.

CPU Central processing unit.

D/A, DAC Digital-to-analog (converter).

EEPROM Electrically erasable programmable read only memor y. aka ‘EEROM’.

EPROM Erasable programmable read only memory. This type of memory requires

exposure to ultra-violet wavelengths in order to erase previous data. aka

‘PROM’.

ESD Electrostatic discharge.

Expanded mode In this mode the in ternal address and data bus lines are connected to

external pins. This enables the device to be used in much more complex

systems, where there is a need for external memor y for example.

TPG

277

Freescale

ii MC68HC05B6GLOSSARY

EVS Evaluation system. One of the range of platforms provided by Freescale for

evaluation and emulation of their devices.

HCMOS High-density complementary metal oxide semiconductor. A se miconductor

technology chosen for its low po w er consumption and good noise immunity.

I/O Input/output; used to describe a bidirectional pin or func tion.

Input capture (IC) This is a functi on provided by the timing system, whereby an external

event is ‘captured’ by storing the value of a counter at the instant the event

is detected.

Interrupt This refers to an asynchronous exter nal event and the handling of it by the

MCU. The external event is detected by the MCU and causes a

predetermined action to occur.

IRQ Interrupt request. The overline indicates that this is an active-low signal

format.

K byte A kilo-byte (of memory); 1024 bytes.

LCD Liquid crystal display.

LSB Least significant byte.

M68HC05 Freescale’s family of 8-bit MCUs.

MCU Microcontroller unit.

MI BUS Interconnect bus. A single wire, medium speed serial communications

protocol.

MSB Most significant byte.

Nibble Half a byte; four bits.

NRZ Non-return to zero.

Opcode The opcode is a byte which identifies the particular instruction and operating

mode to the CPU. See also: prebyte, operand.

Operand The operand is a byte containing information the CPU needs to execute a

particular instruction. There may be from 0 to 3 operands associated with an

opcode. See also: opcode, prebyte.

Output compare (OC) This is a function provided by the timing system, whereby an external

event is generated when an inter nal counter value matches a predefined

value.

PLCC Plastic leaded chip carrier package.

PLL Phase-lock e d loop circuit. This provides a method of frequency

multiplication, to enable the use of a lo w frequency crystal in a high

frequency circuit.

Prebyte This byte is sometimes required to qualify an opcode, in order to fully specify

a particular instruction. See also: opcode, operand.

TPG

278

MC68HC05B6 Freescale

iii

GLOSSARY

Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are

per manently connected to either ground or VDD.

PWM Pulse width modulation. This term is used to describe a technique where the

width of the high and low periods of a wa vef orm is varied, usually to enable

a representation of an analog v alue .

QFP Quad flat pack package.

RAM Random access memory. Fast read and write, but contents are lost when the

power is remov ed.

RFI Radio frequency interference.

RTI Real-time interrupt.

ROM Read-only memory. This type of memory is programmed during device

manufacture and cannot subsequently be altered.

RS-232C A standard serial communications protocol.

SAR Successive approximation register.

SCI Serial communications interface.

Set ‘1’ — the logic one state; the opposite of ‘clear’.

Silicon glen An area in the central belt of Scotland, so called because of the

concentration of semiconductor manufacturers and users found there.

Single chip mode In this mode the device functions as a self contained unit, requiring only I/O

devices to complete a system.

SPI Serial peripheral interface .

Test mode This mode is intended for factory testing.

TTL Transistor-transistor logic.

UART Universal asynchronous receiver transmitter.

VCO Voltage controlled oscillator.

Watchdog see ‘COP’.

Wired-OR A means of connecting outputs together such that the re sulting composite

output state is the logical OR of the state of the individual outputs.

Word Two bytes; 16 bits.

XIRQ Non-maskable interrupt request. The overline indicates that this has an

active-low signal format.

TPG

279

Freescale

iv MC68HC05B6GLOSSARY

THIS PAGE LEFT BLANK INTENTIONALLY

TPG

280

MC68HC05B6 Freescale
v
INDEX
INDEX
In this index n umeric entries are placed first; page references in italics indicate that the reference
is to a figure.
A
A/D converter
block diagram  8–2
during STOP mode  8–6
during WAIT mode  8–6
operation  8–1
registers
ADDATA  8–3
ADSTAT  8–4
PORTD  8–3
A/D converter characteristics  11–8, 11–9, E–24, E–25, 
F–22, F–23, H–25, H–26, I–3
A/D status/control register
ADON  4–5
absolute maximum ratings  11–1
ADDATA – A/D result data register  8–3
ADON – A/D converter on  8–5
ADON – A/D converter on bit  4–5
ADRC – A/D RC oscillator control  8–4
ADSTAT
ADON  8–5
ADRC  8–4
CH3-CH0  8–5
COCO  8–4
ADSTAT – A/D status/control regis ter  8–4
alternate counter register  5–3
analog input  8–6
B
Baud rate register
SCP1, SCP0   6–18
SCR2, SCR1, SCR0  6–19
SCT2, SCT1, SCT0  6–18
block diagrams
MC68HC05B16  D–3
MC68HC05B32  G–2
MC68HC05B4  A–2
MC68HC05B8  B–2
MC68HC705B16  E–2
MC68HC705B16N  F–2
MC68HC705B32  H–4
MC68HC705B5  C–2
PLM system  7–1
programmable timer  5–2
SCI  6–2, 6–2
watchdog system  9–3
bootstrap mode  C–8, E–10, H–12
C
ceramic resonator  2–11
CH3-CH0 – A/D channels 3, 2, 1 and 0  8–5
COCO – Conversion complete flag  8–4
control timing   11–10, 11–11, C–19, E–26, E–27, F–24, 
F–25, H–27, H–28, I–4
COP watchdog  9–3
during STOP mode  9–4
during WAIT mode  9–4
counter  5–1
counter regist er  5–3
CPHA – Clock phase  6–12
CPOL – Clock polarity  6–12
crystal  2–11
D
data direction registers
DDRA, DDRB, DDRC  4–5
data format  6–5
DC electrical characteristics  11–2, 11–5, C–19, E–22, 
E–23, F–20, F–21, H–23, H–24, I–2
E
E1ERA – EEPROM erase/programming bit  3–3, E–7, 
F–7, H–9
E1LAT – EEPROM programming latch enable  3–4
E1LAT – EEPROM programming latch enable bit  E–7, 
F–7, H–10
281
282
283
284
285

Freescale
vi MC68HC05B6INDEX
E1PGM – EEPROM charge pump enable/disable   3–4, 
E–7, F–7, H–10
E6LAT – EPROM programming latch enable bit  E–6, F–6, 
H–9
E6PGM – EPROM program enable bit  E–6, F–6, H–9
ECLK – External clock output bit  4–3
EE1P – EEPROM protect bit  E–9, F–9
EE1P – EEPROM protection bit  H–12
EEPROM  3–1, 3–3
erase operation  3–5
programming operation  3–6
read operation  3–5
STOP mode  3–7
WAIT mode  3–7
EEPROM control register
E1ERA  3–3
E1LAT  3–4
E1PGM  3–4
ECLK  3–3
EEPROM options register
EE1P  E–9, F–9
SEC  E–9, F–9
EEPROM/ECLK control
ECLK  4–3
ELAT – EPROM programming latch enable bit  C–6
EPGM – EPROM programming bit  C–6
EPP – EPROM protect  C–7
EPPT – EPROM protect test  bi t  C–6
EPROM  13–2, C–5, E–5, F–5
control register  C–6, E–6, F–6
options register  C–7
program operation  E–5, F–6, H–8
programming operation  C–5
read operation  E–5, F–5, H–8
EPROM control register
ELAT  C–6
EPGM  C–6
EPPT  C–6
EPROM electrical characteristics  E–28, F–26, H–29
EPROM registers  C–6
EPROM/EEPROM/ECLK control register
E1ERA  E–7, F–7
E1LAT  E–7, F–7
E1PGM  E–7, F–7
E6LAT  E–6, F–6
E6PGM  E–6, F–6
external clock  2–12, D–4, E–5, F–5, G–2
external interrupt  9–7
F
FE – Framing error flag  6–17
H
high speed operation  I–1
I
I/O pin states  4–2
I/O port structure  4–2, 4–2
ICF1 – Input capture flag 1  5–6
ICF2 – Input capture flag 2  5–7
IDLE – Idle line detect flag  6–16
IEDG1 – Input edge 1  5–5
ILIE – Idle line interrupt en able   6–14
Input capture registers
ICR1  5–7
ICR2  5–8
input/output programming  4–1
INTE – External interrupt enable  3–9, 9–9
interrupts
priorities  9–6
SCI  9–10
SWI  9–6
INTP, INTN – External interrupt sensitivit y option s  3–9, 9–9
IRQ  9–7
IRQ sensitivity  9–9
L
LBCL – Last bit clock  6–13
low power modes
SLOW  2–9
STOP  2–6
WAIT  2–8
M
M – Mode  6–11
Mask option register
PBPD  E–8, F–8, H–11
PCPD  E–8, F–9, H–11
RTIM  E–8, F–8, H–11
RWAT  E–8, F–8, H–11
WWAT  E–8, F–8, H–11
mask options
MC68HC05B6  1–3
maskable hardware interrupts  9–7
maskset errata  D–1, H–1
MC68HC05B16  D–1
block diagram  D–3
memory map  D–5
MC68HC05B32  G–1
block diagram  G–2
memory map  G–3
MC68HC05B4
block diagram  A–2
memory map  A–3
MC68HC05B6
block diagram  1–3
mask options  1–3
memory map  3–2
pinouts  12–1, 12–2, 12–3
286

MC68HC05B6 Freescale

vii

INDEX

MC68HC05B8 B–1

block diagram B–2

memory map B–3

MC68HC705B16 E–1

block diagram E–2

memory map E–3

MC68HC705B16N F–1

block diagram F–2

memory map F–3

MC68HC705B32 H–3

block diagram H–4

memory map H–5

MC68HC705B5 C–1

block diagram C–2

memory map C–3

mechanical dimensions 12–4, 12–5, 12–6

memory map

MC68HC05B16 D–5

MC68HC05B32 G–3

MC68HC05B4 A–3

MC68HC05B6 3–2

MC68HC05B8 B–3

MC68HC705B16 E–3

MC68HC705B16N F–3

MC68HC705B32 H–5

MC68HC705B5 C–3

Miscellaneous register

INTE 3–9, 9–9

INTP, INTN 3–9, 9–9

POR 3–9, 9–2

SFA 3–10, 7–3

SFB 3–10, 7–3

SM 2–9, 3–10, 7–3

WDOG 3–10, 9–4

modes of operation

jump to any address 2–4

low power modes 2–6

single chip mode 2–1

NF – Noise error flag 6–17

nonmaskable software int errupt 9–6

OCF1 – Output compare flag 2 5–6

OCF2 – Output compare flag 2 5–7

OCIE – Output compares interrupt enable 5–4

OLV1 – Output level 1 5–5

OLV2 – Output level 2 5–5

Options register

SEC H–12

options register

EE1P H–12

EPP C–7

PBPD C–8

PCPD C–8

RTIM C–7

RWAT C–7

WWAT C–7

OPTR – options register 3–6, C–7

EE1P – EEPROM protection bit 3–7

SEC – Security bi t 3–7

OR – Overrun error flag 6–17

oscillator connections 2–12, D–4

Output compare registers

OCR1 5–9

OCR2 5–10

parallel bootstrap E–13, E–19, F–13, H–16

PBPD – Port B pull-down E–8, F–8

PBPD – Port B pull-down resistors C–8

PCPD – Port C pull-down E–8, F–9

PCPD – Port C pull-down resistors C–8

pin configurations 12–1

pinsIRQ 2–10

OSC1, OSC2 2–11

PA0–PA7, PB0–PB7, PC0–PC7 2–13

PD0/AN0–PD7/AN7 2–13

PLMA, PLMB 2–13

RDI, TDO 2–13

RESET 2–10, 9–3

SCLK 2–13

TCAP1 2–10

TCAP2 2–11

TCMP1, TCMP2 2–11

VDD, VSS 2–10

VPP1 2–13

VRH, VRL 2–13

PLCC 12–1

PLM 5–11

block diagram 7–1

clock selection 7–4

PLMA, PLMB 7–2

POR – Power-on reset bit 3–9, 9–2

port registers

PORTA, PO R TB 4–4

PORTC 4–4

PORTD 4–5

PORTD – Port D data register 8–3

portsA and B 4–2

C 4–3

D 4–3

power-on reset 9–2

programmable timer

block diagram 5–2

Pulse 5–11

pulse length modulation 5–11

registers

PLMA, PLMB 5–11

Freescale
viii MC68HC05B6INDEX
pulse length modulation registers
PLMA, PLMB  5–11
Q
QFP  12–2
R
R8 – Receive data bit 8  6–11
RAM  3–1
RDI  6–6
RDRF – Receive data register full flag  6–16
RE – receiver enable  6–15
receive data in  6–6
receiver  6–3
register outline  3–8
registers  3–1
RESET  9–3, E–5, F–5
reset timing diagram  9–1
resets  9–1
RIE – receiver interrupt enable  6–14
ROM  3–1
RTIM – Reset time  C–7, E–8, F–8
RVU  13–2
RWAT – Watchdog after reset  C–7, E–8, F–8
RWU – receiver wake-up  6–15
S
SBK – Send break  6–15
SCI block diagram  6–2
receiver  6–3
sampling technique  6–7
synchronous transmission  6–9
transmitter  6–3
two-wire system  6–1
SCI interrupts  9–10
SCI registers
BAUD  6–18
SCCR1  6–10
SCCR2  6–14
SCDR  6–10
SCSR  6–16
SCP1, SCP0 – Serial prescaler select bits  6–18
SCR2, SCR1, SCR0 – SCI rate select bits  6–19
SCT2, SCT1, SCT0 – SCI rate select bits  6–18
SDIP  12–3
SEC – Secure  bit  E–9, F–9, H–12
self-check mode  A–5
self-check ROM  3–2
serial bootstrap  E–16
Serial communications control register 1  6–10
CPHA  6–12
CPOL  6–12
LBCL  6–13
M  6–11
R8  6–11
T8  6–11
WAKE  6–11
Serial communications control register 2
ILIE  6–14
RE  6–15
RIE  6–14
RWU  6–15
SBK  6–15
TCIE  6–14
TE  6–14
TIE  6–14
Serial comm u ni c ations data register   6–10
Serial communications status register
FE  6–17
IDLE  6–16
NF  6–17
OR  6–17
RDRF  6–16
TC  6–16
TDRE  6–16
serial RAM loader  2–2, F–16, H–19
SFA – Slow or  fa st m o de  sel e ction for PLMA  3–10, 7–3
SFB – Slow or  fa st m o de  sel e ction for PLMB  3–10, 7–3
single chip mode  2–1
SLOW  2–9
SM – Slow mode  3–10, 7–3
SM – slow mode selection bit  2–9
start bit detection  6–6
STOP  2–6, 3–7, 5–12, 6–21, 7–4, 8–6, 9–4
T
T8 – transmit data bit 8  6–11
TC – Transmit complete flag  6–16
TCIE – Transmit complete interrupt enable  6–14
TDO  6–8
TDRE – Transmit data register empty flag  6–16
TE – Transmitter enable  6–14
TIE – Transmit interrupt enabl e  6–14
Timer control register
IEDG1  5–5
OCIE  5–4
OLV1  5–5
OLV2  5–5
TOIE  5–4
timer interrupts  9–10
timer state diagrams  5–12
Timer status register
ICF1  5–6
ICF2  5–7
OCF1  5–6
OCF2  5–7
TOF  5–6
TOF – Timer overflow status flag  5–6
TOIE – Timer overflow interrupt enable  5–4
transmit data out  6–8

MC68HC05B6 Freescale
ix
INDEX
transmitter  6–3
TSR – Time r sta tus register  5–6
V
verification media  13–2
W
WAIT  2–8, 3–7, 5–12, 6–21, 7–4, 8–6, 9–4
WAKE – Wake-up mode select  6–11
wake-up
address mark  6–6
idle line  6–6
receiver  6–5
WDOG – Watchdog enable/disable  3–10, 9–4
WWAT – Watchdog during WAIT mode  C–7, E–8, F–8

Freescale

xMC68HC05B6INDEX

THIS PAGE LEFT BLANK INTENTIONALLY

CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05B6/D rev. 4)

Motorola wishes to continue to improve the qualit y of its documentation. We would w elcome your feedback on the publication you

have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer).

1. How would you rate the quality of the document? Check one box in each category.

Excellent Poor Excellent Poor

Organization ❏❏❏❏ Tables ❏❏❏❏

Readability ❏❏❏❏ Table of contents ❏❏❏❏

Understandability ❏❏❏❏ Index ❏❏❏❏

Accuracy ❏❏❏❏ Page size/binding ❏❏❏❏

Illustrations ❏❏❏❏ Over all impression ❏❏❏❏

Comments:

2. What is your intended use for this document ? If more than one option appli es, please rank them (1, 2, 3).

Selection of device for new application ❏Other ❏Please specify:

System design ❏

Training purposes ❏

3. How well does this manual enable y ou to perform the task(s) outlined in question 2?

Completely Not at all Comments:

❏❏❏❏

4. How easy is it to find the information you are looking for?

Easy Difficult Comments:

❏❏❏❏

5. Is the level of technical detail in the following sections sufficient to allo w you to understand how the device functions?

Too little deta il Too much detail

Comments:

6. Have you found any errors? If so, please comment:

7. From your point of view, is anything missing from the document? If so , please say what:

❏❏❏❏❏

– Cut along this line to remove –

SECTION 1 INTRODUCTION

SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS

SECTION 3 MEMORY AND REGISTERS

SECTION 4 INPUT/OUTPUT PORTS

SECTION 5 PROGRAMMA BLE TIMER

SECTION 6 SERIAL COMMUNICATIONS INTERFACE

SECTION 7 PULSE LENGTH D/A CONVERTERS

SECTION 8 ANALOG TO DIGITAL CONVER TER

SECTION 9 RESETS AND INTERRUPTS

SECTION 10 CPU CORE AND INSTRUCTION SET

SECTION 11 ELECTRICAL SPECIFICATIONS

SECTION 12 MECHANICAL DATA

SECTION 13 ORDERING INFORMATION

SECTION 14 APPENDICES

SECTION 15 HIGH SPEED OPERATION

TPG

287

13. Currently there is some discussion in the semiconductor indu stry regarding a mov e towards p roviding data sh eets in electronic

for m. If you have any opinion on this subject, please comment.

14. We would be grateful if you would supply the followin g information (at your discretion), or attach you r card.

Name: Phone No:

Position: FAX No:

Department:

Company:

Address:

Thank you fo r helping us improve our documentation,

Graham Forbes, Technical Publications Manager, Motorola Ltd., Scotland.

– Cut along this line to remove –

– Third fold back along this line –

8. How could we improve this document?

9. How would you rate Motorola’s documentation?

Excellent Poor

– In general ❏❏❏❏

– Against other semiconductor suppliers ❏❏❏❏

10. Which semiconductor manufacturer provides the best technical documentation?

11. Which company (in any field) provides the best technical documentation?

12. How many years have you worked with microprocessors?

Less than 1 y ear ❏ 1–3 years

❏3–5 years ❏More than 5 years ❏

– Second f old back along this line –

– Finally, tuck this edge into opposite flap –

✂

By air mail

Par avion

NE PAS AFFRANCHIR

IBRS NUMBER PHQ-B/207/G

CCRI NUMERO PHQ-B/207/G

REPONSE PAYEE

GRANDE-BRETAGNE

Motorola Ltd.,

Colvilles Road,

Kelvin Industrial Estate,

EAST KILBRIDE,

G75 8BR.

GREAT BRITAIN.

F.A.O. Technical Publications Manager

(re: MC68HC05B6/D rev. 4)

NO STAMP REQUIRED

– First fold back along this line –

Semiconductor Products Sector

TPG

288

INTRODUCTION

MODES OF OPERATION AND PIN DESCRIPTIONS

MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

TPG

289

INTRODUCTION

MODES OF OPERATION AND PIN DESCRIPTIONS

MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

TPG

290

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Information in this document is provided solely to enable system and software

implementers to use Freescale Semi conductor products. There are no express or

implied copyright licenses granted her eunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

F reescale Semiconductor assume any liability arising out of the application or use of an y

product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freesca le Semiconductor data sheets and/or sp ecifications can and do v ary

in different applications and actual performance may vary over time. All operat i ng

parameters, including “Typicals”, must be validated for ea ch customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, int ended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sust ain life,

or f or any oth er application in which the failure of the Freesca le Semiconductor product

could create a situation where personal injury or death may occur. Should Buy er

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized appli cation, Buyer shall indemnif y and hold Freescale Semi conductor and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs , damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

Semiconductor was negligent regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks o f Freescale Semiconductor, Inc.

All other product or service names are the property of their respectiv e owners. The ARM

POWERED logo is a registered trademark of ARM Limited. ARM7TDMI-S is a

trademark of ARM Limited. Java and all other Java-based marks are trademarks or

registered trademarks of Sun Microsystems, Inc. in the U .S. and other countries . The

Bluetooth trademarks are owned by their proprietor and used by Freescale

Semiconductor, Inc. under license.

Rev. 4.1

MC68HC05B6/D

08/2005

RoHS-compliant and/or Pb- free versions of Freescale products have the functionality

and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free

counterparts. For further information, see http://www.freescale.com or contact your

Freescale sales representative.

For information on Freescale.s Environmental Products program, go to

http://www.freescale.com/epp.