FQD19N10L / FQU19N10L
FQD19N10L / FQU19 N 10L
100V LOGIC N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as high efficiency
switching DC/DC converters, and DC motor control.
Features
15.6A, 100V, RDS(on) = 0.1 @VGS = 10 V
Low gate charge ( typical 14 nC)
Low Crss ( typical 35 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Absolute Maximu m Ratings TC = 25°C unless otherwise noted
Thermal Characteristics
Symbol Parameter FQD19N10L / FQU19N10L Units
VDSS Drain-Source Voltage 100 V
IDDrain Current - Continuous (TC = 25°C) 15.6 A
- Continuous (TC = 100°C) 9.8 A
IDM Drain Current - Pulsed (Note 1) 62.4 A
VGSS Gate-Source Voltage ± 20 V
EAS Single Pulsed Avalanche Energy (Note 2) 220 mJ
IAR Avalanche Current (Note 1) 15.6 A
EAR Repetitive Avalanche Energy (Note 1) 5.0 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 6.0 V/ns
PDPower Dissipation (TA = 25°C) * 2.5 W
Power Dissipation (TC = 25°C) 50 W
- Derate above 25°C 0.4 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum lead temperature for soldering purposes,
1/8" from case for 5 seconds 300 °C
Symbol Parameter Typ Max Units
RθJC Thermal Resistance, Junction-to-Case -- 2.5 °C/W
RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/W
RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W
* When mounted on the minimum pad size recommended (PCB Mount)
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D
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I-PAK
FQU Series
D-P AK
FQD Series GS
D
GS
D
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
RoHS Compliant
January 2009
QFET
®
FQD19N10L / FQU19N10L
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
Electrical Characteristics TC = 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 1.35mH, IAS = 15.6A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 19A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
Symbol Parame ter Test Condit ions Min Typ Max Units
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA100 -- -- V
BVDSS
/ TJ
Breakdown Vo ltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C -- 0.09 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = 100 V, VGS = 0 V -- -- 1 µA
VDS = 80 V, TC = 125°C -- -- 10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V -- -- -100 nA
On Characteri st ics
VGS(th) Gate Threshold Volt age VDS = VGS, ID = 250 µA1.0 -- 2.0 V
RDS(on) Static Drain-Source
On-Resistance VGS = 10 V, ID = 7.8 A
VGS = 5 V, I D = 7.8 A -- 0.074
0.082 0.10
0.11
gFS Forward Transconductance VDS = 30 V, ID = 7.8 A -- 14 -- S
Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 670 870 pF
Coss Output Capacitance -- 160 210 pF
Crss Reverse Transfer Capacit ance -- 35 45 pF
Switching Characteristics
td(on) Turn-On Delay Time VDD = 50 V, ID = 19 A,
RG = 25
-- 14 38 ns
trTurn-On Rise Time -- 410 830 ns
td(off) Turn-Off De l a y Time -- 20 50 ns
tfTurn -Off Fall Time -- 14 0 290 n s
QgTotal Gate Cha rge VDS = 80 V, ID = 19 A,
VGS = 5 V
-- 14 18 nC
Qgs Gate-Source Charge -- 2.9 -- nC
Qgd Gate-Drain Charge -- 9.2 -- nC
Drain-Source Diod e Characteristics and Maxim um Ratings
ISMaximum Continuous Drain-Source Diode Forward Current -- -- 15.6 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 62.4 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, I S = 15.6 A -- -- 1.5 V
trr Reverse Recovery Time VGS = 0 V, I S = 19 A,
dIF / dt = 100 A/µs
-- 80 -- ns
Qrr Reverse Recovery Charge -- 0.195 -- µC
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
FQD19N10L / FQU19N10L
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
10-1
100
101
150
No tes :
1. VGS = 0V
2. 250μ
s Pu lse T es t
25
IDR, Reverse Drain Current [A]
VSD, So urce-Dr a in voltage [ V ]
0 5 10 15 20 25
0
2
4
6
8
10
12
VDS = 50V
VDS = 80V
Note : ID = 19A
VGS, Gate-Source Voltage [V]
QG, Total Gate Ch a rg e [nC]
10-1 100101
0
300
600
900
1200
1500
1800 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Notes :
1. V GS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Capacitance [pF]
VDS, Drain-Source Voltage [V]
01530456075
0.00
0.06
0.12
0.18
0.24
0.30
VGS = 10V
VGS = 5V
N ote : T J = 25
RDS(ON) [Ω],
Drain-Source On-Resistance
ID, D r a i n Current [A]
0246810
10-1
100
101
Note s :
1 . VDS = 30V
2. 250μ
s Pulse Test
-55
150
25
ID , Drain Cu rr e n t [A ]
VGS , Gate-Sou rce Voltage [V]
10-1 100101
100
101
VGS
To p : 10 .0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bo tto m : 3 .0 V
Notes :
1. 250μ
s Pu lse Te st
2. TC = 25
ID, Drain Current [A ]
VDS, Drain-Source Voltage [V]
Typical Characteristics
Figure 5. C apacitance C haracterist i cs Figure 6. Ga te Ch arge Chara ct eri stics
Figu re 3. On-R esistan ce Variation vs.
Drain Current and Gate Voltage Figure 4. Body Diode Fo rward Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character i stic s
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
FQD19N10L / FQU19N10L
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
No te s :
1 . ZθJC(t) = 2.5 /W M a x .
2 . D uty Fa c t o r, D = t1/t2
3 . TJM - T C = P DM * Z θJC(t)
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJC
(t), Therm al Response
t1, Sq u a re W a ve P u lse Du ra tio n [se c ]
25 50 75 100 125 150
0
4
8
12
16
ID, Drain Current [A ]
TC, Case Temperature [
]
100101102
10-1
100
101
102
10 µs
DC 10 m s
1 ms 100 µs
Op eration in Th is A r e a
is Limited by R DS(on)
Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
ID, Drain Cu rrent [A]
VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
No tes :
1. VGS = 10 V
2. ID = 7.8 A
RDS(ON) , (N o r maliz ed)
Drain-Source On-Resistance
TJ, Junction Tem p erature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
Notes :
1 . VGS = 0 V
2 . ID = 250 μ
A
BV DSS , (N ormaliz e d )
Drain-Sou rce Breakdow n V oltage
TJ, Junction Temperature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figu re 7. Br ea kdown Voltag e Variation
vs. Temperature Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Tr ansient Thermal Response Curve
t1
PDM
t2
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
FQD19N10L / FQU19N10L
Charge
VGS
5V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
Charge
VGS
5V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
5V
VDS RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
5V
VDS RL
DUT
RG
VGS
EAS =LI
AS2
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
L
ID
t p
EAS =LI
AS2
----
2
1
EAS =LI
AS2
----
2
1
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
LL
ID
ID
t p
Gate Charge Test Circuit & Waveform
Resist iv e Swi tc hi ng Tes t Ci rcuit & Wavefor m s
Unclamped Inductive Switching Test Circuit & Waveforms
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
FQD19N10L / FQU19N10L
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
VDS
+
_
Driver
RGSame Typ e
as DUT
VGS dv/dt controlled by RG
•I
SD con trolled by pulse period
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGSame Typ e
as DUT
VGS dv/dt controlled by RG
•I
SD con trolled by pulse period
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
FQD19N10L / FQU19N10L
Package Dimensions
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
TO-252 (DPAK) (FS PKG Code 36)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
millimeters
Par t Weight per unit (gram): 0.33
FQD19N10L / FQU19N10L
Package Dimensions (Continued)
6.60 ±0.20
0.76 ±0.10
MAX0.96
2.30TYP
[2.30±0.20] 2.30TYP
[2.30±0.20]
0.60 ±0.20
0.80 ±0.10
1.80 ±0.20
9.30 ±0.30
16.10 ±0.30
6.10 ±0.20
0.70 ±0.20
5.34 ±0.20
0.50 ±0.10
0.50 ±0.10
2.30 ±0.20
(0.50) (0.50)(4.34)
IPAK
Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation
Rev. I37
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Rev. A1. January 2009
©2009 Fairchild Semiconductor Corporation