fax id: 5223 a CY7C026 Z PRELIMINARY CY7C036 7 CYPRESS i 16K x 16/18 Dual-Port Static RAM Features Automatic power-down ; ; + Expandable data bus to 32/36 bits or more using Mas- * True Dual-Ported memory cells which allow simulta- ter/Slave chip select when using more than one device neous access of the same memory location + On-chip arbitration logic 16K x 16 organization (CY7C026) Semaphores included to permit software handshaking 16K x 18 organization (CY7C036) between ports 0.35-micron CMOS for optimum speed/power High-speed access: 12/15/20 ns Low operating power INT flags for port-to-port communication Separate upper-byte and lower-byte control Pin select for Master or Slave Active: Igg = 180 mA (typical) Commercial and Industrial temperature ranges Standby: Igg3 = 0.05 mA (typical) Available in 100-pin TQFP Fully asynchronous operation + Pin-compatible and functionally equivalent to IDT70261 Logic Block Diagram RW, RWrR UB, UBR CE, CER LB, LBr OE, OER 1] VOg~_-VO1547R 8/9 2] Oo_-VO7/8R 1] VOge_-VO1547L VOo.-VO7/g V/O Control V/O Control Address True Dual-Ported Address AoLAisi Decode RAM Array Decode AorAisr AoL-A13L Aon-A13R CEL Interrupt CER OE, Semaphore OER RW, Arbitration RWp SEM. 3 SEMA BUSY, BUSYa iNT, INTa UBL UBR LB, M/S LBr Notes: 1. WVWOg-l/Oy5 for x16 devices; I/Ogl/O47 for x18 devices 2. /Og-l/O7 for x16 devices; I/OpI/Og for x18 devices. 3. BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation + 3901 North First Street * SanJose + CA 95134 + 408-943-2600 November 7, 1997 - Revised June 26, 19987 CYPRESS PRELIMINARY CY7C026 CY7C036 Functional Description The CY7C026 and CY7036 are low-power CMOS 16K x 16/18 dual-port static RAMs. Various arbitration schemes are includ- ed on the devices to handle situations when multiple proces- sors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple de- vices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provid- ed for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or ad- ditional discrete logic. Application areas include interproces- sor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Pin Configurations Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pin. The CY7C026 and CY7036 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View) a Q 100 99 98 97 96 95 94 93 92 NC NC NC NC VOroL VOuL VOraL VOraL GND VOraL VOrsL VCC GND V/OoR Oi; Oop VCC VOsR Oar V/OsR VO6rR NC NC NC NC 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 40 41 42 /O7p /Ogp =x = =& & 90 89 88 87 86 Aisi Ata AW Ajo. AgL Ag An ca BE8e 85 84 83 82 81 80 79 78 77 76 CY7C026 (16K x 16) 43 44 45 46 47 48 49 50 Aiar Aor AiR Ator Agr Agr A7R Aer=i. = PRELIMINARY 7 CYPRESS CY7C026 CY7C036 Pin Configurations (continued) 100-Pin TQFP Top View edr de dado SSW SERW a as oO CGLLLQVPVQLV@GFQLor reas Sag 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC 1 NC NC 2 NC VOsi 3 Ais. VO47L 4 Ast VOrt 5 Aa VO yet 6 VOraL 7 fa VO qaL 8 AW GND Ao. VO 4sL INT. VO t6L BUSY L Veo GND vec CY7C036 (16K x 18) ont VOor BUSY R VO1R INTR VO oR Aor Voo AiR VO3p Aor VOaR AsR VO5R Aap VOe6r Ai3R VO sr NC VO47R NC NC NC NC 27 28 29 30 31 32 3334 35 36 37 38 39 40 41 42 43 44 45 46.47 48 49 50 ESSERSS SO ST SOLIS GS SESESESS Sl egceg gs ghESReBBccess ees Selection Guide CY7C026 CY7C026 CY7C026 CY7C036 CY7C036 CY7C036 -12 -15 -20 Maximum Access Time (ns) 12 15 20 Typical Operating Current (mA) 195 190 180 Typical Standby Current for Igp3, (mA) (Both ports TTL level) 55 50 45 Typical Standby Current for Igp3 (mA) (Both ports CMOS level) 0.05 0.05 0.05CY7C026 oN 7 CYPRESS PRELIMINARY CY7C036 Pin Definitions Left Port Right Port Description CE, CER Chip Enable RW R/Wr Read/Write Enable OE, OER Output Enable AoLA13L Aor-Ai3R Address VOo.-VO47. /OoR-/017R Data Bus Input/Output SEM, SEMp; Semaphore Enable UBL UBR Upper Byte Select (l/OgI/O 45 for x16 devices; I/Ogl/O47 for x18 devices) LB, LBp Lower Byte Select (I/O9I/O7 for x16 devices; I/Ogl/Og for x18 devices) INT, INTR Interrupt Flag BUSY, BUSYp Busy Flag M/S Master or Slave Select Voc Power GND Ground NC No Connect Maximum Ratings DC Input Voltagel4] deeeeececeeaeaaaeeseeeeeeeeseaeeans 0.5V to + 7.0V (Above which the useful life may be impaired. For user guide- Output Current into Outputs (LOW)... eeeeeeeeeeeees 20 mA lines, not tested.) Static Discharge Voltage 0... eeseseeeeeesseeeeeneeereeeeees >2001V Storage Temperature oo... cece eee ~65C to + 150C Latch-Up Current... cee cece ese eeeeeeeeretas >200 mA Power Apoled ee secsasetevesesssesenseee 55C to+ 125C Operating Range Supply Voltage to Ground Potential .............. 0.3V to + 7.0V Ambient DC Voltage Applied to Outputs Range Temperature Vee in High Z State oo... cecseeessssseesseessseessesseecseeen -0.5V to + 7.0V Commercial OC to +70C oV + 10% Industrial 40C to +85C 5V+ 10% Note: 4. Pulse width < 20 ns.CY7C026 oN 7 cYPRE ss PRELIMINARY CY7C036 Electrical Characteristics Over the Operating Range CY7C026 CY7C036 -12 -15 -20 Symbol Parameter Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Units Vou Output HIGH Voltage (Vec=5V) 2.4 2.4 2.4 V VoL Output LOW Voltage 0.4 0.4 0.4 Vv Vin Input HIGH Voltage 2.2 2.2 2.2 Vv VIL Input LOW Voltage 0.8 0.8 0.8 V loz Output Leakage Current -10 10 -10 10 -10 10 HA lec Operating Current Com'l. 195 | 325 190 | 280 180 | 265 mA (Voc=Max, lout=0 mA) Outputs Disabled Indust. 215 | 305 305 | 290 mA Ispi Standby Current __ | Com. 55 | 75 50 70 45 65 mA (Both Ports TTL Level) CE, & CEg > Vin, ftax Indust. 65 95 60 80 mA Ispe Standby Current _ Com'l. 125 | 205 120 | 180 110 | 160 mA (One Port TTL Level) CE, | [indust. 135 | 205 125 | 175 | mA CEp 2 Vin, ffmax Isp Standby Current Com'l. 0.05 | 0.25 0.05 | 0.25 0.05 | 0.25 | mA (Both Ports CMOS Level) CE, & CEp > Voo-0.2V, f=0 Indust. 0.05 | 0.25 0.05 | 0.25 | mA Ispa Standby Current Com'l. 115 | 185 110 | 160 100 | 140 mA (One Port CMOS Level) CE, | CEp > Vin ffivax) | (Bust 125 | 175 115 | 155 | mA Capacitance Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 10 pF - Voc = 5.0V Court Output Capacitance 10 pF AC Test Loads and Waveforms 5V 5V Ri= 8980 Rry = 2500 OUTPUT, OUTPUT Ri = 8930 C= 30pF OUTPUT C= 30pF T R2= 3470 L CA5 = 5pF 4 1 = Vry= 1.4V R2= 3470 (a) Normal Load (Load 1) (b) Thvenin Equivalent (Load 1) (c) Three-State Delay (Load 2) (Used for tz, tuz, tuzwe & t_zwe ALL INPUT PULSES including scope and jig) Notes: <3ns~> <3ns 5. fax = t/tRc = All inputs cycling at f = 1/tac (except output enable). f= 0 means no address or control lines change. This applies only to inputs at CMOS level standby Isgp3. 6. Tested initially and after any design or process changes that may affect these parameters.CY7C026 oN 7 cYPRE ss PRELIMINARY CY7C036 Switching Characteristics Over the Operating Rangel! CY7C026 CY7C036 12 15 20 Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCLE tac Read Cycle Time 12 15 20 ns tan Address to Data Valid 12 15 20 ns toHA Output Hold From Address Change 3 3 3 ns tace CE LOW to Data Valid 12 15 20 ns tpor OE LOW to Data Valid 10 12 ns tizoc 111 | OE LOW to Low Z 3 3 3 ns tuzoe 111 | OE HIGH to High Z 10 10 12 ns tice 19 1 CE LOW to Low Z 3 3 3 ns tuzce? 10 | CE HIGH to High Z 10 10 12 ns tpl! CE LOW to Power-Up 0 0 0 ns tpp! CE HIGH to Power-Down 12 15 20 ns tape Byte Enable Access Time 12 15 20 ns WRITE CYCLE twe Write Cycle Time 12 15 20 ns tcc CE LOW to Write End 10 12 15 ns taw Address Valid to Write End 10 12 15 ns tHa Address Hold From Write End 0 0 0 ns tga! Address Set-Up to Write Start 0 0 0 ns tpwe Write Pulse Width 10 12 15 ns tsp Data Set-Up to Write End 10 10 15 ns tub Data Hold From Write End 0 0 0 ns tuzwel! 11) R/W LOW to High Z 10 10 12 ns tzwel! M1 R/W HIGH to Low Z 3 3 3 ns twoo!'2! Write Pulse to Data Delay 25 30 45 ns topo"! Write Data Valid to Read Data Valid 20 25 30 ns Notes: 7. Testconditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified lo/loy and 30-pF load capacitance. 8. To access RAM, CE=L, UB=L, SEM-H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tggg time. 9. Atany given temperature and voltage condition for any given device, tyzoe is less than tLzce and tyzo is less than t_zoE- 10. Test conditions used are Load 3. 11. This parameter is guaranteed but not tested. 12. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.CY7C026 oN 7 CYPRESS PRELIMINARY CY7C036 Switching Characteristics Over the Operating Rangel! (continued) CY7C026 CY7C036 -12 15 20 Parameter Description Min. Max. Min. Max. Min. Max. Unit BUSY TIMING!"3) tala BUSY LOW from Address Match 12 15 20 ns teHa BUSY HIGH from Address Mismatch 12 15 20 ns tac BUSY LOW from CE LOW 12 15 20 ns tpHc BUSY HIGH from CE HIGH 12 15 17 ns tps Port Set-Up for Priority ns twp R/W HIGH after BUSY (Slave) ns twu RW HIGH after BUSY HIGH (Slave) 14 13 15 ns tapp!"4! BUSY HIGH to Data Valid 12 15 20 ns INTERRUPT TIMING!" tins INT Set Time 12 15 20 ns tinr INT Reset Time 12 15 20 ns SEMAPHORE TIMING tsop SEM Flag Update Pulse (OE or SEM) 10 10 10 ns tswro SEM Flag Write to Read Time ns tsps SEM Flag Contention Window ns toaa SEM Address Access Time 12 15 20 ns Data Retention Mode Timing The CY7C026 and CY7036 are designed with battery backup in mind. Data retention voltage and supply current are guaran- teed over temperature. The following rules ensure data reten- tion: 1. Chip enable (CE) mustbe held HIGH during data retention, with- in Vec to Vec -0.2V. 2. CE must be kept between Voc 0.2V and 70% of Voc during the power-up and power-down transitions. 3. The RAM can begin operation >tpc after Voc reaches the minimum operating voltage (4.5 volts). Notes: 13. Test conditions used are Load 2. Voc x Lj Data Retention Mode < 4.5V Vec > 2.0V Vee to Vee - 0.2V 4.5V Parameter Test Conditions!"*! Max. Unit ICCpri @ VCCpp = 2V 1.5 mA 14. tppp is a calculated parameter and is the greater of tywoptpwe (actual) or tppp-tgp (actual). 15. CE=Voc, Vin = GND to Veg, Ta = 25C. This parameter is guaranteed but not tested.Fo CY7C026 7 CYPRESS PRELIMINARY CY7C036 Switching Waveforms Read Cycle No.1 (Either Port Address Access)!'17,18] < tac > ADDRESS * * a taa | pe tonn > te tona DATA OUT PREVIOUS DATA VALID *K x x DATA VALID x x Read Cycle No.2 (Either Port CE/OE Access)!'619.20] t CE and [ACE LB or UB tuzce __ tpoe OE tHZOE tLZOE DATA OUT DATA VALID tLZcE tey < loc CURRENT 7 Isp Read Cycle No. 3 (Either Port)!118.19,20] ADDRESS _ x tpp tre > <a al Ow 9 | DATA OUT Notes: 16. R/Wis HIGH for read cycles. __ 17. Device is continuously selected CE = V\_ and UB or LB = Vi. This waveform cannot be used for semaphore reads. 18. OE=Vj. 19. Address valid prior to or coincident with CE transition LOW. _ 20. To access RAM, CE = Vj, UBor LB = Vi_, SEM = Vip. To access sernaphore, CE = Viy, SEM = V_.Fo CY7C026 7 CYPRESS PRELIMINARY CY7C036 Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing!2122.22,241 nt twe > ADDRESS * x % TNL ag [25,26] N / CF N / e toa $< _<_$_$____- tpw_l@4l ie tua RAV A fe tyzwel?/] < t| we. _ >} DATA OUT < NOTE 28 < NOTE 28 _ y__ tsp <_ ty DATA IN Write Cycle No. 2: CE Controlled Timing!?" 2223.29] wt twe ADDRESS * to) taw > [25,26] ~ | cE! 26] KN r<# tsa << tsce et tha > RAV \ / ea tsp ate ty DATA IN Notes: 21. R/W must be HIGH during all address transitions. Le Le 22. Awrite occurs during the overlap (tgog or tpwe) of a LOW CE or SEM and a LOW UB or LB. 23. ty is measured from the earlier of CE or RW or (SEM or RAW) going HIGH at the end of write cycle. 24. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of toye or (Iuzye + tgp) to allow the I/O drivers to turn off and data to be placed on the bus for the required tgp. If OE is HIGH during an RW controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tpye. 25. To access RAM, CE=V, SEM=Vjy. 26. To access upper byte, CE = Vi, UB = Vi, SEM=Vjp. To access lower byte, CE = Vi_, LB = Vi_, SEM= V4. 27. Transition is measured +500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 28. During this period, the I/O pins are in the output state, and input signals must not be applied. 29. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.Fo CY7C026 7 CYPRESS PRELIMINARY CY7C036 Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side! < tsaa> toHA works KOK amas KX KKK _wrmnenes KX XXX t<__ tay >! : [ACE SE HA Ne ux YW on OZ tsp /0 4 DATA jy VALID DATA yr VALID 7 tu > tsa tpwe > RAV T] L Y +~<_| tswapD + tboE > __ if A SAL AA J J. J > Vv, AZZ SAR / jua WRITE CYCLE pg_ READ CYCLE _}, Timing Diagram of Semaphore Contention 31:52,33] AotAat MATCH xX tsps Aor-Aor MATCH x Notes: 30. CE=HIGH for the duration of the above timing (both write and read cycle). 31. Opn ='/O9, = LOW (request semaphore); CER = CE, = HIGH. 32. Semaphores are reset (available to both ports) at cycle start. 33. If tgpg is violated, the sernaphore will definitely be obtained by one side or the other, but which side will get the sernaphore is unpredictable. 10Fo CY7C026 7 CYPRESS PRELIMINARY CY7C036 Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)!*4! in) twe > ADDRESSR * MATCH *K R/AWR Ni tpwe "lV RK / fg tSD pteqp tHD DATA INp * *K VALID tps ADDRESS, * MATCH t BLA | ete toa BUSY K tapD > topp > SK vaup twob Write Timing with Busy Input (M/S=LOW) __ tpwe RAV < two twH BUSY Note: 34. CE, = CER, =LOW. 11Fo CY7C026 7 CYPRESS PRELIMINARY CY7C036 Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration)!5! CE, Valid First: ADDRESS p x ADDRESS MATCH x CE, _ je tps CER tBLe be tBHe BUSY, CE, Valid First: ADDRESS, a x ADDRESS MATCH x fi # i- tps | rr taLe be tayo | BUSY, Busy Timing Diagram No. 2 (Address Arbitration)*! Left Address Valid First: tac or two 4+ ADDRESS _ ADDRESS MATCH *K ADDRESS MISMATCH x ~ tps ADDRESSR x tBLA f BHA BUSY R Right Address Valid First: tac or two ADDRESSR ADDRESS MATCH *K ADDRESS MISMATCH x tps ADDRESS, x < iBLA t BHA BUSY. Note: 35. If tpg is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.=~ CY7C026 PRELIMINARY 77 cypress CV7C036 Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTp: < twe > rooress, >K wares KK [36] r CE, tHA iN RW, _ __ N INT " N fe tyyg 37] __ 5 Right Side Clears INTR: tac ADDRESSR READ 3FFF CER > fo _ tal8/] R/Wa / / / bia OER \ / INTR Fi Right Side Sets INT_: two rooness, > wares KX KK _ tual CER -~\ \ RiWp -_ N\ INT, <__ te? Left Side Clears INT_: tae ADDRESSpR READ 3FFE = trnals7]);. _ N / Notes: 36. ty depends on which enable pin (CE, or RW) is deasserted first. 37. ting OF tin depends on which enable pin (CE_ or RM) is asserted last. 137 CYPRESS PRELIMINARY CY7C026 CY7C036 Architecture The CY7C026 and CY7036 consist of an array of 16K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins per- mit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devic- es can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic pow- er-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Functional Description Write Operation Data must be set up for a duration of tgp before the rising edge of RW in order to guarantee a valid write. A write operation is con- trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 7. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; other- wise the data read is not deterministic. Data will be valid on the port tppp after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tacg after CE or too after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (8FFF) is the mailbox for the right port and the second-highest memory location (S3FFE) is the mailbox for the left port. When one port writes to the other ports mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other ports mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processors interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C026 and CY7036 provide on-chip arbitration to re- solve simultaneous memory location access (contention). If both ports CEs are asserted and an address match occurs within 14 tps of each other, the busy logic will determine which port has access. If tpg is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted ty) q after an address match or tg, c after CE is taken LOW. Master/Slave A M/S pinis provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tg) or tg) a), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin al- lows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C026 and CY7036 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero toa semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tgop before attempting to read the semaphore. The semaphore value will be available tgy;wrp + tpoe after the rising edge of the semaphore write. If the left port was suc- cessful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relin- quished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). Ap_ represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only |/Og is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to ac- cess the semaphore within tgps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guaran- tee which side will control the semaphore.CY7C026 oN 7 cYPRE ss PRELIMINARY CY7C036 Table 1. Non-Contending Read/Write Inputs Outputs CE RW OE UB LB SEM VOo4/047 V/Oo/Og Operation H Xx Xx Xx X H High Z High Z Deselected: Power-Down Xx Xx Xx H H H High Z High Z Deselected: Power-Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L Xx L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes Xx Xx H Xx X X High Z High Z Outputs Disabled H H L Xx Xx L Data Out Data Out Read Data in Semaphore Flag Xx H L H H L Data Out Data Out Read Data in Semaphore Flag H xX xX xX L Data In Data In Write Dj\g into Semaphore Flag xX xX H H L Data In Data In Write Dj\g into Semaphore Flag L X X L X L Not Allowed L X X X L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSY, =BUSYp=HIGH) Left Port Right Port Function RW, CE, OE, Ao_-1 3L INT, R/Wep CER OER Aor-1 3R INTp Set Right INTp Flag L L xX 3FFF xX xX x x x LB9] Reset Right INTp Flag xX xX xX xX xX xX L L 3FFF Hse) Set Left INT, Flag xX xX xX xX Le) L L x 3FFE x Reset Left INT, Flag xX L L 3FFE HE} xX x x x x Table 3. Semaphore Operation Example Function 1/O 9/047 Left | 1/O94/0,7 Right Status No action 1 Semaphore free Left port writes 0 to semaphore Left Port has semaphore token Right port writes 0 to semaphore No change. Right side has no write access to semaphore Left port writes 1 to semaphore Right port obtains semaphore token Left port writes 0 to semaphore No change. Left port has no write access to semaphore Right port writes 1 to semaphore Left port obtains semaphore token Left port writes 1 to semaphore Semaphore free Right port writes 0 to semaphore Right port has semaphore token Right port writes 1 to semaphore Semaphore free Left port writes 0 to semaphore Left port has semaphore token Left port writes 1 to semaphore s/o}; =| =| =| of =| =| ol o a/ =} =| o/ =| =| co] of 4] =] a Semaphore free Notes: 38. If BUSYR=L, then no change. 39. If BUSY,=L, then no change. 15CY7C026 =r. 7 cYPRE ss PRELIMINARY CY7C036 Ordering Information 16K x16 Asynchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C026-12AC A100 100-Pin Thin Quad Flat Pack Commercial 15 CY7C026-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C026-15Al A100 100-Pin Thin Quad Flat Pack Industrial 20 CY7C026-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C026-20Al A100 100-Pin Thin Quad Flat Pack Industrial 16K x18 Asynchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C036-12AC A100 100-Pin Thin Quad Flat Pack Commercial 15 CY7C036-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C036-15Al A100 100-Pin Thin Quad Flat Pack Industrial 20 CY7C036-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C036-20Al A100 100-Pin Thin Quad Flat Pack Industrial Document #: 38800674-B 16CY7C026 = PRELIMINARY CY7C036 Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 16002025 SO e_______ 14.0020.05 SQ _____ 100 76 DIMENSIONS ARE IN MILLIMETERS. HHAAAAR AA RAAAR AAR AAA 7 1 ES 75 r 0.22+0.05 oo R 008 MIN. = =U 0 MIN. 0.20 MAX. = = STAND-DFF = = ap ain (| [ozs = 4 O15 WAX. | HH GAUGE PLANE og = | = = } ~ = et sat or = = 050 020 MIN. = = TYP. he 0.6020.15 = ES 1.00 REF. La 5-4 a 51 51-85048-A POE EEE EEE EEE peta 26 50 aA SEATING PLANE 12%21* 8X) N+ 7 1.402005 4 SEE DeTaIL A Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.