A1354KKTTN-T - Allegro Microsystems

NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.

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for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The

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High Precision 2-Wire Linear Hall Ef fect Sensor IC

With Pulse Width Modulated Output

A1354

For existing customer transition, and for new customers or new appli-

cations, contact Allegro Sales.

Date of status change: April 30, 2012

This device is no longer in production. The device should not be

purchased for new design applications. Samples are no longer available.

Discontinued Product

Description

The A1354 device is a high precision, programmable 2-wire

Hall effect linear sensor IC with a pulse width modulated

(PWM) output. The duty cycle (D) of the PWM output signal

is proportional to the applied magnetic field. The A1354

device converts an analog signal from its internal Hall circuit

to a digitally encoded PWM output signal. The coupled noise

immunity of the digitally encoded PWM output is far superior

to the noise immunity of an analog output signal.

The BiCMOS, monolithic circuit inside of the A1354 integrates

a Hall element, precision temperature-compensating circuitry

to reduce the intrinsic sensitivity and offset drift of the Hall

element, a small-signal high-gain amplifier, proprietary

dynamic offset cancellation circuits, and PWM conversion

circuitry. The dynamic offset cancellation circuits reduce

the residual offset voltage of the Hall element. Hall element

offset is normally caused by device overmolding, temperature

dependencies, and thermal stress. The high frequency offset

cancellation (chopping) clock allows a greater sampling rate,

which increases the accuracy of the output signal and results

in faster signal processing capability.

The A1354 device is provided in a lead (Pb) free 4-pin single

inline package (KT suffix), with 100% matte tin leadframe

plating.

A1354-DS, Rev. 1

Features and Benefits

 Designed for automotive, battery-powered applications

 Customer programmable quiescent duty cycle, sensitivity,

and PWM carrier frequency, through VCC pin

 Simultaneous programming of duty cycle, sensitivity, and

PWM carrier frequency, for system optimization

 Factory programmed sensitivity temperature coefficient

and quiescent duty cycle drift

 Selectable unidirectional or bidirectional quiescent

duty cycles

 Pulse width modulated (PWM) output provides increased

noise immunity compared to analog output

 Temperature-stable quiescent duty cycle output and

sensitivity

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

Package: 4-pin SIP (suffix KT)

Functional Block Diagram

Not to scale

A1354

Continued on the next page…

1 mm case thickness

VCC

GND

RSens

VCC

Temperature

Compensation

Programming

Interface

Chopper

Switches

Programming

Logic

Signal

Recovery

Switched

Capacitor

Control

PWM Carrier

Generation

and Trimming

Regulator

% Duty Cycle

Temperature

Coefficient

Voltage

Controlled

Current

Source

% Duty

Cycle

Sensitivity

and Sensitivity

TC Trim

Amp

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Pin-out Diagram

Branded

Face

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit

Forward Supply Voltage VCC 28 V

Reverse Supply Voltage VRCC –16 V

Forward Supply Current ICC 50 mA

Reverse Supply Current IRCC –50 mA

Operating Ambient Temperature TARange K –40 to 125 ºC

Maximum Junction Temperature TJ(max) 165 ºC

Storage Temperature Tstg –65 to 165 ºC

Terminal List

Number Name Function

1 VCC Input power supply; use bypass capacitor to connect to ground

2 NC Not connected

3 NC Not connected

4 GND Ground

Features and Benefits (continued)

Selection Guide

Part Number Packing*

A1354KKTTN-T 4000 pieces per 13-in. reel

*Contact Allegro® for additional packing options

 Output duty cycle clamps provide short circuit diagnostic

capabilities

 Optional 50% duty cycle calibration test mode at device power-up

 Wide ambient temperature range: –40°C to 125°C

 Resistant to mechanical stress

 Extremely thin package: 1 mm case thickness

2341

OPERATING CHARACTERISTICS (A) Valid with CBYPASS = 0.01 μF, over full operating temperature range, TA , and VCC, unless otherwise

noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit1

ELECTRICAL CHARACTERISTICS

Supply Voltage2VCC 4.5 12 16 V

Supply Current ICC(LOW) –69mA

ICC(HIGH) 13 – 19 mA

Supply Current Ratio3ICC(rat) 2–– –

Power-On Time4tPO

TA = 25°C, CL (of test probe)= 10 pF,

Sens = 0.1%/G, fPWM = fPWM(slow)

– 100 – ms

TA = 25°C, CL (of test probe)= 10 pF,

Sens = 0.1%/G, fPWM = fPWM(fast)

–25– ms

Supply Zener Clamp Voltage VZTA = 25°C, ICC = ICC(max) + 3 mA 28.5 32 – V

Internal Bandwidth BWi

Small signal –3 dB, 100 G(P-P) magnetic input

signal – 200 – Hz

Chopping Frequency5fCTA = 25°C – 200 – kHz

OUTPUT CHARACTERISTICS

Response Time4tRESPONSE

TA = 25°C, Impulse magnetic field of 300 G,

Sens = 0.1%/G, fPWM = fPWM(slow) – 100 – ms

TA = 25°C, Impulse magnetic field of 300 G,

Sens = 0.1%/G, fPWM = fPWM(fast) –25– ms

Clamp Duty Cycles6DCLP(HIGH) TA = 25°C 90 92.5 95 %

DCLP(LOW) TA = 25°C 5 7.5 10 %

Duty Cycle Jitter4,7 JitterPWM

TA = –10°C to 85°C, Sens = 0.12%/G, Measured

over 1000 Output PWM clock periods – ±0.05 – %

Duty Cycle Resolution ResPWM

TA = –10°C to 85°C, Sens = 0.12%/G, Measured

over 1000 Output PWM clock periods – ±0.42 – G

11 G (gauss) = 0.1 mT (millitesla).

2Supply voltage, VCC, is defined as the voltage drop between pin 1 and pin 4 of the device. It does not include the voltage drop across RSENS.

3ICC ratio is defined as ICC(HIGH) / ICC(LOW) for a given PWM cycle.

4See Characteristic Definitions section.

5fC varies up to approximately ±20% over the full operating ambient temperature range, TA, and process.

6Clamp duty cycles are tested with the maximum sensitivity code addressed and an applied magnetic field that is at least 25% greater than

the dynamic range.

7Jitter is dependent on the sensitivity of the device. Values are based on characterization only and are not guaranteed via production testing.

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PROGRAMMING CHARACTERISTICS Valid over full operating voltage range and TA = 25°C

, unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit1

PRE-PROGRAMMING TARGET2

Pre-Programming Quiescent Duty Cycle

Output D(Q)PRE B = 0 G – 50 – %

Pre-Programming Sensitivity SensPRE – 0.08 – %/G

Pre-Programming PWM Output Carrier

Frequency fPWMPRE – 150 – Hz

QUIESCENT DUTY CYCLE PROGRAMMING

Initial Quiescent Duty Cycle Output3D(Q)UNIinit Unipolar device, B = 0 G – 20 – %

D(Q)BIinit Bipolar device, B = 0 G – D(Q)PRE –%

Guaranteed Quiescent Duty Cycle

Programming Range4

D(Q)UNI Unipolar device, B = 0 G 10 – 30 %

D(Q)BI Bipolar device, B = 0 G 40 – 60 %

Quiescent Duty Cycle Output5

Programming Bits

Coarse (range programming) – 1 – bit

Fine (value adjustment) – 9 – bit

Average Quiescent Duty Cycle Output

Step Size6,7 StepD(Q) 0.055 0.075 0.095 %

Quiescent Duty Cycle Output

Programming Resolution8ErrPGD(Q) –StepD(Q)

× ±0.5 –%

SENSITIVITY PROGRAMMING

Initial Sensitivity Sensinit – SensPRE –%/G

Guaranteed Sensitivity Programming

Range9Sens 0.1 – 0.2 %/G

Sensitivity Programming Bits – 8 – bit

Average Sensitivity Step Size6,7 StepSENS 600 800 900 %/G

Sensitivity Programming Resolution8ErrPGSENS –StepSENS

× ±0.5 –%/G

CARRIER FREQUENCY PROGRAMMING

Initial Carrier Frequency fPWM(slow)init –19– Hz

fPWM(fast)init –f

PWMPRE –Hz

Guaranteed Carrier Frequency

Programming Range9

fPWM(slow) 12 – 15.5 Hz

fPWM(fast) 95 – 115 Hz

Coarse Carrier Frequency Programming

Bits10

Coarse (range programming) – 1 – bit

Fine (value adjustment) – 4 – bit

Average Carrier Frequency Step Size6,7 StepfPWM(slow) 0.5 0.8 1.1 Hz

StepfPWM(fast) 4.5 6.4 8.3 Hz

Carrier Frequency Programming

Resolution8ErrPGfPWM –StepfPWM

× ±0.5 –Hz

Continued on the next page…

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PROGRAMMING CHARACTERISTICS (continued) Valid over full operating temperature range, TA , and VCC

, unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit1

CALIBRATION TEST MODE PROGRAMMING

Calibration Test Mode Selection Bit – 1 – bit

LOCK BIT PROGRAMMING

Overall Programming Lock Bit – 1 – bit

11 G (gauss) = 0.1 mT (millitesla).

2Raw device characteristic values before any programming.

3D(Q)UNIinit may be below the clamp duty cycle DCLP(LOW). D(Q) will not appear to respond to programming pulses until D(Q) > DCLP(LOW).

4D(Q)(max) is the value guaranteed with all programming fuses blown (maximum programming code set). The D(Q) range is the total range from

D(Q)init up to and including D(Q)(max). See Characteristic Definitions section.

5Bit for selecting between D(Q)BI and D(Q)UNI programming ranges.

6Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.

7Non-ideal behavior in the programming D-to-A converter (DAC) can cause the step size at each significant bit rollover code to be greater than twice

the maximum specified value of StepD(Q) , StepSENS , or StepfPWM.

8Overall programming value accuracy. See Characteristic Definitions section.

9fPWM(max) is the value available with all programming fuses blown (maximum programming code set). fPWM range is the total range from fPWMinit up

to and including fPWM(max). See Characteristic Definitions section.

10Bit for selecting between fPWM(fast) and fPWM(slow) programming ranges.

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

OPERATING CHARACTERISTICS (B) Valid with CBYPASS = 0.01 μF, over full operating temperature range, TA , and VCC

, unless

otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

FACTORY PROGRAMMED SENSITIVITY TEMPERATURE COEFFICIENT AND SENSITIVITY DRIFT

Sensitivity Temperature Coefficient1TCSens – 0.12 – %/°C

Maximum Sensitivity Drift Through

Temperature Range2,3 ΔSensTC

Sens = SensPRE , D = D(Q)PRE, calculated at

125°C – < ±2 – %

Sensitivity Drift Due to Package

Hysteresis3,4 ΔSensPKG TA = 25°C, after temperature cycling – < ±1.2 – %

FACTORY PROGRAMMED DUTY CYCLE DRIFT

Duty Cycle Drift1,3 ΔD(Q) B = 0 G – 0 – %

Duty Cycle Drift Error3ErrΔD(Q) B = 0 G, Sens = SensPRE , D = D(Q)pre – < ±0.3 – %

ERROR COMPONENTS

Linearity Sensitivity Error3LinERR – < ±1.0 – %

Symmetry Sensitivity Error3,5 SymERR – < ±1.5 – %

1Programmed at 125°C and calculated relative to 25°C.

2Sensitivity drift from expected value at TA after programming TCSENS. See Characteristic Definitions section.

3Specification unit is defined in percent as result of the calculation shown in the Characteristics Definitions section.

4See Characteristic Definitions section.

5Symmetry error is only valid for bipolar devices.

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA 1-layer PCB with copper limited to solder pads 174 ºC/W

*Additional thermal information available on Allegro website.

Thermal Characteristics may require derating at maximum conditions

20 40 60 80 100 120 140 160 180

Temperature, T

(°C)

Power Dissipation, P

(mW)

300

400

200

100

600

500

800

700

900

Power Dissipation versus Ambient Temperature

(RQJA = 174 ºC/W)

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

tHigh – duration of high voltage

tLow – duration of the low voltage

TPeriod – one full frequency cycle

Duty Cycle = (tHigh / TPeriod) × 100%

VCC at Various Duty Cycles

4 μs per division

≈10% Duty Cycle

(Low Clamp)

≈ 50% Duty Cycle

≈ 90% Duty Cycle

(High Clamp)

Unidirectional Field Detection

Duty Cycle Field Detection

10% 0 G

10%-90% 0 to +n G (south)

Bidirectional Field Detection

Duty Cycle Field Detection

50% 0 G

50%-90% 0 to +n G (south)

50%-10% 0 to –n G (north)

tHigh

TPeriod

tLow

tHigh

TPeriod

tLow

tHigh

TPeriod

tLow

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Quiescent Voltage Output and Duty Cycle The operating

output voltage, VOUT , is determined by the PWM output voltage

duty cycle, D. In turn, D is proportional to a change in air gap

between the A1354 Hall element and the magnetic target. The

output duty cycle in the quiescent state (no significant magnetic

field: B = 0 G), D(Q)

, remains steady at the specific programmed

duty cycle throughout the entire operating ranges of VCC and

ambient temperature, TA.

Power-On Time When the supply is ramped to its operating

voltage, the device requires a finite time to power its internal

components before supplying a valid PWM output duty cycle.

Power-On Time, tPO , is defined as the time it takes, with no

applied magnetic field (quiescent state), for the PWM output

voltage duty cycle, D(Q) , to settle within ±5% of its steady state

value, after the power supply has reached its minimum specified

operating voltage, VCC(min).

Response Time The time interval, tRESPONSE , between a) when

the applied magnetic field reaches 90% of its final value, and b)

when the device reaches 90% of its output level corresponding to

the applied magnetic field. tRESPONSE depends on the signal delay

defined by the device filter bandwidth, BWi , and a full PWM

period, which is required for output update.

Guaranteed Quiescent Duty Cycle Output Range The

quiescent duty cycle output, D(Q)

, can be programmed within

the guaranteed quiescent duty cycle range limits: D(Q)(min) and

D(Q)(max). The available guaranteed programming range for D(Q)

falls within the distributions of the initial duty cycle, D(Q)init

, and

of the maximum programming code for setting D(Q) , as shown in

figure 1.

Average Quiescent Duty Cycle Output Step Size The

average quiescent duty cycle output step size, StepD(Q) , for a

single device is determined using the following calculation:

D(Q)maxcode – D(Q)mincode

2n –1

StepD(Q) =, (1)

where:

n is the number of available programming bits in the trim range,

2n –1 is the value of the maximum programming code in the

range, and

D(Q)maxcode is the quiescent output duty cycle at code 2n –1.

Quiescent Duty Cycle Output Programming Resolution

The programming resolution for any device is half of its pro-

gramming step size. Therefore, the typical programming resolu-

tion is:

ErrPGD(Q)(typ) =0.5 × StepD(Q)(typ) .

(2)

Quiescent Output Duty Cycle Drift Through Tempera-

ture Range Due to internal component tolerances and thermal

considerations, the quiescent duty cycle temperature coefficient,

TCD(Q), may drift from its nominal value over the range of the

operating ambient temperature, TA. For purposes of specification,

the Quiescent Duty Cycle Output Drift Through Temperature

Range, D(Q) (%), is defined as:

D(Q)(TA) – D(Q)(25°C)

∆D(Q) =.

(3)

D(Q) should be calculated using the actual measured values of

D(Q)(ΔTA) and D(Q)(25°C) rather than ideal programming target

values.

Sensitivity The presence of a south polarity magnetic field,

perpendicular to the branded face of the package, increases the

output duty cycle from its quiescent value toward the maximum

duty cycle limit. The amount of the output duty cycle increase

is proportional to the magnitude of the magnetic field applied.

Conversely, the application of a north polarity field decreases the

output duty cycle from its quiescent value. This proportionality is

specified as the magnetic sensitivity, Sens (%/G), of the device,

and it is defined for bipolar devices as:

D(BPOS) – D(BNEG)

BPOS – BNEG

Sens =, (4)

Characteristic Definitions

Guaranteed D(Q)

Programming

Range

D(Q)(min) D(Q)(max)

Max Code D(Q)

Distribution

Min Code D(Q)

Distribution

Initial D(Q)

Distribution

Figure 1. Quiescent output duty cycle versus time

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

and for unipolar devices as:

D(BPOS) – D(Q)

BPOS

Sens =, (5)

where BPOS and BNEG are two magnetic fields with opposite

polarities.

Guaranteed Sensitivity Range The magnetic sensitivity,

Sens, can be programmed around its nominal value within the

sensitivity range limits: Sens(min) and Sens(max). Refer to the

Guaranteed Quiescent Duty Cycle Output Range section for a

conceptual explanation of how value distributions and ranges are

related.

Average Sensitivity Step Size Refer to the Average Qui-

escent Duty Cycle Output Step Size section for a conceptual

explanation.

Sensitivity Programming Resolution Refer to the Quies-

cent Duty Cycle Output Programming Resolution section for a

conceptual explanation.

Guaranteed Carrier Frequency Range The PWM output

signal carrier frequency, fPWM, can be programmed around its

nominal value in fast mode or slow mode.

Average Carrier Frequency Step Size Refer to the Average

Quiescent Duty Cycle Output Step Size section for a conceptual

explanation.

Carrier Frequency Programming Resolution Refer to the

Quiescent Duty Cycle Output Programming Resolution section

for a conceptual explanation.

Sensitivity Temperature Coefficient Device Sensitiv-

ity changes as temperature changes, with respect to its pro-

grammed sensitivity temperature coefficient, TCSENS. TCSENS

is programmed at 125°C, and calculated relative to the nominal

sensitivity programming temperature of 25°C. TCSENS (%/°C) is

defined as:

SensT2 – SensT1

SensT1 T2–T1

TCSens =×

100% ,

























(6)

where T1 is the nominal Sens programming temperature of 25°C,

and T2 is the TCSENS programming temperature of 125°C. The

expected value of Sens over the full ambient temperature range,

SensEXPECTED(TA), is defined as:

SensT1× [100% +TCSENS (TA –T1)]

SensEXPECTED(TA) =100 % (7)

SensEXPECTED(TA) should be calculated using the actual measured

values of SensT1 and TCSENS rather than ideal programming

target values.

Sensitivity Drift Through Temperature Range Second

order sensitivity temperature coefficient effects cause the mag-

netic sensitivity, Sens, to drift from its expected value over the

operating ambient temperature range, TA. For purposes of speci-

fication, the sensitivity drift through temperature range, SensTC,

is defined as:

SensTA – SensEXPECTED(TA)

SensEXPECTED(TA)

∆SensTC =×

100% .

(8)

Sensitivity Drift Due to Package Hysteresis Package

stress and stress relaxation can cause the device sensitivity at

TA = 25°C to change during and after temperature cycling.

For purposes of specification, the sensitivity drift due to package

hysteresis, SensPKG, is defined as:

Sens(25°C)2 – Sens(25°C)1

Sens(25°C)1

∆SensPKG =×

100% ,

(9)

where Sens(25°C)1 is the programmed value of sensitivity at

TA = 25°C, and Sens(25°C)2 is the value of sensitivity at TA =

25°C, after temperature cycling TA up to 125°C, down to –40°C,

and back to up 25°C.

Linearity Sensitivity Error The A1354 is designed to provide

a linear output in response to a ramping applied magnetic field.

Consider two magnetic fields, B1 and B2. Ideally, the sensitivity

of a device is the same for both fields, for a given supply voltage

and temperature. Linearity error is present when there is a differ-

ence between the sensitivities measured at B1 and B2.

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Linearity Error is calculated separately for the positive

(LinERRPOS

) and negative (LinERRNEG ) applied magnetic fields.

Linearity error (%) is measured and defined as:

=×% ,

¾–¾

LinERRPOS D(+B½)– D(Q) 

–

D(+B) D(Q)













=×% ,

¾–¾

LinERRNEG D(–B½)– D(Q) 

–

D(–B) D(Q)













(10)

where:

|D(Bx) – D(Q)|

SensBx=. (11)

Then:

LinERR = max( LinERRPOS , LinERRNEG ) . (12)

Note that unipolar devices only have positive linearity error

(LINERRPOS).

Symmetry Sensitivity Error The magnetic sensitivity of an

A1354 device is constant for any two applied magnetic fields of

equal magnitude and opposite polarities. Symmetry error,

SymERR (%), is measured and defined as:

=×% ,

¾–¾

SymERR D(Q)– D(–B)

–

D(+B) D(Q)













(13)

where SensBx is as defined in equation 11, and BPOS and BNEG

are positive and negative magnetic fields such that |BPOS| =

|BNEG|. Note that the symmetry error specification is only valid

for bipolar devices.

Jitter The duty cycle of the PWM output may vary slightly over

time despite the presence of a constant applied magnetic field and

a constant carrier frequency for the PWM signal. This phenom-

enon is known as jitter, JitterPWM (%), and is defined as:

DBmax – DBmin

JitterPWM =,

(14)

where DBmax and DBmin are the maximum and minimum duty

cycles measured the over 1000 PWM clock periods with a con-

stant applied magnetic field.

Resolution The ability to derive the value of the applied mag-

netic field from the device output is affected by jitter. The resolu-

tion of the magnetic field, RESPWM (G), is defined as:

JitterPWM

Sens

RESPWM =. (15)

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for

switchpoint accuracy is the small signal voltage developed

across the Hall element. This voltage is disproportionally small

relative to the offset that can be produced at the output of the

Hall element. This makes it difficult to process the signal while

maintaining an accurate, reliable output over the specified operat-

ing temperature and voltage ranges. Chopper stabilization is a

unique approach used to minimize Hall offset on the chip. The

patented Allegro technique, namely Dynamic Quadrature Offset

Cancellation, removes key sources of the output drift induced by

thermal and mechanical stresses. This offset reduction technique

is based on a signal modulation-demodulation process. The

undesired offset signal is separated from the magnetic field-

induced signal in the frequency domain, through modulation.

The subsequent demodulation acts as a modulation process for

the offset, causing the magnetic field-induced signal to recover

its original spectrum at base band, while the DC offset becomes

a high frequency signal. The magnetic-sourced signal then can

pass through a low-pass filter, while the modulated DC offset is

suppressed. The chopper stabilization technique uses a 200 kHz

high frequency clock. For demodulation process, a sample and

hold technique is used, where the sampling is performed at twice

the chopper frequency (400 kHz). This high-frequency operation

allows a greater sampling rate, which results in higher accuracy

and faster signal-processing capability. This approach desensi-

tizes the chip to the effects of thermal and mechanical stresses,

and produces devices that have extremely stable quiescent Hall

output voltages and precise recoverability after temperature

cycling. This technique is made possible through the use of a

BiCMOS process, which allows the use of low-offset, low-noise

amplifiers in combination with high-density logic integration and

sample-and-hold circuits.

Amp

Regulator

Clock/Logic

Hall Element

Sample and

Hold

Low-Pass

Filter

Typical Application Drawings

VCC

GND

RSENS

CBYPASS

0.01 μF

CBYPASS

0.01 μF

A1354

VCC

GND

RSENS

A1354

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Overview

Programming is accomplished by sending a series of input voltage

pulses serially through the VCC pin of the device. Unique combi-

nations of different voltage amplitude pulses control the internal

programming logic of the device to select a programmable param-

eter and set its value. There are three voltage levels that must be

taken into account when programming using a high voltage pulse,

VPH (consisting of a VP(LOW) – VP(HIGH) – VP(LOW) sequence),

and a mid voltage pulse, VPM (consisting of a VP(LOW) – VP(MID)

– VP(LOW) sequence). The low voltage level, VP(LOW)

, separates the

VPH and VPM programming pulses.

The 1354 features Try mode, Blow mode, and Lock mode:

• In Try mode, the value of multiple programmable parameters

may be set and measured simultaneously. The parameter values

are stored temporarily, and reset after cycling the supply volt-

age.

• In Blow mode, the value of a single programmable parameter

may be set, measured, and permanently set by blowing solid-

state fuses internal to the device. Additional parameters may be

blown sequentially. This mode is used for blowing the device-

level fuse, which permanently blocks the further programming

of all parameters.

• Lock mode prevents all future programming of the device. This

is accomplished by blowing a special fuse using blow mode.

The programming sequence is designed to help prevent the device

from being programmed accidentally; for example, as a result of

noise on the supply line. Although any programmable variable

power supply can be used to generate the pulse waveforms, Allegro

highly recommends using the Allegro Sensor IC Evaluation Kit,

available on the Allegro website On-line Store. The manual for that

kit is available for download free of charge, and provides addi-

tional information on programming these devices.

Definition of Terms

choice of programmable modes and parameters.

Bitfield The internal fuses unique to each register, represented as

a binary number. Incrementing the bitfields of a particular register

causes its programmable parameter to change, based on the internal

programming logic.

Key A series of mid voltage pulses used to select a register, with a

value expressed as the decimal equivalent of the binary value. The

LSB of a register is denoted as key 1, or bitfield 0.

Code The number used to identify the combination of fuses

activated in a bitfield, expressed as the decimal equivalent of the

binary value. The LSB of a bitfield is denoted as code 1, or bit 0.

Addressing Incrementing the bit field code of a selected regis-

ter by serially applying a pulse train through the VCC pin of the

device. Each parameter can be measured during the addressing pro-

cess, but the internal fuses must be blown before the programming

code (and parameter value) becomes permanent.

Fuse Blowing Applying a high pulse of sufficient duration to

permanently set an addressed bit by blowing a fuse internal to the

device. Once a bit (fuse) has been blown, it cannot be reset.

Blow Pulse A high pulse of sufficient duration to blow the

addressed fuse.

Cycling the Supply Powering-down, and then powering-up the

supply voltage. Cycling the supply is used to clear the program-

ming settings in Try mode.

Programming Guidelines

Programming Pulse Requirements, Protocol at TA = 25 °C

Characteristic Symbol Notes Min. Typ. Max. Unit

Programming

Voltage

VP(LOW)

Measured at the VCC pin.

4.5 5 5.5 V

VP(MID) 13 15 16 V

VP(HIGH) 26 27 28 V

Programming

Current IP

Minimum supply current required to ensure proper fuse blowing. In addition, a

minimum capacitance, CBLOW = 0.1 μF, must be connected between the VCC and

GND pins during programming to provide the current necessary for fuse blowing.

The blowing capacitor should be removed and the load capacitance used for properly

programming duty cycle measurements.

300 – – mA

Pulse Width

tLOW Duration of VP(LOW) for separating VP(MID) and VP(HIGH) pulses. 40 – – μs

tACTIVE Duration of VP(MID) and VP(HIGH) pulses for register selection or bitfield addressing. 40 – – μs

tBLOW Duration of VP(HIGH) pulses for fuse blowing. 40 – – μs

Pulse Rise Time tPr Rise time required for transitions from VP(LOW) to either VP(MID) or VP(HIGH). 5 – 100 μs

Pulse Fall Time tPf Fall time required for transitions from VP(HIGH) to either VP(MID) or VP(LOW). 5 – 100 μs

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Mode and Parameter Register Selection

Each mode and programmable parameter can be accessed through

a specific register. To select a register, a sequence of voltage

pulses consisting of a VPH pulse, a series of VPM pulses, and a

VPH pulse (with no VCC supply interruptions) must be applied

serially to the VCC pin. The number of VPM pulses is called the

key, and uniquely identifies each register. The pulse train used for

selection of the first register, key 1, is shown in figure 2.

The A1354 has two registers that select among the three program-

ming modes:

Blow and Lock

Try

Also, it has four registers that select among the seven program-

mable parameters:

Sensitivity, Sens

Coarse quiescent duty cycle, D(Q)

Fine quiescent duty cycle output, D(Q)

Coarse pulse width modulated carrier frequency

Pulse width modulated carrier frequency, fPWM

Calibration Test Mode

Overall device Lock Bit, LOCK

Bitfield Addressing

After a parameter register has been selected, a VPH pulse transi-

tions the programming logic into the bitfield addressing state.

Applying a series of VPM pulses to the VCC pin of the device, as

shown in figure 3, increments the bitfield of the selected param-

eter.

When addressing the bitfield, the number of VPM pulses is

represented by a decimal number called the code. Addressing

activates the corresponding fuse locations in the given bitfield by

incrementing the binary value of an internal DAC. The value of

the bitfield (and code) increments by one with the falling edge of

each VPM pulse, up to the maximum possible code for the reg-

ister (see the Programming Logic table). As the code increases,

the value of the programmable parameter changes. Measurements

can be taken after each VPM pulse to determine if the desired

result for the programmable parameter has been reached. Cycling

the supply voltage resets all the locations in the bitfield that have

unblown fuses to their initial states.

Fuse Blowing

After the required code is found for a given parameter, its value

can be set permanently by blowing individual fuses in the

appropriate register bitfield. Blowing is accomplished by apply-

ing a VPH pulse, called a blow pulse, of sufficient duration at the

VP(HIGH) level to permanently set an addressed bit by blowing a

fuse internal to the device. Due to power requirements, the fuse

for each bit in the bitfield must be blown individually. To accom-

plish this, the code representing the desired parameter value

must be translated to a binary number. For example, as shown

in figure 4, decimal code 5 is equivalent to the binary number

101. Therefore bit 2 (code 4) must be addressed and blown, the

device power supply cycled, and then bit 0 (code 1) addressed

and blown. An appropriate sequence for blowing code 5 is shown

Figure 2. Parameter selection pulse train. This shows the sequence for

selecting the register corresponding to key 1, indicated by a single VPM

pulse.

Figure 3. Bitfield addressing pulse train. Addressing the bitfield by

incrementing the code causes the programmable parameter value to

change. The number of bits available for a given programming code, n,

varies among parameters; for example, the bitfield for D(Q) has 6 bits

available, which allows 63 separate codes to be used.

V+

LOW

ACTIVE

P(HIGH)

P(MID)

P(LOW)

V+

VP(HIGH)

VP(MID)

VP(LOW)

Code 1

Code 2

– 2

Code 2

– 1

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

in figure 5. The order of blowing bits, however, is not important.

Blowing bit 0 first, and then bit 2 is acceptable.

Note: After blowing, the programming is not reversible, even

after cycling the supply power. Although a register bitfield fuse

cannot be reset after it is blown, additional bits within the same

example, if bit 1 (binary 10) has been blown, it is still possible to

blow bit 0. The end result would be binary 11 (decimal code 3).

Locking the Device

After the desired code for each parameter is programmed, the

device can be locked to prevent further programming of any

parameters.

Additional Guidelines

The additional guidelines in this section should be followed to

ensure the proper behavior of these devices:

• A 0.1 F blowing capacitor, CBLOW, must be mounted between

the VCC pin and the GND pin during programming, to ensure

enough current is available to blow fuses.

• The CBLOW blowing capacitor must be replaced in the final ap-

plication with a 10 nF bypass capacitor for proper operation.

• The application capacitance, CBYPASS, should be used when

measuring the output duty cycle during programming. The

blowing capacitor, CBLOW, should be removed during measure-

ment and should only be applied when blowing fuses.

• The power supply used for programming must be capable of

delivering at least 26 V and 300 mA.

• Be careful to observe the tLOW delay time before powering

down the device after blowing each bit.

• The following programming sequence is recommended:

1. Coarse fPWM

2. Fine fPWM

3. Coarse D(Q)

4. Sens

5. Fine D(Q)

6. LOCK (only after all other parameters have been pro-

grammed and validated, because this prevents any further

programming of the device)

Figure 4. Example of code 5 broken into its binary components, which are

code 4 and code 1.

Figure 5. Example of Blow mode programming pulses applied to the VCC pin. In this example, Fine D(Q) (Parameter

Key 2) is addressed to code 4 (corresponding to bit 2) and its value is permanently blown.

(Decimal Equivalent)

Code 5

Bit Field Selection

Address Code Format

Code in Binary

Fuse Blowing

Target Bits

Fuse Blowing

Address Code Format

(Binary)

1 0 1

Bit 2 Bit 0

Code 4 Code 1

(Decimal Equivalents)

V+

Mode

Selection

Parameter

Selection

(Key 1)

P(HIGH)

P(MID)

P(LOW)

(Key 2) (Code 4)

Addressing

Bitfield 2

BLOW

Code 4

Blow

Low

Cycle VCC

supply

Cycle VCC

supply

1121234

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Programming Modes

Try Mode This mode allows multiple programmable parameters

to be tested simultaneously without permanently setting any

values. In this mode, each VPH pulse will indefinitely loop the

programming logic through the Mode Select, Register Select, and

Bitfield Select states, as long as there are no interruptions in the

VCC supply.

To enter Try mode, after powering the VCC supply and entering

the Initial state, send one VPH pulse to enter Mode Select state,

and then two VPM pulses (Mode Selection key 2).

Select the required parameter register and address its bitfield.

When addressing the bitfield, each VPM pulse increments the

value of the parameter register, up to the maximum possible

code (see the Programming Logic table). The addressed param-

eter value is stored in the device, even after the programming

drive voltage is removed from the VCC pin, allowing its value

to be measured. To test an additional programmable parameter

in conjunction with the original, enter an additional VPH pulse

on the VCC pin to re-enter the parameter selection field. Select

a different parameter register, and address its bitfield without

any supply interruptions. Both parameter values are stored and

can be measured after removing the programming drive voltage.

Multiple programming combinations can be tested to achieve

optimal application accuracy. See figure 6 for an example of the

Try mode pulse train.

When testing the device in Try mode, it is recommended to select

parameter register 4, the null register, before tests. This recom-

mendation is because the programming voltage levels overlap the

VCC operating levels, so varying VCC during tests in Try mode may

unintentionally result in device programming.

Registers can be addressed and re-addressed an indefinite

number of times, and in any order. After the required code is

found for each register, cycle the supply voltage and blow the

bitfield fuse using Blow mode. Note that for accurate time mea-

surements, the blow capacitor, CBLOW

, should be removed during

output voltage measurement.

Blow Mode After the required value of the programmable

parameter is found using Try mode, the corresponding code

should be blown to make the value permanent. To do this, select

the required parameter register, and address and blow each

required bit separately (as described in the Fuse Blowing sec-

tion). The supply must be cycled between blowing each bit of a

given code. After a bit is blown, cycling the supply will not reset

its value.

Single parameters can still be addressed in Blow mode before

fuse blowing (simultaneous addressing of multiple parameters,

as in Try mode, is not possible). After powering the VCC supply,

select the required parameter register and address its bitfield.

When addressing the bitfield, each VPM pulse increments the

value of the parameter register, up to the maximum possible code

(see Programming Logic table). The addressed parameter value

is stored in the device, even after the programming drive voltage

is removed from the VCC pin, allowing its value to be measured.

Note that for accurate time measurements, the blow capacitor,

CBLOW, should be removed during output voltage measurement.

It is not possible to decrement the value of the register without

resetting the parameter bitfield. To reset the bit field, and thus the

value of the programmable parameter, cycle the supply voltage.

It is possible to switch between Try and Blow modes where

single programmable parameters can be blown in Blow mode

while other parameters can still be tested in Try mode.

Lock Mode To lock the device, address the LOCK bit, and

apply a blow pulse with CBLOW in place. After locking the

device, no future programming of any parameter is possible.

Figure 6. Example of Try mode programming pulses applied to the VCC pin. In this example, Sensitivity (Parameter Key 1) is

addressed to code 3, and D(Q) (Parameter Key 2) is addressed to code 2. The values set in the Sensitivity and D(Q) registers

are stored in the device until the supply is cycled. Permanent fuse blowing cannot be accomplished in Try mode.

V+

Mode Selection:

Try Mode

Parameter

Selection:

Sens/Coarse D

(Q)

(Key 2)

P(HIGH)

P(MID)

P(LOW)

(Key 1) (Code 3)

Addressing

Bitfields 0 and 1

Parameter

Selection:

Fine D

(Q)

(Key 2) (Code 2)

Addressing

Bitfield 1

1212121123

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Programming State Machine

Power-up

Initial

Bitfield Select

Sens/

Coarse

D(Q)

Fine

D(Q)

[Parameter Register Key sequence]

[Bitfield Code sequence]

[Optional: test output]

VPMVPM VPM VPM

VPMVPM

VPM

VPM VPM VPM

(Bitfield 0) 2

(Bitfield 1) 3

(Bitfields 0

and 1)

Null

fPWM /

Coarse

fPWM

Calibration

Test Mode

/LOCK

Mode Select

Blow

/Lock

Try

[Mode Register Key sequence]

[Try Mode]

2n – 1

n= bits in

Fuse

Blowing

User Power-down

Required

VPM

VPM VPM

2 s VPH

Blow or Lock

Mode?

Yes

VPH

VPM = VP(LOW) → VP(MID) → VP(LOW)

VPH

= VP(LOW) → VP(HIGH) → VP(LOW)

Initial State A known state to which the programming logic is

reset after system power-up. All the bitfield locations that have

intact fuses are reset to logic 0. VPM pulses have no effect. To enter

the Mode Select state, apply a single VPH pulse to the VCC pin.

Mode Select State This state allows the selection of the Mode

applying VPM pulses to the VCC pin. Register keys select among

the following programing modes:

• 1 pulse – Blow and Lock

• 2 pulses – Try

To enter the Parameter Select state, apply 2 VPH pulses to the

VCC pin.

Parameter Select State This state allows the selection of the

Parameter register containing the bitfields to be programmed.

Applying VPM pulses to the VCC pin increments through the

Parameter registers:

• 1 pulse – Sensitivity / Coarse D(Q)

• 2 pulses – Fine D(Q)

• 3 pulses – PWM Frequency / Coarse PWM Frequency

• 4 pulses – Null

• 5 pulses – Calibration Test Mode / Device LOCK

To enter the Bitfield Select state, apply 1 VPH pulse to the VCC pin.

Bitfield Select State This state allows the selection of the indi-

vidual bitfields to be programmed in the selected Parameter regis-

ter (see the Programming Logic table). Applying VPM pulses to

the VCC pin increments the bitfield.

In Try mode, to re-enter the Parameter Selection state, apply 1

VPH pulse on the VCC pin. The previously addressed parameter

retains its value as long as VCC is not cycled.

In Blow or Lock mode, to leave the Bitfield Select state requires

either cycling VCC or blowing the fuses for the selected code.

Note: Merely addressing the bitfield does not permanently set

the value of the selected programming parameter; fuses must be

blown to do so.

Fuse Blowing State To blow an addressed bitfield, apply a

VPH pulse to the VCC pin. Power to the device should then be

cycled before additional programming is attempted. Note: Each

bit representing a decimal code must be blown individually (see

the Fuse Blowing section).

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Programming Logic

Bitfield Address

Description

Binary Format

(MSB → LSB)

Decimal Equivalent

Code

Mode Register Selection

Blow / Lock

1 01 1 Blow or Lock

Try

2102Try

Parameter Register Selection

Sensitivity / Coarse D(Q)

000000000 0 Initial value; D(Q) = D(Q)PRE

, Sens = SensPRE

011111111 255 Maximum gain value in range

100000000 256

Enable Coarse D(Q) bit; switch from bidirectional

programming to unidirectional programming,

D(Q) = D(Q)UNIinit

Fine D(Q) (B = 0 gauss)

000000000 0 Initial value

011111111 255 Maximum D(Q) in range

100000000 256 Switch from programming increasing D(Q) to

programming decreasing D(Q)

111111111 511 Minimum D(Q) in range

PWM Frequency /Coarse PWM Frequency

00000 0 Initial value; fPWM = fPWMPRE

01111 15 Minimum fPWM in fPWM(fast) range

10000 16

Enable Coarse fPWM bit; switch from fPWM(fast)

programming to fPWM(slow) programming,

fPWM = fPWM(slow)init

11111 63 Minimum fPWM in fPWM(slow) range

Null

4––

Recommended to be selected before and during test

measurements performed in Try mode

Calibration Test Mode / Lock All

0000000000 0 Initial value

0000010000 16 Enable 50% duty cycle Calibration Test Mode bit

1000000000 512 LOCK bit; lock all device registers

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

This example demonstrates the programming of the device. The

recommended sequence for programming is shown in the Addi-

tional Guidelines section, but for this example, we start at setting

the register for Fine Duty Cycle and then go on to final locking of

the device.

To find the correct duty cycle value:

1. Power-on the system.

This resets all unprogrammed bits in all registers to 0. The

device enters the Initial state.

2. Send one VPH pulse to enter the Mode Select state.

3. Send two VPM pulses to select the Try mode.

4. Send two VPH pulses to enter the Register Select state.

5. Send two VPM pulses to select the Fine D(Q) register.

6. Send one VPH pulse to enter the Bitfield Select state.

The Fine D(Q) register is reset to 000000000.

7. For this example, send one hundred and twenty-eight VPM

pulses to set bitfield 7 (010000000, decimal 128).

Now we can measure the device output to see if this is the

required value. Assume for this example that the value is slightly

too low. So we proceed to change it, as follows:

8. Send one VPM pulse to increment the Fine D(Q) code by 1.

This yields a total register value of 129 by setting bitfield 0:

010000001.

Assume we measure the device and find this is the correct duty

cycle value we require. We are finished trying values for this

parameter, and now want to set the value permanently by blowing

the corresponding bitfield fuses. Blowing fuses is done one bit-

field (one fuse) at a time. We are setting two bitfields, so we have

to blow them in two stages:

9. Reset the device by powering it off and on.

The device returns to the Initial state.

10. Send one VPH pulse to enter the Mode Select state.

11. Send one VPM pulse to select the Blow mode.

12. Send two VPH pulses to enter the Register Select state.

13. Send two VPM pulses to select the Fine D(Q) register.

14. Send one VPH pulse to enter the Bitfield Select state.

The Fine D(Q) register is reset to 000000000.

15. Send one hundred and twenty-eight VPM pulses to set bit-

field 7. (The bitfields can be set in any order.)

16. Send one VPH pulse to exit the Bitfield Select state.

The bitfield fuse is blown.

One of the two bitfields is programmed. Now we program the

other bitfield:

17. Repeat steps 9 to 14 to select the Fine D(Q) register again and

enter the Bitfield Select state. This time, however, the register

resets to 010000000, because bit 7 has been permanently set.

18. Send one VPM pulse to set bit 0.

19. Send one VPH pulse to exit the Bitfield Select state.

The bitfield fuse is blown.

Program the remaining parameter by repeating the above steps.

After programming all parameters, we can lock the device:

20. Reset the device by powering it off and on. The device returns

to the Initial state.

21. Send one VPH pulse to enter the Mode Select state.

22. Send one VPM pulse to select the Lock mode.

23. Send two VPH pulses to enter the Register Select state.

24. Send five VPM pulses to select the LOCK register. The regis-

ter resets either to 0000000000, or to 0000010000 if Calibra-

tion Test mode has been previously enabled.

25. Send one VPH pulse to enter the Bitfield Select state.

26. Send five hundred and twelve VPM pulses to set the LOCK

bit, bitfield 9.

27. Send one VPH pulse to exit the Bitfield Select state. The bit-

field fuse is blown. Programming of the device is complete.

Optionally, test the results, or power-off the device.

Programming Example

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The Calibration Test mode is provided so that the user can com-

pensate for differences in the ground potential between the A1354

and any interface circuitry used to measure the pulse width of the

A1354 output. This test mode is optional and must be enabled

by blowing its programming bit. After the test mode bit has been

blown, the device enters Calibration Test mode every time the

device is powered-up.

In customer applications the PWM interface circuitry (body con-

trol module: BCM in figure 7) and the A1354 may be powered

via different power and ground circuits. As a result, the ground

reference for the A1354 may differ from the ground reference of

the BCM. In some customer applications this ground difference

can be as large as ± 0.5 V.

Differences in the ground reference for the A1354 and the BCM

can result in variations in the threshold voltage used to measure

the duty cycle of the A1354. If the PWM conversion threshold

voltage varies, then the duty cycle will vary because there is a

finite rise time, tr , and fall time, tf , in the PWM waveform. This

problem is shown in figure 8.

The Calibration Test mode allows end users to compensate

for any threshold errors that result from a difference in system

ground potentials. While the A1354 is in the test period, the

Calibration Test Mode

VOH

VOL

Figure 8. When the threshold voltage is correctly centered between VOH and VOL, the duty cycle accurately coincides with the

applied magnetic field. If the threshold voltage is raised, the output duty cycle appears shorter than expected. Conversely, if

the threshold voltage is lowered, the output duty cycle is longer than expected.

GND

GND1

A1354

BCM

VCC

CBYPASS

GND2

10 nF 10 nF

4.7 kΩ

Figure 7: In many applications the A1354 may be powered using a different ground

reference than the BCM. This may cause the ground reference for the A1354 (GND 1) to

differ from the ground reference of the BCM (GND 2) by as much as to ±0.5 V.

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

device output waveform is a fixed 50% duty cycle (the pro-

grammed quiescent duty cycle value) regardless of the applied

external magnetic field. After powering-up, the A1354 outputs

its quiescent duty cycle waveform for 800 ms, regardless of the

applied magnetic field (see figure 9). This allows the BCM to

compare the measured quiescent duty cycle with an ideal 50%

duty cycle.

After the initial 800 ms has elapsed, the duty cycle corresponds to

an applied magnetic field as expected. The 800 ms calibration test

time corresponds to a PWM frequency of 125 Hz. If the PWM

frequency is programmed away from its target of 125 Hz, the

duration of the calibration test time will scale inversely with the

change in PWM frequency.

Figure 9. Calibration Test Mode. After powering-on, the A1354 outputs a 50% duty cycle for

the first 800 ms, regardless of the applied magnetic field (Calibration Test mode in effect).

After the initial 800 ms has elapsed, the output responds to a magnetic field as expected.

The example in this figure assumes that a large +B (south polarity) field is applied to the

device after the initial 800 ms.

During Calibration Teat mode

PMW output = 50% duty cycle

After the calibration expires, PWM output

proportional to external magnetic field

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

High Precision 2-Wire Linear Hall Ef fect Sensor IC

with Pulse Width Modulated Output

A1354

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

Package KT, 4-Pin SIP

The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;

5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

DThermoplastic Molded Lead Bar for alignment during shipment

Active Area Depth 0.37 mm REF

Hall element, not to scale

0.54

REF

0.54

REF

12.14±0.05

1.27 NOM

0.89

MAX

0.89

MAX

10°

2.60

1.35

2431

5.21 +0.08

–0.05

5.21 +0.08

–0.05

3.43 +0.08

–0.05

0.41 +0.08

–0.05

1.50 +0.08

–0.05

0.20 +0.08

–0.05

1.00 +0.08

–0.05

1.00 +0.08

–0.05

Mold Ejector

Pin Indent

Branded

Face

For Reference Only; not for tooling use (reference DWG-9202)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Gate and tie bar burr area

Dambar removal protrusion (16X)

Standard Branding Reference View

N = Device part number

Y = Last two digits of year of manufacture

W = Week of manufacture

YYWW

NNNN

Branding scale and appearance at supplier discretion