AD7521LN - National Semiconductor

TL/H/5689

DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter

DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter

May 1996

DAC1020/DAC1021/DAC1022

10-Bit Binary Multiplying D/A Converter

DAC1220/DAC1222

12-Bit Binary Multiplying D/A Converter

General Description

The DAC1020 and the DAC1220 are, respectively, 10 and

12-bit binary multiplying digital-to-analog converters. A de-

posited thin film R-2R resistor ladder divides the reference

current and provides the circuit with excellent temperature

tracking characteristics (0.0002%/§C linearity error temper-

ature coefficient maximum). The circuit uses CMOS current

switches and drive circuitry to achieve low power consump-

tion (30 mW max) and low output leakages (200 nA max).

The digital inputs are compatible with DTL/TTL logic levels

as well as full CMOS logic level swings. This part, combined

with an external amplifier and voltage reference, can be

used as a standard D/A converter; however, it is also very

attractive for multiplying applications (such as digitally con-

trolled gain blocks) since its linearity error is essentially in-

dependent of the voltage reference. All inputs are protected

from damage due to static discharge by diode clamps to Va

and ground.

This part is available with 10-bit (0.05%), 9-bit (0.10%), and

8-bit (0.20%) non-linearity guaranteed over temperature

(note 1 of electrical characteristics). The DAC1020,

DAC1021 and DAC1022 are direct replacements for the 10-

bit resolution AD7520 and AD7530 and equivalent to the

AD7533 family. The DAC1220 and DAC1222 are direct re-

placements for the 12-bit resolution AD7521 and AD7531

family.

Features

YLinearity specified with zero and full-scale adjust only

YNon-linearity guaranteed over temperature

YIntegrated thin film on CMOS structure

Y10-bit or 12-bit resolution

YLow power dissipation 10 mW @15V typ

YAccepts variable or fixed reference b25VsVREFs25V

Y4-quadrant multiplying capability

YInterfaces directly with DTL, TTL and CMOS

YFast settling timeÐ500 ns typ

YLow feedthrough errorÐ(/2 LSB @100 kHz typ

Equivalent Circuit Note. Switches shown in digital high state

TL/H/5689–1

10-BIT D/A CONVERTERS

Ordering Information

Temperature Range 0§Cto70

40§Cto85

Non- 0.05% DAC1020LCN AD7520LN,AD7530LN DAC1020LCV DAC1020LIV

Linearity 0.10% DAC1021LCN AD7520KN,AD7530KN

0.20% DAC1022LCN AD7520JN,AD7530JN

Package Outline N16A V20A

12-BIT D/A CONVERTERS

Temperature Range 0§Cto70

40§Ctoa

85§C

Linearity

Non- 0.05% DAC1220LCN AD7521LN,AD7531LN DAC1220LCJ AD7521LD,AD7531LD

0.20% DAC1222LCN AD7521JN,AD7531JN DAC1222LCJ AD7521JD,AD7531JD

Package Outline N18A J18A

Note. Devices may be ordered by either part number.

C1996 National Semiconductor Corporation RRD-B30M96/Printed in U. S. A. http://www.national.com

Absolute Maximum Ratings (Note 5)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Vato Gnd 17V

VREF to Gnd g25V

Digital Input Voltage Range Vato Gnd

DC Voltage at Pin 1 or Pin 2 (Note 3) b100 mV to Va

Storage Temperature Range b65§Ctoa

150§C

Lead Temperature (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260§C

Dual-In-Line Package (ceramic) 300§C

ESD Susceptibility (Note 4) 800V

Operating Ratings

Min Max Units

Temperature (TA)

DAC1020LIV, DAC1220LCJ,

DAC1222LCJ b40 a85 §C

DAC1020LCN, DAC1020LCV,

DAC1021LCN 0 a70 §C

DAC1022LCN, DAC1220LCN 0 a70 §C

DAC1222LCN 0 a70 §C

Electrical Characteristics (Vae15V, VREF e10.000V, TAe25§C unless otherwise specified)

DAC1020, DAC1021, DAC1220, DAC1222

Parameter Conditions DAC1022 Units

Min Typ Max Min Typ Max

Resolution 10 12 Bits

Linearity Error TMINkTAkTMAX,

b10VkVREFka10V,

(Note 1) End Point Adjustment Only

(See Linearity Error in Definition of Terms)

10-Bit Parts DAC1020, DAC1220 0.05 0.05 % FSR

9-Bit Parts DAC1021 0.10 0.10 % FSR

8-Bit Parts DAC1022, DAC1222 0.20 0.20 % FSR

Linearity Error Tempco b10VsVREFsa10V, 0.0002 0.0002 % FS/§C

(Notes 1 and 2)

Full-Scale Error b10VsVREFsa10V, 0.3 1.0 0.3 1.0 % FS

(Notes 1 and 2)

Full-Scale Error Tempco TMINkTAkTMAX, 0.001 0.001 % FS/§C

(Note 2)

Output Leakage Current TMINsTAsTMAX

IOUT 1 All Digital Inputs Low 200 200 nA

IOUT 2 All Digital Inputs High 200 200 nA

Power Supply Sensitivity All Digital Inputs High, 0.005 0.005 % FS/V

14VsVas16V, (Note 2),

(Figure 2)

VREF Input Resistance 10 15 20 10 15 20 kX

Full-Scale Current Settling RLe100Xfrom 0 to 99. 95%

Time FS

All Digital Inputs Switched 500 500 ns

Simultaneously

VREF Feedthrough All Digital Inputs Low, 10 10 mVp-p

VREFe20 Vp-p @100 kHz

J Package (Note 4) 6 9 6 9 mVp-p

N Package 2 5 2 5 mVp-p

Output Capacitance

IOUT 1 All Digital Inputs Low 40 40 pF

All Digital Inputs High 200 200 pF

IOUT 2 All Digital Inputs Low 200 200 pF

All Digital Inputs High 40 40 pF

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Electrical Characteristics (Vae15V, VREF e10.000V, TAe25§C unless otherwise specified) (Continued)

DAC1020, DAC1021, DAC1220, DAC1222

Parameter Conditions DAC1022 Units

Min Typ Max Min Typ Max

Digital Input

(Figure 1)

Low Threshold TMINkTAkTMAX 0.8 0.8 V

High Threshold TMINkTAkTMAX 2.4 2.4 V

Digital Input Current TMINsTAsTMAX

Digital Input High 1 100 1 100 mA

Digital Input Low b50 b200 b50 b200 mA

Supply Current All Digital Inputs High 0.2 1.6 0.2 1.6 mA

All Digital Inputs Low 0.6 2 0.6 2 mA

Operating Power Supply

(Figures 1 and 2)

5 15 5 15 V

Range

Note 1: VREFeg10V and VREFeg1V. A linearity error temperature coefficient of 0.0002% FS for a 45§C rise only guarantees 0.009% maximum change in

linearity error. For instance, if the linearity error at 25§C is 0.045% FS it could increase to 0.054% at 70§C and the DAC will be no longer a 10-bit part. Note,

however, that the linearity error is specified over the device full temperature range which is a more stringent specification since

it includes

the linearity error

temperature coefficient.

Note 2: Using internal feedback resistor as shown in

Figure 3

Note 3: Both IOUT 1 and IOUT 2 must go to ground or the virtual ground of an operational amplifier. If VREFe10V, every millivolt offset between IOUT 1 or IOUT 2,

0.005% linearity error will be introduced.

Note 4: Human body model, 100 pF discharged through a 1.5 kXresistor.

Note 5: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 6: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,iJA, and the ambient temepature, TA. The maximum

allowable power dissipation at any temperature is PDe(TJMAX bTA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this

device, TJMAX e125§C, and the typical junction-to-ambient thermal resistance of the J18 package when board mounted is 85§C/W. For the N18 package, iJA is

120§C/W, for the N16 this number is 125§C/W, and for the V20 this number is 95§C/W.

Typical Performance Characteristics

TL/H/5689–2

FIGURE 1. Digital Input Threshold vs

Ambient Temperature

FIGURE 2. Gain Error Variation vs Va

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Typical Applications

The following applications are also valid for 12-bit systems

using the DAC1220 and 2 additional digital inputs.

Operational Amplifier Bias Current (

Figure 3

)

The op amp bias current, Ib, flows through the 15k internal

feedback resistor. BI-FET op amps have low Iband, there-

fore, the 15k cIberror they introduce is negligible; they are

strongly recommended for the DAC1020 applications.

VOS Considerations

The output impedance, ROUT, of the DAC is modulated by

the digital input code which causes a modulation of the op-

erational amplifier output offset. It is therefore recommend-

ed to adjust the op amp VOS.R

OUT is E15k if more than 4

digital inputs are high; ROUT is E45k if a single digital input

is high, and ROUT approaches infinity if all inputs are low.

Operational Amplifier VOS Adjust (

Figure 3

)

Connect all digital inputs, A1–A10, to ground and adjust the

potentiometer to bring the op amp VOUT pin to within g1

mV from ground potential. If VREF is less than 10V, a finer

VOS adjustment is required. It is helpful to increase the reso-

lution of the VOS adjust procedure by connectinga1kX

resistor between the inverting input of the op amp to

ground. After VOS has been adjusted, remove the 1 kX.

Full-Scale Adjust (

Figure 4

)

Switch high all the digital inputs, A1–A10, and measure the

op amp output voltage. Use a 500Xpotentiometer, as

shown, to bring

VOUT

to a voltage equal to VREF c

1023/1024.

SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER

Op Amp Family CFRiPV

Circuit Settling Circuit Small

Time, tsSignal BW

LF357 10 pF 2.4k 25k Va1.5 ms1M

LF356 22 pF %25k Va3ms 0.5M

LF351 24 pF %10k Vb4ms 0.5M

LM741 0 %10k Vb40 ms 200 kHz

TL/H/5689–3

VOUT eb

REF #A1

2aA2

4aA3

8a### A10

1024 J

b10V sVREF s10V

0sVOUT sb1023

1024 VREF

where ANe1 if the ANdigital input is high

ANe0 if the ANdigital input is low

FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying

Configuration (Digital Attenuator)

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Typical Applications (Continued)

FIGURE 4. Full-Scale Adjust

FIGURE 5. Alternate Full-Scale Adjust: (Allows Increasing or Decreasing the Gain)

TL/H/5689–4

VOUT 1 eb

REF #A1

2aA2

4aA3

8a### A10

1024 J

VOUT2 eVREF #A1

2aA2

4aA3

8a### A10

1024 Jc#B1

2aB2

4aB3

8a### B10

1024 J

where VREF can be an AC signal

FIGURE 6. Precision Analog-to-Digital Multiplier

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Typical Applications (Continued)

TL/H/5689–5

VOUT eb

REF #A1

2aA2

4a###aA10

1024 b1

1024 J

where: AN ea

1ifA

Ninput is high

AN eb

1ifA

Ninput is low

COMPLEMENTARY OFFSET BINARY

(BIPOLAR) OPERATION

DIGITAL INPUT VOUT

0000000000 a

REF

0000000001 V

REF c1022/1024

0111111111 V

REF c2/1024

1000000000 0

1000000001 b

REF c2/1024

1111111111b

REF (1022/1024)

Note that:

#IOUT 1 aIOUT 2 eVREF

RLADDER

c#1023

1024 J

#By doubling the output range we get half the

resolution

#The 10M resistor, adds a 1 LSB ‘‘thump’’, to

allow full offset binary operation where the out-

put reaches zero for the half-scale code. If

symmetrical output excursions are required,

omit the 10M resistor.

FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration

Operational Amplifiers VOS Adjust (

Figure 7

)

a) Switch all the digital inputs high; adjust the VOS potenti-

ometer of op amp B to bring its output to a value equal

tob(VREF/1024) (V).

b) Switch the MSB high and the remaining digital inputs

low. Adjust the VOS potentiometer of op amp A, to bring

its output value to withina1mVfrom ground potential.

For VREF k10V, a finer adjust is necessary, as already

mentioned in the previous application.

Gain Adjust (Full-Scale Adjust)

Assuming that the external 10k resistors are matched to

better than 0.1%, the gain adjust of the circuit is the same

with the one previously discussed.

TL/H/5689–6

TRUE OFFSET BINARY OPERATION

DIGITAL INPUT VOUT

1111111111V

REF c1022/1024

1000000000 0

0000000000 b

REF

tse1.8 ms

use LM336 for a voltage reference

FIGURE 8. Bipolar Configuration with a Single Op Amp

#R4 e(2AVbb1) R, R2

R1 eAVb

AVbb1,

R3 aR1

R2 eR; AVbeVOUT(PEAK)

VREF

,Re20k

#Example: VREF e2V, VOUT (swing) jg10V: AVbe5V

Then R4 e9R, R1 e0.8 R2. If R1 e0.2R then R2 e0.25R,

R3 e0.64R

FIGURE 9. Bipolar Configuration with

Increased Output Swing

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Typical Applications (Continued)

VOUT ebVREF

#A1

2aA2

4aA3

8a... A10

1024 J

where: VREF can be an AC signal

#By connecting the DAC in the feedback loop of an opera-

tional amplifier a linear digitally control gain block can be

realized

#Note that with all digital inputs low, the gain of the amplifier

is infinity, that is, the op amp will saturate. In other words, we

cannot divide the VREF by zero!

FIGURE 10. Analog-to-Digital Divider (or Digitally Gain Controlled Amplifier)

VOUT eVREF %A1

2aA2

4a...aA10

1024

2aA2

4a...aA10

1024 –or VOUT eVREF #1023 bN

where: 0 sNs1023

Ne0 for ANeall zeros

Ne1 for A10 e1, A1–A9 e0

Ne1023 for ANeall 1’s

FIGURE 11. Digitally controlled Amplifier-Attenuator

TL/H/5689–7

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Typical Applications (Continued)

TL/H/5689–8

#Output frequency efCLK

512 ;f

MAX j2 kHz

#Output voltage range e0V b10V peak

#THD k0.2%

#Excellent amplitude and frequency stability with temperature

#Low pass filter shown has a 1 kHz corner (for output frequencies below 10 Hz,

filter corner should be reduced)

#Any periodic function can be implemented by modifying the contents of the look

up table ROM

#No start up problems

FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM

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Typical Applications (Continued)

MM74C00 Ð NAND gates

MM74C32 Ð OR gates

MM74C74 Ð D flip-flop

MM74C193 Ð Binary up/

down counters

TL/H/5689–9

#Binary up/down counter digitally ‘‘ramps’’ the DAC

output

#Can stop counting at any desired 10-bit input code

#Senses up or down count overflow and automatically

reverses direction of count

FIGURE 13. A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits

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Definition of Terms

Resolution: Resolution is defined as the reciprocal of the

number of discrete steps in the D/A output. It is directly

related to the number of switches or bits within the D/A. For

example, the DAC1020 has 210 or 1024 steps while the

DAC1220 has 212 or 4096 steps. Therefore, the DAC1020

has 10-bit resolution, while the DAC1220 has 12-bit resolu-

tion.

Linearity Error: Linearity error is the maximum deviation

from

a straight line passing through the endpoints of the

D/A transfer characteristic.

It is measured after calibrating

for zero (see VOS adjust in typical applications) and full-

scale. Linearity error is a design parameter intrinsic to the

device and cannot be externally adjusted.

Power Supply Sensitivity: Power supply sensitivity is a

measure of the effect of power supply changes on the D/A

full-scale output.

Settling Time: Full-scale settling time requires a zero to full-

scale or full-scale to zero output change. Settling time is the

time required from a code transition until the D/A output

reaches within g(/2 LSB of final output value.

Full-Scale Error: Full-scale error is a measure of the output

error between an ideal D/A and the actual device output.

Ideally, for the DAC1020 full-scale is VREFb1 LSB. For

VREFe10V and unipolar operation, VFULL-SCA-

LEe10.0000VÐ9.8 mVe9.9902V. Full-scale error is ad-

justable to zero as shown in

Figure 5

TL/H/5689–10

ab1b2

(a) End point test after zero and full-scale adjust.

The DAC has 1 LSB linearity error.

(b) By shifting the full-scale calibration on of the DAC of

Figure (b1)

we could pass the ‘‘best straight line’’ (b2)

test and meet the g(/2 linearity error specification.

Note. (a), (b1) and (b2) above illustrate the difference between ‘‘end point’’ National’s linearity test (a) and ‘‘best straight line’’ test. Note that both devices in (a) and

(b2) meet the g(/2 LSB linearity error specification but the end point test is a more ‘‘real life’’ way of characterizing the DAC.

Connection Diagrams

DAC102X

Dual-In-Line Package

TL/H/5689–13

DAC1020

PLCC Package

TL/H/5689–12

DAC122X

Dual-In-Line Package

TL/H/5689–11

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Physical Dimensions inches (millimeters) unless otherwise noted

Cavity Dual-In-Line Package (J)

Order Number DAC1220LCJ or DAC1222LCJ

NS Package Number J18A

Molded Dual-In-Line Package (N)

Order Number DAC1020LCN, DAC1021LCN or DAC1022LCN

NS Package Number N16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number DAC1220LCN, DAC1221LCN or DAC1222LCN

NS Package Number N18A

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DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter

DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Plastic Leaded Chip Carrier (V)

Order Number DAC1020LCV or DAC1020LIV

NS Package Number V20A

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failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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