Description
The A3932 is a three-phase MOSFET con trol ler for use with
bipolar brushless DC motors. Its high gate-current drive
capability allows driving a wide range of N-channel power
MOSFETs and can support motor supply voltages to 50 V.
Bootstrapped high-side drive blocks provide the float ing
positive supplies for the gate drive and minimize the component
count normally required. The high-side cir cuit ry also em ploys a
unique FET monitoring circuit that ensures the gate voltages are
at the proper levels before turn-on and during the ON cycle.
Internal fixed off-time PWM current-control circuitry can be
used to regulate the maximum load current to a desired value.
The peak load-current limit is set by the user’s selection of
an input reference volt age and external sensing resistor. The
fixed off-time pulse duration is set by a user-selected external
RC timing network. For added flexibility, the PWM input can
be used to provide speed/torque control, allowing the internal
current control circuit to set the maximum current limit.
Optional synchronous rectification is included. This feature will
short out the current path through the power MOSFET reverse
body diodes during the PWM off-cycle current decay. This can
minimize power dissipation in the power MOSFET, eliminate
the need for external power clamp diodes, and potentially allow
more eco nom i cal choices for the MOSFET application.
The A3932 includes the commutation logic for Hall sensors
configured for 120 degree spacing. Power MOSFET protection
features include bootstrap capacitor charging current monitor,
undervoltage monitor, motor-lead short-to-ground, and thermal
shutdown.
The ‘–S–’ part-number suffix in di cates an operating temperature
range of -20°C to +85°C. The ‘–LD–’ suffix in di cates a 38-lead
TSSOP package. The initial ‘–TR–’ variant suffix indicates
tape and reel packing. The ‘–T’ final variant suffix indicates
lead (Pb) free composition, with 100% matte tin leadframe
plating.
26301.101H
Features and Benefits
▪ Drives wide range of N-channel MOSFETs
▪ Synchronous rectification
▪ Power MOSFET protection
▪ Adjustable dead time for cross-conduction pro tec tion
▪ 100% duty cycle operation
▪ Selectable fast or slow current-decay modes
▪ Internal PWM peak current control
▪ High-current gate drive
▪ Motor lead short-to-ground protection
▪ Internal 5 V regulator
▪ Brake input
▪ PWM torque-control input
▪ Fault-diagnostic output
▪ Tachometer output
▪ Thermal shutdown
▪ Undervoltage protection
Three-Phase Power MOSFET Controller
Packages
Not to scale
A3932
38-pin TSSOP (suffi x LD)
Three-Phase Power MOSFET Controller
A3932
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Packing
A3932SLDTR-T 4000 pieces per reel
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Supply Voltage VBB 50 V
Peak Regulator Voltage VREG 15 V
Logic Input Voltage Range VIN –0.3 to VLCAP + 0.3 V
Sense Voltage Range VSENSE –5 to 1.5 V
Output Voltage Range V
SA, SB, SC Pins –5 to 50 V
GHA, GHB, GHC Pins –5 to VBB + 17 V
CA, CB, CC Pins VSx + 17 V
Operating Ambient Temperature TARange S –20 to 85 ºC
Junction Temperature TJ150 ºC
Storage Temperature Tstg –55 to 150 ºC
Three-Phase Power MOSFET Controller
A3932
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
38-pin TSSOP (suffi x LD)
CA
FAULT
LCAP
VREG
GLC
SC
NC
NC
NC
GHC
RESET
CC
GLB
SB
GHB
CB
GLA
SA
GHA
H3
MODE
H1
NC
NC
PGND
AGND
DEAD
VBB
REF
NC
SENSE
RC
PWM
TACH
SR
BRAKE
DIR
H2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
FAULT
CONTROL
LOGIC
Pin-Out Diagram
Three-Phase Power MOSFET Controller
A3932
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
NOTE — For 12 V applications, VBB is shorted to VREG.
The VREG absolute maximum rating (15 V) must not be
ex ceed ed.
Three-Phase Power MOSFET Controller
A3932
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Parameter Symbol Conditions
Limits
Min Typ Max Units
Supply Current
Quiescent Current IBB RESET high, coast mode, stopped – – 8.0 mA
Reference Voltage VLCAP ILCAP = -3 mA 4.75 5.0 5.25 V
Output Voltage VREG VBB = VREG ≤15 V, IREG = -10 mA 10.8 – 13.2 V
18 V ≤ VBB ≤ 50 V, IREG = -10 mA 12.4 13 13.6 V
VBB = 13.2 V to 18 V, IREG = -10 mA – VBB - 2.5 – V
Output Voltage Regulation VREG(IREG) IREG = -1 to -30 mA, coast – 25 – mV
VREG(VBB) IREG = -10 mA, coast – 40 – mV
Digital Logic Levels
Logic Input Voltage
VIH All inputs except SR 2.0 – – V
SR input only 3.0 – – V
VIL All inputs except SR – – 0.8 V
SR input only – – 1.8 V
Logic Input Current IIH VIH = 2 V -30 – -90 μA
IIL VIL = 0.8 V -50 – -130 μA
Gate Drive
Low-Side Output Voltage VGLxH IGLx = 0 VREG - 0.8 VREG - 0.5 – V
High-Side Output Voltage VGHxH IGHx = 0 10.4 11.6 12.8 V
Pulldown Switch Resistance rDS(on) IGLx = 50 mA – 4.0 –
Pullup Switch Resistance rDS(on) IGHx = -50 mA – 14 –
Low-Side Output
Switching Time
trGLx 10% to 90%, with Cload – 120 – ns
tfGLx 90% to 10%, with Cload –60–ns
High-Side Output
Switching Time
trGHx 10% to 90%, with Cload – 120 – ns
tfGHx 90% to 10%, with Cload –60–ns
Propagation Delay Time
(PWM to gate output)
tpr GHx, GLx rising, Cload = 0 – 220 – ns
tpf GHx, GLx falling, Cload = 0 – 110 – ns
Maximum Dead Time tdead GHx to GLx, VDEAD = 0 V, Cload = 0 3.5 5.6 7.6 μs
Minimum Dead Time tdead GLx to GHx, IDEAD = 780 μA, Cload = 0 50 100 150 ns
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = 25°C; VBB = 18 V to 50 V; CLCAP
,
Cboot = 0.1 μF; CREG = 10 μF; Cload = 3300 pF; fPWM = 22.5 kHz Square Wave; Two Phases Active.
NOTES: 1. Typical Data is for design information only.
2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.
Continued —
Three-Phase Power MOSFET Controller
A3932
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = 25°C; VBB = 18 V to 50 V; CLCAP
,
Cboot = 0.1 μF; CREG = 10 μF; Cload = 3300 pF; fPWM = 22.5 kHz Square Wave; Two Phases Active.
Parameter Symbol Con di tions Limits
Min Typ Max Units
Bootstrap Capacitor
Bootstrap Charge Current ICx 100 – – mA
Bootstrap Output Voltage VCx VSx = 0, ICx = 0, VREG = 13 V 10.4 11.6 12.8 V
Bootstrap Resistance rCx ICx = -50 mA – 9.0 12 Ω
Current Limit Circuitry
Input Offset Voltage Vio 0 V ≤ VIC ≤ 1.5 V – – ±5.0 mV
SENSE Input Current ISENSE VIC ≥ 0 V, VID ≤ 1.5 V – -25 – μA
REFERENCE Input Current IREF VIC ≥ 0 V, VID ≤ 1.5 V –0–μA
Blank Time tblank RT = 56 kΩ, CT = 470 pF – 0.91 – μs
RC Charge Current IRC -0.9 -1.0 -1.1 mA
RC Voltage Threshold VRCL 1.0 1.1 1.2 V
VRCH 2.7 3.0 3.3 V
Protection Circuitry
Bootstrap Charge Threshold ICx – -9.0 – mA
Motor Short-to-Ground Monitor
VDSH VBB - VSX, high side on 1.3 2.0 2.7 V
Undervoltage Threshold UVLO Increasing VREG 9.2 9.7 10.2 V
Decreasing VREG 8.6 9.1 9.6 V
FAULT Output Voltage VFAULT IO = 1 mA – – 0.5 V
TACH Output Voltage VTACH IO = 1 mA – – 0.5 V
TACH Output Pulse Width tTACH IO = 1 mA, CTACH = 50 pF – 0.75 – μs
Thermal Shutdown Temp. TJ– 165 – °C
Thermal Shutdown Hyster-
esis ∆TJ–10–°C
Thermal Resistance RθJA
Package EQ Four-layer PCB
– 37 – °C/W
Package LD Four-layer PCB
– 51 – °C/W
NOTES:
1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
Three-Phase Power MOSFET Controller
A3932
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
RESET — A logic input used to enable the device, internally
pulled up to VLCAP (+5 V). A RESET = 1 will disable the de vice
and force all gate drivers to 0 V, coasting the motor. A RESET
= 0 allows the gate drive to follow the commutation logic. The
RESET = 1 overrides BRAKE.
GLA/GLB/GLC — Low-side, gate-drive outputs for ex ter nal
NMOS drivers. External series-gate resistors (as close as pos-
sible to the NMOS gate) can be used to con trol the slew rate
seen at the power-driver gate, thereby controlling the di/dt and
dv/dt of the SA/SB/SC outputs. GLx = 1 (or “high”) means that
the upper half (PMOS) of the driver is turned on and its drain
will source current to the gate of the low-side FET in the exter-
nal motor-driving bridge. GLx = 0 (or “low”) means that the
lower half (NMOS) of the driver is turned on and its drain will
sink current from the external FET’s gate circuit.
SA/SB/SC — Directly connected to the motor, these terminals
sense the volt ag es switched across the load. These ter mi nals are
also connected to the neg a tive side of the bootstrap ca pac i tors
and are the negative supply connections for the fl oating high-
side drivers.
GHA/GHB/GHC — High-side, gate-drive outputs for external
NMOS drivers. External se ries-gate resistors can be used to
control the slew rate seen at the power-driver gate, thereby con-
trolling the di/dt and dv/dt of the SA/SB/SC outputs.
GHx = 1 (or “high”) means that the upper half (PMOS) of the
driver is turned on and its drain will source current to the gate of
the high-side FET in the external motor-driving bridge. GHx =
0 (or “low”) means that the lower half (NMOS) of the driver is
turned on and its drain will sink current from the external FET’s
gate circuit.
CA/CB/CC — High-side connections for the bootstrap ca pac i-
tors, positive supply for high-side gate drivers. The boot strap
capacitors are charged to approximately VREG when the as so -
ci at ed output Sx terminal is low. When the output swings high,
the voltage on this ter mi nal rises with the output to provide the
boosted gate voltage needed for N-channel power MOSFETs.
Terminal Descriptions
continued next page
LD Name
1 RESET
2 GLC
3SC
4,5,18,
23,37,38
NC
6 GHC
7CC
8 GLB
9SB
10 GHB
11 CB
12 GLA
13 SA
14 GHA
15 CA
16 VREG
17 LCAP
19 FAULT
20 MODE
21 VBB
22 H1
24 H3
25 H2
26 DIR
27 BRAKE
28 SR
29 TACH
30 PWM
31 RC
32 SENSE
33 REF
34 DEAD
35 AGND
36 PGND
Three-Phase Power MOSFET Controller
A3932
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FAULT — Open-drain output to indicate fault condition; FAULT
= 1 (external pull-up) for any of the following:
1 – invalid HALL input code,
2 – undervoltage condition detected at VREG.
3 – thermal shutdown, or
4 – motor lead (SA/SB/SC) shorted to ground.
Except for a short-to-ground fault that only turns off the
high-side drivers, faults will force a coast condition that turns off
all power MOSFETs. Only the short-to-ground fault is latched
but is cleared at each com mu ta tion. If the motor has stalled
due to a short-to-ground being detected, toggling the RESET
ter mi nal or repeating a power-up sequence will clear the fault.
Typically pulled up to VLCAP (+5 V) with an external 5.1 kΩ
resistor.
MODE — A logic input to set current-decay method, internally
pulled up to VLCAP (+5 V). When in slow-decay mode (MODE
= 1), only the high-side MOSFET is switched off during a
PWM-off cycle. The fast-decay mode (MODE = 0) switches
both the high-side and low-side MOSFETs.
H1/H2/H3 — Hall-sensor inputs; internally pulled up to VLCAP
(+5 V). Con fi g ured for 120° electrical spacing.
DIR — A logic input to reverse rotation, see Commutation Truth
Table. Internally pulled up to VLCAP (+5 V).
BRAKE — An active-low logic input for a braking function.
A BRAKE = 0 will turn on the low-side FETs and turn off the
high-side FETs. This will effectively short-circuit the BEMF in
the wind ings and brake the motor. The braking torque applied
will depend on the speed. Internally pulled up to VLCAP (+5 V).
RESET = 1 overrides BRAKE and will coast the motor.
SR — Synchronous rectifi cation input. An SR = 0 disables this
feature, forcing current decay through the body diodes of the
power MOSFETs. An SR = 1 will result in ap pro pri ate high-
and low-side gate outputs to switch in re sponse to a PWM-off
com mand. Internally pulled up to VLCAP (+5 V). See also the
Input Logic table.
TACH — An open-drain digital output whose frequency is pro-
portional to speed of rotation. A pulse appears at every HALL
transition. Typ i cal ly pulled up to VLCAP (+5 V) with an external
5.1 kΩ resistor.
PWM — Speed control input, internally pulled up to VLCAP
(+5 V). A PWM = 0 turns off selected drivers. A PWM = 1 will
turn on selected drivers as determined by H1/H2/H3 input logic.
Hold ing PWM = 1 allows speed/torque control solely by the
internal current-limit circuit with the REF analog voltage. See
also the Input Logic table .
RC — An analog input used to set the fi xed off time with an
external resistor (RT) and capacitor (CT). The tblank time is con-
trolled by the value of the external ca pac i tor (see Ap pli ca tions
Information). See Application Information.
SENSE — An analog input to the current-lim it com par a tor.
A voltage rep re sent ing load current appears on this ter mi nal dur-
ing on time, when it reaches REF voltage, the comparator trips
and load current decays for the fi xed off-time interval. Volt-
age transients seen at this ter mi nal when the drivers turn on are
ignored for time tblank.
REF — An analog input to the current-lim it com par a tor. Volt-
age applied here with respect to AGND sets the peak load cur-
rent.
Ipeak = VREF/RS.
VREG — A regulated 13 V output; supply for low-side gate
drive and boot strap capacitor charge circuits. It is good practice
to connect a decoupling capacitor from this ter mi nal to AGND,
as close to the de vice ter mi nals as pos si ble. This terminal should
be shorted to VBB for 12 V applications.
VBB — The A3932 supply voltage. It is good practice to con-
nect a decoupling capacitor from this ter mi nal to AGND, as
close to the de vice ter mi nals as pos si ble.
LCAP — Con nec tion for 0.1 μF decoupling capacitor for the
internal 5 V reference. This terminal can source no more than
3 mA for the DEAD input, TACH and FAULT outputs.
DEAD — An analog input. A resistor between DEAD and
LCAP is selected to adjust the turn-off to turn-on time. This
delay is needed to prevent shoot-through in the external power
MOSFETs. See Applications Information for details on setting
dead time.
AGND — The low-level (analog) reference point.
PGND — The return for all low-side gate drivers. This should
be connected to the system power ground.
Terminal Descriptions (cont’d)
Three-Phase Power MOSFET Controller
A3932
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Commutation Truth Table
Logic Inputs Driver Outputs Motor Terminals
H1 H2 H3 DIR GLA GLB GLC GHA GHB GHC SA SB SC
1 0 1 1 0 0 1 1 0 0 H Z L
1 0 0 1 0 0 1 0 1 0 Z H L
1 1 0 1 1 0 0 0 1 0 L H Z
0 1 0 1 1 0 0 0 0 1 L Z H
0 1 1 1 0 1 0 0 0 1 Z L H
0 0 1 1 0 1 0 1 0 0 H L Z
1 0 1 0 1 0 0 0 0 1 L Z H
1 0 0 0 0 1 0 0 0 1 Z L H
1 1 0 0 0 1 0 1 0 0 H L Z
0 1 0 0 0 0 1 1 0 0 H Z L
0 1 1 0 0 0 1 0 1 0 Z H L
0 0 1 0 1 0 0 0 1 0 L H Z
Input Logic
MODE PWM SR RESET Operation
0 0 0 0 PWM chop mode, fast decay, all drivers off
0 1 0 0 Peak current limit, selected drivers on
1 0 0 0 PWM chop mode. slow decay, selected low side drivers on
1 1 0 0 Peak current limit, selected drivers on
0 0 1 0
PWM chop mode, fast decay with opposite of selected drivers on
0 1 1 0 Peak current limit, selected drivers on
1 0 1 0 PWM chop, slow decay with both low-side drivers on
1 1 1 0 Peak current limit, selected drivers on
X X X 1 All gate drive outputs off, clear fault logic, coast
L = Low (less positive) level
H = High (more positive) level
X = Don’t care
Z = High impedance
1 = Active or true logic condition
0 = Inactive or false logic condition
Three-Phase Power MOSFET Controller
A3932
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Applications Information
Additionally, a 0.1 μF (or larger) decoupling capacitor
should be connected between LCAP and AGND as close to the
device terminals as possible.
Protection Circuitry. The A3932 has several protection
features:
1) Bootstrap Circuit. The bootstrap capacitor is charged
whenever a low-side MOSFET is on, Sx output goes low,
and the load current recirculates. This happens constantly
during normal operation. The high-side MOSFET will not be
allowed to turn on before the charging has decayed to less than
approximately 9 mA. No fault will be registered.
When a phase’s high-side driver is on for a long time (100%
duty cycle operation) its charge pump is designed to maintain
VGS > 9 V on the bridge FET if IGHx (the load on the gate driver)
< 10 μA.
2) Hall Invalid. Illegal codes for the HALL inputs (000 or
111) will force a fault and coast the motor. Noisy Hall lines
may cause double TACH pulses and, therefore, code errors that
produce faults. Additional external pullup loading and fi ltering
may be required depending on the system.
3) VREG Undervoltage.
An internal regulator supplies the
low-side gate driver and the bootstrap charge current. It is critical
to ensure that VREG is at the proper level before enabling any of the
outputs. The undervoltage circuit is active during power-up and
will force a motor coast condition (all gate drives, GHx and GLx =
0) until VREG is greater than approximately 9.7 V.
4) Thermal Shutdown. A junction temperature greater than
165°C will signal a fault and coast the motor (all gate drives
LOW). If the junction temperature then falls to less than 155°C
(hysteresis), the fault will be cleared.
5) Motor Lead Shorted to Ground. The A3932 will signal
a fault if a motor lead is shorted to ground. A short to ground
is assumed after a high side is turned on and greater than 2 V is
measured between the drain (VBB) and source (SA/SB/SC) of the
high-side power MOSFET. This fault is cleared at the beginning
of each commutation. If a stalled motor results from a fault, the
fault can only be cleared by toggling the RESET terminal or by a
power-up sequence.
Synchronous Rectifi cation. To reduce power dissipation
in the external MOSFETs, the A3932 control logic turns on the
appropriate low-side and high-side driver during the load-current
recirculation, PWM-off cycle. Synchronous rectifi cation allows
current to fl ow through the MODE-selected MOSFET, rather
than the body diode, during the decay time. The body diodes of
the SR power MOSFETs will conduct only during the dead time
required at each PWM transition.
Dead Time. It is required to have a dead-time delay between a
high- or low-side turn off and the next turn-on event to prevent
cross conduction. The potential for cross conduction occurs with
synchronous rectifi cation, direction changes, PWM, or after a
bootstrap capacitor charging cycle. The dead time is set by a
resistor (Rdead) between the DEAD terminal and LCAP
(+5 V) and can be set between 100 ns and 5.5 μs.
The following equations are valid for Rdead between 5.6 kΩ
and 470 kΩ. At 25°C,
tdead (nom, ns) = 37 + (11.9 x 10-3 x (Rdead + 500))
For predicting worst case, over voltage and temperature
extremes,
tdead (min, ns) = 10 + (6.55 x 10-3 x (Rdead + 350))
tdead (max, ns) = 63 + (17.2 x 10-3 x (Rdead + 650))
For comparison with IDEAD test currents,
IDEAD = (VLCAP – Vbe)/(Rdead + Rint)
where (nominal values) VLCAP = 5 V, Vbe = 0.7 V at 25°C, and
Rint = 500 Ω.
Rather than use Rdead values near 470 kΩ, set DEAD =
ground (VDEAD = 0 V), which activates an internal (IDEAD =
10 μA) current source.
The choice of power MOSFET and external series gate
resistance determines the selection of the dead-time resistor. The
dead time should be made long enough to cover the variation of
the MOSFET gate capacitance and series gate resistance (both
external and internal to the A3932) tolerances.
Decoupling. The internal reference, VREG, supplies current
for the gate-drive circuit. As the gates are driven high they
will require current from an external capacitor to support the
transients. This capacitor should be placed as close as possible
to the VREG terminal. Its value should be at least 20 times larger
than the bootstrap capacitor. continued next page
Three-Phase Power MOSFET Controller
A3932
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Applications Information (cont’d)
Current Control. Internal fi xed off-time PWM circuitry is
implemented to limit load current to a desired value. When a
high-side and low-side MOSFET are turned on, current will
increase in the motor winding until it reaches a value given by
ITRIP ≈ VREF/RS.
At the trip point, the sense comparator resets the source-
enable latch, turning off the high-side driver. Load inductance
causes the current to recirculate (decay) for the fi xed off time.
The current path during recirculation is determined by the
confi guration of the MODE and SR inputs.
An external resistor (RT) and capacitor (CT), connected
in parallel from the RC terminal to AGND, are used to set the
fi xed off-time period (toff = RT x CT). RT should be in the range
of 10 kΩ to 500 kΩ. The toff should be in the range of 10 μs to
50 μs. Larger values for toff can result in audible noise problems.
Torque control can be implemented by varying the REF
input voltage as long as the PWM input stays high. If direct
control of the torque/current is desired by PWM input, a voltage
can be applied to the REF input to set an absolute maximum
current limit.
PWM Blank. The capacitor (CT) also serves as the means to
set the blank time duration. At the end of the PWM off cycle, a
high-side gate selected by the commutation logic will turn on.
At this time, large current transients can occur during the reverse
recovery time (trr) of the intrinsic body diodes of the external
power MOSFETs. To prevent false tripping of the current-sense
comparator, the blank function disables the comparator for a
time
tblank = 1.9 x CT/(0.001 - [2/RT])
The user must ensure that CT is large enough to cover the
current-spike duration.
Braking. The A3932 will dynamically brake by forcing all
low-side MOSFETs on and all high-side MOSFETs off. This
will effectively short-circuit the BEMF and brake the motor.
During braking, the load current can be approximated by:
IBRAKE = VBEMF/RL
Because the load current does not fl ow through the sense
resistor during a dynamic brake, care must be taken to ensure
that the power MOSFET’s maximum ratings are not exceeded.
RESET = 1 overrides BRAKE and turns all motor bridge
FETs off, coasting the motor.
Low-Voltage Operation. Although VREG can be connected
to VBB for 12 V systems, the VREG maximum rating of 15 V
must be observed including transients. If transients cannot be
adequately controlled, use VREG in the regulator mode (not
connected to VBB). With VBB less than 18 V, the VREG output
voltage level specifi cation may not be met. Note that in this
mode the VREG undervoltage threshold may leave the system
with little headroom if VBB is less than 12 V.
Driving an H Bridge. The A3932 may be used to drive an
H bridge (e.g., a brush dc motor load) by hard wiring one state
for the Hall inputs (e.g., H1 = H2 = 1 (HIGH), H3 = 0 (LOW)).
Leave the appropriate phase driver outputs fl oating (in this case
CC, GHC, SC, and GLC because, from the Commutation Truth
Table, SC = Z). The DIR input controls the motor rotation while
the PWM, MODE, and SR inputs control the motor current
behavior as described in the Input Logic table.
Layout. Careful consideration must be given to PCB layout
when designing high-frequency, fast-switching, high-current
circuits.
1) The analog ground (AGND), the power ground (PGND),
and the high-current return of the external MOSFETs (the
negative side of the sense resistor) should return separately to the
negative side of the motor supply fi ltering capacitor. This will
minimize the effect of switching noise on the device logic and
analog reference.
2) Minimize stray inductances by using short, wide copper
runs at the drain and source terminals of all power MOSFETs.
This includes motor lead connections, the input power buss,
and the common source of the low-side power MOSFETs. This
will minimize voltages induced by fast switching of large load
currents.
3) Kelvin connect the SENSE terminal PC trace to the positive
side of the sense resistor.
Three-Phase Power MOSFET Controller
A3932
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
1.20 MAX
0.10
4º
9.70
4.40 6.40 6.00
1.60
0.15
0.22
0.25
SEATING
PLANE
0.50
0.50
C0.10
38X C
0.30
21
38
21
38
GAUGE PLANE
SEATING PLANE
A
ATerminal #1 mark area
All dimensions nominal, not for tooling use
(reference JEDEC MO-153 BD-1)
Dimensions in millimeters
B
BReference pad layout (reference IPC SOP50P640X110-38M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
PCB Layout Reference View
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2002-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Package LD, 38-Pin TSSOP
