Freescale Semicondu ctor
Produ ct Br ief DSP56301PB
Rev. 2, 11/2005
© Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.
DSP56301
24-Bit Digital Signal Proc essor
The DSP56301 is a member of the DSP56300 core family of pr ogrammable CMOS DSPs. This family uses a high-
performance, si ngle clock cycle per instruction engine. Significant architectural features of the DSP56300 core
family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56301 performs at
66/80/100 MIPS using an internal 66/80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich
instruction set and low power dissipation, as well as increa sing levels of speed and power, enablin g wireless,
telecommunications, and multimed ia products.
Figu re 1. DSP56301 Block D iagram
PLL OnCE™
Clock
Generator
Internal
Data
Bus
Switch
Program RAM
4096 × 24
or
(3072 × 2 4 and
Instruction
Cache
1024 × 24 )
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODC/IRQC
MODB/IRQB
External
Data Bus
Switch
14
MODA/IRQA
DSP56300
652
24-Bit
24
24
X Data
RAM
2048 × 24
Y Data
RAM
2048 × 24
DDB
DAB
Memory Expa n s i on A rea
Peri pheral
Core
YM_EB
XM_EB
PM_EB
PIO_EB
Expa nsion Area
6
SCI
Interface
JTAG 6
3
RESET
MODD/IRQD
PINIT/NMI
2
Boot-
strap
ROM
E
XTAL
XTAL
ADDRESS
CONTRO
L
DATA
Triple
Timer Host
Interface ESSI
Interface
Address
Generation
Unit
Six Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24+56→56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Mngmnt
External
Bus
Interface
&
I - Cache
Control
External
Address
Bus
Switch
DSP56301 Product Brief, Rev. 2
2Freescale Semiconducto r
DSP56301 Features
DSP5 6301 Features
• High-performance DSP56300 core
— 66/80/100 Mil lion Instruc tions Per Second (MIPS) with a 66/ 80/100 MHz clock at 3.3 V
— Obj ect code compa tible with the DSP56000 core
— Highly parallel instruction set
— Fully pipelined 24 x 24-bit parallel multiplier-accumulator
— 56- b it parallel bar r e l s h if te r
— 24-bit or 16-bit arithmetic support under software control
— Position independent code support
— Add ressing modes optimized for DSP applications
— On-chip instruction cache controller
— On-chip memory-expandable hardware stack
— Nested hardware DO loops
— F ast au to - r etu r n int err u p ts
— On-chip concurrent six-channel DMA controller
— On-chip Phase Lock Loop (PLL) and clock generator
— On-Chip Emulation (OnCE™) module
— Joi nt Action Test Group (JTAG) Test Acce ss Port (TAP)
— Address tracing mode that reflects internal accesses at the external port
• On- chip me mor ies
— Pr o gram RAM, I n struction Cache , X d ata RAM, and Y data RAM size are p rogrammable :
—192 × 24-bit boot st rap ROM
• Off-chip memory expansion
— Data memory expansi on to two 16 M x 24-bit word memory spa ce s
— Prog r am me mory expansion to one 16 M x 24-bit word m emory space
— Exte r nal memory expa ns ion port
— Chip Select Logic requir ing no additional circuitry to interface to S RAMs and SSRAMs
— On-chip DRAM controller that requires no additional circuit r y to inter f ac e to DRAMs
• On-chip peripherals
— 32- bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with no additional interface logic
required for other DSP563xx buses
— ISA int erface requires only 74L S45-style buffe r
— Two Enhanc ed Synchronou s Serial Interfaces (ESSI)
— Ser ial Communications Interface (SCI) with baud r ate generator
— Triple timer module
— Up to 42 programm able General Pu rpos e I/O pins (GPIO), depending on whic h peripherals are enabled
• Reduced power dissipation
— Very low power CMOS design
— Wait and Stop low power standby modes
— Fully-static logic, operation frequency down to 0 Hz (DC)
— Optimized powe r management circ uitry
Instruction
Cache Switch
Mode Program
RAM Size Instruction
Cache Size X Dat a RA M
Size Y Data R am
Size
disabled disabled 4096 × 24-bi t 02048 × 24-bit 2048 × 24-bit
enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit
disabled enabled 2048 × 24-bit 03072 × 24-bit 3072 × 24-bit
enabled enabled 1024 × 24-bi t 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit
Target Appl ications
DSP56301 Product Brief, Rev. 2
Freescale Semiconductor 3
Target Appl icat io ns
The DSP56301 is intended as for general-purpose digital signal processing, pa rticularly in multimedia and
telecommunication applications, such as videoc onferencing and cellular telephony.
Prod uct Docume ntatio n
The documents listed in Table 1 are required for a complete descr i ption of the DSP56301 and are necessa ry to
desi gn w ith the part pr ope rl y. D ocu me n ta tion is av aila ble from a local Frees cal e di strib u tor, a Freescal e
semiconductor sales office, a Freescale Literature Distribution Center, or the Freescale web site listed on the back
cover of this document.
Table 1. DSP56301 Doc um entation
Topic Description Order Number
DSP56300 Family Manual Detai led description of the DSP56300 family
architecture and the 24-bit cor e process or and
instruction set
DSP56300FM
DSP56301 User’s Manual Detai led description of DSP56301 m em ory,
peripherals, and interfaces DSP56301UM
DSP56301 Technical Data DSP56301 pin and packa ge descriptions;
electrical and timing specifications DSP56301
DSP56301PB
Rev. 2
2/2005
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