CYPRESS PRELIMINARY fax id: 5425 CY7C4255V CY7C4265V 8K/16Kx18 Low Voltage Deep Sync FIFOs Features * 3.3V operation for low power consumption and easy integration into low voltage systems * High-speed, low-power, first-in first-out (FIFO) memories 8K x 18 (CY7C4255V) 16K x 18 (CY7C4265V) 0.5 micron CMOS for optimum speed/power High-speed 67-MHz operation (15 ns read/write cycle times) Low power _ loc= 25 mA Igg= 2 mA Fully asynchronous and simultaneous read and write operation Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags Retransmit function * Output Enable (OE) pin * Independent read and write enable pins * Supports free-running 50% duty cycle clock inputs Width Expansion Capability Depth Expansion Capability * 68-pin PLCC and 64-pin (10x10 STQFP) * Pin-compatible density upgrade from CY7C42K5V family Pin-compatible 3.3V solution for CY7C4255/65 Functional Description The CY7C4255V/65V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfac- es. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5V Low Voltage Synchranous FIFO family. The CY7C4255V/65V can be cascaded to increase FIFO depth. Programmable features include Almost Fuli/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buff- ering needs, including high-speed data acquisition, multiprocessor in- terfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continu- ally written into the FIFO on each cycle, The output port is controlled in a similar manner by a free-running read clock (ROLK) and a read enable pin (HEN). In addition, the CY7C4255V/65V have an output enable pin (OE). The read and write clocks may be tied together for single-ciock operation or the two clocks may be run independently for asynchronous readAwrite applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Fuil/Aimost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXl, RxXI), cascade output (WXO, AXO), and First Load (FD pins. The WXO and RXO pins are connected to the WXI and RX! pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and FiXI pins of the first device. The FL pin of the first device is tied to Vsg and the FL pin of allthe remaining devices should be tied to Veo: Logic Block Diagram WeLK = WEN | | FLAG PROGRAM WRITE THT REGISTER CONTROL 2 : | we FF ras RAM cena ARRAY LOGIC ba CaF 8K x 18 EHODE 16K x 18 4A WRITE READ POINTER z POINTER ? Ut RS RESET LOGIC rT THREE-STATE READ _ OUTPUTREGISTER Q aOR EXPANSION CONTROL RX 3) oe ro Gori? nck ata 4255V-1 For the most recent information, visit the Cypress web site at www.cypress.com 2-34=. CYPRESS PRELIMINARY CY7C4255V CY7C4265V Pin Configurations CY7C4255V CY7C4265V 4265V-~-2 Functional Description (continued) The CY7C4255V/65V provides five status pins. These pins are de- coded to determine one of five states: Empty, Aimost Empty, Half Full, Almost Full, and Full (see Table 2), The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion config- urations. In the depth expansion, this pin provides the ex- pansion out {WXO) information that is used to signal the next FIFO when it will be activated. Selection Guide Maximum Current (igg4) (MA) CY7C4255V CY7C4265V Density 8K x 18 16K x 18 Package 68-pin PLCC 68-pin PLCC 64-pin (10x10) | 64-pin (10x10) STQFP STQFP STQFP Top View CY7C4255V CY7C4265V i PGP POPBWP Z LONOU UO & 4255V-3 The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag archi- tecture guarantees that the flags will remain valid from one clock cycle to the next. The Almost Empty/Aimost Full flags become synchronous if the Voc/SMODE is tied to Vgg. All configurations are fabricated using an advanced 0.5y CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.CY7C4255V CYPRESS PRELIMINARY CY7C4265V Pin Definitions Signal Name Description vo Function | Do-17 Data Inputs 1 | Data inputs for an 18-bit bus | Qo17 Data Outputs | Data outputs for an 18-bit bus WEN Write Enable 1 | Enables the WCLK input REN Read Enable 1 | Enables the RCLK input WCLK Write Clock | |The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When CD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock | | The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When CD is asserted, RCLK reads data out of the programmabie flag- off- set register. WXO/HF Write Expansion | | Dual-Mode Pin: Out/Half Full Flag Single device or width expansion Half Full status flag. Cascaded Write Expansion Out signal, connected to WXT of next device. EF Empty Flag | When EF is LOW, the FIFO is empty. EF is synchronized fo RCLK. FF Full Flag | When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset Almost Empty value programmed into the FIFO. PAE is asynchronous when Voc/SMODE is tied to Voc: it is synchronized to RCLK when Voc/SMODE is tied to Vgg. PAF Programmable | When PAF is LOW, the FIFO is almost full based on the almost full offset value Almost Full programmed into the FIFO. PAF is asynchronous when Voc/SMODE is tied to Voc) it is synchronized to WCLK when Voc/SMODE is tied to Vgg. [Db Load f | When CD is LOW, Do_17 (Qo_17) are written (read) into (from) the programma- bie-flag-offset register. FL/RT First Load/ | | Dual-Mede Pin: Retransrnit Cascaded ~ The first device in the daisy chain will have FL tied to Vgg; all other | devices will have FL tied to Vcc. In standard mode or width expansion. FT is tied to Vgg on all devices. Not Cascaded - Tied to Vgg. Retransmit function is also available in standalone made by strobing AT. Wx! Write Expansion { | Cascaded Connected to WXO of previaus device. Input Not Cascaded Tied to Vgg. RT Read Expansion 1 | Cascaded ~ Connected to RXO of previous device. input Not Cascaded Tied to Vag. RXO Read Expansion | O | Cascaded - Connected to RX} of next device. Output | AS Reset | | Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable | | When OF is LOW, the FIFOs data outputs drive the bus to which they are con- nected. if OE is HIGH, the FIFOs outputs are in High Z (high-impedance) state. : Vec/SMODE | Synchronous 1 | Dual-Mode Pin ' Aimost Empty/ Asynchronous Almost Empty/Almost Full flags tied to Voc. Aimost Full Flags Synchronous Almost Empty/Almost Full flags tied to Vgg. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature Ambient Temperature with Power Applied... ee cc cererereeeeeseaes 55C to +125C teeebeceeeeeaseenssasesneseree ~65C to +150C Supply Voltage to Ground Potential......... 0.5V to Vee+0.5V DC Voltage Applied to Outputs in High Z State... cee eee -0.5V to Vee+0.5V DC input Voitage -O.5V to Vect0.5V Output Current into Outputs (LOW)... ee 20 mA Static Discharge VOHAGEe ...... eee cee etree eteetteteees >2001V (per MIL-STD-883, Method 3015} Latch-Up Current... ices seers ectntanetincness >200 mA 2-36CY7C4255V CYPRESS PRELIMINARY CY7C4265V Operating Range Ambient Range Temperature Vec Commercial aG to +70C 3.3V + 300 mV and 600 mV Industrial 40C to +85C 3.3V +300 mV and 600 mV L Electrica! Characteristics Over the Operating Range 7CA255V/65V-15 7TC4255V/65V25 Parameter Description Test Conditions Min. Max. Min. Max. Unit Vou Output HIGH Voltage Voc = Min., 24 2.4 v lon = -2.0 MA Vor Output LOW Voltage Veco = Min., 0.4 0.4 Vv lo, = 8.0 mA a Vigil input HIGH Voltage 2.0 Veco 2.0 Veco Vv : v7! Input LOW Voltage -0.5 0.8 ~0.5 0.8 Vv hx input Leakage Voc = Max. -10 +10 -10 +10 pA Current loz. Output OFF OE > Vin. ~10 +10 10 +10 BA lozH High Z Current Vss < Vo < Veco j leo! Active Power Supply Com'| 25 25 mA Current Ind : 30 mA lec2) Average Standby Com! 2 2 mA Current ind | mA Capacitance"! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f= 1 MHz, 5 pF | Court Output Capacitance Veo = 3.3V 7 pF AC Test Loads and Waveforms: ! Riz 330Q 3.3V ow ALL INPUT PULSES OUTPU Cc. T R2=5100 INCLUDING L JIG AND ~ - SCOPE Equivalent ta: THEVENIN EQUIVALENT Rth=2000 OUTPUT owe Vth=2.0V Notes: 4255V-5 1. The V4 and V), specifications apply for all inputs except WXI, AX!. The WXT, RXT pin is not a TTL input. It is connected to either AXO, WXO of the revious device or Vg. 2. @ Vi and Vy specifications apply for all inputs except WXT, RX. The WXI, RXI pin is not a TTL input. tt is connected to either AXO, WXO of the previous device or Vg. 3. Input signals switch from OV to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 2OMHz. while data inputs switch at 10MHz. Outputs are unloaded. All inputs = Veg 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/AT which is at V.,. All outputs are unloaded. Tested initially and after any design or process changes that may affect these parameters. CG, = 30 pF far all AC parameters except for toyiz. CG. = 5 pF for touz. ane 2-37CY7C4255V CYPRESS PRELIMINARY CY7C4265V Switching Characteristics Over the Operating Range 7C4255V/65V-15 7C4255V/65V-25 Parameter Description Min. Max. Min. Max. Unit ts Clock Cycie Frequency 66.7 40 MHz ta Data Access Time 2 10 2 15 ns toLk Clock Cycle Time 15 25 ns touKH Clock HIGH Time 6 10 ns teoLKL Clock LOW Time 6 10 ns tos Data Set-Up Time 4 6 ns tou Data Hold Time 0 i ns tens Enable Set-Up Time 4 6 ns tenn Enabie Hold Time 0 1 ns tas Reset Pulse Width!! 15 28 ns tasa Reset Recovery Time 10 15 ns tasr Reset to Flag and Output Time 15 25 ns tear Retransmit Pulse Width 35 45 ns tetR Retransmit Recovery Time 65 75 ns toz Output Enable to Output in Low Z12] 0 ns log Output Enable to Output Valid 3 8 12 ns tonz Output Enable to Output in High Zz! B 12 ns twrr Write Clock to Full Flag 10 15 ns taer Read Clock to Empty Flag 10 15 ns tparasynch _| Clock to Programmable Aimost-Full Flagl! 16 20 ns (Asynchronous mode, Voc/SMODE tied to Vec) tearsynch Clock to Programmable Almost-Fuli Flag 10 15 ns (Synchronous mode, Voo/SMUDE tied to Vg) tpazaaynch Clock to Programmable Aimost-Empty Flag! 16 20 ns (Asynchronous mode, Voc/SMUODE tied to Vo) tpaesynch Clock to Programmable Almost-Full Flag 10 15 ns {Synchronous mode, Veo/SMODE tied to Vss) tur Clock to Half-Fult Flag 16 20 ns txo Clock to Expansion Out 10 16 ns toy Expansion in Pulse Width 6.5 10 ns tyis Expansion in Set-Up Time 5 10 ns toxewt Skew Time between Read Clack and Write Clock for 6 10 ns Full Flag tsxewe Skew Time between Read Clock and Write Clock for 6 10 ns Empty Fiag tgxews Skew Tirne between Read Clock and Write Clock for 15 18 ns Programmable Almost Empty and Programmable Al- mast Full Flags (Synchronous Mode onty) Notes: 7. Pulse widths less than minimum values are not allowed. 8. Values guaranteed by design, not currently tested. toarasynety tPaEaayncty Sfler program register write wil not be valid until 5 ns + toae ey. 2-38CY7C4255V CYPRESS PRELIMINARY CY7C4265V Switching Waveforms Write Cycle Timing WCLK Do -Diz NO OPERATION oa RCLK re Read Cycle Timing 4255V~6 Touk foLKH toLkL RCLK teNH NO OPERATION Qo -Qy7 VALID DATA tsxewa "1 WCLK WEN \ 4256V-7 Notes: 10. & is the minirnum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the ffaing edge of FICLK and the rising edge of WCLK is less than lgxey;, then FE may nal change state urtl the next WCLK ring 11. tage e rcrvum sme between ang LK seat eT NCL eg to guararve el EF vi goHIGH urge cunt deck ye Itthe time between the Tising edge of WCLK and the rising edge of RCLK is tess than tgxeywo. then EF may not change state until the next RCL rising edge. 2-39ay: CY7C4255V PRELIMINARY CYPRESS CY7C4265V Switching Waveforms (continued) Reset Timing!'#! RS REN, WEN lasF EF,PAE tasr FF,PAF, AF tasr 9-817 SRA S \oe=0 4255V-8 First Data Word Latency after Reset with Simultaneous Read and Write WCLK Dg-D17 Do (FIRSTVALID WRITE) tsxewa RCLK touz [*-__ loz ________ OE N 4255V-9 Notes: 12. The clocks (RCLK, WCLK) can be free- running @ Guring rese reset 13. After reset, the outputs will be LOW if OE = 14. when lerewp 2! minimum rey atre| FAL imoanan ote The Latency Timing Wher tsxewe < Minimum specification, tr, (maximum) = either 2to, + tgxewe Of toLk + foxewe 5. The first word is available he a pete ater IEF goes Nee Haas 2-40a: CY7C4255V i PRELIMINARY Switching Waveforms (continued) Empty Flag Timing wax A NNN NN tos tps Do-Pir Ey OOOCCOCON Bh KQOOCK TEN: tENH tens teNH WEN [14] [14] KE ter) ___ le ter RCLK Sf) oN SY] M tsxewe tREF tREF tskew2 ae EF a REN \ GE [ty 09-O17 OO DKOIXK KK KKK bo 4255V~10 Full FlagTiming NO WRITE NO WRITE WCLK oN tsxewi tps texewd" 4 DATA WRITE = t 2-00 KK KMS ORTAWRTE XK KK RON {wer twer {wer FF A of ven \ Ren ~\ A VY VN VA NY | j TNH tenn tens tens REN Low DE ge ty ta Qo ~Qi7 DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ 4255V-11 2-41CY7C4255V PRELIMINARY CY7C4265V 7 CYPRESS Switching Waveforms (continued) HalfFull Flag Timing tcLKH fouKL wouK MNF NSN tens | ten WEN pm thE HALF FULL + 4 HF HALF FULL ORLESS OR MORE HALF FULLOR LESS RCLK A258V-12 Programmable Almost Empty Flag Timing touKH toLKL WCLK MON NY ON tpae 118) N+ 1 WORDS WORDS IN FIFO PAE IN FIFO trae > RCLK tens REN AX ' 4256V~13 Note: 16. PAE is offset = n. Number of data words into FIFO already =n. 2-42CY7C4255V j PRELIMINARY SP Cypress CY7C4265V Switching Waveforms (continued) Programmable Almost Empty Fiag Timing (applies only in SMODE (SMODE is LOW) tcLKH fouKL weik MONON NY tens | teny N 4 WEN NS | a Note 17 PAE N+ 1 WORDS INFIFO Note 19 tPAEsynch tens | teNH 4255-14 Programmable Almost Full Flag Timing toLkH tCLKL wore HN KY YK WCLK tens | teny WEN 3 INS. K t 2] Pr FULL- _M WORDS par! INFIFO2] FULL~ (M+t) WORDS IN FIFO! {par RCLK tens REN XQ 4255V~15. Notes: 17. PAE offset-n. 18. is fhe mirimum time between a ising WOLK and a rising RCLK acige for PAE to change state during that clock cycie. {f the time between the edge of WCLK and the ding AICLK is lags than tg PRE may not state unt! the next RCLIC 19, i a read is preformed Sexson rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW. 20. PAF offset =m. Number of data words written into FIFO already = 8192 ~ (m + 1) for the CY7C4255V and 16384 ~ (m + 1) for the CY7C4265V. 21. PAF is offset = 22, 8192-m words. in CY7C4255V and 16384 m words in CY7C4265V. 23. 8192 - (m+ 1) words in CY7C4255V and 16384 ~ (m + 1} CY7C4265V, 2-48CY7C4255V PRELIMINARY Ge p2855 CYTCA2E5V Switching Waveforms (continued) Programmable Almost Full Flag Timing (applies only when SMODE is low) toLKH +t tex. Note 24 WCLK NE, Ga 4, ee tens | ten WEN QS LZ note 25 it~ tear PAF FULL- M+4 WORDS rNoreer IN FIFO ~ ia ae ens tens | ten FEN IN 4 4255V-16 Write Programmable Registers tok TCLKH >| teLkL tens tenn e KZ tens ee WEN NK tos fpH PAE OFFSET PAE OFFSET PAF OFFSET Do ~D1g 4255V~17 Notes: 24, lf awrite is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when PAF goes LOW. 25, PAF offset =m. 26. tgxews is the minimum time between a rising ACLK and a rising WCLK edge for PAF to state during that clock cycle. If the time between the edge of RCLK and the Rising edge of WCLK is less than tgxew, then PAF may not change state until the next WCLK rising edge. 2-44CY7C4255V ; CYPRESS PRELIMINARY CY7C4265V Switching Waveforms (continued) Read Programmable Registers teik > toLKH } teLkL RCLK # FVD NIN SY tens tenn 1D N y iv AA AZAD tENS bea N WEN ~~ K t ty Qo -O47 KKK KKK UNKNOWN PAE OFFSET xX PAF OFFSET PAE OFFERS 4255V-18 Write Expansion Out Timing WCLK [s txo tens wen LLL 4255V~-19 Read Expansion Qut Timing torkH WCLK Note 28 xo RXO lh txo S} TENS Leal FEN LL 42356V-20 Write Expansion in Timing txt Wx! 4255V~21 Notes: 27. Write to Last Physical Location. 28. Read from Last Pnysical Location.CY7C4255V PRELIMINARY CY7C4265V CYPRESS Switching Waveforms (continued) Read Expansion In Timing ky oo RCLK xis 4255V~22 Retransmit Timing!@9 5 31) fo FU/AT 7 tpaep /<___ > taTR REN/WEN EF/FF and all async flags /PAE/PAF 4265V-23 Notes: 29. Clocks are free running in this case. 30. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at taza. 31. For the synchronous PAE and PAF flags (GMODE), an appropriate clock cycie is necessary after tayp to update these flags. 2-46i PRELIMINARY CYPRESS CY7C4255V CY7C4265V Architecture The CY7C4255V/65V consists of an array of 8K/16K words of 18 bits each (implemented by a dual-port array of SRAM celts), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, AS), and flags (EF, PAE, HE PAF FF). The CY7C4255V/65V also includes the control signals WRI, AXI, WXO, RX for depth expansion. Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only it OF is asserted. In order for the FIFO to reset to its default state, a falling edge must occur on HS and the user must not read or write while R& is LOW. FIFO Operation When the WEN signal is active (LOW), data present on the Dg_ 47 pins is written into the FIFO on each rising edge of the WCLK signal. Similarty, when the REN signal is active LOW, data in the FIFO mem- ory will be presented on the Qo. +7 outputs. New data will be present- ed on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up teysg before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Qo_47 out- puts when OE is deasserted. When OE is enabled (LOW), data in the output register will be available to the Qo..,7 outputs after tOE. If de- vices are cascaded, the OF function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO jis full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Qg_17 outouts even after additional reads occur. Programming The CY7C4255V/65V devices contain two 14-bit offset regis- ters. Data present on Dp_1 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags becorne active. If the user elects not to program the FIFCs flags, the defautt offset values are used (see Table 2). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs Dp_; is written into the Empty offset register on the first LOW-to-HIGH transi- tion of the write clock (WCLK). When the CD pin and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK), The third transi tion of the write clock (WCLK) again writes to the Empty offset register (see Table 1). Writing aii offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the CD pin HIGH, the FIFO is returned to normal read/write operation. When the CD pin is set LOW, ard WEN is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the output lines when the CD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK). Table 1. Write Offset Register DD | WEN | weik!! Selection 0 0 Writing to offset registers: Empty Offset 1 Full Offset CS 0 1 No Operation Write into FIFO No Operation [J | tf Note: 32. The same selection sequence apniies to reading from the registers. REN 4s enabled and read is on the LOW-+40-HIGH transition of ACLK. Flag Operation The CY7C4255V/65V devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are syn- chronous, PAE and PAF are synchronous if VCC/SMODE is tied to Veg Full Flag The Fuil Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e, itis exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state ot REN. EF is synchronized to RCLK, ie., itis exclusively updated by each rising edge of RCLK. Programmable Almost Empty/Almost Full Flag The CY7C4255V/65V features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (de- scribed in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be assertad, signify- ing that the FIFO is either Almost Full or Aimost Empty. See Table 2 for a description of programmabie flags. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. 2-47PRELIMINARY CYPRESS CY7C4255V CY7C4265V Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since Table 2. Flag Truth Table the last RS cycle. A HIGH pulse on AT resets the internal read point- er to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tarp after the retransmit pulse. With every valid read cycie after retransmit, previously access- ed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative iocations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. | Number of Words in FIFO 7C4255V 8K x 18 7C4265V - 16K x 18 FF PAF HF PAE EF 0 0 H H H L L 1 to nl 1 to nl H H H L H (n+1) to 4096 (n+1) to 8192 H H H H H 4097 to (8192-(m+1)) 8193 to (16384 -(m+1)) H H L H H (8192m)4I to 8191 (16384-m)1 to 16383 H L L H H 8192 46384 L L L H H Notes: 33. n= Empty Ofiset (Default Values: CY7C4255V/CY7C4265V n = 127). 34, m= Full t (Default Values: CY7C4255V/CY7C4265V n = 127). Width Expansion Configuration The CY7C4255V/65V can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode ail control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags of every FIFO; the PAE and PAF flags can be detected from any one device. This technique will avoid reading data from, or writing data to the FIFO that is staggered by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 7 demonstrates a 36-word width by using two CY7C4255V/65Vs. RESET (RS) RESET (RS) DATA IN(D) 36, | 18 18, : r READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) lt OUTPUT ENABLE (OE) sono 704255V PROGRAMMABLE (PAF PROGRAMMABLE(PAE) 704258V 7C4268V |_ PROGRAMMABLE (PAF) or FC4265V HALF FULL FLAG (HF) EMPTY FLAG (EF) =o SR FULL FLAG (FF) 18, DATA OUT (Q) 364 a > FIRST LOAD (FL) = WRITE EXPANSION IN (WRI) READ EXPANSION IN (XI) a) 4255V~-24 Figure 1. Block Diagram of 8K x18/16K x 18 Low Voltage Synchronous FIFO Memory Used in a Width Expansion Configuration 2-48PRELIMINARY CYPRESS CY7C4255V CY7C4265V Depth Expansion Configuration (with Programmable Flags) The CY7C4255V/65V can easily be adapted to applications requiring more than 8192/16384 words of buffering. Figure 2 shows Depth Expansion using three CY7C-42X5Vs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) controt input. 2. All other devices must have FT in the HIGH state. 3. The Write Expansion Out (WX) pin of each device must be tied to the Write Expansion in (WX) pin of the next device. 4. Tne Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (FIX]) pin of the next device. 5. Ali Load (LD) pins are tied together. 6. The Haif-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together thase respective flags for monitoring. The composite PAE and PAF flags are not precise. WO AXO 7CA255V 7C4265V FL FF PAF EF WX RXT WXO RXO 7C4255V DATAIN (D) FL fr PAF 7C4265V DATA OUT (Q) EF WXT RXI WRITECLOCK (WCLK) WRITEENABLE WXO RXO READ CLOCK (RCLK) READ ENABLE (REN) 7C4255V RESET (RS) LOAD (CB) FF PAF WI FIRST LOAD (FL) 7C4265V OUTPUTENABLE (OE) 4255V-25 Figure 2. Siock Diagram of 8Kx18/16Kx18 Low Voltage Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration 2-49ae ss PRELIMINARY CY7C4255V CY7C4265V Ordering information 8Kx18 Low Voltage Deep Sync FIFO Ordering Code Name 16Kx18 Low Voltage Deep Sync FIFO ns) Ordering Code Name 15 4 68-Lead Document #: 38-00653 2-50