LTC4357
1
4357fd
Features
applications
Description
Positive High Voltage
Ideal Diode Controller
The LTC
®
4357 is a positive high voltage ideal diode control-
ler that drives an external N-channel MOSFET to replace a
Schottky diode. When used in diode-OR and high current
diode applications, the LTC4357 reduces power consump-
tion, heat dissipation, voltage loss and PC board area.
The LTC4357 easily ORs power sources to increase total
system reliability. In diode-OR applications, the LTC4357
controls the forward voltage drop across the MOSFET to
ensure smooth current transfer from one path to the other
without oscillation. If the power source fails or is shorted,
a fast turn-off minimizes reverse current transients.
48V, 10A Diode-OR
n Reduces Power Dissipation by Replacing a Power
Schottky Diode with an N-Channel MOSFET
n 0.5µs Turn-Off Time Limits Peak Fault Current
n Wide Operating Voltage Range: 9V to 80V
n Smooth Switchover without Oscillation
n No Reverse DC Current
n Available in 6-Lead (2mm × 3mm) DFN and
8-Lead MSOP Packages
n N + 1 Redundant Power Supplies
n High Availability Systems
n AdvancedTCA Systems
n Telecom Infrastructure
n Automotive Systems
4357 TA01
LTC4357
GND
IN OUT
VDD
GATE
FDB3632
VINA
48V
VOUT TO LOAD
LTC4357
GND
IN OUT
VDD
GATE
FDB3632
VINB
48V
*SEE FIGURES 2 AND 3 FOR ADDITIONAL OPTIONAL COMPONENTS
Power Dissipation vs Load Current
typical application
CURRENT (A)
0
0
POWER DISSIPATION (W)
1
2
3
4
5
6
2 4 6 8
4357 TA01b
10
DIODE (MBR10100)
FET (FDB3632)
POWER
SAVED
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
LTC4357
2
4357fd
absolute MaxiMuM ratings
Supply Voltages
IN ............................................................ –1V to 100V
OUT, VDD .............................................. –0.3V to 100V
Output Voltage
GATE (Note 3) ........................ VIN – 0.2V to VIN + 10V
(Notes 1, 2)
TOP VIEW
VDD
NC
GND
OUT
IN
GATE
DCB PACKAGE
6-LEAD (2mm s 3mm) PLASTIC DFN
4
5
7
GND
6
3
2
1
TJMAX = 125°C, θJA = 90°C/W
EXPOSED PAD (PIN 7) PCB GND CONNECTION OPTIONAL
1
2
3
4
IN
NC
NC
GATE
8
7
6
5
OUT
VDD
NC
GND
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 163°C/W
Operating Ambient Temperature Range
LTC4357C ................................................ 0°C to 70°C
LTC4357I.............................................. –40°C to 85°C
LTC4357H .......................................... –40°C to 125°C
LTC4357MP ....................................... –55°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package ...................................................... 300°C
pin conFiguration
orDer inForMation
LEAD FREE FINISH
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4357CDCB#TRMPBF LTC4357CDCB#TRPBF LCXF 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC4357IDCB#TRMPBF LTC4357IDCB#TRPBF LCXF 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC4357HDCB#TRMPBF LTC4357HDCB#TRPBF LCXF 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4357CMS8#PBF LTC4357CMS8#TRPBF LTCXD 8-Lead Plastic MSOP 0°C to 70°C
LTC4357IMS8#PBF LTC4357IMS8#TRPBF LTCXD 8-Lead Plastic MSOP –40°C to 85°C
LTC4357HMS8#PBF LTC4357HMS8#TRPBF LTCXD 8-Lead Plastic MSOP –40°C to 125°C
LTC4357MPMS8#PBF LTC4357MPMS8#TRPBF LTFWZ 8-Lead Plastic MSOP –55°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4357MPMS8 LTC4357MPMS8#TR LTFWZ 8-Lead Plastic MSOP –55°C to 125°C
LTC4357
3
4357fd
electrical characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VOUT = VDD, VDD = 9V to 80V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Operating Supply Range l9 80 V
IDD Supply Current l0.5 1.25 mA
IIN IN Pin Current VIN = VOUT ±1V l150 350 500 µA
IOUT OUT Pin Current VIN = VOUT ±1V l80 210 µA
DVGATE External N-Channel Gate Drive
(VGATE – VIN)
VDD, VOUT = 20V to 80V
VDD, VOUT = 9V to 20V
l
l
10
4.5
12
6
15
15
V
V
IGATE(UP) External N-Channel Gate Pull-Up Current VGATE = VIN, VIN – VOUT = 0.1V l–14 –20 –26 µA
IGATE(DOWN) External N-Channel Gate Pull-Down
Current in Fault Condition
VGATE = VIN + 5V l1 2 A
tOFF Gate Turn-Off Time VIN – VOUT = 55mV –|
––1V,
VGATE – VIN < 1V, CGATE = 0pF
l300 500 ns
DVSD Source-Drain Regulation Voltage
(VIN – VOUT)
VGATE – VIN = 2.5V l10 25 55 mV
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
IN or 100V above GND. Driving this pin to voltages beyond this clamp may
damage the device.
typical perForMance characteristics
VDD Current (IDD vs VDD) IN Current (IIN vs VIN) OUT Current (IOUT vs VOUT)
VDD (V)
0
IDD (µA)
400
600
80
4357 G01
200
020 40 60
800 VDD = VOUT = VIN ± 1V
VIN (V)
0
IIN (µA)
200
300
80
4357 G02
100
020 40 60
400 VDD = VOUT = VIN + 1V
VDD = VOUT = VIN – 1V
VOUT (V)
0
IOUT (µA)
60
120
80
4357 G03
020 40 60
180
30
90
150
VDD = VOUT = VIN + 1V
VDD = VOUT = VIN – 1V
LTC4357
4
4357fd
typical perForMance characteristics
OUT Current (IOUT vs VIN)
FET Turn-Off Time
vs GATE Capacitance
FET Turn-Off Time
vs Initial Overdrive
GATE Current vs Forward Drop
(IGATE vs DVSD)
DVGATE vs GATE Current
(DVGATE vs IGATE)
VSD (mV)
–50
–50
IGATE (µA)
–25
0
25
0 50
4357 G04
100 150
$VGATE = 2.5V
IGATE (µA)
0
0
$VGATE (V)
5
10
15
5 10 15 20
4357 G05
25
VIN > 18V
VIN = 12V
VIN = 9V
VIN (V)
0
IOUT (µA)
75
100
125
6 10 14
4357 G06
50
25
0
2 4 812
VOUT = 12V, VIN = VDD
VINITIAL (V)
0
tPD (ns)
200
300
0.8
4357 G08
100
00.2 0.4 0.6 1.0
400 VIN = 48V
$VSD = VINITIAL –1V
FET Turn-Off Time
vs Final Overdrive
VFINAL (V)
–1
tPD (ns)
1000
1500
–0.2
4357 G09
500
0–0.8 –0.6 –0.4 0
2000 VIN = 48V
$VSD = 55mV VFINAL
FET Load Current vs DVSD
CGATE (nF)
0
tOFF (ns)
300
400
500
80
4357 G07
200
100
0
20 40 60
VGATE < VIN + 1V
$VSD = 55mV –1V
∆VSD (mV)
0
LOAD CURRENT (A)
6
8
10
75
4357 G10
4
2
0
25 50
VIN = 48V WITH FET (FDB3632)
LTC4357
5
4357fd
pin Functions
Exposed Pad: Exposed pad may be left open or connected
to GND.
GATE: Gate Drive Output. The GATE pin pulls high, enhanc-
ing the N-channel MOSFET when the load current creates
more than 25mV of voltage drop across the MOSFET.
When the load current is small, the gate is actively driven
to maintain 25mV across the MOSFET. If reverse current
develops more than –25mV of voltage drop across the
MOSFET, a fast pull-down circuit quickly connects the
GATE pin to the IN pin, turning off the MOSFET.
GND: Device Ground.
IN: Input Voltage and GATE Fast Pull-Down Return. IN is
the anode of the ideal diode and connects to the source
of the N-channel MOSFET. The voltage sensed at this pin
is used to control the source-drain voltage across the
MOSFET. The GATE fast pull-down current is returned
through the IN pin. Connect this pin as close as possible
to the MOSFET source.
NC: No Connection. Not internally connected.
OUT: Drain Voltage Sense. OUT is the cathode of the ideal
diode and the common output when multiple LTC4357s
are configured as an ideal diode-OR. It connects to the
drain of the N-channel MOSFET. The voltage sensed at
this pin is used to control the source-drain voltage across
the MOSFET.
VDD: Positive Supply Input. The LTC4357 is powered from
the VDD pin. Connect this pin to OUT either directly or
through an RC hold-up circuit.
4357 BD
CHARGE PUMP
–+
–
+
+
–
FPD
COMP
GATE
AMP
25mV25mV
IN GATE
17V OUT
GND
IN
VDD
+
–
block DiagraM
LTC4357
6
4357fd
operation
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the point
of load. The disadvantage of this approach is the forward
voltage drop and resulting efficiency loss. This drop reduces
the available supply voltage and dissipates significant
power. Using an N-channel MOSFET to replace a Schottky
diode reduces the power dissipation and eliminates the
need for costly heat sinks or large thermal layouts in high
power applications.
The LTC4357 controls an external N-channel MOSFET to
form an ideal diode. The voltage across the source and
drain is monitored by the IN and OUT pins, and the GATE
pin drives the MOSFET to control its operation. In effect
the MOSFET source and drain serve as the anode and
cathode of an ideal diode.
At power-up, the load current initially flows through the
body diode of the MOSFET. The resulting high forward
voltage is detected at the IN and OUT pins, and the
LTC4357 drives the GATE pin to servo the forward drop
to 25mV. If the load current causes more than 25mV of
voltage drop when the MOSFET gate is driven fully on,
the forward voltage is equal to RDS(ON) • ILOAD.
If the load current is reduced causing the forward drop
to fall below 25mV, the MOSFET gate is driven lower by
a weak pull-down in an attempt to maintain the drop at
25mV. If the load current reverses and the voltage across
IN to OUT is more negative than –25mV the LTC4357
responds by pulling the MOSFET gate low with a strong
pull-down.
In the event of a power supply failure, such as if the output
of a fully loaded supply is suddenly shorted to ground,
reverse current temporarily flows through the MOSFET that
is on. This current is sourced from any load capacitance
and from the other supplies. The LTC4357 quickly responds
to this condition turning off the MOSFET in about 500ns,
thus minimizing the disturbance to the output bus.
MOSFET Selection
The LTC4357 drives an N-channel MOSFET to conduct
the load current. The important features of the MOSFET
are on-resistance, RDS(ON), the maximum drain-source
voltage, VDSS, and the gate threshold voltage.
Gate drive is compatible with 4.5V logic-level MOSFETs
in low voltage applications (VDD = 9V to 20V). At higher
voltages (VDD = 20V to 80V) standard 10V threshold MOS-
FETs may be used. An internal clamp limits the gate drive
to 15V between the GATE and IN pins. An external Zener
clamp may be added between GATE and IN for MOSFETs
with a VGS(MAX) of less than 15V.
The maximum allowable drain-source voltage, BVDSS,
must be higher than the power supply voltage. If an input
is connected to GND, the full supply voltage will appear
across the MOSFET.
ORing Two-Supply Outputs
Where LTC4357s are used to combine the outputs of two
power supplies, the supply with the highest output voltage
sources most or all of the load current. If this supply’s
output is quickly shorted to ground while delivering load
current, the flow of current temporarily reverses and
flows backwards through the LTC4357’s MOSFET. When
the reverse current produces a voltage drop across the
MOSFET of more than –25mV, the LTC4357’s fast pull-down
activates and quickly turns off the MOSFET.
If the other, initially lower, supply was not delivering load
current at the time of the fault, the output falls until the
body diode of its ORing MOSFET conducts. Meanwhile,
the LTC4357 charges its MOSFET gate with 20µA until the
forward drop is reduced to 25mV. If instead this supply was
delivering load current at the time of the fault, its associ-
ated ORing MOSFET was already driven at least partially
on, and the LTC4357 will simply drive the MOSFET gate
harder in an effort to maintain a drop of 25mV.
applications inForMation
LTC4357
7
4357fd
applications inForMation
Figure 1. Droop Sharing Redundant Supplies
Load Sharing
The application in Figure 1 combines the outputs of multiple,
redundant supplies using a simple technique known as
droop sharing. Load current is first taken from the highest
output, with the low outputs contributing as the output
voltage falls under increased loading. The 25mV regulation
technique ensures smooth load sharing between outputs
without oscillation. The degree of sharing is a function of
RDS(ON), the output impedance of the supplies and their
initial output voltages.
Input Short-Circuit Faults
The dynamic behavior of an active, ideal diode entering
reverse bias is most accurately characterized by a delay
followed by a period of reverse recovery. During the delay
phase some reverse current is built up, limited by parasitic
resistances and inductances. During the reverse recovery
phase, energy stored in the parasitic inductances is trans-
ferred to other elements in the circuit. Current slew rates
during reverse recovery may reach 100A/µs or higher.
High slew rates coupled with parasitic inductances in se-
ries with the input and output paths may cause potentially
destructive transients to appear at the IN and OUT pins
of the LTC4357 during reverse recovery. A zero imped-
ance short-circuit directly across the input of the circuit
is especially troublesome because it permits the highest
possible reverse current to build up during the delay phase.
When the MOSFET finally commutates the reverse current
the LTC4357 IN pin experiences a negative voltage spike,
while the OUT pin spikes in the positive direction.
To prevent damage to the LTC4357 under conditions of
input short-circuit, protect the IN pin and OUT pin as
shown in Figure 2. The IN pin is protected by clamping
to the GND pin in the negative direction. Protect the OUT
pin with a clamp, such as with a TVS or TransZorb, or with
a local bypass capacitor of at least 10µF. In low voltage
applications the MOSFET's drain-source breakdown may
be sufficient to protect the OUT pin, provided BVDSS +
VIN < 100V.
Parasitic inductance between the load bypass and the
LTC4357 allows a zero impedance input short to collapse
the voltage at the VDD pin, which increases the total turn-off
time (tOFF). For applications up to 30V, bypass the VDD pin
with 39µF; above 30V use at least 100µF. If VDD is powered
from the output side, one capacitor serves to guard against
VDD collapse and also protect OUT from voltage spikes.
If the OUT pin is protected by a diode clamp or if VDD is
powered from the input side, decouple the VDD pin with a
separate 100Ω, 100nF filter (see Figure 3). In applications
above 10A increase the filter capacitor to 1µF.
LTC4357
8
4357fd
Design Example
The following design example demonstrates the calcula-
tions involved for selecting components in a 12V system
with 10A maximum load current (see Figure 4).
First, calculate the RDS(ON) of the MOSFET to achieve the de-
sired forward drop at full load. Assuming VDROP = 0.1V,
RDS(ON) ≤VDROP
ILOAD
=0.1V
10A
RDS(ON) ≤10mΩ
The Si4874DY offers a good solution, in an S8 package
with RDS(ON) = 10mΩ(max) and BVDSS of 30V.
The maximum power dissipation in the MOSFET is:
P = ILOAD2 • RDS(ON) = (10A)2 • 10mΩ = 1W
With less than 39µF of local bypass, the recommended RC
values of 100Ω and 0.1µF were used in Figure 4.
Since BVDSS + VIN is much less than 100V, output clamp-
ing is unnecessary.
Figure 3. Protecting Against Collapse of VDD During Reverse Recovery
applications inForMation
Figure 2. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pin.
The Polarity of Step Recovery Spikes is Shown Across Parasitic Inductances
4357 F02
LTC4357
+ –
GND
IN OUT
VDD
GATE
M1
REVERSE RECOVERY CURRENT
VIN
INPUT
SHORT
DIN
SBR1U-
150SA
INPUT PARASITIC
INDUCTANCE
COUT
10µF
VOUT
CLOAD
DCLAMP
SMAT70A
OR
+ –
OUTPUT PARASITIC
INDUCTANCE
4357 F03
LTC4357
GND
IN OUT
VDD
GATE
M1
OUTPUT PARASITIC
INDUCTANCE
VIN
R1
100Ω
C1
100nF
INPUT
SHORT COUT
VOUT
CLOAD
OR
Figure 4. 12V, 10A Diode-OR
4357 F04
LTC4357
GND
IN OUT
VDD
GATE
M2
Si4874DY
VIN2
12V
R1
100Ω
C1
0.1µF
R1
100Ω
C1
0.1µF
LTC4357
GND
IN OUT
VDD
GATE
M1
Si4874DY
VIN1
12V
VOUT
TO LOAD
LTC4357
9
4357fd
Layout Considerations
Connect the IN and OUT pins as close as possible to the
MOSFET’s source and drain pins. Keep the traces to the
MOSFET wide and short to minimize resistive losses. See
Figure 5.
applications inForMation
Figure 5. Layout Considerations
For the DFN package, pin spacing may be a concern at
voltages greater than 30V. Check creepage and clearance
guidelines to determine if this is an issue. To increase the
pin spacing between high voltage and ground pins, leave
the exposed pad connection open. Use no-clean solder
to minimize PCB contamination.
LTC4357
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
D
MOSFET
IN
GATE
OUT
VIN VOUT
4357 F05
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
D
VIN
OUTGATE
IN
4
5
7
6
3
2
1
VOUT
LTC4357
10
4357fd
typical applications
–12V Reverse Input Protection
4357 TA03
LTC4357
GND
IN OUT
VDD
GATE
M1
Si4874DY
VIN
12V
D1
MMBD1205
CLOAD
VOUT
12V
10A
–48V Reverse Input Protection
4357 TA04
LTC4357
GND
IN OUT
VDD
GATE
M1
FDB3632
VIN
48V
D1
MMBD1205
CLOAD
DCLAMP
SMAT70A
VOUT
48V
10A
Solar Panel Charging a Battery
4357 TA02
LTC4357
GND
IN OUT
12V
BATTERY
VDD
GATE
M1
FDB3632
C1
0.1µF
R1
100Ω
14V
SHUNT
REGULATOR
+
LOAD
100W
SOLAR
PANEL
4357 TA05
LTC4357
GND
IN OUT
VDD
GATE
M1
FDS3672
10M
VIN
48V
5A
G1
BSS123
C1
0.1µF
R1
100Ω
DCLAMP
SMAT70A
VOUT
ON OFF
Low Current Shutdown
LTC4357
11
4357fd
package Description
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
3.00 p0.10
(2 SIDES)
2.00 p0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 p0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 p 0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
s 45o CHAMFER
0.25 p 0.05
1.35 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 p0.05
(2 SIDES)
2.15 p0.05
0.70 p0.05
3.55 p0.05
PACKAGE
OUTLINE
0.50 BSC
LTC4357
12
4357fd
package Description
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
MSOP (MS8) 0307 REV F
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 p 0.152
(.193 p .006)
8765
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
LTC4357
13
4357fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision history
REV DATE DESCRIPTION PAGE NUMBER
D 09/10 Revised θJA value for MS8 package in Pin Configuration section and added MP-grade to Order Information section 2
Added two new plots and revised remaining curves in Typical Performance Characteristics section 3, 4
Updated Electrical Characteristics section 4
Revised Figure 2 and Figure 4 in Applications Information section 8
(Revision history begins at Rev D)
LTC4357
14
4357fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com
LINEAR TECHNOLOGY CORPORATION 2007
LT 0910 REV D • PRINTED IN USA
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–48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V
LTC4252-1/LTC4252-2/
LTC4252-1A/LTC4252-2A
–48V Hot Swap Controllers in MS8/MS10 Fast Active Current Limiting, Supplies from –15V, Drain Accelerated
Response
LTC4253 –48V Hot Swap Controller with Sequencer Fast Active Current Limiting, Supplies from –15V, Drain Accelerated
Response, Sequenced Power Good Outputs
LT4256 Positive 48V Hot Swap Controller with
Open-Circuit Detect
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output,
Up to 80V Supply
LTC4260 Positive High Voltage Hot Swap Controller With I2C and ADC, Supplies from 8.5V to 80V
LTC4261 Negative High Voltage Hot Swap Controller With I2C and 10-Bit ADC, Adjustable Inrush and Overcurrent Limits
LTC4352 Ideal Diode Controller with Monitor Controls N-Channel MOSFET, 0V to 18V Operation
LTC4354 Negative Voltage Diode-OR Controller
and Monitor
Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation
LTC4355 Positive Voltage Diode-OR Controller
and Monitor
Controls Two N-Channel MOSFETs, 0.5µs Turn-Off, 80V Operation
LT4356-1/LT4356-2/
LT4356-3
Surge Stopper, Overvoltage and Overcurrent
Protection Regulator
Wide Operation Range: 4V to 80V, Reverse Input Protection to –60V,
Adjustable Output Clamp Voltage
4357 TA06
LTC4357
GND
IN OUT
VDD
GATE
FDB3632
PLUG-IN CARD
CONNECTOR 1
BACKPLANE
CONNECTORS
PLUG-IN CARD
CONNECTOR 2
48V VOUT1
VOUT2
GND
SMAT70A
SMAT70A
CHOLDUP
GND
LTC4357
GND
IN OUT
VDD
GATE
FDB3632
GND
Hot Swap
CONTROLLER
Hot Swap
CONTROLLER
+
CHOLDUP
+