October 2006 Rev 4 1/64
1
M50FLW080A
M50FLW080B
8-Mbit (13 x 64-Kbyte Blocks + 3 × 16 × 4 Kbyte Sectors)
3-V supply, Firmware Hub / low-pin-count Flash memory
Feature summary
■Flash mem or y
– Compatib le with eit her the LPC inte rface or
the FWH interface (Intel Spec rev1.1) used
in PC BIOS applications
– 5-signal communication interface
supporting Read and Write operations
– 5 additional general-purpose inputs for
platform design flexibility
– Synchronized with 33 MHz PCI clock
■16 blocks of 64 Kbytes
– 13 blocks of 64 Kbytes each
– 3 blocks, subdivided into 16 uniform
sectors of 4 Kbytes each
Two bloc ks at the top and one at the bottom
(M50FLW080A)
One block at the top a nd two at the bottom
(M50FLW080B)
■Enhanced security
– Hardware Write Protect pins fo r block
protection
– Register-based Read and Write Protection
– Individual Loc k Register for each 4 KByte
sector
■Supply voltage
–V
CC = 3.0 to 3.6 V for Program, Erase and
Read operations
–V
PP = 12 V for Fast Program and Erase
■Two interfaces
– Auto Detection of Firmware Hub (FWH) or
Low Pin Count (LPC) memory cycles for
embedded operation with PC chipsets
– Address/Address Multiplexed (A/A Mux)
interface for programming equipment
compatibility.
■Programming time: 10 µs typical
■Program/Erase Controller
– Embedded Program and Erase algorithms
– Status Register bits
■Program/Erase Suspend
– Read other Blocks/Sectors during Progr am
Suspend
– Program other Blocks/Sectors during Erase
Suspend
■ELectronic signature
– Manufacturer Code: 20h
– Device Code (M50FLW 08 0A) : 80 h
– Device Code (M50FLW 08 0B) : 81 h
■Packages
– ECOPACK® (RoHS compliant)
TSOP32 (NB)
8 × 14 mm
PLCC32 (K)
TSOP40 (N)
10 × 20 mm
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Contents M50FLW080A, M50FLW080B
2/64
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Firmware Hub/low-pin-count (FWH/LPC) signal descriptions . . . . . . . . . 13
2.1.1 Input/Output communications (FWH0/LAD0-FWH3/LAD3) . . . . . . . . . . 13
2.1.2 Input communication frame (FWH4/LFRAME) . . . . . . . . . . . . . . . . . . . 13
2.1.3 Identification inputs (ID0-ID3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.4 General-purpose inputs (GPI0-GPI4) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.5 Interface configuration (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.6 Interface Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.7 CPU Reset (INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.8 Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.9 Top Block Lock (TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.10 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.11 Reserved for Future Use (RFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Address/Address multiplexed (A/A Mux) signal descriptions . . . . . . . . . . 15
2.2.1 Address inputs (A0-A10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.4 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.5 Row/Column Address Select (RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Supply signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2 VPP optional supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.3 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Firmware Hub/low-pin-count (FWH/LPC) bus operations . . . . . . . . . . . . 17
3.1.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.3 Bus Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.6 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M50FLW080A, M50FLW080B Contents
3/64
3.2 Address/Address multiplexed (A/A Mux) bus operations . . . . . . . . . . . . . 19
3.2.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5 Quadruple Byte Program command (A/A Mux interface) . . . . . . . . . . . . . 27
4.6 Double/Quadruple Byte Program command (FWH mode) . . . . . . . . . . . . 27
4.7 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.8 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.9 Sector Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.10 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.11 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.12 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Program/Erase Controller status (bit SR7) . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Erase Suspend status (bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Erase status (bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4 Program status (bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5 VPP status (bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6 Program Suspend status (bit SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.7 Block/Sector Protection status (bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.8 Reserved (bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 Firmware Hub/low-pin-c ount (FWH/LPC) interface
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.2 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Contents M50FLW080A, M50FLW080B
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6.1.3 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Firmware Hub/low-pin-count (FWH/LPC) General-Purpose
Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7 Pr ogram and Erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Appendix A Block and sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Appendix B Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
M50FLW080A, M50FLW080B List of tables
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List of tables
Table 1. Signal names (FWH/LPC interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Signal names (A/A Mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Addresses (M50FLW080A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Addresses (M50FLW080B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Memory identification input configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. FWH Bus Read field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. FWH Bus Write field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. LPC Bus Read field definitions (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. LPC Bus Write field definitions (1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. A/A Mux bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Configuration Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16. Lock Register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. General-Purpose Input Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18. Program and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 20. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. FWH/LPC interface AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. A/A Mux interface AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 23. Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 24. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25. FWH/LPC interface clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 26. FWH/LPC Interface AC signal timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 27. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 28. A/A Mux interface Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. A/A Mux interface Write AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 33. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 34. M50FLW080A block, sector and Lock Register addresses . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 35. M50FLW080B block, sector and Lock Register addresses . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
List of figures M50FLW080A, M50FLW080B
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List of figures
Figure 1. Logic diagram (FWH/LPC interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Logic diagram (A/A Mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. PLCC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. TSOP32 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. TSOP40 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. FWH Bus Read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. FWH Bus Write waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. LPC Bus Read waveforms (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. LPC Bus Write waveforms (1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. FWH/LPC interface AC measurement I/O waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. A/A Mux interface AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. FWH/LPC interface clock waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. FWH/LPC interface AC signal timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 15. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 16. A/A Mux interface Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. A/A Mux interface Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package outline . . . . . . . . . . 48
Figure 19. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline . . . . . . . . . . . . 49
Figure 20. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package outline . . . . . . . . . . . 50
Figure 21. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Double/Quadruple Byte Program flowchart and pseudo code (FWH mode only). . . . . . . . 57
Figure 23. Quadruple Byte Program flowchart and pseudo code (A/A Mux interface only). . . . . . . . . 58
Figure 24. Program Suspend and Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25. Chip Erase flowchart and pseudo code (A/A Mux interface only). . . . . . . . . . . . . . . . . . . . 60
Figure 26. Sector/Block Erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 27. Erase Suspend and Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 62
M50FLW080A, M50FLW080B Summary description
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1 Summary description
The M50FLW080 is a 8 Mbit (1M x8) non-volatile memory that can be read, erased and
reprogr amm ed. These op er ations can b e performed using a single lo w voltage (3 .0 to 3. 6V)
supply. For fast programming and fast erasing on production lines, an optional 12V power
supply can be used to reduce the erasing and programming time.
The memory is divided into 16 Unif orm Blocks of 64 KBytes e ach, three of wh ich are divided
into 16 unif orm sectors of 4 KBytes each (see Appe ndix A f or details). All b locks and sectors
can be erased independently. So, it is possible to preserve valid data while old data is
erased. Blocks can be protected individually to prevent accidental program or erase
commands from modifying their contents.
Progr a m a nd erase co mmands a re written to t he Comman d I nte rface of the memory. An on-
chip Program/Erase Controller simplifies the process of programming or erasing the
memory by taking care of all of the special operations that are required to update the
memory contents. The end of a progr am or erase op eration can be detected and any error
conditions identified. The command set to control the memory is consistent with the JEDEC
standards.
Two different bus interfaces are supported by t he memory:
●The primary interface, the FWH/LPC Interface, uses Intel’s proprietary Firmware Hub
(FWH) and Lo w Pin Count (LPC) p rotocol. T his has been desig ned to remo v e the ne ed
for the ISA bus in current PC Chipsets. The M50FLW080 acts as the PC BIOS on the
Low Pin Count bus for these PC Chipsets.
●The secondary interface, t he Address/Address Multiplexed (or A/A Mux) Interface, is
designed to be compatible with cur rent Flash Programmers, for production line
programming prior to fitting the device in a PC Moth erboard.
In order to meet enviro nmental requirements, ST of fers the M50FLW080A and
M50FLW080B in ECOPACK® packages. ECO PACK® packages are Lead-free and RoHS
compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
The memory is supplied with all the bits erased (set to ’1’).
Summary description M50FLW080A, M50FLW080B
8/64
Figure 1. Logic diagram (FWH/LPC interfac e)
Table 1. Signal names (FWH/LPC interface)
FWH0/LAD0-FWH3/LAD3 Input/Output Communications
FWH4/LFRAME Input Communication Frame
ID0-ID3 Identification Inputs
(ID0 and ID1 are Reserved for Future Use (RFU) in LPC mode)
GPI0-GPI4 General Purpose Inputs
IC Interface Configuration
RP Interface Reset
INIT CPU Reset
CLK Clock
TBL Top Bloc k L ock
WP Write Protect
RFU Reserved for Future Use. Leave disconnected
VCC Supply Vo ltage
VPP Optional Supply Voltage for Fast Program and Erase Operations
VSS Ground
NC Not Connected Internally
AI09229B
4
FWH4/LFRAME
FWH0/LAD0
FWH3/LAD3
VCC
M50FLW080A
M50FLW080B
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID3
GPI0-
GPI4
VPP
M50FLW080A, M50FLW080B Summary description
9/64
Figure 2. Logic diagram (A/A Mux interface)
Table 2. Signal names (A/A Mux interface)
IC Interface Configuration
A0-A10 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
GOutput Enable
WWrite Enable
RC Row/ Co lu mn Ad dre ss Se le ct
RP Interf ace Reset
VCC Supply Voltage
VPP Optional Supply Voltage for Fast Program and Erase Operations
VSS Ground
NC Not Connected Internally
AI09230B
11
RC
DQ0-DQ7
VCC
M50FLW080A
M50FLW080B
IC
VSS
8
G
W
RP
A0-A10
VPP
Summary description M50FLW080A, M50FLW080B
10/64
Figure 3. PLCC connections
1. Pins 27 and 28 are not internally connected.
Figure 4. TSOP32 connections
AI09231C
GPI4
NC
FWH4/LFRAME
RFU
17
ID1/RFU
ID0/RFU
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
RFU
GPI1
TBL
ID3
ID2
GPI0
WP
9
CLK
VSS
1
RP
VCC
NC
GPI2
RFU
32
VPP
VCC
M50FLW080A
M50FLW080B
GPI3
IC (VIL)
RFU
INIT
NC
25
VSS
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A10
RC
RP
A8
VPP
VCC
A9
NC
W
VSS
VCC
NC
DQ7
IC (VIH)
G
NC
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
VSS
A/A Mux A/A Mux
A/A MuxA/A Mux
AI09701B
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
DQ7
G
NC
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1/RFU
FWH1/LAD1
FWH2/LAD2
GPI3
TBL ID2
GPI0
WP
NC
NC
RFU
GPI4
NC FWH4/LFRAME
RFU
FWH3/LAD3
VSS
RFU
RFU
CLK
RP
VPP
VCC M50FLW080A
M50FLW080B
8
1
9
16 17
24
25
32
ID3
VSS
INIT
IC
NC
GPI2 FWH0/LAD0
GPI1 ID0/RFU
NC
NC
IC (VIH)
NC
NC
RC
RP
VPP
VCC
A10
VSS
M50FLW080A, M50FLW080B Summary description
11/64
Figure 5. TSOP40 connections
Table 3. Addresses (M50FLW080A)
Block Size (KByte) Address Range Sector Size (KByte)
64 F0000h-FFFFFh 16 x 4 KBytes
64 E0000h-EFFFFh 16 x 4 KBytes
64 D0000h-DFFFFh
13 x 64 KBytes
64 C0000h-CFFFFh
64 B0000h-BFFFFh
64 A0000h-AFFFFh
64 90000h-9FFFFh
64 80000h-8FFFFh
64 70000h-7FFFFh
64 60000h-6FFFFh
64 50000h-5FFFFh
64 40000h-4FFFFh
64 30000h-3FFFFh
64 20000h-2FFFFh
64 10000h-1FFFFh
64 00000h-0FFFFh 16 x 4 KBytes
AI09232C
A1
A0
DQ0
A7
A4 A3
A2
A6
A5
A9
A8
W
VSS
VCC
DQ7
G
NC
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A/A Mux
A/A Mux
ID1/RFU
FWH1/LAD1
FWH2/LAD2
GPI3
TBL ID2
GPI0
WP
NC
VCC
NC
IC (VIL)
RFU
GPI4
NC
VSS
FWH4/LFRAME
RFU
FWH3/LAD3
VSS
VCC
RFU
RFU
NC
CLK
RP
NC
VPP
VCC
NC
M50FLW080A
M50FLW080B
10
1
11
20 21
30
31
40
ID3
NC INIT
NC NC
GPI2 FWH0/LAD0
GPI1 ID0/RFU
VSS
NC
NC
NC
IC (VIH)
NC
NC
NC
NC
RC
RP
VPP
VCC
NC
A10
VSS
VSS
VCC
Summary description M50FLW080A, M50FLW080B
12/64
Table 4. Addresses (M50FLW080B)(1)
1. Also see Appendix A, Table 34 and Table 35 for a full listing of the Block Addresses.
Block size (KByte) Address range Sector size (KByte)
64 F0000h-FFFFFh 16 x 4 KBytes
64 E0000h-EFFFFh
13 x 64 KBytes
64 D0000h-DFFFFh
64 C0000h-CFFFFh
64 B0000h-BFFFFh
64 A0000h-AFFFFh
64 90000h-9FFFFh
64 80000h-8FFFFh
64 70000h-7FFFFh
64 60000h- 6FFFFh
64 50000h- 5FFFFh
64 40000h- 4FFFFh
64 30000h-3FFFFh
64 20000h-2FFFFh
64 10000h-1FFFFh 16 x 4 KBytes
64 00000h-0FFFFh 16 x 4 KBytes
M50FLW080A, M50FLW080B Signal descriptions
13/64
2 Signal descriptions
There are tw o distinct bus int erf aces av ailable on this de vice. The active inte rf ace is selected
before power-up, or during Rese t, using the Interface Configuration Pin, IC.
The signals f or each in terf ace are discu ssed in the Firmware Hub/lo w-pin-count (FWH/LPC)
signal descriptions section and the Address/Address multiplexed (A/A Mux) signal
descriptions section, respectively, while the supply signals are discussed in the Supply
signal descriptions section.
2.1 Firmware Hub/low-pin-count (FWH/LPC) signal descriptions
Please see Figure 1 and Table 1.
2.1.1 Input/Output communications (FWH0/LAD0-FWH3/LAD3)
All Input and Outp ut Communications wit h the memory take place on the se pins. Addresses
and Data for Bus Read and Bus Write operations ar e encoded on these pins.
2.1.2 Input communication frame (FWH4/LFRAME)
The Input Communication Frame (FWH4/LFRAME) signal indicates the start of a bus
operat ion. Whe n In pu t Comm u nicat ion Frame is Low, VIL, on the rising edge of th e Clock, a
new bus operation is initiated. If I nput Communication Fr ame is Low, VIL, during a bus
operat ion then the oper ation is abo rted. When Input Comm unication Frame is High, VIH, the
current bus operation is either proceeding or the bus is idle.
2.1.3 Identification inputs (ID0-ID3)
Up to 16 memories can be addressed on a bus, in the Firmware Hub (FWH) mode. The
Identification Inputs allow each device to be given a unique 4-bit address. A ‘0’ is signified
on a pin by driving it Low, VIL, or leaving it floating (since there is an internal pull-down
resistor, with a value of RIL). A ‘1’ is signified on a pin by driving it High, VIH (and there will
be a leakage current of ILI2 th ro ug h the pin ).
By con v ention , the boot m emory must have add ress ‘0000’, an d all additional me mories are
given addresses, allocated sequentially, from ‘0001’.
In the Low Pin Count (LPC) mode, the identification Inputs (ID2-ID3) can address up to 4
memories on a b us . I n th e LPC mode , the ID 0 and ID1 signa ls are Reserved for Futu re Use
(RFU). The value on address A20-A21 is compared to the hardware strapping on the ID2-
ID3 lines to select the memory that is being addressed. For an address bit to be ‘1’, the
corresponding ID pin can be left floating or driven Low, VIL (again, with the internal pull-
down resistor, with a value of RIL). For an address bit to be ‘0’, the corr esponding ID pin
must be driven High, VIH (and there will be a leakage current of ILI2 through the pin, as
specified in Table 24). For details, see Table 5.
Signal descriptions M50FLW080A, M50FLW080B
14/64
2.1.4 General-purpose inputs (GPI0-GPI4)
The General Purpose Inputs can be used as digital inputs for the CPU to read, with their
contents being a vai lab l e in the Gener al Purpose Inputs Regist er. The pins must have st able
data throughout the entire cycle that reads the Gen eral Purpose Input Register. These pins
should be driven Low, VIL, or High, VIH, and must not be left floating.
2.1.5 Interface configuration (IC)
The Interface Configuration input selects whether t he FWH/LPC interface or the
Address/Address Multiple xed (A/A Mux) Interface is used. The state of the Interface
Configura tion, I C, sh ould no t be changed d uring oper ation o f th e memory de vice , excep t for
selecting the desir ed interface in the period before power-up or during a Reset.
To select the FWH/LPC Interface , the Interface Configuration pin should be left to float or
driven Low, VIL. To select the Address/Address Multiplexed (A/A Mux) Interface, t he pin
should be driven High, VIH. An internal pull-down resistor is included with a value of RIL;
there will be a leakage current of ILI2 through each pin when pulled to VIH.
2.1.6 Interface Reset (RP)
The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is
driven Low, VIL, the memory is in Reset mode (the outputs go to high impedance, and the
current consumption is minimized). When RP is driven High, VIH, t he device is in normal
operation. After exiting Reset mode, the memory enters Read mode.
2.1.7 CPU Reset (INIT)
The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It beh aves
identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
2.1.8 Clock (CLK)
The Clock, CLK, input is used to clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI
specification.
2.1.9 Top Block Lock (TBL)
The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed.
When Top Block Lock, TBL, is driven Low, VIL, program and erase operations in the Top
Block have no effect, regardless of the state of the Loc k Register. When Top Block Lock,
TBL, is driven High, VIH, the protection of the Block is determined by the Lock Registers.
The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks
0 to 14). For details, see Appendix A.
Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and
must not be changed until the operation has completed, otherwise unpredictable results
ma y occur. Similarly, unpredict ab le behavior is possib le if WP is changed during Prog ram o r
Erase Suspend, and care should be taken to avoid this.
M50FLW080A, M50FLW080B Signal descriptions
15/64
2.1.10 Write Protect (WP)
The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 14) from being
changed. When Write Protect, WP, is driven Low, VIL, Program and Erase operatio ns in the
Main Blocks have no effect, regardless of the state of the Lock Register. When Write
Protect, WP, is driven High, VIH, the pr otection of the Block or Sector is determined by the
Lock Registers. The state of Write Protect, WP, does not affect the protection of the Top
Block (Block 15). For details, see Appendix A.
Write Protect, WP, must be set prior to a Progr am or Erase operation is initiated, and must
not be changed until the operation has completed otherwise unpredictable results may
occur. Similarly, unpredictable behavior is possible if WP is changed during Program or
Erase Suspend, and care should be taken to avoid this.
2.1.11 Reserved for Future Use (RFU)
Reserved f or Future Use ( RFU). These pins do not present ly ha v e assigned function s. The y
must be left disconnected, except for ID0 and ID1 (when in LPC mode) which can be left
connected. The electrical characteristics for these signals are as described in the
“Identification inputs (ID0-ID3)” section.
2.2 Address/Address multiplexed (A/A Mux) signal descriptions
Please see Figure 2 and Table 2.
2.2.1 Address inputs (A0-A10)
The Address Inputs are used to set the Row Address bits (A0-A10) and the Column
Address bits (A11-A19). They are latched during any bus operation by the Row/Column
Address Select input, RC.
2.2.2 Data inputs/outputs (DQ0-DQ7)
The Data Inputs/Outputs hold the data that is to be written to or read from the memory. They
output the data stored at the selected address during a Bus Read operation. During Bus
Write operations they carry the commands that are sent to the Command Interface of the
internal state machine. T he Da ta Inp uts/Ou tput s, DQ0-DQ7, are la tch ed during a Bus Write
operation.
2.2.3 Output Enable (G)
The Output Enable signal, G, controls the output buffers during a Bus Read operation.
2.2.4 Write Enable (W)
The Write Enable signal, W, controls the Bus Write operation of the Command Interface.
2.2.5 Row/Column Address Select (RC)
The Row/ Column Address Select input selects whether the Address Inputs are to be latched
into the Row Address bits (A0-A10) or the Column Address bits (A11-A19). The Row
Address bits are latched on the falling edge of RC whereas the Column Address bits are
latched on its rising edge.
Signal descriptions M50FLW080A, M50FLW080B
16/64
2.3 Supply signal descriptions
The Supply Signals are the same for both interfaces.
2.3.1 VCC supply voltage
The VCC Supply Voltage supplies the power for all operations (read, program, erase, etc.).
The Command Interface is disa bled when the VCC Supply Voltage is less than the Lockout
Voltage, VLKO. This is to prevent Bus Write operations from accidentally damaging the data
during pow er up, power down and power sur ges. If the Program/Erase Controller is
programming or erasing during this time, the operation aborts, and the memory contents
that were being altered will be in valid. After VCC becomes valid, the Command Interface is
reset to Read mode.
A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS
Ground pin to deco uple the curr ent su rges fr om th e po w er supply. Both VCC Supply Voltage
pins must be connected to the power supply. The PCB track widths must be sufficient to
carry the currents required during program and erase operations .
2.3.2 VPP optional supply voltage
The VPP Optional Supp ly Voltage pin is used to select the Fast Progr am (see the Quadruple
Byte Program command description in A/A Mux interface and the Double/Quadruple Byte
Program command description in FWH mode) and Fast Erase options of the memory.
When VPP = VCC, program and erase operations take place as normal. When VPP = VPPH,
Fast Program and Erase operations are used. Any other voltage input to VPP will result in
undefined be h avior, and should not be used.
VPP should not be set to VPPH for more than 80 hours during the life of the memory.
2.3.3 VSS ground
VSS is the reference for all the voltage measurements.
Table 5. Memory identification input configuration (LPC mode)
Memory Number ID3 ID2 A21 A20
1 (Boot memory) VIL or float VIL or float 1 1
2V
IL or float VIH 10
3V
IH VIL or float 0 1
4V
IH VIH 00
M50FLW080A, M50FLW080B Bus operations
17/64
3 Bus operations
The two interfaces, A/A Mux and FWH/LPC, support similar operations, but with diffe rent
bus signals and timing s. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full
functionality, while the Address/Addr ess Mult iplexed (A/A Mux) Interface is orientated for
erase and progr am operat ions.
See the sections below, The Firmware Hub/low-pin-count (FWH/ LPC) bus operations and
Address/Address m ultiplexed (A/A Mux) bus operations, for details of t he bus oper a tions on
each interface.
3.1 Firmware Hub/low-pin-count (FWH/LPC) bus operations
The M50FLW080 automatically identifies the type of FWH/LPC protocol from the first
received nibble (START nibble ) and decodes the data that it receives afterwards, according
to the chosen FWH or LPC mode. The Firmware Hub/Low Pin Count (FWH/LPC) Interface
consists of four data sign als (FWH0/LAD0- FWH3/LAD3 ), one co ntro l line (FWH4/L FRAME )
and a cloc k (CLK).
Protection against accidental or malicious data corruption is achieved using two additional
signals (TBL and WP ). And tw o reset sign als (RP and INIT) are a vailable to put the memo ry
into a known state.
The data, control and clock signals are designed to be compatible with PCI electrical
specifications. The interface operates with clock spe eds of up to 33MHz.
The f ollowing oper ations can be perf ormed using the ap propriate bus cycles: Bus Re ad, Bus
Write, Standby, Reset and Block Protection.
3.1.1 Bus Read
Bus Read operations are used to read from the memory cells, specific registers in the
Command Interface or Firmware Hub/ Low Pin Coun t Register s . A v alid Bus Read oper ation
starts on the rising edge of th e Clock signal when the Input Communication Frame,
FWH4/LFRAME, is Low, VIL, and the correct Start cycle is present on FWH0/LAD0-
FWH3/LAD3. On subsequent clock cycles the Host will send to the memory:
●ID Select, Address and other control bits on FWH0-FWH3 in FWH mode.
●Type+Dir Address and other control bits on LAD0-LAD3 in LPC mode.
The device resp onds by out putting Sync dat a until the w ait states h av e e lapsed, follo w ed b y
Data0-Data3 and Data4-Data7.
See Table 6 and Table 8, and Figure 6 and Figure 8, f or a description of the Field defi nitions
f or each clock cycle of the transfer . See Table 26, and Figure 14, f or details on the timings of
the signals.
Bus operations M50FLW080A, M50FLW080B
18/64
3.1.2 Bus Write
Bus Write operations are used to write to the Command I nterface or Firmware Hub/ Lo w Pin
Count Registers. A valid Bus Write operation starts on the rising edge of th e Clock signal
when Input Comm unicat ion Frame, FWH4/L FRAME, is Lo w, VIL, and t he corr ect St art cycle
is present on FWH0/LAD0-FWH3/LAD3. On subsequent Clock cycles the Host will send to
the memory:
●ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0-FWH3
in FWH mode.
●Cycle Type + Dir, Address, other control bits, Data0 -Data3 and Data4-Data7 on LAD0-
LAD3.
The device responds by outputting Sync data un til the wait states have elapsed.
See Table 7 and Table 9, and Figure 7 and Figure 9, f or a description of the Field defi nitions
f or each clock cycle of the transfer . See Table 26, and Figure 14, f or details on the timings of
the signals.
3.1.3 Bus Abort
The Bus Abort opera tion can be used to abort the current bu s opera tion immediat ely. A Bus
Abort occurs when FWH4/LFRAME is driven Low, VIL, during the bus oper ation. The device
puts the Input/Output Communication pins, FWH0/LAD0-FWH3/LAD3, to high impedance.
Note that, during a Bus Write operation, the Command Interface starts executing the
command as soon as the data is fully received. A Bus Abort during the f inal TAR cycles is
not guaranteed to abort the command. The bus, how ever, will be released immediately.
3.1.4 Standby
When FWH4/LFRAME is High, VIH, the device is put into Standby mode, where
FWH0/LAD0-FWH3/LAD3 are put int o a high-impedance state and the Supply Current is
reduced to the Standby level, ICC1.
3.1.5 Reset
During the Reset mode, all internal circuits are switched off, the device is desele cted, and
the outputs are put to high-impedance. The device is in the Reset mode when Interface
Reset, RP, or CPU Reset, INIT, is driven Low, VIL. RP or INIT must be held Low, VIL, for
tPLPH. The memory reverts to the Read mode upon return from the Reset mode, and the
Lock Registers return to their default stat es regardles s of their states before Reset. If RP or
INIT goes Low, VIL, during a Program or Erase opera tion, the operation is aborted and the
affected memory cells no longer contain valid data. The device can take up to tPLRH to abort
a Program or Erase operation.
3.1.6 Block Protection
Block Protection can be forced using the signals Top Block Loc k, TBL, and Write Protect ,
WP, regardless of the state of the Lock Registers.
M50FLW080A, M50FLW080B Bus operations
19/64
3.2 Address/Address multiplexed (A/A Mux) bus operations
The Address/Address Mult iple xed (A/A Mux) Interface has a more traditional-style inte rf ace .
The signals consist of a m ultiplex ed address sig nals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional signal, RP, can be used to reset th e mem ory.
The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash
Programming equipment for faster factory programming. Only a subset of the features
available to the Firmware Hub (FWH)/Low Pin Count (LPC) Interface are available; these
include all the Commands but exclude the Security features and other registers.
The f ollowing oper ations can be perf ormed using the ap propriate bus cycles: Bus Re ad, Bus
Write, Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux) Interface is selected, all the blocks are
unprotected. It is not possible to protect any blocks through this interface.
3.2.1 Bus Read
Bus Read operations are used to read the contents of the Memory Array, the Electronic
Signature or th e Status Register. A valid Bus Read operation begins by latching the Row
Address and Column Address signals into the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Write Enable (W) and Interface Reset (RP) must
be High, VIH, and Output Enable , G, Low, VIL. The Data Inputs/Outputs will output the value,
according to the timing constraints specified in Figure 16, and Table 28.
3.2.2 Bus Write
Bus Write operations are used to write to the Command Interface. A valid Bus Write
operat ion begins by latching the Row Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The
data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset,
RP, must be High, VIH; and Write Enable , W, must be Low, VIL. The Data Inputs/Outputs are
latched on th e rising edge of Write Enab le, W. See Figure 17, and Table 29, f or details of the
timing requirements.
3.2.3 Output Disable
The data outpu ts are high-impedance when the Output Enable, G, is at VIH.
3.2.4 Reset
During the Reset mode, all internal circuits are switched off, the device is desele cted, and
the outputs are put at high-impedance. The device is in the Reset mode when RP is Low,
VIL. RP must be held Low, VIL for tPLPH. If RP goes Lo w, VIL, during a Program or Erase
operation, the oper ation is aborted, and the affected memory cells no longer contain valid
data. The memory can take up to tPLRH to abort a Program or Erase oper ation.
Bus operations M50FLW080A, M50FLW080B
20/64
Figure 6. FWH Bus Read waveforms
Tabl e 6. FWH Bus Read field definitions
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the contents of FWH0-
FWH3 indicate the start of a FWH Read cycle.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
3-9 7 ADDR XXXX I
A 28-bit address is transferred, with the most significant nibble
first. For the multi-byte read operation, the least significant bits
(MSIZE of them) are treated as Don't Care, and the read operation
is started with each of these bits reset to 0. Address lines A20-21
and A23-27 are treated as Don’t Care during a normal memory
arra y access , with A22=1, but are taken into account f or a register
access, with A22=0. (See Table 15)
10 1 MSIZE XXXX I
This one clock cycle is driven by the host to determine the number
of Bytes that will be transferred. M50FLW080 supports: single
Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer
(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).
11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
12 1 TAR 1111b
(float) OThe FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
13-14 2 WSYNC 0101b O The FWH Flash Memory driv es FWH0-FWH3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not yet
available. Two wait-states are always included.
15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b , indicating
that data will be available during the next clock cycle.
16-17 M=2n DATA XXXX O Data transfer is two CLK cycles, starting with the least significant
nibble . If multi-Byte read operation is enabled, repeat cycle-16 and
cycle-17 n times, where n = 2MSIZE.
previous
+1 1 TAR 1111b O The FWH Flash Memory driv es FWH0-FWH3 to 1111b to indicate
a tur naround cycle.
previous
+1 1TAR
1111b
(float) N/A The FWH Flash Memory floats its outputs, the host takes control
of FWH0-FWH3.
AI08433B
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE TAR SYNC DATA TAR
117123M2
M50FLW080A, M50FLW080B Bus operations
21/64
Figure 7. FWH Bus Write waveforms
Table 7. FWH Bus Write field definitions
Clock
Cycle
Number
Clock
Cycle
Count Field FWH0-
FWH3 Memory
I/O Description
1 1 START 1110b I On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
2 1 IDSEL XXXX I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash Memory
is being addressed.
3-9 7 ADDR XXXX I
A 28-bit address is transferred, with the most significant
nibble first. Address lines A20-21 and A23-27 are treated as
Don’t Care during a normal memory array access, with
A22=1, but are taken into account for a register access, with
A22=0. (See Table 15)
10 1 MSIZE XXXX I 0000(Sin gle Byte Transfer) 0001 (Double Byte Transfer)
0010b (Quadruple Byte Transfer).
11-18 M=2/4/8 DATA XXXX I
Data transfer is two cycles, starting with the least significant
nibble. (The first pair of nibbles is that at the address with A1-
A0 set to 00, the second pair with A1-A0 set to 01, the third
pair with A1-A0 set to 10, and the fourth pair with A1-A0 set
to 11. In Double Byte Program the first pair of nibbles is that
at the address with A0 set to 0, the second pair with A0 set to
1)
previous +1 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a
tur naround cycle.
previous +1 1 TAR 1111b
(float) OThe FWH Flash Memory takes control of FWH0-FWH3 during
this cycle.
previous +1 1 SYNC 0000b O The FWH Flas h Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
previous +1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
previous +1 1 TAR 1111b
(float) N/A The FWH Flash Memory floats its outputs and the host takes
control of FWH 0 -FW H 3.
AI08434B
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START IDSEL ADDR MSIZE DATA TAR SYNC TAR
1171M212
Bus operations M50FLW080A, M50FLW080B
22/64
Figure 8. LPC Bus Read waveforms (1-byte)
Table 8. LPC Bus Read field definitions (1-byte)
Clock
Cycle
Number
Clock
Cycle
Count Field LAD0-
LAD3 Memory
I/O Description
1 1 START 0000b I On the rising edge of CLK with LFRAME Low ,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
21
CYCTYPE
+ DIR 0100b I
Indicates the type of cycle and selects 1-byte
reading. Bits 3:2 must be 01b. Bit 1 indicates
the direction of transfer: 0b fo r read. Bit 0 is
Don’t Care.
3-10 8 ADDR XXXX I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set
to 1. A22=1 for memory access, and A22=0
for register access. Table 5 shows the
appropriate values for A21-A20.
11 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
12 1 TAR 1111b
(float) OThe LPC Flash Memory takes control of
LAD0-LAD3 during this cycle.
13-14 2 WSYNC 0101b O
The LPC Flash Memory drives LAD0-LAD3
to 0101b (short wait-sync) for two clock
cycles, indicating that the data is not yet
available. Two wait-states are always
included.
15 1 RSYNC 0000b O The LPC Flash Memory drives LAD0-LAD3
to 0000b , indicating that data will be av ailable
during the next clock cycle.
16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with
the least significant nibble.
18 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3
to 1111b to indicate a turnaround cycle.
19 1 TAR 1111b
(float) N/A The LPC Flash Memory floats its outputs, the
host takes control of LAD0-LAD3.
AI04429
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START CYCTYPE
+ DIR ADDR TAR SYNC DATA TAR
1182322
M50FLW080A, M50FLW080B Bus operations
23/64
Figure 9. LPC Bus Write waveforms (1 b yte)
Table 9. LPC Bus Write field definitions (1 byte)
Clock
Cycle
Number
Clock
Cycle
Count Field LAD0-
LAD3 Memory
I/O Description
1 1 START 0000b I On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
21
CYCTYPE
+ DIR 011Xb I Indicates the type of cycle. Bits 3:2 must be
01b. Bit 1 indicates the direction of transfer: 1b
for write. Bit 0 is don’t care (X).
3-10 8 ADDR XXXX I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to
1. A22=1 for memory access, and A22=0 for
register access. Table 5 shows the appropriate
values for A21-A20.
11-12 2 DATA XXXX I Data transfer is two cycles, star ting with the
least significant nibble.
13 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
14 1 TAR 1111b
(float) OThe LPC Flash Memory takes control of LAD0-
LAD3 during this cycle.
15 1 SYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to
0000b, indicating it has received data or a
command.
16 1 TAR 1111b O The LPC Flash Me mory drives LAD0-LAD3 to
1111b, indicating a turnaround cycle.
17 1 TAR 1111b
(float) N/A The LPC Flash Memory floats its outputs and
the host takes control of LAD0-LAD3.
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START CYCTYPE
+ DIR ADDR DATA TAR SYNC TAR
1182212
Bus operations M50FLW080A, M50FLW080B
24/64
Tabl e 10. A/A Mux bus oper ations
Operation G WRP VPP DQ7-DQ0
Bus Read VIL VIH VIH Don't Care Data Output
Bus Write VIH VIL VIH VCC or VPPH Data Input
Output Disable VIH VIH VIH Don't Care Hi-Z
Reset VIL or VIH VIL or VIH VIL Don't Care Hi-Z
M50FLW080A, M50 FLW080B Command interface
25/64
4 Command interface
All Bus Write operations to the device are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings, and verifies the correct execution of the
Program and Eras e commands. The Program/Erase Controller provides a Status Register
whose output ma y be read at any time to monitor the progress or the result of the operation.
The Command Interface reverts to the Read mode when power is first applie d, or when
e xiting from Reset. Command sequences must be f ollowed exactly. An y in valid comb ination
of commands will be ignored. See Table 11 for the available Command Codes.
The f ollowing command s are the basic commands used to re ad from, write to , and configure
the device. The following text descriptions should be read in conjunction with Table 13.
4.1 Read Memory Array command
The Read Memory Array command returns the device to its Read mode, where it behaves
like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array
command and return the device to Read mode. Once the command is issued, the device
remains in Read mode until another command is issued. From Read mode, Bus Read
operations access the memory array.
If the Program/Erase Controller is executing a Program or Erase operation, the device will
not accept any Read Memory Array commands until the operation has completed.
For a multibyte read, in the FWH mode, the address, that w as transmitted with the
command, will be automatically aligned, according to the MSIZE granularity. For example, if
MSIZE=7, regardless of any values that are provided for A6-A0, the first output will be from
the location for which A6-A0 are all ‘0’s.
Table 11. Command codes
Hexa-decimal Command
10h Alternative Program Setup, Double/Quadruple Byte Program Setup, Chip
Erase Confirm
20h Block Erase Setup
32h Sector Erase Setup
40h Program, Double/Quadruple Byte Program Setup
50h Clear Status Register
70h Read Status Register
80h Chip Erase Setup
90h Read Electronic Signature
B0h Program/Erase Suspend
D0h Program/Erase Resume, Block Erase Confirm, Sector Erase Confirm
FFh Read Memor y Array
Command interface M50FLW080A, M50FLW080B
26/64
4.2 Read Status Register command
The Read Status Register command is used to read the Status Register. One Bus Write
cycle is required to issue the Read Status Register command. On ce the command is issued,
subsequent Bus Read operations re ad the Status Register until another command is issued .
See the section on the Status Register for det ails on the definitions of the Status Register
bits.
4.3 Read Electronic Signature command
The Read Electronic Signature command is used to read the Manufacturer Code and the
Device Code. One Bus Write cycle is required to issue the Read Electronic Signature
command. Once the command is issued, the Man ufacturer Code and Device Code can be
read using conventional Bus Read operations, and the addresses shown in Table 12.
The device remain s in this m ode until an ot her comm and is issue d. Tha t is, subsequent Bus
Read opera tions continue to read the Manufact urer Code, or the Device Code, and not the
Memory Array.
4.4 Program command
The Prog ram command can be used to prog ram a v alue to one address in the memory arra y
at a time.
The Progr am command works b y changing appropriate bits fr om ‘1’ to ‘0’. ( It cannot chan ge
a bit from ‘0’ back to ‘1’. Attempting to do so will not modify the value of the bit. Only the
Erase command can set bits back to ‘1’. and does so for all of the bi ts in the b lock.)
Two Bus Write operations are required to issue the Program command. The second Bus
Write cycle latches the address and data, and starts the Program/Erase Controller.
Once the comman d is issued, subse quent Bus Read o perations r ead the v alue in the Status
Register. (See the section on the Status Register for details on the definitions of the Status
Register bits.)
If the address falls in a protected block, the Program operation will abort, the data in the
memor y array will not be changed, and the Status Register will indicate the error.
During the Program operation, the memory will only accept the Read Status Register
command and the Program/Erase Suspend command. All other commands are ignored.
See Figure 21, for a suggested flowchart on using the Program command. Typical Program
times are given in Table 18.
Table 12. Electronic Signature Codes
Code Address(1)
1. A22 should be ‘1’, and the ID lines and upper address bits should be set according to the rules illustrated in
Table 5, Table 6 and Table 8.
Data
Manufacturer Code ...00000h 20h
Device Code M50FLW080A
M50FLW080B ...00001h 80h
81h
M50FLW080A, M50 FLW080B Command interface
27/64
4.5 Quadruple Byte Program command (A/A Mux interface)
The Quadruple Byte Program Command is used to program four adjacent Bytes in the
memory array at a time. The four Bytes must differ only fo r addresses A0 and A1.
Programming should not be attempted when V PP is not at VPPH.
Fiv e Bus Write oper ati o ns are req uired t o issu e the comma nd . The se co nd , thir d and fo urth
Bus Write cycles latch the respectiv e addresses and dat a of the first, second and third Bytes
in the Program/Erase Controller. The fifth Bus Write cycle latches the address and data of
the fourth Byte and starts the Program/Erase Controller. Once the command is issued,
subsequent Bus Read o per ations re ad the value in th e Status Register. (See the section on
the Status Register for details on the definitions of the Status Register bits.)
During the Quadruple Byte Progr am operation, the memory will only accept the Read Status
Register and Program/Erase Suspend commands. All other commands are ignored.
Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’
and attempting to do so will not modify its value. One of the erase commands must be used
to set all of the bits in the block to ‘1’.
See Figure 23, for a suggested flowchart on usin g the Quadruple Byte Program command.
Typical Quadruple Byte Program times are given in Table 18.
4.6 Double/Quadruple Byte Program command (FWH mode)
The Double/Quadruple Byte Program Command can be used to pr ogra m two/four adjacent
Bytes to the memory arra y at a time . The tw o Byt es must d iffer only for address A0; the four
Bytes must differ only for addresses A0 and A1.
Two Bus Write oper ations are required to issue the command. The second Bus Write cycle
latches the start address and two/four data Bytes and starts the Program/Erase Controller.
Once the command is issued, subsequent Bus Read operations read the contents of the
Status Register. (See the section on the Status Register for details on the definitions of the
Status Register bi ts.)
During the Double/Quadruple Byte Program operation the memory will only accept the Read
Status register and Program/Erase Suspend commands. All other commands are ignored.
Note that the Dou ble /Quadruple Byte Progr am comma nd cannot change a bit set to ‘0’ bac k
to ‘1’ and attempting to do so will not modify its value. One of the erase commands must be
used to set all of the bits in the block to ‘1’.
See Figure 22, for a suggested flowchart on using the Double/Quadruple Byte Program
command. Typical Double/Quadruple Byte Program times are given in Table 18.
Command interface M50FLW080A, M50FLW080B
28/64
4.7 Chip Erase command
The Chip Erase Command erases the entire memory array, setting all of the bits to ‘1’. All
previous data in the memory array are lost. This command, though, is only available under
the A/A Mux interface.
Two Bus Write operations are required to issue the command, and to start the
Program/Erase Controller. Once the command is issued, subsequent Bus Read operations
read the contents of the Status Register. (See the section on the Status Register for details
on the definitions of the Status Register bits.)
Erasing should not be attempted when V PP is not at VPPH, otherwise the result is uncertain.
During the Chip Erase operation, the memory will only accept the Read Status Register
command. All other commands are ignored.
See Figure 25, for a suggested flowchart on using the Chip Erase command. Typical Chip
Erase times are given in Table 18.
4.8 Block Erase command
The Block Erase comm and is used to erase a block, setting all of the bits to ‘1’. All previous
data in the block are lost.
Two Bus Write oper ations are required to issue the command. The second Bus Write cycle
latches the block address and starts the Program/Erase Controller. Once the command is
issued, subsequent Bus Read operat ions read the con tents of the Sta tus Register. (See the
section on the Status Register for details on the definitions of the Status Register bits.)
If the block, or if at least one sector of the b lock (for the blocks that are split into sectors), is
protected (FWH/LPC only) then the Block Erase operation will abort, the data in the block
will not be changed, and the Status Register will indicate the error.
During the Block Erase operation the memory will only accept the Read Status Register and
Program/Erase Suspend commands. All other command s are ignored.
See Figure 26, for a suggeste d flo wchart on using the Block Eras e command. Typical Block
Erase times are given in Table 18.
4.9 Sector Erase command
The Sector Er ase command is used to erase a Unif orm 4-KByte Sector, setting all of the bits
to ‘1’. All previous data in the sector are lost.
Two Bus Write oper ations are required to issue the command. The second Bus Write cycle
latches the Sector address and starts the Program/Erase Controller. Once the command is
issued, subsequent Bus Read operat ions read the con tents of the Sta tus Register. (See the
section on the Status Register for details on the definitions of the Status Register bits.)
If the Sector is protected (FWH/LPC only), the Sector Erase operation will abort, the data in
the Sector will not be changed, and the Status Register will indicate the error.
During the Sector Erase operation the memory will only accept the Read Status Register
and Program/Erase Suspend commands. All other commands are ignored.
See Figure 26, for a suggested flowchart on using the Sector Erase Command. Typical
Sector Erase times are given in Table 18.
M50FLW080A, M50 FLW080B Command interface
29/64
4.10 Clear Status Register command
The Clear St atus Register command is used to reset Status Register bits SR1, SR3, SR4
and SR5 to ‘0’. One Bus Write is required to issue the command. Once the comm and is
issued, the device returns to its previous mode, subsequent Bus Read operations continue
to output the data from the same area, as before .
Once set, these Status Regist er bits remain set. They do not automatically return to ‘0’, for
example, when a new program or erase command is issued. If an error has occurred, it is
essential that any error bits in the Status Register are cleared, by issuing the Clear Status
Register command, before attempting a new program or erase command.
4.11 Program/Erase Suspend command
The Program/Era se Suspend command is used to pause the Program/Erase Controller
during a progr am or Se cto r/Block Erase oper ation . One Bus Write cycle is require d to issue
the command.
Once the command has been issued, it is necessary to poll the Program/ Erase Controller
Status bit unt il the Progr am/Erase Cont roller has pause d. No other com mands are accepted
until the Program/Erase Controller has paused. After the Program/Erase Controller has
paused, the device continues to output the contents of the Status Register until another
command is issued.
During the polling period, between issuing the Program/Erase Suspend command and the
Program/Erase Controller pausing, it is possible for the operation to complete. Once the
Progr am/Erase Co ntroller Status bit indicates that the Program/Er ase Controller is no longer
active, the Program Suspend Status bi t or the Erase Suspend Status bit can be used to
determine if the operation has completed or is suspended.
During Program/Erase Suspend, the Read Memory Array, Read Status Register, Read
Electronic Signature and Program/Erase Resume commands will be accepted by the
Command Interface. Additionally, if the suspended operation was Sector Erase or Block
Erase then the program command will also be accepted. However, it should be noted that
only the Sectors/Blocks not being erased may be read or programmed correctly.
See Figure 24, and Figure 27, for suggested flowcharts on using the Program/Erase
Suspend command. Typical times and delay durations are given in Table 18.
4.12 Program/Erase Resume command
The Progr am/Erase Resume co mmand can be used to restart the Progra m/Erase Controller
after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the
command. Once the command is issued, subsequent Bus Read operations r ead the
contents of the Stat us Register.
Command interface M50FLW080A, M50FLW080B
30/64
Table 13. Commands
Command
Cycle
Bus operations(1)
1st 2nd 3rd 4th 5th
Addr Data Addr Data Addr Data Addr Data Addr Data
Read Memory Array(2),(3),(4) 1+ X FFh Read
Addr Read
Data (Read
Addr2) (Read
Data2) (Read
Addr3) (Read
Data3) (Read
Addr4) (Read
Data4)
Read Status Register(5),(3) 1+ X 70h X Status
Reg (X) (Status
Reg) (X) (Status
Reg) (X) (Status
Reg)
Read Electronic Signature(3) 1+ X 90h or
98h Sig
Addr Signat
ure (Sig
Addr) (Signat
ure) (Sig
Addr) (Signatu
re) (Sig
Addr) (Signat
ure)
Progr am / Multiple Byte
program (FWH)(6),(7),(4) 2X
40h or
10h Prog
Addr Prog
Data
Quadrup l e Byte Program
(A/A Mux)(6),(8) 5X30hA1Prog
Data1 A2 Prog
Data2 A3 Prog
Data3 A4 Prog
Data4
Chip Erase(6) 2 X 80h X 10h
Block Erase(6) 2X20hBAD0h
Sector Erase(6) 2X32hSAD0h
Clear Status Register(9) 1X50h
Program/Erase suspend(10) 1XB0h
Program/Erase resume(11) 1XD0h
Invalid reserved(12)
1X00h
1X01h
1X60h
1X2Fh
1XC0h
1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read
Electronic Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles
are WRITE.
BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC
mode), and A21 and A20 are set according to the rules shown in Table 5 (for LPC mode)
2. After a Read Memory Array command, read the memory as normal until another command is issued.
3. “1+” indicates that there is one write cycle, followed by any number of read cycles.
4. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read
Operation is all that is needed.
5. After a Read Status Register command, read the Status Register as normal until another command is issued.
6. After the erase and program commands read the Status Register until the command completes and another command is
issued.
7. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t
Care. PD is two or four Bytes depending on Msize code.
8. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.
9. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.
10. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during
Erase Suspend) and Program/Erase Resume commands can be issued.
11. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status
Register until the Program/Erase Controller completes and the memory returns to Read Mode.
12. Do not use Invalid or Reserved commands.
M50FLW080A, M50FLW080B Status Register
31/64
5 Status Register
The Status Register provides information on the current or previous Program or Erase
operat ion. The bits in the Status Regist er convey specific information about the progress of
the operation.
To read the St atus Reg iste r, the Read Sta tus Register com mand can b e issue d. Th e Stat u s
Register is automatically read after Program, Er ase and Program/Erase Resume
commands are issued. The Status Register can be read from any address.
The text descriptions, below, should be read in conjunction with Table 14, where the
meanings of the Status Register bits a re summarized.
5.1 Program/Erase Controller status (bit SR7)
Thi s bit indicates whether the Program/Erase Con troller is active or inactive. When the
Program/Erase Controller Status bit is ‘0’, the Program/Erase Controller is acti ve; when the
bit is ‘1’, the Program/Erase Controller is inactive.
The Program/Erase Controller Status is ‘0’ immediately after a Program/ Erase Suspend
command is issued, until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses, the bit is ‘1’.
The end of a Program and Erase operation can be found by polling the Program/Erase
Controller Status bit can be polled. The other bits in the Status Register should not be tested
until the Program/Erase Controller has completed the operation (and the Program/Erase
Controller Status bit is ‘1’).
After the Program/Erase Contro ller has completed its operation, the Erase Status, Program
Status, VPP Status and Block/Sector Protection Status bits should be tested for errors.
5.2 Erase Suspend status (bit SR6)
This bit indicates that an Erase operation has been suspended, and that it is waiting to be
resumed. The Erase Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is ‘1’ (Prog ram/Er ase Controller inactive). After a
Program/Erase Suspend command is issued, the memory may still complete the operation
rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’, the Program/Erase Controller is active or has
completed its operation. When the bit is ‘1’, a Program/Erase Suspend command has been
issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued, the Erase Suspend Status bit returns
to ‘0’.
Status Register M50FLW080A, M50FLW080B
32/64
5.3 Erase status (bit SR5)
This bit indicates if a problem has occurred during the erasing of a Sector or Block. The
Erase Statu s bit should be read once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Era se Stat us b it is ‘0’, t he memory has successfully verified that the Sector /Blo ck
has been erased correctly. When the Erase Status bit is ‘1’, the Program/Erase Controller
has applied the maximum number of pulses to the Sector/Block and still failed to verify that
the Sector/Block has been erased correctly.
Once the Erase Status bit is set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register
command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new command will appear to hav e failed, too.
5.4 Program status (bit SR4)
This bit indicates if a pr ob lem ha s occurre d during the progr a mming of a byte . The Prog ra m
Status bit should be read once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Program Status bit is ‘0’, the memory has successfully verified that the byte has
been programmed correctly. When the Program Status bit is ‘1’, the Program/Er ase
Controller has applied the maximum number of pulses to the byte and still failed to verify
that the byte has bee n programmed correctly.
Once the Program Status bit is set to ‘1’, it can only be reset to ‘0’ b y a Clear Stat us Register
command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new command will appear to hav e failed, too.
5.5 VPP status (bit SR3)
This bit indicates whether an inv a lid v oltage was de tected on the V PP pin at the beginning of
a Program or Erase operation. The VPP pin is only sampled at the beginning of the
operation. Indeterminate results can occur if VPP becomes invalid during a Program or
Erase operation.
Once the VPP Status bit set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register
command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new command will appear to hav e failed, too.
M50FLW080A, M50FLW080B Status Register
33/64
5.6 Program Suspend status (bit SR2)
This bit indicates that a Program operation has been suspended, and that it is waiting to be
resumed. The Program Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is ‘1’ (Prog ram/Er ase Controller inactive). After a
Program/Erase Suspend command is issued, the memory may still complete the operation
instead of ent ering the Suspend mode.
When the Program Suspend Status bit is ‘0’, the Program/Erase Controller is active, or has
completed its operation. When the bit is ‘1’, a Program/Erase Suspend command has been
issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued, the Program Suspend Status bit
returns to ‘0’.
5.7 Block/Sector Protection status (bit SR1)
The Block/Sector Protection Status bit can be used to identify if the Program or Erase
operation has tr ied to modify the conten ts of a pr ot ec te d block or sector. When the
Bloc k/Sector Protect ion Sta tus bit is re set to ‘0’, no Pro g r am or Er ase oper ation s have been
attempted on protected blocks or sectors since the last Clear Status Register comma nd or
hardware reset. When the Block/Sector Protection Status bit is ‘1’, a Program or Erase
operation has been attempted on a protected block or sector.
Once it is set to ‘1’, the Block/Sector Pr otect ion St atu s bi t ca n o nly be re set to ‘0’ by a Cle ar
Status Register command or by a hard ware rese t. If it is set to ‘1’, it should be r eset bef ore a
new Prog ram or Erase command is issued, otherwise the ne w command will appear to hav e
failed, too.
Using the A/A Mux Interface, the Block/Sector Protection Status bit is always ‘0’.
5.8 Reserved (bit SR0)
Bit 0 of the Status Register is reserved. Its value should be masked.
Status Register M50FLW080A, M50FLW080B
34/64
Table 14. Status Register bits
Operation SR7 SR6 SR5 SR4 SR3 SR2 SR1
Program active ‘0’ X(1)
1. For Program operations during Erase Suspend, the SR6 bit is ‘1’, otherwise the SR6 bit is ‘0’.
‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Program suspended ‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’
Program completed successfully ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘1’ ‘1’ ‘0’ ‘0’
Program failure due to Block/Sector Protection
(FWH/LPC Inte rface only) ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘1’
Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’
Erase activ e ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
Erase failure due to VPP Error ‘1’ ‘0’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’
Erase failure due to Bloc k/Sector Protection
(FWH/LPC Inte rface only) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’
Erase failure due to failed cell(s) in block or sector ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’
M50FLW080A, M50FLW080B Firmware Hub/low-pin-count (FWH/LPC) interface Configuration
35/64
6 Firmware Hub/low-pin-count (FWH/LPC) interface
Configuration Registers
When the Firmware Hub Interface/Low Pin Count is selected , several addit ional registers
can be accessed. These registers control the protection status of the Blocks/Sectors, read
the General Purpose Input pins and identi fy the memory using the manufacture r code. See
Table 15 for the memory map of the Configuration Register s. The Configuration registers
are accessed directly without using any specific command code. A single Bus Write or Bus
Read Opera tion, with the appropriate addre ss (including A22=0), is all that is n eeded.
6.1 Lock Registers
The Lock Registers control the protection status of the Blocks/Sectors. Each Block/Sector
has its own Lock Register. Three bits within ea ch Lock Register control the protection of
each Block/Sector: the Write Lock Bit, the Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written. Care should be taken, thou gh, when writing.
Once the Lock Down Bit is set, ‘1’, further modifications to the Lock Register cannot be
made until it is cleared again by a reset or pow er-up.
See Table 16 for details on the bit definitions of the Lock Registers.
6.1.1 Write Lock
The Write Lock Bit determines whether the contents of the Block/Sector can be modified
(using the Program or Era se Command). When the Write Lock Bit is set, ‘1’, the
Block/Sector is write protected – any operations that attempt to change the data in the
Block/Sector will f ail, and the Status Register will report the error. When the Write Lock Bit is
reset, ‘0’, the Bloc k/Sector is not write protected b y the Loc k Register, and ma y be modified,
unless it is write protected by some ot her means.
If the Top Block Lock signal, TBL, is Low, VIL, then the Top Block (Block 15) is write
protected, and cannot be modified. Similarly, if the Write Protect signal, WP, is Low, VIL, then
the Main Blocks (Blocks 0 to 14) are write protected, and cannot be modi fied. For details,
see Appendix A and Table 16.
After power-up, or reset, the Write Lock Bit is always set to ‘1’ (write-protected).
6.1.2 Read Lock
The Read Lock bit determines whether th e co nte n ts of the Block/Sector can be rea d (in
Read mode). When the Read Lock Bit is set, ‘1’, the Block/Sector is read protected – any
operation that attempts to read the contents of the Bloc k/Sector will read 00h instead. When
the Read Lock Bit is reset, ‘0’, read operations are allowed in the Block/Sector, and return
the value of the data that had been programmed in the Block/Sector.
After power-up, or reset, the Read Lock Bit is always reset to ‘0’ (not read-protected).
Firmware Hub/low-pin-count (FWH/LPC) interface Configuration Registers M50FLW080A,
36/64
6.1.3 Lock Down
The Lock Down Bit provides a mechanism for protecti ng softwar e data from simple hacking
and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write
Loc k, Read Loc k and Loc k Down Bits cannot be perf ormed. A reset, or po wer-up, is required
before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write
Lock, Read Lock and Lock Do wn Bits can be changed.
1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0,
and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to
Table 9.
Table 15. Configuration Register map
Mnemonic Register Name Memory
Address Default
Value Access
Lock Registers (For details, see Appendix A)
GPI_REG Firmware Hub/Low Pin Count (FWH/LPC)
General Purpose Input Register FBC0100h N/A R
MANU_REG Manufacturer Code Register FBC0000h 20h R
Table 16. Lock Register bit definitions
Bit Bit Name Value Function(1)
1. Applies to the registers that are defined in Table 34 and Table 35.
7-3 Reserved
2 Read-Lock ‘1’ Bus Read operations in this Block or Sector always return 00h.
‘0’ Bus read operations in this Block or Sector return the Memory Array
contents. (Default value).
1 Lock-Down ‘1’
Changes to the Read-Lock bit and the Write-Lock bit cannot be
performed. Once a ‘1’ is written to the Lock-Down bit it cannot be
cleared to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP
or INIT) or after power-up.
‘0’ Read-Lock and Write-Lock can be changed by writing new values to
them. (Default value).
0Write-Lock ‘1’ Program and Erase operations in this Block or Sector will set an error
in the Status Register. The memory contents wi ll not be changed.
(Default value).
‘0’ Program and Erase operations in this Block or Sector are executed
and will modify the Block or Sector contents.
M50FLW080A, M50FLW080B Firmware Hub/low-pin-count (FWH/LPC) interface Configuration
37/64
6.2 Firmware Hub/low-pin-count (FWH/LPC) General-Purpose
Input Register
The FWH/LPC General Purpose Input Register holds the state of the General Purpose
Input pins, GPI0-GPI4. When this register is read, the state of these pins is returned. This
register is read-only. Writing to it has no effect.
The signals on the FWH/LPC Interface General Purpose Input pins should remain constant
throughout the whole Bus Read cycle.
6.3 Manufacturer Code Register
Reading the Manufacturer Code Register returns the value 20h, which is the Manufacturer
Code for STMicroelectr onics. This re gister is read-only. Writing to it has no effect.
Table 17. General-Purpose Input Register definition
Bit Bit Name Value Function(1)
1. Applies to the General Purpose Inputs Register (GPI-REG).
7-5 Reserved
4GPI4 ‘1’ Input Pin GPI4 is at VIH
‘0’ Input Pin GPI4 is at VIL
3GPI3 ‘1’ Input Pin GPI3 is at VIH
‘0’ Input Pin GPI3 is at VIL
2GPI2 ‘1’ Input Pin GPI2 is at VIH
‘0’ Input Pin GPI2 is at VIL
1GPI1 ‘1’ Input Pin GPI1 is at VIH
‘0’ Input Pin GPI1 is at VIL
0GPI0 ‘1’ Input Pin GPI0 is at VIH
‘0’ Input Pin GPI0 is at VIL
Program and Erase times M50FLW080A, M50FLW080B
38/64
7 Program and Erase times
The Program and Erase times are shown in Table 18.
Table 18. Program and Erase times
Parameter Interface Test Condition Min Typ(1)
1. TA = 25°C, VCC = 3.3V
Max Unit
Byte Program 10 200 µs
Double Byte Program FWH VPP = 12V ± 5% 10(2)
2. Time to program two Bytes.
200 µs
Quadruple Byte Program A/A Multiplexed
FWH VPP = 12V ± 5% 10(3)
3. Time to program four Bytes.
200 µs
Block Program VPP = 12V ± 5% 0.1(4)
4. Time obtained executing the Quadruple Byte Program command.
5s
VPP = VCC 0.4 5
Sector Erase (4 KBytes)(5)
5. Sampled only, not 100% tested.
VPP = 12V ± 5% 0.4 4 s
VPP = VCC 0.5 5
Block Erase (64 KBytes) VPP = 12V ± 5% 0.75 8 s
VPP = VCC 110
Chip Erase A/A Multiplexed VPP = 12V ± 5% 10 s
Program/Erase Suspend to
Program pause(5) 5µs
Program/Erase Suspend to Block
Erase/Sector Erase pause(5) 30 µs
M50FLW080A, M50FLW080B Maximum rating
39/64
8 Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 19. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
VIO Input or Output range(1)
1. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may
overshoot to VCC + 2V for less than 20ns during transitions.
–0.50 VCC + 0.6 V
VCC Supply Voltage –0.50 4 V
VPP Program Voltage –0.6 13 V
VESD Electrostatic Discharge Voltage (Human Body
model)(2)
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
–2000 2000 V
DC and AC parameters M50FLW080A, M50FLW080B
40/64
9 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 20, Table 21 and Table 22. Designers should check that the operatin g conditions in
their circuit match the operating conditions when relying on the quoted parameters.
Figure 10. FWH/LPC interface AC measurement I/O waveforms
Table 20. Operating conditions
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 3.0 3.6 V
TAAmbient Operating Temperature –20 85 °C
Table 21. FWH/LPC interface AC measu rement conditions
Parameter Value Unit
Load Capacita nce (C L)10pF
Input Rise and Fall Times ≤ 1.4 ns
Input Pulse Voltages 0.2 VCC and 0.6 VCC V
Input and Output Timing Ref. Voltages 0.4 VCC V
Table 22. A/A Mux interface AC measurement conditions
Parameter Value Unit
Load Capacita nce (C L)30pF
Input Rise and Fall Times ≤ 10 ns
Input Pulse Voltages 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 V
AI03404
0.6 VCC
0.2 VCC
0.4 VCC
IO > ILO
IO < ILO IO < ILO
Input and Output AC Testing Waveform
Output AC Tri-state Testing Waveform
M50FLW080A, M50FLW080B DC and AC parameters
41/64
Figure 11. A/A Mux interface AC mea surement I/O waveform
Figure 12. AC mea surement load circuit
Table 23. Impedance(1)
1. TA = 25°C, f = 1MHz.
Symbol Parameter Test Condition Min Max Unit
CIN(2)
2. Sampled only, not 100% tested.
Input Capacitance VIN = 0V 13 pF
CCLK(2) Clock Capacitance VIN = 0V 3 12 pF
LPIN(3)
3. See PCI Specification.
Recommended Pin
Inductance 20 nH
AI01417
3V
0V
1.5V
AI08430
VDD
CL
CL includes JIG capacitance
16.7kΩ
DEVICE
UNDER
TEST
0.1µF
VDD
0.1µF
VPP
16.7kΩ
DC and AC parameters M50FLW080A, M50FLW080B
42/64
Table 24. DC charact eristics
Symbol Parameter Interface Test Condition Min Max Unit
VIH Input High Voltage FWH 0.5 VCC VCC + 0.5 V
A/A Mux 0.7 VCC VCC + 0.3 V
VIL Input Lo w Voltage FWH/LPC –0.5 0.3 VCC V
A/A Mux -0.5 0.8 V
VIH(INIT)INIT Input High Voltage FWH/LPC 1.1 VCC + 0.5 V
VIL(INIT)INIT Input Low Voltage FW H/LPC –0.5 0.2 VCC V
ILI(1) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA
ILI2 IC, IDx Input Leakage
Current IC, ID0, ID1, ID2, ID3(2)= VCC 200 µA
RIL IC , IDx Input Pull Lo w
Resistor 20 100 kΩ
VOH Output High Voltage FWH/LPC IOH = –500µA 0.9 VCC V
A/A Mux IOH = –100µAV
CC – 0.4 V
VOL Output Low Voltage FWH/LPC IOL = 1.5mA 0.1 VCC V
A/A Mux IOL = 1.8mA 0.45 V
ILO Output Leakage
Current 0V ≤ VOUT ≤ VCC ±10 µA
VPP1 VPP Voltage 3 3.6 V
VPPH VPP Voltage (Fast
Erase) 11.4 12.6 V
VLKO(3) VCC Lockout Voltage 1.8 2.3 V
ICC1 Supply Current
(Standby) FWH/LPC FWH4/LFRAME = 0.9VCC, VPP = VCC
All other inputs 0.9VCC to 0.1VCC
VCC = 3.6V, f(CLK) = 33MHz 100 µA
ICC2 Supply Current
(Standby) FWH/LPC FWH4/LFRAME = 0.1 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6 V, f(CLK) = 33 MHz 10 mA
ICC3
Supply Current (Any
internal operation
active) FWH/LPC VCC = VCC max, VPP = VCC
f(CLK) = 33 MHz, IOUT = 0mA 60 mA
ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA
ICC5(3) Supply Current
(Program/Erase) A/A Mux Program/Erase Controller Active 20 mA
IPP VPP Supply Current
(Read/Standby) VPP > VCC 400 µA
IPP1(3) VPP Supply Current
(Program/Erase active) VPP = VCC 40 mA
VPP = 12V ± 5% 15 mA
1. Input leakage currents include High-Z output leakage for all bidirectional buffers with tri-state outputs.
2. ID0 and ID1 are RFU in LPC mode.
3. Sampled only, not 100% tested.
M50FLW080A, M50FLW080B DC and AC parameters
43/64
Figure 13. FWH/LPC interface clock waveform
1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz
devices may be guaranteed by design rather than tested. Refer to PCI Specification.
Table 25. FWH/LPC interface cloc k characteristics
Symbol Parameter Test Condition Va lue Unit
tCYC CLK Cycle Time(1) Min 30 ns
tHIGH CLK High Time Min 11 ns
tLOW CLK Low Time Min 11 ns
CLK Slew Rate peak to peak Min 1 V/ns
Max 4 V/ns
AI03403
tHIGH tLOW
0.6 VCC
tCYC
0.5 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.4 VCC, p-to-p
(minimum)
DC and AC parameters M50FLW080A, M50FLW080B
44/64
Figure 14. FWH/LPC interface AC signal timing waveforms
CLK
FWH0-FWH3/
LAD0-LAD3
VALID
tCHQV tCHQZ
tCHQX
tCHDX
tDVCH
VALID
OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA
AI09700
tCHFH
tFLCH
FWH4
START CYCLE
Table 26. FWH/LPC Interface AC signal timing characteristics
Symbol PCI Symbol Parameter Value Unit
tCHQV tval CLK to Data Out Min 2 ns
Max 11 ns
tCHQX(1) ton CLK to Active
(Float to Active Delay) Min 2 ns
tCHQZ toff CLK to Inactive
(Active to Float Delay) Max 28 ns
tAVCH
tDVCH tsu Input Set-up Time(2) Min 7 ns
tCHAX
tCHDX thInput Hold Time(2) Min 0 ns
tFLCH Input Set-up time on FWH4 Min 10 n s
tCHFH Input Hold time on FWH4 Min 5 ns
1. The timing measurements for Active/Float transitions are def ined when the current through the pin equals the leakage
current specification.
2. Applies to all inputs except CLK and FWH4.
M50FLW080A, M50FLW080B DC and AC parameters
45/64
Figure 15. Reset AC waveforms
Table 27. Reset AC characteristics
Symbol Parameter Test Condition Value Unit
tPLPH RP or INIT Reset Pulse Width Min 100 ns
RP or INIT Slew Rate(1)
1. See Chapter 4 of the PCI Specification.
Rising edge only Min 50 mV/ns
tPHFL RP or INIT High to
FWH4/LFRAME Low FWH/LPC Interface
only Min 30 µs
tPHWL
tPHGL
RP High to Write Enable or
Output Enable Low A/A Mux Inte rface only Min 50 µs
RP, INT
Ai09705
W, G, FWH4/LFRAME
tPLPH tPHWL, tPHGL, tPHFL
DC and AC parameters M50FLW080A, M50FLW080B
46/64
Figure 16. A/A Mux interface Read AC waveforms
AI03406
tAVAV
tCLAX tCHAX
tGLQX
tGLQV
tGHQX
VALID
A0-A10
G
DQ0-DQ7
RC
tCHQV
tGHQZ
COLUMN ADDR VALID
W
RP
tPHAV
ROW ADDR VALID NEXT ADDR VALID
tAVCL tAVCH
Tabl e 28. A/A Mux interface Read AC characteristic s
Symbol Parameter Test Condition Value Unit
tAVAV Read Cycle Time Min 250 ns
tAVCL Row Address Valid to RC Low Min 50 ns
tCLAX RC Low to Row Address Transition Min 50 ns
tAVCH Column Address Valid to RC high Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tCHQV(1) RC High to Output Valid Max 150 ns
tGLQV(1) Output Enable Low to Output Valid Max 50 ns
tPHAV RP High to Row Address Valid Min 1 µs
tGLQX Output Enable Low to Output Transition Min 0 ns
tGHQZ Output Enable High to Output Hi-Z Max 50 ns
tGHQX Output Hold from Output Enable High Min 0 ns
1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.
M50FLW080A, M50FLW080B DC and AC parameters
47/64
Figure 17. A/A Mux inter face Write AC waveforms
AI04185
tCLAX
tCHAX
tWHDXtDVWH
VALID SRD
A0-A10
G
DQ0-DQ7
RC
tCHWH
C1
W
R1
tAVCL
tAVCH
R2 C2
tWLWH
tWHWL
VPP
tVPHWH tWHGL
tQVVPL
DIN1 DIN2
Write erase or
program setup
Write erase confirm or
valid address and data
Automated erase
or program delay Read Status
Register Data Ready to write
another command
Tabl e 29. A/A Mux interface Write AC characteristics
Symbol Parameter Test Condition Value Unit
tWLWH Write Enable Low to Write Enable High Min 100 ns
tDVWH Data Valid to Write Enable High Min 50 ns
tWHDX Write Enable High to Data Transition Min 5 ns
tAVCL Row Address Val id to RC Low Min 50 ns
tCLAX RC Lo w to Row Address Transition Min 5 0 ns
tAVCH Column Address Valid to RC High Min 50 ns
tCHAX RC High to Column Address Transition Min 50 ns
tWHWL Write Enable High to Write Enable Low Min 100 ns
tCHWH RC High to Write Ena ble High Min 50 ns
tVPHWH(1) VPP High to Write Enable High Min 100 ns
tWHGL Write Enable High to Output Enable Low Min 30 ns
tWHRL Write Enable High to RB Low Min 0 ns
tQVVPL(1) (2) Output Valid, RB High to VPP Low Min 0 ns
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
Package mechanical M50FLW080A, M50FLW080B
48/64
10 Package mechanical
Figure 18. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package
outline
1. Drawing is not to scale.
Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 3.18 3.56 0.125 0.140
A1 1.53 2.41 0.060 0.095
A2 0.38 – 0.015 –
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
CP 0.10 0.004
D 12.32 12.57 0.485 0.495
D1 11.35 11.51 0.447 0.453
D2 4.78 5.66 0.188 0.223
D3 7.62 – – 0.300 – –
E 14.86 15.11 0.585 0.595
E1 13.89 14.05 0.547 0.553
E2 6.05 6.93 0.238 0.273
E3 10.16 – – 0.400 – –
e1.27 – – 0.050 – –
F 0.00 0.13 0.000 0.005
R0.89 – – 0.035 – –
N32 32
PLCC-A
D
E3 E1 E
1 N
D1
D3
CP
B
E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
E2
D2 D2
M50FLW080A, M50FLW080B Package mechanical
49/64
Figure 19. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline
1. Drawing is not to scale.
Tabl e 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
α0° 5° 0° 5°
B 0.170 0.270 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D 13.800 14.200 0.5433 0.5591
D1 12.300 12.500 0.4843 0.4921
e 0.500 – – 0.0197 – –
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
N32 32
TSOP-a
D1
E
1N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
Package mechanical M50FLW080A, M50FLW080B
50/64
Figure 20. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package outline
1. Drawing is not to scale.
Tabl e 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.100 0.0039
D1 10.000 9.900 10.100 0.3937 0.3898 0.3976
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
L 0.500 0.700 0.0197 0.0276
L1 0.800 0.0315
α3° 0° 5° 3° 0° 5°
TSOP40-M
B
e
DIE
C
E1
E
20
140
D1
CP
21
LA1 α
A
A2 L1
0.25
M50FLW080A, M50FLW080B Part numbering
51/64
11 Part numbering
Devices are shipped from the factory with the memory content bits erased to ’1’.
F or a list of a vailab le options ( Speed, Package , etc.) or f o r further information on an y aspect
of this device, ple ase contact the ST Sales Office nearest to you.
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
Table 33. Ordering information scheme
Example: M50FLW080 A K 5 T G
Device Type
M50 = Flash Memory for PC BIOS
Architecture
FL = Firmware Hub/Low Pin Count Interface
Operating Voltage
W = VCC = 3.0 to 3.6V
Device Function
080 = 8 Mbit (x8), Uniform Blocks and Sectors
Array Matrix
A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors
B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors
Package
K = PLCC32
NB = TSOP32: 8 x 14mm(1)
1. The TSOP32 package is only available in devices of the A type array matrix.
N = TSOP40: 10 x 20mm(2)
2. Devices delivered in this package are Not Recommended for New Design.
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK ® (RoHs compliant)
Block and sector address table M50FLW080A, M50FLW080B
52/64
Appendix A Block and sector address table
Table 34. M50FLW080A block, sector and Lock Regi ster addresses
Block Size
(KByte) Address Range Bloc k No and
Type Sector Siz e
(KByte) Sector No Register
Address
64
FF000h-FFFFFh
15
(Top)
4 47 FBFF002
FE000h-FEFFFh 446 FBFE002
FD000h-FDFFFh 445 FBFD002
FC000h-FCFFFh 444 FBFC002
FB000h-FBFFFh 443 FBFB002
FA000h-FAFFFh 442 FBFA002
F9000h-F9FFFh 441 FBF9002
F8000h-F8FFFh 440 FBF8002
F7000h-F7FFFh 439 FBF7002
F6000h-F6FFFh 438 FBF6002
F5000h-F5FFFh 437 FBF5002
F4000h-F4FFFh 436 FBF4002
F3000h-F3FFFh 435 FBF3002
F2000h-F2FFFh 434 FBF2002
F1000h-F1FFFh 433 FBF1002
F0000h-F0FFFh 432 FBF0002
64
EF000h-EFFFFh
14
(Main)
431 FBEF002
EE000h-EEFFFh 430 FBEE002
ED000h-EDFFFh 429 FBED002
EC000h-ECFFFh 428 FBEC002
EB000h-EBFFFh 427 FBEB002
EA000h-EAFFFh 426 FBEA002
E9000h-E9FFFh 425 FBE9002
E8000h-E8FFFh 424 FBE8002
E7000h-E7FFFh 423 FBE7002
E6000h-E6FFFh 422 FBE6002
E5000h-E5FFFh 421 FBE5002
E4000h-E4FFFh 420 FBE4002
E3000h-E3FFFh 419 FBE3002
E2000h-E2FFFh 418 FBE2002
E1000h-E1FFFh 417 FBE1002
E0000h-E0FFFh 416 FBE0002
M50FLW080A, M50FLW080B Block and sector address table
53/64
1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0,
and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to
Table 9.
64 D0000h-DFFFFh 13 (Main) FBD0002
64 C0000h-CFFFFh 12 (Main) FBC0002
64 B0000h-BFFFFh 11 (Main) FBB0002
64 A0000h-AFFFFh 10 (Main) FBA0002
64 90000h-9FFFFh 9 (Main) FB90002
64 80000h-8FFFFh 8 (Main) FB80002
64 70000h-7FFFFh 7 (Main) FB70002
64 60000h-6FFFFh 6 (Main) FB60002
64 50000h-5FFFFh 5 (Main) FB50002
64 40000h-4FFFFh 4 (Main) FB40002
64 30000h-3FFFFh 3 (Main) FB30002
64 20000h-2FFFFh 2 (Main) FB20002
64 10000h-1FFFFh 1 (Main) FB10002
64
0F000h-0FFFFh
0
(Main)
415 FB0F002
0E000h-0EFFFh 414 FB0E002
0D000h-0DFFFh 413 FB0D002
0C000h-0CFFFh 412 FB0C002
0B000h-0BFFFh 411 FB0B002
0A000h-0AFFFh 410 FB0A002
09000h-09FFFh 4 9 FB09002
08000h-08FFFh 4 8 FB08002
07000h-07FFFh 4 7 FB07002
06000h-06FFFh 4 6 FB06002
05000h-05FFFh 4 5 FB05002
04000h-04FFFh 4 4 FB04002
03000h-03FFFh 4 3 FB03002
02000h-02FFFh 4 2 FB02002
01000h-01FFFh 4 1 FB01002
00000h-00FFFh 4 0 FB00002
Table 34. M50FLW080A block, sector and Lock Regi ster addresses (continued)
Block Size
(KByte) Address Range Bloc k No and
Type Sector Siz e
(KByte) Sector No Register
Address
Block and sector address table M50FLW080A, M50FLW080B
54/64
Table 35. M50FLW080B block, sector and Lock Regi ster addresses
Block Size
(KByte) Address Range Block No
and Type Sector Size
(KByte) Sector No Register
Address
64
FF000h-FFFFFh
15
(Top)
447FBFF002
FE000h-FEFFFh 446 FBFE002
FD000h-FDFFFh 445 FBFD002
FC000h-FCFFFh 444 FBFC002
FB000h-FBFFFh 443 FBFB002
FA000h-FAFFFh 442 FBFA002
F9000h-F9FFFh 441 FBF9002
F8000h-F8FFFh 440 FBF8002
F7000h-F7FFFh 439 FBF7002
F6000h-F6FFFh 438 FBF6002
F5000h-F5FFFh 437 FBF5002
F4000h-F4FFFh 436 FBF4002
F3000h-F3FFFh 435 FBF3002
F2000h-F2FFFh 434 FBF2002
F1000h-F1FFFh 433 FBF1002
F0000h-F0FFFh 432 FBF0002
64 E0000h-EFFFFh 14 (Main) FBE0002
64 D0000h-DFFFFh 13 (Main) FBD0002
64 C0000h-CFFFFh 12 (Main) FBC0002
64 B0000h-BFFFFh 11 (Main) FBB0002
64 A0000h-AFFFFh 10 (Main) FBA0002
64 90000h-9FFFFh 9 (Main) FB90002
64 80000h-8FFFFh 8 (Main) FB80002
64 70000h-7FFFFh 7 (Main) FB70002
64 60000h-6FFFFh 6 (Main) FB60002
64 50000h-5FFFFh 5 (Main) FB50002
64 40000h-4FFFFh 4 (Main) FB40002
64 30000h-3FFFFh 3 (Main) FB30002
64 20000h-2FFFFh 2 (Main) FB20002
M50FLW080A, M50FLW080B Block and sector address table
55/64
1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0,
and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to
Table 9.
64
1F000h-1FFFFh
1 (Main)
431 FB1F002
1E000h-1EFFFh 430 FB1E002
1D000h-1DFFFh 429 FB1D002
1C000h-1CFFFh 428 FB1C002
1B000h-1BFFFh 427 FB1B002
1A000h-1AFFFh 426 FB1A002
19000h-19FFFh 425 FB19002
18000h-18FFFh 424 FB18002
17000h-17FFFh 423 FB17002
16000h-16FFFh 422 FB16002
15000h-15FFFh 421 FB15002
14000h-14FFFh 420 FB14002
13000h-13FFFh 419 FB13002
12000h-12FFFh 418 FB12002
11000h-11FFFh 417 FB11002
10000h-10FFFh 416 FB10002
64
0F000h-0FFFFh
0
(Main)
415 FB0F002
0E000h-0EFFFh 414 FB0E002
0D000h-0DFFFh 413 FB0D002
0C000h-0CFFFh 412 FB0C002
0B000h-0BFFFh 411 FB0B002
0A000h-0AFFFh 410 FB0A002
09000h-09FFFh 4 9 FB09002
08000h-08FFFh 4 8 FB08002
07000h-07FFFh 4 7 FB07002
06000h-06FFFh 4 6 FB06002
05000h-05FFFh 4 5 FB05002
04000h-04FFFh 4 4 FB04002
03000h-03FFFh 4 3 FB03002
02000h-02FFFh 4 2 FB02002
01000h-01FFFh 4 1 FB01002
00000h-00FFFh 4 0 FB00002
Table 35. M50FLW080B block, sector and Lock Regi ster addresses (continued)
Block Size
(KByte) Address Range Block No
and Type Sector Size
(KByte) Sector No Register
Address
Flowcharts and pseudo codes M50FLW080A, M50FLW080B
56/64
Appendix B Flowcharts and pseudo codes
Figure 21. Program flowchart and pseudo code
1. A Status check of SR1 (Protected Block/Sector), SR3 (VPP invalid) and SR4 (Program Error) can be made
after each Program operation by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
Write 40h or 10h
AI09092
Start
Write Address
and Data
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Program command:
– Write 40h or 10h
– Write Address and Data
(memory enters read status state after
the Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1,
– Enter the "VPP invalid" error handler
If SR4 = 1,
– Enter the "Program error" error handler
YES
End
YES
NO
SR1 = 0 Program to Protected
Block/Sector Error (1, 2)
If SR1 = 1,
– Enter the "Program to protected
block/sector" error handler
Suspend
Suspend
Loop
NO
YES
FWH/LPC
Interface
Only
M50FLW080A, M50FLW080B Flowcharts and pseudo codes
57/64
Figure 22. Double/Quadruple Byte Pr og ram flowcha rt and pseudo code (FWH mode
only)
1. A Status check of SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation
by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. A0 and/or A1 are treated as Don’t Care (A0 for Double Byte Program and A1-A0 for Quadruple Byte
Program).
For Double Byte Program: Starting at the Start Address, the first data Byte is programmed at the even
address, and the second at the odd address.
For Quadruple Byte Program: Starting at the Start Address, the first data Byte is programmed at the
address that has A1-A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that
has A1-A0 at 10, and the fourth at the address that has A1-A0 at 11.
AI09093
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Double/Quadruple Byte Program command:
– write 40h or 10h
– write Start Address and 2/4 Data Bytes
(3)
(memory enters read status state after
the Double/Quadruple Byte Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1, VPP invalid error:
– error handler
If SR4 = 1, Program error:
– error handler
Suspend
Suspend
Loop
NO
YES
Write 40h or 10h
Start
Write Start Address
and 2/4 Data Bytes
(3)
YES
End
YES
NO
SR1 = 0 Program to Protected
Block/Sector Error (1, 2) If SR1 = 1,
Program to protected block/sector error:
– error handler
Flowcharts and pseudo codes M50FLW080A, M50FLW080B
58/64
Figure 23. Quadruple Byte Program flowchart and pseudo code (A/A Mux interface
only)
1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation
by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address
bits A0 and A1.
AI09099
Write Address 4
& Data 4
(3)
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1
(3)
– write Address 2 & Data 2
(3)
– write Address 3 & Data 3
(3)
– write Address 4 & Data 4
(3)
(memory enters read status state after
the Quadruple Byte Program command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1, VPP invalid error:
– error handler
If SR4 = 1, Program error:
– error handler
End
YES
Suspend
Suspend
Loop
NO
YES
Write 30h
Start
Write Address 1
& Data 1
(3)
Write Address 2
& Data 2
(3)
Write Address 3
& Data 3
(3)
M50FLW080A, M50FLW080B Flowcharts and pseudo codes
59/64
Figure 24. Progra m Suspend and Resume flowchart and pseudo code
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
Write 70h
AI08426B
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR2 = 1
Program Continues
Write a read
Command
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while SR7 = 0
If SR2 = 0 Program completed
Write D0h Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Read data from
another address
Start
Write B0h
Program Complete
Write FFh
Read Data
Flowcharts and pseudo codes M50FLW080A, M50FLW080B
60/64
Figure 25. Chip Erase flowchart and pseudo code (A/A Mux interface only)
1. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
Write 80h
AI08428B
Start
Write 10h
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4, SR5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Chip Erase command:
– write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)
do:
– read Status Register
while SR7 = 0
If SR3 = 1, VPP invalid error:
– error handler
If SR4, SR5 = 1, Command sequence error:
– error handler
YES
NO
SR5 = 0 Erase Error (1) If SR5 = 1, Erase error:
– error handler
End
YES
M50FLW080A, M50FLW080B Flowcharts and pseudo codes
61/64
Figure 26. Sector/Block Erase flowchart and pseudo code
1. If the Block Erase command is used on a block that is split into 4KByte sectors, each of the 16 sectors of
the block should be unlocked before performing the erase operation.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
Write 20h/32h
AI09094
Start
Write Block/Sector
Address and D0h
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4, SR5 = 0
VPP Invalid
Error (1)
Command
Sequence Error (1)
Block/Sector Erase command:
– Write 20h/32h
– Write Block/Sector Address and D0h
(memory enters read Status Register after
the Block/Sector Erase command)
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
– Enter suspend program loop
If SR3 = 1,
– Enter the "VPP invalid" error handler
If SR4, SR5 = 1,
– Enter the "Command sequence"error handler
YES
NO
SR5 = 0 Erase Error (1)
YES
NO
Suspend
Suspend
Loop
If SR5 = 1,
– Enter the "Erase Error" error handler
End
YES
NO
SR1 = 0 Erase to Protected
Block/Sector Error (1)
If SR1 = 1,
– Enter the "Erase to protected Block/Sector"
error handler
YES
FWH/LPC
Interface
Only
Flowcharts and pseudo codes M50FLW080A, M50FLW080B
62/64
Figure 27. Erase Suspend and Resume flowchart and pseudo code
Write 70h
AI08429B
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR6 = 1
Erase Continues
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read Status Register
while SR7 = 0
If SR6 = 0, Erase completed
Write D0h
Read data from
another block/sector
or
Program
Start
Write B0h
Erase Complete
Write FFh
Read Data
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
M50FLW080A, M50FLW080B Revision history
63/64
12 Revision history
Table 36. Document revision history
Date Version Changes
02-Feb-2004 0.1 First Issue
21-Apr-2004 0.2 TSOP32 package added
24-May-2004 1.0 First public release
18-Aug-2004 2.0 Pins 2 and 5 of the TSOP32 Connections illustration corrected
21-Jun-2005 3.0 Datasheet status changed to Full Datasheet.
26-Oct-2006 4
Document converted to new ST template.
Packages are ECOPACK® compliant. TLEAD removed from Table 19:
Absolute maximum ratings. Blank option removed below Plating
Technology in Table 33: Ordering information scheme .
TSOP40 (N) package is Not Recommended f or New Design. TSOP32
(NB) package only available in A type array matrix devices. TSOP40
package specifications updated (see Table 32 and Figure 20).
M50FLW080A, M50FLW080B
64/64
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