1N8026 - GeneSiC Semiconductor

- 1 -

TS14001

Version 1.5

nanoSmart® Ultra-Low-Power Linear Regulator

DESCRIPTIONS FEATURES

Block Diagram

GND

EN

VOUT

Reference

Voltage

VCC

Current

Limit

FB

The TS14001 linear regulator is an ultra-low-

power circuit which draws low nA level

quiescent current at light load, but has the

capability to regulate current loads as high as

200mA.

APPLICATIONS

 Portable electronics

 RFID

 Industrial

 Medical

 Energy harvesting systems

 SmartCard

 Ultra-low nA operating current at light load

 Best-in-class quiescent current of 20nA at

Iload=0

 Best-in-class quiescent current of 100pA in

disable mode

 Output voltage options of 1.2V - 4.2V in

100mV steps (programmed at

manufacturing)

 Accurate output regulation

 Over-current protection

SUMMARY SPECIFICATIONS

 Low input operating voltage of 2.5V to 5.5V

 Packaged in a 8pin VDFN (2x2)

- 2 -

TS14001

Version 1.5

TYPICAL APPLICATION

Load

GND

EN

VOUT

VCC

FB

TS14001

COUT

CBYP

PIN-OUT CONFIGURATION

PIN #

NAME

I/O/P

DESCRIPTION

1

GND

P

Ground

2

VOUT

O

Regulated Output Voltage

3

NC

No Connect (connect to GND or float)

4

NC

No Connect (connect to GND or float)

5

NC

No Connect (connect to GND or float)

6

FB

I

Feedback Input

7

VCC

P

Input Power

8

EN

I

Enable Input

ABSOLUTE MAXIMUM RATINGS

Over operating free–air temperature range unless otherwise noted(1,2,3)

PIN / PARAMETER

VALUE

UNIT

VCC, VOUT, EN, FB

-0.3 to 6.0

V

Electrostatic Discharge (Human Body Model)

2

kV

Operating Junction Temperature Range, TJ

-20 to 85

C

Storage Temperature Range, TSTG

-65 to 150

C

Lead Temperature (soldering, 10 seconds)

260

C

Note 1: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

Note 2: All voltage values are with respect to network ground terminal.

Note 3: ESD testing is performed according to the respective JESD22 JEDEC standard.

- 3 -

TS14001

Version 1.5

THERMAL CHARACTERISTICS

Package

DFN

JA (C/W)

(See Note 4)

JC (C/W)

(See Note 5)

8 pin

73.1

10.7

Note 4: This assumes a FR4 board only.

Note 5: This assumes a 1oz. Copper JEDEC standard board with thermal vias. See Exposed Pad section and application note for more information.

RECOMMENDED OPERATING CONDITIONS

Parameter

Min

Typ

Max

Unit

Unregulated Supply Input Voltage (VCC)

2.5

5.5

V

Enable Input (EN)

0

5

V

Regulated Supply Output Voltage (VOUT) typical

1.2

4.2

V

Operating Ambient Temperature, TA (Note 6)

-40

55

°C

Operating Junction Temperature, TJ

-40

85

°C

Input Bypass Capacitor (CBYP)

2.2

uF

Output Bypass Capacitor (COUT)

1

2.2

4.7

uf

Note 6: TA Max shown here is a guideline. Higher TA can be tolerated if TJ does not exceed the Absolute Maximum Rating.

CHARACTERISTICS

Electrical characteristics, VCC = 2.5V to 5V, TJ = 25C, unless otherwise noted

Symbol

Parameter

Condition

Min

Typ

Max

Unit

VBAT

Input Supply Voltage

2.5

5.5

V

VilEN

Input Low Logic Level

0.3*VCC

V

VihEN

Input High Logic Level

0.7*VCC

V

Iqq

Quiescent Current

VCC = 2.5V to 5.5V, IOUT = 0

20

nA

Iqq-disable

Quiescent Current:

Disable Mode

IOUT = 0, EN = 0

100

pA

Iop-gnd

Operating Current

VCC = VCC_MIN, IOUT = 200mA

(Note 7)

200

uA

VCC = VCC_NOM, IOUT = 200mA

(Note 7)

200

uA

VCC = VCC_MAX, IOUT = 200mA

(Note 7)

200

uA

Iout

Load Capability

Voutnominal from 1.2V to 3.5V

0

200

mA

Voutnominal >3.5V

0

100

Note 7: If Voutnominal < 2.5V, then VCC_MIN = 2.5V, otherwise VCC_MIN = Vout + 0.3V. VCC_MAX is always 5.5V. VCC_NOM is the average of VCC_MAX and

VCC_MIN.

- 4 -

TS14001

Version 1.5

CHARACTERISTICS CONTINUED

Electrical characteristics, VCC = 2.5V to 5V, TJ = 25C, unless otherwise noted

Symbol

Parameter

Condition

Min

Typ

Max

Unit

VLine

DC Line Regulation

VCC = VCC_MIN to VCC_MAX,

VOUT =1.8V to 4.2V,

IOUT = 50mA

0.5

4

%

VCC = VCC_MIN to VCC_MAX,

VOUT < 1.8V,

IOUT = 50mA

4

%

VLoad

DC Load Regulation

VCC = VCC_NOM,

IOUT = 0.02mA to 200mA,

1

3

%

Ilimit

Current Limit

IOUT measured at

VOUT = 0.9*Voutnominal ;

Voutnominal from 1.2V to 3.5V

250

mA

IOUT measured at

VOUT = 0.9*Voutnominal ;

Voutnominal >3.5V

175

- 5 -

TS14001

Version 1.5

TYPICAL CHARACTERISTICS

Iqq Performance

Iqq Performance vs. Load Current

Line Regulation Performance

VOUT Performance vs. Temperature

- 6 -

TS14001

Version 1.5

Dropout Voltage When VOUT Drops By 3%

Load Regulation Performance

Dropout Voltage = VCC - VOUT

Load Step Response

Line Step Response

- 7 -

TS14001

Version 1.5

Output Enable Timing

- 8 -

TS14001

Version 1.5

PACKAGE MECHANICAL DRAWINGS

- 9 -

TS14001

Version 1.5

RECOMMENDED PCB LAND PATTERN

- 10 -

TS14001

Version 1.5

APPLICATION USING A MULTI-LAYER PCB

To maximize the efficiency of this package for application on a single layer or multi-layer PCB, certain guidelines must be

followed when laying out this part on the PCB.

The following are guidelines for mounting the exposed pad IC on a Multi-Layer PCB with ground a plane.

JEDEC standard FR4 PCB Cross-section:

Multi-Layer Board (Cross-sectional View)

In a multi-layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to

the internal ground plane. The efficiency of this method depends on several factors, including die area, number of thermal vias,

thickness of copper, etc.

Package Thermal Pad

Solder Pad (Land Pattern)

Thermal Via's

Package Outline

Package and PCB Land Configuration

For a Multi-Layer PCB

(square) Package Solder Pad

Package Solder Pad

(bottom trace)

Thermal Via

Component Traces

Thermal Isolation

Power plane only

1.5748mm

0.0 - 0.071 mm Board Base

& Bottom Pad

0.5246 - 0.5606 mm

Power Plane

(1oz Cu)

1.0142 - 1.0502 mm

Ground Plane

(1oz Cu)

1.5038 - 1.5748 mm

Component Trace

(2oz Cu)

2 Plane

4 Plane

- 11 -

TS14001

Version 1.5

The above drawing is a representation of how the heat can be conducted away from the die using an exposed pad package. Each

application will have different requirements and limitations and therefore the user should use sufficient copper to dissipate the

power in the system. The output current rating for the linear regulators may have to be de-rated for ambient temperatures

above 85C. The de-rate value will depend on calculated worst case power dissipation and the thermal management

implementation in the application.

APPLICATION USING A SINGLE LAYER PCB

Layout recommendations for a Single Layer PCB: utilize as much Copper Area for Power Management. In a single layer board

application the thermal pad is attached to a heat spreader (copper areas) by using low thermal impedance attachment method

(solder paste or thermal conductive epoxy).

In both of the methods mentioned above it is advisable to use as much copper traces as possible to dissipate the heat.

IMPORTANT:

If the attachment method is NOT implemented correctly, the functionality of the product is not guaranteed. Power

dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board.

Mold compound

Die

Epoxy Die attach

Exposed pad

Solder

Thermal Vias with Cu plating

Single Layer, 2oz Cu

Ground Layer, 1oz Cu

Signal Layer, 1oz Cu

Bottom Layer, 2oz Cu

20% Cu coverage

90% Cu coverage

5% - 10% Cu coverage

Note: NOT to Scale

Use as much Copper Area

as possible for heat spread

Package Thermal Pad

Package Outline

- 12 -

TS14001

Version 1.5

ORDERING INFORMATION

TS14001-CvvvDFNR

vvv

Output Voltage*

012

1.2 V

018

1.8 V

025

2.5 V

033

3.3 V

042

4.2 V

* Custom values also available (1.2V - 4.2V typical in 100mV increments)

- 13 -

TS14001

Version 1.5

Legal Notices

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by

updates. It is your responsibility to ensure that your application meets with your specifications. “Typical” parameters which may be provided in Triune

Systems data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for your application by your technical experts. TRIUNE SYSTEMS MAKES NO REPRESENTATIONS

OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE

INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR

PURPOSE. Triune Systems disclaims all liability arising from this information and its use. Triune System products are not designed, intended, or

authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for

any other application in which the failure of the Triune Systems product could create a situation where personal injury or death may occur. Should the

Buyer purchase or use Triune Systems products for any such unintended or unauthorized application, the Buyer shall indemnify and hold Triune Systems,

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney

fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Triune Systems was negligent regarding the design or manufacture of the part. No licenses are conveyed, implicitly or otherwise, under any

Triune Systems intellectual property rights.

Trademarks

The Triune Systems® name and logo, MPPT-lite™, and nanoSmart® are trademarks of Triune Systems, LLC. in the U.S.A..

All other trademarks mentioned herein are property of their respective companies.