XRT7295AT
DS3/SonetSTS-1
Integrated Line Receiver
Rev.1.20
E2000 EXAR Corporation,48720 KatoRoad,Fremont, CA94538 z(510)668-7000 zFAX (510)668-7017
December2000-2
FEATURES
DFullyIntegrated ReceiveInterfaceforDS3 and
STS-1RateSignals
DIntegrated Equalization (Optional)and Timing
Recovery
DLoss-of-Signaland Loss-of-Lock Alarms
DVariableInputSensitivityControl
D5V PowerSupply
DPinCompatiblewithXRT7295AE and XRT7295AC
DCompanion DevicetoT7296 Transmitter
APPLICATIONS
DInterfacetoDS-3Networks
DDigitalCross-ConnectSystems
DCSU/DSUEquipment
DPCMTestEquipment
DFiberOpticTerminals
GENERALDESCRIPTION
The XRT7295ATDS3/SONETSTS-1integrated line
receiverisafullyintegrated receiveinterfacethat
terminatesa bipolarDS3(44.736Mbps)orSonetSTS-1
(51.84Mbps)signaltransmitted overcoaxialcable.(See
Figure 13).
The device also providesthe functionsofreceive
equalization (optional),automatic-gaincontrol(AGC),
clock-recoveryand dataretiming,loss-of-signaland
loss-of-frequency-lock detection.The digitalsystem
interfaceisdual-rail,withreceived positive and negative
1sappearing asunipolardigitalsignalson separate
outputleads.The on-chip equalizerisdesigned forcable
distancesof0to 450ft. fromthe cross-connect frameto
the device.The receiveinputhasavariableinput
sensitivity control,providing three differentsensitivity
settings, to adaptlongercables.High inputsensitivity
allowsforsignificantamountsof flatloss withinthe
system.Figure 1 showsthe block diagramof the device.
The XRT7295ATdeviceismanufactured using linear
CMOStechnology.The XRT7295ATisavailablein a
20-pin plasticSOJpackage forsurfacemounting.
Twoversionsof the chip are available,one isforeither
DS3 orSTS-1 operation (the XRT7295AT, thisdata
sheet),and the otherisforE3 operation(the XRT7295AE,
refertothe XRT7295AE datasheet).Bothversionsare
pincompatible.
ForeitherDS3 orSTS-1,an inputreferenceclock at
44.736MHzor51.84MHzprovidesthe frequency
referenceforthe device.
ORDERINGINFORMATION
PartNo.PackageOperating
TemperatureRange
XRT7295ATIW20 Lead 300 Mil JEDECSOJ-40°Cto+85°C
XRT7295AT
2
Rev.1.20
BLOCK DIAGRAM
Figure 1.Block Diagram
Attenuator
AGC
Peak
Detector
SlicersPhase
Detector
Loop
FilterVCO
Digital
LOS
Detector
Analog
LOS
Frequency Phase
Aquisition Circuit
Equalizer
Tuning Ckt.
Analog
LOS
Gain&
Equalizer
2
RIN
18 4 5 20 1 11 9 12 10
16
15
7
19
17 3 6 13 8
14
REQB
LOSTHR
ICT TMC1TMC2EXCLKRLOL
RLOS
RNDATA
RPDATA
RCLK
LPF1 LPF2VDDAGNDA VDDDGNDD VDDCGNDC
Retimer
XRT7295AT
3
Rev.1.20
PIN CONFIGURATION
VDDA
LOSTHR
REQB
ICT
GNDA
RIN
TMC1
LPF1
RPDATA
RNDATA
RCLK
EXCLK
LPF2
TMC2
RLOS
RLOL
VDDCGNDD
VDDDGNDC
20 LeadSOJ(Jedec,0.300”)
201
1110
2
3
4
5
6
7
15
14
13
12
17
16
8
9
19
18
PIN DESCRIPTION
Pin#SymbolTypeDescription
1GNDAAnalog Ground.
2RINIReceive Input.Analog receiveinput. Thispinisinternallybiased atabout1.5Vinseries
with 50 kW.
3,6TMC1-TMC2ITestModeControl1 and 2. Internaltestmodesare enabled withinthe device byusing
TMC1 and TMC2.Usersmust tiethese pinstothe ground plane.
4,5 LPF1-LPF2IPLL Filter1 and 2.An externalcapacitor (0.1mF±20%)is connected between these pins.
7RLOSOReceive Loss-of-signal. Thispinis sethigh on loss of the datasignalat the receiveinput.
(See Table 6)
8RLOLOReceive PLL Loss-of-lock.Thispinis sethigh on loss ofPLL frequency lock.
9GNDD DigitalGround forPLL Clock.Ground lead forall circuitryrunning synchronouslywith
PLL clock.
10 GNDC DigitalGround forEXCLK.Ground lead forall circuitryrunning synchronouslywith
EXCLK.
11 VDDD5VDigitalSupply(±10%) forPLL Clock.Powerforall circuitryrunning synchronously
withPLL clock.
12 VDDC5VDigitalSupply(±10%) forEXCLK.Powerforall circuitryrunning synchronouslywith
EXCLK.
13 EXCLKIExternalReference Clock.AvalidDS3(44.736MHz±100ppm)orSTS-1(51.84MHz+
100ppm)clock mustbe provided at thisinput. The duty cycle ofEXCLK,referenced toVDD
/2levels,mustbe within 40%-60%with a minimumrise and fall time(10%to 90%)of5ns.
14 RCLKOReceive Clock.Recovered clock signaltothe terminalequipment.
15 RNDATAOReceive Negative Data.Negative pulse data output tothe terminalequipment. (See
Figure 11.)
16 RPDATAOReceive Positive Data.Positive pulse data output tothe terminalequipment. (See
Figure 11)
17 ICTIIn-circuitTestControl(Active-low). If ICTisforced low,all digitaloutputpins(RCLK,
RPDATA,RNDATA,RLOS,RLOL)are placed in a high-impedancestateto allowforin-cir-
cuit testing.Thereisan internalpull-up on thispin.
18 REQBIReceive Equalization Bypass.Ahigh on thispin bypassesthe internalequalizer.Alow
placesthe equalizerinthe data path.
19 LOSTHR ILoss-of-signalThresholdControl.The voltage forced on thispincontrolsthe inputloss-
of-signalthreshold.Three settingsare provided byforcing GND,VDD/2,orVDD.Thispin
mustbe set tothe desired levelupon power-up and should notbe changed during opera-
tion.
20 VDDA5VAnalog Supply(±10%).
XRT7295AT
4
Rev.1.20
ELECTRICALCHARACTERISTICS
TestConditions:TA=-40°Cto+85°C,VDD =5V+10%
TypicalValues areforVDD =5.0V,25°C,and RandomData.MaximumValues areforVDD =5.5Vall 1s Data.
SymbolParameterMin.Typ.Max.UnitCondition
ElectricalCharacteristics
IDD PowerSupplyCurrent
DS3 82
79
106
103
mA
mA
REQB=0
REQB=1
STS--1 87
83
111
108
mA
mA
REQB=0
REQB=1
LogicInterface Characteristics
InputVoltage
VILLowGNDD 0.5V
VIHHigh VDDD-0.5VDDDV
OutputVoltage
VOLLowGNDD 0.4V-5.0mA
VOHHigh VDDD-0.5VDDDV5.0mA
CIInputCapacitance 10 pF
CLLoad Capacitance 10 pF
ILInputLeakage -10 10 mA-0.5toVDD +0.5V
(all inputpinsexcept2,3,4,5,6,
17,18,&19)
20 500 mA0V(pin 17)
10 100 mA VDD (pin 2)
-50 -5mAGNDD (pin 2)
Specifications are subject tochangewithoutnotice
ABSOLUTEMAXIMUMRATINGS
PowerSupply-0.5Vto+6.5V.....................
Storage Temperature-40°Cto+125°C............
PowerDissipation 700 mW.......................
XRT7295AT
5
Rev.1.20
XR-T7296
Transmitter
Cross
Connect
Frame
DSX-3
orSTSX-1Type 728A
CoaxialCable
0-450 ft.0-450 ft.
SystemA
XRT7295AT
SystemB
Figure 2.Application Diagram
Receiver
SYSTEMDESCRIPTION
Receive PathConfigurations
Inthe receivesignalpath(see Figure 1), the internal
equalizercan be included by setting REQB=0 or
bypassed by setting REQB=1.The equalizerbypass
option allowseasy interfacing of the XRT7295ATdevice
intosystemsalready containing externalequalizers.
Figure 3 illustratesthe receive path options.
InCase1ofFigure 3, the signalfromthe DSX-3
cross-connect feedsdirectlyintoRIN. Inthismode, the
usershouldsetREQB=0,engaging the equalizerinthe
data path.
InCase 2 ofFigure 3,external line build-out(LBO)and
equalizernetworks precede the XRT7295ATdevice. In
thismode, the signalatRINisalreadyequalized,and the
on-chipfilters should be bypassed by setting REQB=1.
In applicationswherethe XRT7295ATdeviceisused to
monitorDS3transmitteroutputsdirectly, the receive
equalizershould be bypassed.
Maximuminputamplitude underall conditionsis850mV
pk.
XRT7295AT
6
Rev.1.20
Figure 3.ReceiverConfigurations
Existing
Off-chip
Networks
0-450 ft.
CASE 2:
D
S
X
225 ft.
LBO
Closed For
225-450 ft.
OfCable
75
0.01mF
0.1mF
RIN
REQBLPF1
LPF2
XRT7295AT
CASE 1:0-450 ft.
RIN
XRT7295AT
REQB
D
S
X
0.01mF
75
0.1mF
LPF1
LPF2
1
0
Fixed
Equalizer
XRT7295AT
7
Rev.1.20
DS3SIGNALREQUIREMENTSAT THEDSX
Pulsecharacteristics arespecified at the DSX-3,whichis
an interconnection and testpointreferred to asthe
cross-connect(see Figure 2.)The cross-connectexists
at the pointwherethe transmitted signalreachesthe
distribution framejack.Table 1 liststhe signal
requirements.Currently, twoisolated pulsetemplate
requirementsexist: the ACCUNET T45 pulsetemplate
(see Table2and Figure 4)and the G.703 pulsetemplate
(see Table 3 and Figure 5).Table 2 and Table 3 givethe
associated boundaryequationsforthe templates.The
XRT7295ATcorrectlydecodesanytransmitted signal
thatmeetsone of thesetemplatesat the cross-connect.
ParameterSpecification
Line Rate44.736 Mbps¦20 ppm
Line Code Bipolarwiththree-0substitution (B3ZS)
TestLoad 75 W¦5%
PulseShape Anisolated pulsemust fit the templateinNOTAGorFigure 5.1The pulse amplitude maybe scaled by
aconstant factortofit the template.The pulse amplitude mustbe between 0.36vpkand 0.85vpk,
measured at the centerof the pulse.
PowerLevelsForand all 1stransmitted pattern, the powerat22.368 ±0.002MHzmustbe -1.8to+5.7dBm,and
the powerat44.736 ±0.002MHzmustbe -21.8dBmto-14.3dBm.2,3
Notes
1The pulsetemplate proposed byG.703 standardsis showninFigure 5 and specified inTable 3.The proposed G.703 standards
furtherstatethat the voltage inatimeslotcontaining a 0 mustnotexceed ±5%of the peakpulse amplitude,except forthe residue
ofpreceding pulses.
2The powerlevels specified bythe proposed G.703 standardsareidenticalexcept that the poweristo be measured in 3kHzbands.
3The all 1spatternmustbe a pure all 1s signal,without framing orothercontrolbits.
Table 1.DSX-3Interconnection Specification
LowerCurve UpperCurve
TimeEquation TimeEquation
T±-0.36 0T±-0.68 0
-0.36 ±T±+0.28 0.5(1+sin{p/2}[1+T/0.18]) -0.68 ±T±+0.36 0.5(1+sin{p/2}[1+T/0.34])
0.28 ±T0.11e-3.42(T-0.3)0.36 ±T0.05 +0.407e-1.84(T-0.36)
Table 2.DSX-3Pulse TemplateBoundaries forACCUNET T45 Standards(See Figure 4.)
XRT7295AT
8
Rev.1.20
Figure 4.DSX-3IsolatedPulse TemplateforACCUNET T45 Standards
1.0
0.8
0.6
0.4
0.2
0-1.0-0.5 0 0.5 1.0 1.5 2.0
TimeSlots-Normalized To Peak Location
NormalizedAmplitude
LowerCurve UpperCurve
TimeFunction TimeFunction
T±-0.36 0T±-0.65 0
-0.36 ±T±+0.28 0.5(1+sin{p/2}[1+T/0.18])-0.65 ±T±01.05 1-e-4.6(T+0.65)
0.28 ±T0.11e-3.42(T-0.3)0±T±0.36 0.5(1+sin{p/2}[1+T/0.34])
0.36 ±T0.05+0.407e-1.84(T-0.36)
Table 3.DSX-3Pulse TemplateBoundaries forG.703 Standards(See Figure 5)
Figure 5.DSX-3IsolatedPulse TemplateforG.703 Standards
1.0
0.8
0.6
0.4
0.2
0-1.0-0.5 0 0.5 1.0 1.5 2.0
TimeSlots-Normalized To Peak Location
NormalizedAmplitude
XRT7295AT
9
Rev.1.20
STS-1SIGNALREQUIREMENTSAT THE STSX
ForSTS-1 operation, the cross-connectisreferred at the
STSX-1.Table 4 liststhe signalrequirementsat the
STSX-1. Instead of the DS3isolated pulsetemplate,an
eye diagram mask is specified forSTS-1 operation
(TA-TSY-000253).The XRT7295ATcorrectlydecodes
anytransmitted signalthatmeetsthe mask shownin
Figure 6 at the STSX-1.
ParameterSpecification
Line Rate 51.84 Mbps
Line Code Bipolarwiththree-0substitution (B3ZS)
TestLoad 75W±5%
PowerLevelsAwide-band powerlevelmeasurement
at the STSX-1interface usingalow-pass
filterwith a 3dBcutoff frequency ofat
least200MHziswithin-2.7 dBmand 4.7
dBm.
Table 4.STSX-1Interconnection Specification
Figure 6.STSX-1IsolatedPulse TemplateforBellcoreTA-TSY-000253
1.0
0.8
0.6
0.4
0.2
0-1.0-0.5 0 0.5 1.0 1.5 2.0
TimeSlots-Normalized To Peak Location
NormalizedAmplitude
LINETERMINATION AND INPUTCAPACITANCE
The recommended receivetermination is shownin
Figure 3 The 75 Wresistorterminatesthe coaxialcable
withits characteristicimpedance.The 0.01mFcapacitor
toRINcouplesthe signal intothe receiveinputwithout
disturbing the internallygenerated DC biaslevelpresent
on RIN.The inputcapacitance at the RINpinis2.8pF
typical.
LOSS LIMITSFROMTHEDSX-3TOTHERECEIVE
INPUT
The signalat the cross-connectmaytravelthrough a
distribution frame,coaxialcable,connector,splitters,and
back planesbeforereaching the XRT7295ATdevice.
This section definesthe maximumdistribution frame and
cableloss fromthe cross-connect tothe XRT7295AT
input.
The distribution framejack mayintroduce 0.6±0.55 dB
ofloss.Thisloss maybe any combination of flator
shaped (cable)loss.
The maximumcable distance between the pointwhere
the transmitted signalexitsthe distribution framejack and
the XRT7295ATdeviceis450 ft. (see Figure 2.)The
coaxialcable(Type 728A)used forspecifying this
distancelimitation hasthe loss and phasecharacteristics
showninFigure 7 and Figure 8.Othercabletypesalso
maybe acceptableifdistancesarescaled tomaintain
cableloss equivalent toType 728Acableloss.
TIMINGRECOVERY
ExternalLoop FilterCapacitor
Figure 3 showsthe connection to an external0.1mF
capacitorat the LPF1/LPF2 pins.This capacitorispartof
the PLL filter.Anon-polarized,low-leakage capacitor
should be used.Aceramic capacitorwiththe value 0.1mF
±20%isacceptable.
XRT7295AT
10
Rev.1.20
OUTPUTJITTER
The total jitterappearing on the RCLKoutputduring
normaloperation consistsof twocomponents.First,
somejitterappearson RCLKbecause ofjitteron the
incoming signal.(The nextsection discussesthe jitter
transfercharacteristic,which describesthe relationship
between inputand outputjitter.)Second,noisesources
withinthe XRT7295ATdevice and noisesourcesthatare
coupled intothe devicethrough the powersuppliesand
data pattern dependentjitterdue tomisequalization of the
inputsignal,all createjitteron RCLK.The magnitude of
thisinternallygenerated jitterisafunction of the PLL
bandwidth,whichinturnisafunction of the input1s
density.Forhigher1sdensity, the amountofgenerated
jitterdecreases.Generated jitteralso dependson the
qualityof the powersupplybypassing networks used.
Figure 12 showsthe suggested bypassing network,and
Table5liststhe typicalgenerated jitterperformance.
Figure 7.Loss Characteristicof728A
CoaxialCable(450 ft.)
Figure 8.Phase Characteristicof728A
CoaxialCable(450 ft.)
12
10
8
6
4
2
01.0 2.0 5.0 10 20 50 100
Frequency (MHz)
100
80
60
40
20
01.02.0 5.0 10 20 50 100
Frequency (MHz)
Loss (dB)
Phase (Degree)
JITTERTRANSFER CHARACTERISTIC
The jittertransfercharacteristicindicatesthe fraction of
inputjitterthatreachesthe RCLKoutputasafunction of
inputjitterfrequency.Table 5 showsImportantjitter
transfercharacteristicparameters.Figure 9 alsoshowsa
typicalcharacteristic,withthe operating conditionsas
described inTable 5.Although existing standardsdo not
specifyjittertransfercharacteristicrequirements, the
XRT7295ATinformation isprovided hereto assistin
evaluation of the device.
ParameterTypMax Unit
Generated Jitter1
All 1spattern 1.0 nspeak-to-peak
Repetitive“100”
pattern1.5 nspeak-to-peak
JitterTransfer
C
h
a
r
a
c
t
e
r
i
s
t
i
c
2
C
h
a
r
a
c
t
e
r
i
s
t
i
c
2
Peaking
0
.
0
5
d
B
P
e
a
k
i
n
g
f3dB
0
.
0
5
205
d
B
kHz
Notes
1Repetitiveinputdata pattern atnominalDSX-3levelwithVDD
=5VTA=25°C.
2Repetitive“100 ”inputatnominalDSX-3levelwithVDD =5V,
TA=25°C.
Table 5.GeneratedJitterand JitterTransfer
Characteristics
XRT7295AT
11
Rev.1.20
JITTER ACCOMMODATION
Underall allowable operating conditions, the jitter
accommodation of the XRT7295ATdevice exceedsall
systemrequirementsforerror-free operation
(BER<1E-9).The typical(VDD =5V,T=25°C,DSX-3
nominalsignal level)jitteraccommodation forthe
XRT7295ATis showninFigure 10.
FALSE-LOCK IMMUNITY
False-lock isdefined asthe condition whereaPLL
recovered clock obtains stable phase-lock atafrequency
notequaltothe incoming datarate.The XRT7295AT
device usesacombination frequency/phase-lock
architectureto prevent false-lock.An on-chipfrequency
comparatorcontinuously comparesthe EXCLKreference
tothe PLL clock. If the frequency difference between the
EXCLKand PLL clock exceedsapproximately±0.5%,
correction circuitryforcesre-acquisition of the proper
frequency and phase.
ACQUISITIONTIME
If avalidinputsignal isassumed to be alreadypresentat
RIN, the maximumtime between the application ofdevice
powerand error-free operation is20ms. If powerhas
alreadybeen applied, the intervalbetween the application
ofvalid data(orthe action ofvalid datafollowing a loss of
signal)and error-free operation is4ms.
LOSS-OF-LOCK DETECTION
As stated above, the PLL acquisitionaidcircuitrymonitors
the PLL clock frequency relativetothe EXCLKfrequency.
The RLOL alarmisactivated if the difference between the
PLL clock and the EXCLKfrequency exceeds
approximately±0.5%.
Thiswill notoccuruntil atleast250 bitperiodsafterloss of
inputdata.
Figure 9.TypicalPLL JitterTransfer
Characteristic
1
0
-5
-4
-3
-2
-1
100 500 1K5K10K50K100K500K
PEAK =0.05dB
f3dB=205kHz
Frequency (Hz)
MagnitudeResponse (dB)
1 10 100 1K10K100K1000K
40
10
1.0
0.1
XRT7295AT Typical
PUB54014
G.824
TR-TSY-000499
Category1
TR-TSY-000499
Category2
5k10
10k5
60k1
300k0.5
1M0.4
XRT7295AT Typical
Sinewave JitterFrequency (Hz)
Figure 10. InputJitterTolerance atDSX-3Level
Jitter
Frequency
(Hz)
Jitter
Amplitude
(U.I.)
Peak-Peak Sinewave Jitter(U.I.)
XRT7295AT
12
Rev.1.20
Ahigh RLOL outputindicatesthat the acquisition circuitis
working to bring the PLL into properfrequency lock.
RLOLremainshigh until frequency lock hasoccurred;
however, the minimumRLOL pulsewidthis32 clock
cycles.
PHASE HITS
Inresponseto a phase hitinthe inputdata, the
XRT7295ATreturnsto errorfree operation inless than
2ms.During the requisition time,RLOSmaytemporarily
be indicated.
LOSS-OF-SIGNALDETECTION
Figure 1 showsthatanalog and digitalmethodsof
loss-of-signal(LOS)detection arecombined tocreatethe
RLOSalarmoutput. RLOSis setifeitherthe analog or
digitaldetection circuitryindicatesLOShasoccurred.
ANALOG DETECTION
The analog LOSdetectormonitorsthe peakinputsignal
amplitude.RLOSmakesa high-to-lowtransition (input
signalregained)when the inputsignalamplitude exceeds
the loss-ofsignalthreshold defined inTable 6.The RLOS
low-to-high transition (inputsignal loss)occursatalevel
typically1.0 dBbelowthe high-to-lowtransition level.The
hysteresispreventsRLOSchattering.Onceset, the
RLOSalarmremainshigh foratleast32 clock cycles,
allowing forsystemdetection ofa LOScondition without
the use ofan external latch.
To allowforvarying levelsofnoise and crosstalkin
differentapplications, three loss-of-signalthreshold
settingsare available using the LOSTHR pin.Setting
LOSTHR =VDD providesthe lowestloss-of-signal
threshold;LOSTHR =VDD/2(can be produced using two
50 kW±10%resistorsasavoltage dividerbetween
VDDDand GNDD)providesan intermediatethreshold;
and LOSTHR =GND providesthe highest threshold.The
LOSTHR pinmustbe set toitsdesired value atpower-up
and mustnotbe changed during operation.
DIGITALDETECTION
In addition tothe signalamplitude monitoring of the
analog LOSdetector, the digitalLOSdetectormonitors
the recovered data 1sdensity.The RLOSalarmgoes
high if160 ±32 ormoreconsecutive 0soccurinthe
receive datastream.The alarmgoeslow when atleast
ten 1soccurin a string of32 consecutive bits.This
hysteresispreventsRLOSchattering and guaranteesa
minimumRLOSpulsewidth of32 clock cycles.Note,
however, thatRLOSchattercan still occur.When
REQB=1,inputsignal levelsabovethe analog RLOS
thresholdcan still be lowenoughtoresultinahigh biterror
rate.The resultantdatastream(containing)errors can
temporarilyactivatethe digitalLOSdetector,and RLOS
chattercan occur.Therefore,RLOSshould notbe used
asa biterror ratemonitor.
RLOSchattercan also occurwhen RLOLisactivated
(high).
XRT7295AT
13
Rev.1.20
Data
RateREQBLOSTHR Min.
ThresholdMax.
ThresholdUnit
DS3 0 0 60 220 mVpk
VDD/2 40 145 mVpk
VDD 25 90 mVpk
1 0 45 175 mVpk
VDD/2 30 115 mVpk
VDD 20 70 mVpk
STS-1 0 0 75 275 mVpk
VDD/2 50 185 mVpk
VDD 30 115 mVpk
1 0 55 220 mVpk
VDD/2 35 145 mVpk
VDD 25 90 mVpk
Notes
-Lowerthresholdis1.5 dBbelowupperthreshold.
-The RLOSalarmisan indication of the absence ofan inputsignal,nota biterror rateindication(independentof the RLOSstate).The
devicewill attempt torecovercorrect timing data.The RLOSlow-to-high transition typicallyoccurs1dBbelowthe high tolowtransi-
tion.
Table 6.Analog Loss-of-SignalThresholds
RECOVERED CLOCK AND DATATIMING
Table 7 and Figure 11 summarizethe timing relationships
between the logic signalsRCLK,RPDATA,and RNDATA.
The duty cycleisreferenced toVDD/2thresholdlevel.
RPDATAand RNDATAchange on the rising edge of
RCLKand arevalid during the falling edge ofRCLK.A
positive pulse atRINcreatesa high levelon RPDATAand
alowlevelon RNDATA.Anegative pulse at the input
createsa high levelon RNDATAand a lowlevelon
RPDATA,and a received zero produceslowlevelson
bothRPDATAand RNDATA.
IN-CIRCUIT TESTCAPABILITY
When pulled low, the ICTpinforcesall digitaloutput
buffers(RCLK,RPDATA,RNDATA,RLOS,RLOL pins)to
be placed in a high outputimpedancestate.Thisfeature
allowsin-circuit testing to be done on neighboring devices
withoutconcernforXRT7295ATdevice bufferdamage.
Aninternalpull-up device(nominally50kW)isprovided on
thispintherefore,users can leavethispin unconnected
fornormaloperation.Testequipmentcan pull ICTlow
during in-circuit testing withoutdamaging the device.
Thisisthe onlypinforwhichinternalpull-up/pull-downis
provided.
XRT7295AT
14
Rev.1.20
TIMINGCHARACTERISTICS
TestConditions:All Timing Characteristics areMeasruredwith10pF Loading,-40°C±TA±+85°C,VDD =
5V±10%
SymbolParameterMin TypMax Unit
tRCH1RCH2Clock RiseTime(10%-90%)4 ns
tRCL2RCL1 Clock Fall Time(10%-90%)4 ns
tRCHRDVReceivePropagation Delay10.6 3.7 ns
Clock DutyCycle 45 50 55 %
Table 7.SystemInterface Timing Characteristics
Figure 11.Timing DiagramforSystemInterface
RCLK
RPDATA
OR
RNDATA
(RC)
(RD)
tRCHRDVtRCL2RCL1 tRCH1RCH2
tRCLRDX
tRDVRCL
BOARD LAYOUTCONSIDERATIONS
PowerSupplyBypassing
Figure 12 illustratesthe recommended powersupply
bypassing network.A0.1mFcapacitorbypassesthe
digitalsupplies.The analog supplyVDDAisbypassed by
using a 0.1mFcapacitorand a shield bead thatremoves
significantamountsofhigh-frequencynoise generatedby
the systemand bythe devicelogic.Good quality,
high-frequency (lowlead inductance)capacitors should
be used.Finally,itismostimportant thatall ground
connectionsbe made toalow-impedance ground plane.
Receive Input
The connectionstothe receiveinputpin,RIN,mustbe
carefully considered.Noise-coupling mustbe minimized
along the pathfromthe signalentering the boardtothe
inputpin.Anynoisecoupled intothe XRT7295ATinput
directlydegradesthe signal-to-noiseratio of the input
signaland maydegrade sensitivity.
PLL FilterCapacitor
The PLL filtercapacitorbetween pinsLPF1 and LPF2
mustbe placedas closetothe chip aspossible.The LPF1
and LPF2 pinsare adjacent, allowing forshortlead
lengthswithnocrossoverstothe externalcapacitor.
Noise-coupling intothe LPF1 and LPF2 pinsmay
degrade PLL performance.
Handling Precautions
Although protection circuitryhasbeen designed intothis
device,properprecautions shouldbetaken to avoid
exposureto electrostaticdischarge (ESD)during
handling and mounting.
XRT7295AT
15
Rev.1.20
C4
SensitiveNode
ShieldBead1
+5V
C6
GNDA VDDA
GNDD
GNDC
VDDC
VDDD
0.1mF
XRT7295AT
0.1mF
Figure 12.RecommendedPowerSupply
Bypassing Network
Notes
1Recommended shield beadsarethe Fair-Rite
2643000101 orthe Fair-Rite 2743019446 (surface
mount).
COMPLIANCE SPECIFICATIONS
DCompliancewithAT&TPublication 54014,“ACCU-
NETRT45 ServiceDescription and InterfaceSpec-
ifications,”June 1987.
DCompliancewithANSIStandardT1.102-1989,
“DigitalHierarchy-ElectricalInterfaces,”1989.
DCompliancewithCompatibilityBulletin 119,
“Interconnection Specification forDigital
Cross-Connects,”October1979.
DCompliancewithCCITT RecommendationsG.703
and G.824,1988.
DCompliancewithTR-TSY-000499,“TransportSys-
temsGenericRequirements(TSGR):Common Re-
quirements,”December1988.
DCompliancewithTA-TSY-000253,“Synchronous
OpticalNetwork(SONET)TransportSystemGener-
icCriteria,”February1990.
XRT7295AT
16
Rev.1.20
1
5
1
6
1
4
1
3
1
2
1
1
1
0
9
2 1 3 4 5 6 7 8
R22
22K
VCC
VCC
L
O
S
T
H
R
1
2
3
4
5
6
7
8
R21
22K
1234
865
S1
SWDIP-4
RLOS
TP
RLOL
TP
RECEIVER
MONITOR
OUTPUTS
RLOL
8
RLOS
7
RIN
2
EXCLK
13
V
D
D
A
20
V
D
D
C
1
2
V
D
D
D
1
1
GNDD 9
GNDC 10
GNDA1
REQB18
14
RNDATA15
RPDATA16
TMC13
TMC26
LPF1
4
LPF2
5
LOSTHR 19
ICT/17
C2
0.01mF
R2
75
R6
75
INPUT
SIGNAL
EXTERNAL
CLOCK
B1
B2
R1 50
R5 50
R8 39
R10 39
R739
B5
TCLK
P2
GND
V
D
D
A
V
D
D
D
6
LLOOP3
RLOOP2
DS3,STS-1/E3/4
TAOS5
ICT/26
TXLEV 25
ENCODIS11
DECODIS12
RCLK
RNDATA
28
RPDATA
27
DMO
18
BPV
13
TNDATA
8
TCLK
9
TPDATA
7
GNDA21
GNDD 10
MTIP20
MRING19
TTIP23
TRING22
RCLKO17
RPOS16
RNEG15
RNRZ14
U2
XRT7296
RNEG
RCLKO
RPOS
LLOOP
RLOOP
T3/E3
TAOS
TXLEV
ICT
ENCODIS
DECODIS
RECEIVER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S2
SWDIP-8
OUTPUTS
R3 36
R4 36 T1
PE65966
B6
TRING
TTIP
R15 270
R16 270
RNRZ
B4
TNDATA
B3
TPDATA
C6
0.1mF
C3
0.1mF
C4
0.1mF
BT1
FERRITE BEAD
FERRITE BEAD#FAIR RITE2643000101
C7
0.1mF
E1
22mF
P1
VCC RX
TRANSMITER
MONITOR
OUTPUTS
DMO
BPV
C9
0.1mFE2
22mF
C8
0.1mF
TRANSFORMER#PULSE ENGINEERING
BT2
FERRITE BEADC5
0.1mF
PE 65966
PE 65967 INSURFACEMOUNT
VCC TX
U1
XRT7295AT
7
RCLK
P3
R
E
Q
B
I
C
T
+
+
1
24
Figure 13.TypicalApplication Schematic
XRT7295AT
17
Rev.1.20
SYMBOLMINMAXMINMAX
A0.145 0.200 3.60 5.08
A10.025 --- 0.64 ---
A20.120 0.140 3.05 3.56
B0.014 0.020 0.36 0.51
C0.008 0.013 0.20 0.30
D0.496 0.512 12.60 13.00
E0.292 0.300 7.42 7.62
E10.262 0.272 6.65 6.91
e 0.050 BSC1.27 BSC
H0.335 0.347 8.51 8.81
R0.030 0.040 0.76 1.02
INCHES MILLIMETERS
e
20 11
20 LEAD SMALL OUTLINEJLEAD
(300 MILJEDECSOJ)
Rev.1.00
10
D
EH
BA1
Seating
Plane
Note:The controldimension isthe inchcolumn
1
A2A
CR
E1
XRT7295AT
18
Rev.1.20
NOTICE
EXAR Corporation reservesthe right tomakechangestothe products contained inthispublication in ordertoim-
prove design,performance or reliability.EXAR Corporation assumesno responsibilityforthe use ofany circuitsde-
scribed herein,conveys no license underanypatentorother right, and makesno representation that the circuitsare
free ofpatentinfringement. Chartsand schedules contained herein are onlyforillustration purposesand may vary
depending upon a user’s specificapplication.Whilethe information inthispublication hasbeen carefully checked;
no responsibility,however,isassumed forinaccuracies.
EXAR Corporation doesnotrecommend the use ofanyofitsproductsinlifesupportapplicationswherethe failure or
malfunction of the productcan reasonablybe expected tocausefailure of the lifesupportsystemortosignificantly
affectits safetyoreffectiveness.Productsare notauthorized foruseinsuch applicationsunless EXAR Corporation
receives,inwriting,assurancestoits satisfaction that: (a)the risk ofinjuryordamage hasbeen minimized;(b)the
userassumesall suchrisks;(c)potential liabilityofEXAR Corporation isadequatelyprotected underthe circum-
stances.
Copyright2000 EXAR Corporation
DatasheeteDecember2000
Reproduction,in partorwhole,without the priorwritten consentofEXAR Corporation isprohibited.
