Nonvolatile Memory 1-Kbit E7PROM SDA 2116 Preliminary data Type | Ordering code | Package SDA 2116 | Q67100-A2128 | DIP 8 Features @ Word-organized programmable nonvolatile memory in n-channel floating-gate technology @ 128 x 8 bit organization @ Supply voltage 5 Vv, programming voltage 24 V @ A total of 3 lines provides data transfer and chip control between processing unit and E2PROM @ Data (8 bits), address (7 bits) and control information input (1 bit) as well as serial data output @ More than 10? reprogramming cycles per address @ Data retention in excess of 10 years (within specified operating temperature range) @ Unlimited number of reads without refresh @ Erase and write cycle in 50 ms each Maximum ratings Supply voltage 1 range Voc 0.3 to 6 Vv Supply voltage 2 range Vpp 0.3 to 26 Vv Input voltage range V 0.3 to 6 Vv Power dissipation Py 75 mW Storage temperature range Tstg 40 to 125 Cc Thermal resistance {system-air) Rithsa 100 K/W Operating range Supply voltage Voc 4.5 to 5.5 V Ambient temperature Ta Oto 70 c 146SDA 2116 Static characteristics min typ max Supply voltage 1 Voc 4.5 5 5.5 Vv Supply current 1 loc 5 mA Supply voltage 2 Vpp 22.81) 241) 25.67 | V Supply current 2 Ip 2 mA Inputs Ve 0.5 Vv (D,@, CE) Vu 3.0 V Vi=5.5V qy 10 pA Data output D (open drain) V=0.5V { 0.5 mA Vya=5.5V qIy 10 pA Clock pulse @ High duration @, 2.5 60 ps Low duration before/after ,, GD 5 ps before/after CE transition G. 5 ys before/after D change o, 2.5 ps Data D before/after trailing edge Dy 2.5 HS DL 2.5 us Time between rising and trailing edge CE referenced to D At 2.5 ps Erase time ter 50 100 ms Write time twr 50 100 ms 1) Voltage peaks higher than the static value of Vpp must be avoided, e.g. by a Z diode between the inputs 6 and 1. 147 MI Be . ~~SDA 2116 Block diagram Control Unit Pin description Row Deco- der Column Decoder Gate Control Data Latch D7 Memory Drain Control Address/ Control Latch Pin Symbol Function 1 Ves GND 2 CE Chip enable 3 Voc Supply voltage 5 V 4 D Data input/output 5 @ Clock input 6 Vpp Programming voltage 24 V 7 TP Test input, to Veg 8 TG Test input, remains open 148SDA 2116 Data transfer and chip control Total data transfer between processing unit and E2PROM memory requires 3 lines, each of which has several functions. a) Data tine D: - bidirectional serial data transfer - serial address input - clocked input of control information - direct control input b) Clock line @: data, address and control bit input data output - start data output with data transfer from memory into the shift register, or start data change when reprogramming. c) Chip enable line CE: - chip reset and data input (active high) - chip activating (active low) The data address and contro! information is clocked into the chip before the chip is enabled. This data remains stored in the shift register during reprogramming and reading, until the second clock pulse has been received. The following data must be applied: a) Memory read: One 8-bit control word comprising 7 address bits AO to AG (AO as LSB first) - 1 control bit, SB =0, after A6 b) Memory change (Erase and/or write) 16 bits input information comprising - 8 bits, DO to D7, is new memory information (DO as LSB first) ~ 7 bits, AO to A6, is address information (AO as LSB after D7 first) 1 bitis control information, SB = 1, after A6 Read (figure 1) After the negative edge of CE and the data input is received, the read operation starts through the selected word address when SB =0. With the first clock pulse after GE = 0, the data word is transferred out of the selected memory address into the shift register. After the first -pulse has been terminated, the data output becomes low in impedance and the first data bit DO can be read. With each following clock pulse, a further data bit will be passed on to the output. The data line again turns high in impedance after the positive edge of CE. 149SDA 2116 Reprogramming (figure 2) A complete reprogramming operation normally consists of an erase cycle and a following write cycle. During erase every bit of the selected word will become 1 and during write each bit of the word becomes 0 according to the information in the shift register. After the chip has received the data and then been enabled, reprogramming starts if SB = 1 is present in the relevant cell of the shift register. Whether an erase or write cycle is triggered, depends on the information of the data line D during chip activation. Erasing a word into the 1-status requires a 1 at the data input during the negative edge CE. Should, however, a write cycle into O-status be started, then a O must be on the data line during negative edge of CE. To start programming a start pulse must be applied to clock input, and the control information at D must remain stable until its positive edge is received. The active data change starts with the trailing edge of this start pulse. The programming cycle will be terminated by a reset of the chip enable; e.g. by applying CE = 1. The reprogramming of a word begins with the erase procedure. CE = 1 ends the erase cycle. The control bit in the shift register SB = 1 , which is also required for the write cycle, remains stable even after termination of erase cycle. In order to write the selected word, the data line D must be switched from 1 to 0, the chip must again be activated with CE = 0 and with the aid ofa Start pulse, the data change can be started. Erase and write can, of course, also be done separately. To obtain a stable 1 in all 8 bits of the selected memory address during erasing, a data word with all bits 1 must be read in before the erasing process begins. If data is written into a previously not erased memory word the O status of the old and the new information will be added. Reset and supply voltages A non-addressed memory automatically remains in reset position through CE = 1. All flipflops in the process control section are reset. The information in the shift register, however, remains stable and will only be changed by shifting data. If it is not possible to ensure a defined position for the signal states (quiescent state CE = high, = low) during switch-on and switch-off of the supply voltages, data loss occuring during unintentional decoding-out of Program instructions can be avoided by enabling Vpp after Vo, and disabling it before Voc. ~~ I 7 ETC wr wn eeSDA 2116 Read cycle (1-Kbit E27 PROM) . 7 0 S @ ; [1\ [\ [s\ ~ [2\ /s\ 0) YOK TEAK CHG 2 eS Data Input, Address and Start * Data at Output Data Control Bit Transfer Figure 1 Reprogramming cycle (1-Kbit E7PROM) Spel De" 0:0" ASS Data Input, Data Word, Start | | Start | twr | Address and Control Bit | Erase ter Write Figure 2 151