1
FEATURES
1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
D OR P PACKAGE
(TOP VIEW)
DESCRIPTION
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007www.ti.com
POWER-DISTRIBUTION SWITCHES
•UL Listed - File No. E169910•33-m Ω(5-V Input) High-Side MOSFET Switch•Short-Circuit and Thermal Protection•Overcurrent Logic Output•Operating Range . . . 2.7 V to 5.5 V•Logic-Level Enable Input•Typical Rise Time . . . 6.1 ms•Undervoltage Lockout•Maximum Standby Supply Current . . . 10 μA•No Drain-Source Back-Gate Diode•Available in 8-Pin SOIC and PDIP Packages•Ambient Temperature Range, – 40 °C to 85 °C•2-kV Human-Body-Model, 200-VMachine-Model ESD Protection
The TPS202x family of power distribution switches is intended for applications where heavy capacitive loads andshort circuits are likely to be encountered. These devices are 50-m ΩN-channel MOSFET high-side powerswitches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive isprovided by an internal charge pump designed to control the power-switch rise times and fall times to minimizecurrent surges during switching. The charge pump requires no external components and allows operation fromsupplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS202x limits the outputcurrent to a safe level by switching into a constant-current mode, pulling the overcurrent ( OC) logic output low.When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing thejunction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from athermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switchremains off until valid input voltage is present.
The TPS202x devices differ only in short-circuit current threshold. The TPS2020 limits at 0.3-A load, theTPS2021 at 0.9-A load, the TPS2022 at 1.5-A load, the TPS2023 at 2.2-A load, and the TPS2024 at 3-A load(see Available Options ). The TPS202x is available in an 8-pin small-outline integrated-circuit (SOIC) packageand in an 8-pin dual in-line package (DIP) and operates over a junction temperature range of – 40 °C to 125 °C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
†Current Sense
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Table 1. AVAILABLE OPTIONS
PACKAGED DEVICESRECOMMENDED MAXIMUM TYPICAL SHORT-CIRCUITT
A
ENABLE CONTINUOUS LOAD CURRENT LIMIT AT 25 °C
SMALL OUTLINE PLASTIC DIPCURRENT (A) (A)
(D)
(1)
(P)
0.2 0.3 TPS2020D TPS2020P0.6 0.9 TPS2021D TPS2021P– 40 °C to 85 °C Active low 1 1.5 TPS2022D TPS2022P1.5 2.2 TPS2023D TPS2023P2 3 TPS2024D TPS2024P
(1) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2020DR)
TPS2020 FUNCTIONAL BLOCK DIAGRAM
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNO.NAME
D OR P
EN 4 I Enable input. Logic-low turns on power switch.GND 1 I GroundIN 2, 3 I Input voltageOC 5 O Overcurrent. Logic output, active-lowOUT 6, 7, 8 O Power-switch output
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DETAILED DESCRIPTION
POWER SWITCH
CHARGE PUMP
DRIVER
ENABLE ( EN)
OVERCURRENT ( OC)
CURRENT SENSE
THERMAL SENSE
UNDERVOLTAGE LOCKOUT
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 m Ω(V
I(IN)
= 5 V).Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT whendisabled.
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gateof the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requiresvery little supply current.
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associatedelectromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and falltimes of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce thesupply current to less than 10 μA when a logic-high is present on EN. A logic-zero input on EN restores bias tothe drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOSlogic levels.
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition isencountered. The output remains asserted until the overcurrent or overtemperature condition is removed.
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently thanconventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitrysends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET intoits saturation region, which switches the output into a constant-current mode and holds the current constant whilevarying the voltage on the load.
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately140 °C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20 °C, theswitch turns back on. The switch continues to cycle off and on until the fault is removed.
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a controlsignal turns off the power switch.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
over operating free-air temperature range (unless otherwise noted)
(1)
V
I(IN)
(2)
Input voltage range – 0.3 V to 6 VV
O(OUT)
(2)
Output voltage range – 0.3 V to V
I(IN)
+ 0.3 VV
I(EN)
Input voltage range – 0.3 V to 6 VI
O(OUT)
Continuous output current Internally limitedContinuous total power dissipation See Dissipation Rating TableT
J
Operating virtual junction temperature range – 40 °C to 125 °CT
stg
Storage temperature range – 65 °C to 150 °CLead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 °CElectrostatic discharge (ESD) protection: Human body model 2 kVMachine model 200 VCharged device model (CDM) 750 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
DISSIPATION RATING TABLE
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
D 725 mW 5.8 mW/ °C 464 mW 377 mWP 1175 mW 9.4 mW/ °C 752 mW 611 mW
MIN MAX UNIT
V
I(IN)
2.7 5.5 VInput voltageV
I(EN)
0 5.5 VTPS2020 0 0.2TPS2021 0 0.6I
O
Continuous output current TPS2022 0 1 ATPS2023 0 1.5TPS2024 0 2T
J
Operating virtual junction temperature – 40 125 °C
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ELECTRICAL CHARACTERISTICS
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= rated current, EN = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
POWER SWITCH
V
I(IN)
= 5 V, T
J
= 25 °C, I
O
= 1.8 A 33 36V
I(IN)
= 5 V, T
J
= 85 °C, I
O
= 1.8 A 38 46V
I(IN)
= 5 V, T
J
= 125 °C, I
O
= 1.8 A 44 50V
I(IN)
= 3.3 V, T
J
= 25 °C, I
O
= 1.8 A 37 41V
I(IN)
= 3.3 V, T
J
= 85 °C, I
O
= 1.8 A 43 52V
I(IN)
= 3.3 V, T
J
= 125 °C, I
O
= 1.8 A 51 61Static drain-source on-stater
DS(on)
mΩresistance
V
I(IN)
= 5 V, T
J
= 25 °C, I
O
= 0.18 A 30 34V
I(IN)
= 5 V, T
J
= 85 °C, I
O
= 0.18 A 35 41V
I(IN)
= 5 V, T
J
= 125 °C, I
O
= 0.18 A 39 47V
I(IN)
= 3.3 V, T
J
= 25 °C, I
O
= 0.18 A 33 37V
I(IN)
= 3.3 V, T
J
= 85 °C, I
O
= 0.18 A 39 46V
I(IN)
= 3.3 V, T
J
= 125 °C, I
O
= 0.18 A 44 56V
I(IN)
= 5.5 V, C
L
= 1 μF, T
J
= 25 °C, R
L
= 10 Ω6.1t
r
Rise time, output msV
I(IN)
= 2.7 V, C
L
= 1 μF, T
J
= 25 °C, R
L
= 10 Ω8.6V
I(IN)
= 5.5 V, C
L
= 1 μF, T
J
= 25 °C, R
L
= 10 Ω3.4t
f
Fall time, output msV
I(IN)
= 2.7 V, C
L
= 1 μF, T
J
= 25 °C, R
L
= 10 Ω3
ENABLE INPUT ( EN)
V
IH
High-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 2 V4.5 V ≤V
I(IN)
≤5.5 V 0.8V
IL
Low-level input voltage V2.7 V ≤V
I(IN)
≤4.5 V 0.5I
I
Input current EN= 0 V or EN = V
I(IN)
– 0.5 0.5 μAt
on
Turnon time C
L
= 100 μF, R
L
= 10 Ω20
mst
off
Turnoff time C
L
= 100 μF, R
L
= 10 Ω40
CURRENT LIMIT
TPS2020 0.22 0.3 0.4TPS2021 0.66 0.9 1.1T
J
= 25 °C, V
I
= 5.5 V,I
OS
Short-circuit output current OUT connected to GND, TPS2022 1.1 1.5 1.8 ADevice enabled into short circuit
TPS2023 1.65 2.2 2.7TPS2024 2.2 3 3.8
SUPPLY CURRENT
T
J
= 25 °C 0.3 1Supply current, low-level output No load on OUT EN = V
I(IN)
μA– 40 °C≤T
J
≤
10125 °CT
J
= 25 °C 58 75Supply current, high-level output No load on OUT EN = 0 V μA– 40 °C≤T
J
≤
75 100125 °COUT connected – 40 °C≤T
J
≤Leakage current EN = V
I(IN)
10 μAto ground 125 °C
UNDERVOLTAGE LOCKOUT
Low-level input voltage 2 2.5 VHysteresis T
J
= 25 °C 100 mV
OVERCURRENT ( OC)
Output low voltage I
O
= 10 mA, V
OL(OC)
0.4 VOff-state current
(2)
V
O
= 5 V, V
O
= 3.3 V 1 μA
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
(2) Specified by design, not production tested.
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PARAMETER MEASURMENT INFORMATION
RL CL
OUT
trtf
90% 90%
10%
10%
50% 50%
90%
10%
VO(OUT)
VI(EN)
VO(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton toff
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 1. Test Circuit and Voltage Waveforms
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TABLE OF TIMING DIAGRAMS
24 6 8 10 12 14 16 18 20
t − Time − ms
0
VIN = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
VI(EN) (5 V/div)
2 4 6 8 10 12 14 16 18 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
PARAMETER MEASURMENT INFORMATION (continued)
FIGURE
Turnon Delay and Rise TIme 2Turnoff Delay and Fall Time 3Turnon Delay and Rise TIme with 1- μF Load 4Turnoff Delay and Rise TIme with 1- μF Load 5Device Enabled into Short 67, 8, 9, 10,TPS2020, TPS2021, TPS2022, TPS2023, and TPS2024, Ramped Load on Enabled Device
11TPS2024, Inrush Current 127.9- ΩLoad Connected to an Enabled TPS2020 Device 133.7- ΩLoad Connected to an Enabled TPS2020 Device 143.7- ΩLoad Connected to an Enabled TPS2021 Device 152.6- ΩLoad Connected to an Enabled TPS2021 Device 162.6- ΩLoad Connected to an Enabled TPS2022 Device 171.2- ΩLoad Connected to an Enabled TPS2022 Device 181.2- ΩLoad Connected to an Enabled TPS2023 Device 190.9- ΩLoad Connected to an Enabled TPS2023 Device 200.9- ΩLoad Connected to an Enabled TPS2024 Device 210.5- ΩLoad Connected to an Enabled TPS2024 Device 22
Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time
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24 6 8 10 12 14 16 18 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
24 6 8 10 12 14 16 18 20
t − Time − ms
VI(EN) (5 V/div)
0
VI(IN) = 5 V
CL = 1 µF
RL = 27 Ω
TA = 25°C
VO(OUT) (2 V/div)
VI(EN)
VO(OUT)
12 3 4 5 6 7 8 9 10
t − Time − ms
VI(EN) (5 V/div)
0
IO(OUT) (1 A/div)
VI(EN)
IO(OUT)
VI(IN) = 5 V
TA = 25°CTPS2024
TPS2023
TPS2022
TPS2021
TPS2020
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (500 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 4. Turnon Delay and Rise Time with 1- μF Load Figure 5. Turnoff Delay and Fall Time with 1- μF Load
Figure 6. Device Enabled Into Short Figure 7. TPS2020, Ramped Load on Enabled Device
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20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
20 40 60 80 100 120 140 160 180 200
t − Time − ms
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
TA = 25°C
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 8. TPS2021, Ramped Load on Enabled Device Figure 9. TPS2022, Ramped Load on Enabled Device
Figure 10. TPS2023, Ramped Load on Enabled Device Figure 11. TPS2024, Ramped Load on Enabled Device
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1 2 3 4 5 6 7 8 9 10
t − Time − ms
0
II(IN) (500 mA/div)
VI(EN)
II(IN) RL = 10 Ω
TA = 25°C
VI(EN) (5 V/div)
470 µF
47 µF
150 µF
200 400 600 800 1000 12001400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (200 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 7.9 Ω
TA = 25°C
50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (500 mA/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
200 400 600 800 1000 12001400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 3.7 Ω
TA = 25°C
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 12. TPS2024, Inrush Current Figure 13. 7.9- ΩLoad Connected to an Enabled TPS2020Device
Figure 14. 3.7- ΩLoad Connected to an Enabled TPS2020 Figure 15. 3.7- ΩLoad Connected to an Enabled TPS2021Device Device
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50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
200 400 600 800 1000 12001400 1600 1800 2000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 2.6 Ω
TA = 25°C
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (1 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (2 A/div)
VO(OC)
IO(OUT) VI(IN) = 5 V
RL = 1.2 Ω
TA = 25°C
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 16. 2.6- ΩLoad Connected to an Enabled TPS2021 Figure 17. 2.6- ΩLoad Connected to an Enabled TPS2022Device Device
Figure 18. 1.2- ΩLoad Connected to an Enabled TPS2022 Figure 19. 1.2- ΩLoad Connected to an Enabled TPS2023Device Device
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100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (2 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
100 200 300 400 500 600 700 800 900 1000
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (5 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.9 Ω
TA = 25°C
50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO(OC) (5 V/div)
0
IO(OUT) (5 A/div)
VO(OC)
IO(OUT)
VI(IN) = 5 V
RL = 0.5 Ω
TA = 25°C
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 20. 0.9- ΩLoad Connected to an Enabled TPS2023 Figure 21. 0.9- ΩLoad Connected to an Enabled TPS2024Device Device
Figure 22. 0.5- ΩLoad Connected to an Enabled TPS2024Device
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TYPICAL CHARACTERISTICS
4.5
4
3.5 2.5 3 3.5 4 4.5
− Turn-on Delay Time − ms
5
5.5
7.5
5 5.5 6
VI − Input Voltage − V
td(on)
6
6.5
7TA = 25°C
CL = 1 µF
17
16.5
162.5 3 3.5 4 4.5
17.5
18
5 5.5 6
VI − Input Voltage − V
− Turn-off Delay Time − ms
td(off)
TA = 25°C
CL = 1 µF
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
TABLE OF GRAPHS
FIGURE
t
d(on)
Turnon delay time vs Output voltage 23t
d(off)
Turnoff delay time vs Input voltage 24t
r
Rise time vs Load current 25t
f
Fall time vs Load current 26Supply current (enabled) vs Junction temperature 27Supply current (disabled) vs Junction temperature 28Supply current (enabled) vs Input voltage 29Supply current (disabled) vs Input voltage 30vs Input voltage 31I
OS
Short-circuit current limit
vs Junction temperature 32vs Input voltage 33vs Junction temperature 34r
DS(on)
Static drain-source on-state resistance
vs Input voltage 35vs Junction temperature 36V
I
Input voltage Undervoltage lockout 37
TURNON DELAY TIME TURNOFF DELAY TIMEvs vsOUTPUT VOLTAGE INPUT VOLTAGE
Figure 23. Figure 24.
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3.25
2.75
2.5 0 0.5
− Fall Time − ms
3.5
1 1.5 2
3
IL − Load Current − A
tf
TA = 25°C
CL = 1 µF
5.5
50 0.5 1
− Rise Time − ms
6
6.5
1.5 2
IL − Load Current − A
tr
TA = 25°C
CL = 1 µF
55
45
35−50 −25 0 25 50
65
75
75 100 150
TJ − Junction Temperature − °C
Supply Current (Enabled) − Aµ
125
VI(IN) = 3.3 V
VI(IN) = 4 V
VI(IN) = 5 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
1
0
−1−50 −25 0 25 50
4
5
75 100 150
TJ − Junction Temperature − °C
Supply Current (Disabled) − Aµ
125
3
2
VI(IN) = 4 V
VI(IN) = 2.7 V
VI(IN) = 5 V
VI(IN) = 5.5 V
VI(IN) = 3.3 V
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
RISE TIME FALL TIMEvs vsLOAD CURRENT LOAD CURRENT
Figure 25. Figure 26.
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 27. Figure 28.
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55
45
35 2.5 3 3.5 4 4.5
65
75
5 5.5 6
VI − Input Voltage − V
Supply Current (Enabled) − Aµ
TJ = 125°C
TJ = 85°C
TJ = 25°C
TJ = 0°C
TJ = −40°C
1
0
−1 2.5 3 3.5 4 4.5
4
5
5 5.5 6
VI − Input Voltage − V
Supply Current (Disabled) − Aµ
3
2TJ = 85°C
TJ = 0°C
TJ = −40°C
TJ = 125°C
TJ = 25°C
1.5
0.5
02 3 4
2.5
3.5
5 6
VI − Input Voltage − V
− Short-Circuit Current Limit − A
IOS
1
2
3
TPS2023
TPS2022
TPS2021
TPS2020
TPS2024
TA = 25°C
1.5
0.5
0
−50 −25 0
2.5
3.5
25 100
TJ − Junction Temperature − °C
− Short-Circuit Current Limit − A
IOS
1
2
3
TPS2023
TPS2022
TPS2021
TPS2020
TPS2024
50 75
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)vs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 29. Figure 30.
SHORT-CIRCUIT CURRENT LIMIT SHORT-CIRCUIT CURRENT LIMITvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 31. Figure 32.
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20
−50 −25 0
40
60
25 150
TJ − Junction Temperature − °C
30
50
VI = 2.7 V
50 75 100 125
VI = 3.3 V
VI = 5.5 V
IO = 0.18 A
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
20
2.5 3 3.5
40
60
4 6
VI − Input Voltage − V
30
50
4.5 5
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
5.5
TJ = 25°C
TJ = 125°C
TJ = −40°C
IO = 0.18 A
20 3 3.5
40
60
4 6
VI − Input Voltage − V
30
50
4.5 5 5.5
TJ = 25°C
TJ = 125°C
IO = 1.8 A
TJ = −40°C
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
20
−50 −25 0
40
60
25 150
TJ − Junction Temperature − °C
30
50 VI = 3.3 V
50 75 100 125
VI = 4 V
VI = 5.5 V
IO = 1.8 A
Ω
rDS(on) − Static Drain-Source On-State Resistance − m
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCEvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 33. Figure 34.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCEvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 35. Figure 36.
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2−50 0 50 100
2.4
2.5
150
TJ − Temperature − °C
2.3
2.2
Start Threshold
Stop Threshold
2.1
VI− Input V oltage − V
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
UNDERVOLTAGE LOCKOUT
Figure 37.
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APPLICATION INFORMATION
IN
OC
EN GND
0.1 µF
2,3
5
4
6,7,8
0.1 µF22 µF
Load
1
OUT
TPS2024
Power Supply
2.7 V to 5.5 V 10 kΩ
POWER SUPPLY CONSIDERATIONS
OVERCURRENT
OC RESPONSE
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 38. Typical Application
A 0.01- μF to 0.1- μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load isheavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,bypassing the output with a 0.01- μF to 0.1- μF ceramic capacitor improves the immunity of the device toshort-circuit transients.
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase theseries resistance of the current path. When an overcurrent condition is detected, the device maintains a constantoutput current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is presentlong enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before thedevice is enabled or before V
I(IN)
has been applied, see Figure 6 . The TPS202x senses the short andimmediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive loadoccurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 13 – 22).After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches intoconstant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. Thecurrent is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device isexceeded (see Figures 7 – 11). The TPS202x is capable of delivering current up to the current-limit thresholdwithout damaging the device. Once the threshold has been reached, the device switches into its constant-currentmode.
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition isencountered. The output remains asserted until the overcurrent or overtemperature condition is removed.Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting fromthe inrush current flowing through the device, charging the downstream capacitor. An RC filter can be connectedto the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowersthe inrush current flow through the device during hot-plug events by providing a low impedance energy source,thereby reducing erroneous overcurrent reporting.
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GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS202x
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS202x
Rpullup
V+
Rfilter
Rpullup
Cfilter
V+
POWER DISSIPATION AND JUNCTION TEMPERATURE
THERMAL PROTECTION
UNDERVOLTAGE LOCKOUT (UVLO)
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 39. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to passlarge currents. The thermal resistances of these packages are high compared to those of power packages; it isgood design practice to check power dissipation and junction temperature. The first step is to find r
DS(on)
at theinput voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature ofinterest and read r
DS(on)
from Figures 33 – 36. Next, calculate the power dissipation using:P
D
= r
DS(on)
×I
2
Finally, calculate the junction temperature:T
J
= P
D
×R
θJA
+ T
A
where:
T
A
= Ambient temperature °CR
θJA
= Thermal resistance — SOIC = 172 °C/W, PDIP = 106 °C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generallysufficient to get an acceptable answer.
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present forextended periods of time. The faults force the TPS202x into constant current mode, which causes the voltageacross the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal tothe input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protectioncircuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sensecircuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continuesto cycle in this manner until the load fault or input power is removed.
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltagefalls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertionsystems where it is not possible to turn off the power switch before input power is removed. The UVLO alsokeeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch isenabled. Upon reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltageovershoots.
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GENERIC HOT-PLUG APPLICATIONS (See Figure 40 )
Power
Supply Block of
Circuitry
TPS2024
GND
IN
IN
EN
OUT
OUT
OUT
OC
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2020 , , TPS2021TPS2022 , TPS2023 , TPS2024
SLVS175C – DECEMBER 1998 – REVISED SEPTEMBER 2007
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.These are considered hot-plug applications. Such implementations require the control of current surges seen bythe main power supply and the card being inserted. The most effective way to control these surges is to limit andslowly ramp the current and voltage being applied to the card, similar to the way in which a power supplynormally turns on. Because of the controlled rise times and fall times of the TPS202x series, these devices canbe used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature ofthe TPS202x also ensures the switch is off after the card has been removed, and the switch remains off duringthe next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion of the cardor module.
Figure 40. Typical Hot-Plug Implementation
By placing the TPS202x between the V
CC
input and the rest of the circuitry, the input power reaches this devicefirst after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at theoutput of the device. This implementation controls system surge currents and provides a hot-pluggingmechanism for any device.
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PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2020D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2020DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2020DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2020DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2021D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2021DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2021DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2021DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2021P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
TPS2021PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
TPS2022D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2022DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2022DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2022DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2023D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2023DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2023DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2023DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2023P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
TPS2023PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
TPS2024D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2024DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2024DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2024DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2024P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
TPS2024PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF TPS2020, TPS2021, TPS2022, TPS2024 :
•Automotive: TPS2020-Q1, TPS2021-Q1, TPS2022-Q1, TPS2024-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2020DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2021DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2022DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2023DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2024DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2020DR SOIC D 8 2500 340.5 338.1 20.6
TPS2021DR SOIC D 8 2500 340.5 338.1 20.6
TPS2022DR SOIC D 8 2500 340.5 338.1 20.6
TPS2023DR SOIC D 8 2500 340.5 338.1 20.6
TPS2024DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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