MC33368DR2 - ON Semiconductor

August, 2011 − Rev. 11

1Publication Order Number:

MC33368/D

MC33368

High Voltage GreenLinet

Power Factor Controller

The MC33368 is an active power factor controller that functions as a

boost preconverter in off−line power supply applications. MC33368 is

optimized for low power, high density power supplies requiring a

minimum board area, reduced component count and low power

dissipation. The narrow body SOIC package provides a small

footprint. Integration of the high voltage startup saves approximately

0.7 W of power compared to resistor bootstrapped circuits.

The MC33368 features a watchdog timer to initiate output

switching, a one quadrant multiplier to force the line current to follow

the instantaneous line voltage a zero current detector to ensure critical

conduction operation, a transconductance error amplifier, a current

sensing comparator, a 5.0 V reference, an undervoltage lockout

(UVLO) circuit which monitors the VCC supply voltage and a CMOS

driver for driving MOSFETs. The MC33368 also includes a

programmable output switching frequency clamp. Protection features

include an output overvoltage comparator to minimize overshoot, a

restart delay timer and cycle−by−cycle current limiting.

Features

•Lossless Off−Line Startup

•Output Overvoltage Comparator

•Leading Edge Blanking (LEB) for Noise Immunity

•Watchdog Timer to Initiate Switching

•Restart Delay Timer

•This is a Pb−Free Device*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

SO−16

D SUFFIX

CASE 751K

1

16

MARKING

DIAGRAM

A = Assembly Location

WL = Wafer Lot

YY, Y = Year

WW = Work Week

G = Pb−Free Package

PIN CONNECTIONS

116

13

12

11

10

9

2

3

4

5

6

7

8

5.0 Vref

Restart Delay

Voltage FB

Current Sense

Zero Current

AGND

Line

LEB

Comp

Mult

Frequency Clamp

VCC

Gate

PGND

SO−16

http://onsemi.com

(TOP VIEW)

MC33368D

AWLYWWG

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

1

16

MC33368

http://onsemi.com

2

Figure 1. Representative Block Diagram

This device contains 240 active transistors.

Restart Delay

Output

Overvoltage

Multiplier/

Error

Amplifier

Current

Sense

WatchdogTimer/

Zero Current Detector

FB

Restart Delay

Comp

Mult

LEB

Current Sense

ZC Det Frequency

Clamp

Internal Bias

Generator

UVLO

S

RQ

PWM

Line

VCC

Vref

AGND

Gate

PGND

Frequency

Clamp

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted)

Rating Symbol Value Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply Voltage (Transient)

ÁÁÁÁ

VCC

ÁÁÁÁÁÁ

20

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply Voltage (Operating)

ÁÁÁÁ

VCC

ÁÁÁÁÁÁ

16

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Line Voltage

ÁÁÁÁ

VLine

ÁÁÁÁÁÁ

500

ÁÁÁ

V

Current Sense, Multiplier, Compensation, Voltage Feedback, Restart Delay and Zero

Current Input Voltage

Vin1 −1.0 to +10 V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LEB Input, Frequency Clamp Input

ÁÁÁÁ

Vin2

ÁÁÁÁÁÁ

−1.0 to +20

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Zero Current Detect Input

ÁÁÁÁ

Iin

ÁÁÁÁÁÁ

±5.0

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Restart Diode Current

ÁÁÁÁ

Iin

ÁÁÁÁÁÁ

5.0

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Dissipation and Thermal Characteristics

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

D Suffix, Plastic Package Case 751K

Maximum Power Dissipation @ TA = 70°C PD450 mW

Thermal Resistance, Junction−to−Air RqJA 178 °C/W

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Operating Junction Temperature

ÁÁÁÁ

TJ

ÁÁÁÁÁÁ

150

ÁÁÁ

°C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Operating Ambient Temperature

ÁÁÁÁ

TA

ÁÁÁÁÁÁ

−25 to +125

ÁÁÁ

°C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Storage Temperature Range

ÁÁÁÁ

Tstg

ÁÁÁÁÁÁ

−55 to +150

ÁÁÁ

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

NOTE: ESD data available upon request.

MC33368

http://onsemi.com

3

ELECTRICAL CHARACTERISTICS (VCC = 14.5 V, for typical values TA = 25°C, for min/max values TJ = −25 to +125°C)

Characteristic Symbol Min Typ Max Unit

ERROR AMPLIFIER

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Bias Current (VFB = 5.0 V)

ÁÁÁÁÁ

IIB

ÁÁÁÁÁ

−

ÁÁÁÁÁ

0

ÁÁÁ

1.0

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Offset Voltage (VComp = 3.0 V)

ÁÁÁÁÁ

VIO

ÁÁÁÁÁ

−

ÁÁÁÁÁ

2.0

ÁÁÁ

50

ÁÁÁ

mV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transconductance (VComp = 3.0 V)

ÁÁÁÁÁ

gm

ÁÁÁÁÁ

30

ÁÁÁÁÁ

51

ÁÁÁ

80

ÁÁÁ

mmho

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Source (VFB = 4.6 V, VComp = 3.0 V)

Output Sink (VFB = 5.4 V, VComp = 3.0 V)

ÁÁÁÁÁ

IO

ÁÁÁÁÁ

9.0

ÁÁÁÁÁ

17.5

ÁÁÁ

30

ÁÁÁ

mA

OVERVOLTAGE COMPARATOR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Voltage Feedback Input Threshold

ÁÁÁÁÁ

VFB(OV)

ÁÁÁÁÁ

1.07 VFB

ÁÁÁÁÁ

1.084 VFB

ÁÁÁ

1.1 VFB

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation Time to Output

ÁÁÁÁÁ

TP

ÁÁÁÁÁ

−

ÁÁÁÁÁ

705

ÁÁÁ

−

ÁÁÁ

ns

MULTIPLIER

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Bias Current, VMult (VFB = 0 V)

ÁÁÁÁÁ

IIB

ÁÁÁÁÁ

−

ÁÁÁÁÁ

−0.2

ÁÁÁ

−1.0

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Threshold, VComp

ÁÁÁÁÁ

Vth(M)

ÁÁÁÁÁ

1.8

ÁÁÁÁÁ

2.1

ÁÁÁ

2.4

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Dynamic Input Voltage Range

ÁÁÁÁÁ

ÁÁÁ

V

Multiplier Input VMult 0 to 2.5 0 to 3.5 −

Compensation VComp Vth(M) to

(Vth(M) + 1.0)

Vth(M) to

(Vth(M) + 2.0)

−

Multiplier Gain (VMult = 0.5 V, VComp = Vth(M) + 1.0 V) K 0.25 0.51 0.75 1/V

ȧ

ȡ

Ȣ

K+

VCS Threshold

VMult ǒVComp–V

th(M)Ǔȧ

ȣ

Ȥ

ÁÁÁÁÁ

ÁÁÁ

VOLTAGE REFERENCE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Voltage Reference (IO = 0 mA, TJ = 25°C)

ÁÁÁÁÁ

Vref

ÁÁÁÁÁ

4.95

ÁÁÁÁÁ

5.0

ÁÁÁ

5.05

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Line Regulation (VCC = 10 V to 16 V)

ÁÁÁÁÁ

Regline

ÁÁÁÁÁ

−

ÁÁÁÁÁ

5.0

ÁÁÁ

100

ÁÁÁ

mV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Load Regulation (IO = 0 − 5.0 mA)

ÁÁÁÁÁ

Regload

ÁÁÁÁÁ

−

ÁÁÁÁÁ

5.0

ÁÁÁ

100

ÁÁÁ

mV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Total Output Variation Over Line, Load and Temperature

ÁÁÁÁÁ

Vref

ÁÁÁÁÁ

4.8

ÁÁÁÁÁ

−

ÁÁÁ

5.2

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Maximum Output Current

ÁÁÁÁÁ

IO

ÁÁÁÁÁ

5.0

ÁÁÁÁÁ

10

ÁÁÁ

−

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reference Undervoltage Lockout Threshold

ÁÁÁÁÁ

Vth

ÁÁÁÁÁ

−

ÁÁÁÁÁ

4.5

ÁÁÁ

−

ÁÁÁ

V

ZERO CURRENT DETECTOR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Threshold Voltage (Vin Increasing)

ÁÁÁÁÁ

Vth

ÁÁÁÁÁ

1.0

ÁÁÁÁÁ

1.2

ÁÁÁ

1.4

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Hysteresis (Vin Decreasing)

ÁÁÁÁÁ

VH

ÁÁÁÁÁ

100

ÁÁÁÁÁ

200

ÁÁÁ

300

ÁÁÁ

mV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Delay to Output

ÁÁÁÁÁ

Tpd

ÁÁÁÁÁ

−

ÁÁÁÁÁ

127

ÁÁÁ

−

ÁÁÁ

ns

CURRENT SENSE COMPARATOR

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Bias Current (VCS = 0 to 2.0 V)

ÁÁÁÁÁ

IIB

ÁÁÁÁÁ

−

ÁÁÁÁÁ

0.2

ÁÁÁ

1.0

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Offset Voltage (VMult = −0.2 V)

ÁÁÁÁÁ

VIO

ÁÁÁÁÁ

−

ÁÁÁÁÁ

4.0

ÁÁÁ

50

ÁÁÁ

mV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Maximum Current Sense Input Threshold (VComp = 5.0 V,

VMult = 5.0 V)

ÁÁÁÁÁ

Vth(max)

ÁÁÁÁÁ

1.3

ÁÁÁÁÁ

1.5

ÁÁÁ

1.8

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Delay to Output (VLEB = 12 V, VComp = 5.0 V, VMult = 5.0 V)

(VCS = 0 to 5.0 V Step, CL = 1.0 nF)

ÁÁÁÁÁ

tPHL(in/out)

ÁÁÁÁÁ

50

ÁÁÁÁÁ

270

ÁÁÁ

425

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

FREQUENCY CLAMP

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Frequency Clamp Input Threshold

ÁÁÁÁÁ

Vth(FC)

ÁÁÁÁÁ

1.9

ÁÁÁÁÁ

2.0

ÁÁÁ

2.1

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Frequency Clamp Capacitor Reset Current (VFC = 0.5 V)

ÁÁÁÁÁ

Ireset

ÁÁÁÁÁ

0.5

ÁÁÁÁÁ

1.7

ÁÁÁ

4.0

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Frequency Clamp Disable Voltage

ÁÁÁÁÁ

VDFC

ÁÁÁÁÁ

−

ÁÁÁÁÁ

7.3

ÁÁÁ

8.0

ÁÁÁ

V

MC33368

http://onsemi.com

4

ELECTRICAL CHARACTERISTICS (continued) (VCC = 14.5 V, for typical values TA = 25°C, for min/max values TJ = −25 to +125°C)

Characteristic UnitMaxTypMinSymbol

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DRIVE OUTPUT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Source Resistance (Current Sense = 0 V, VGate = VCC − 1.0 V)

Sink Resistance (Current Sense = 3.0 V, VGate = 1.0 V)

ÁÁÁÁÁ

ROH

ROL

ÁÁÁÁÁ

4.0

ÁÁÁÁÁ

8.6

7.2

ÁÁÁ

20

ÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Voltage Rise Time (25% − 75%) (CL = 1.0 nF)

ÁÁÁÁÁ

tr

ÁÁÁÁÁ

−

ÁÁÁÁÁ

55

ÁÁÁ

200

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Voltage Fall Time (75% − 25%) (CL = 1.0 nF)

ÁÁÁÁÁ

tf

ÁÁÁÁÁ

−

ÁÁÁÁÁ

70

ÁÁÁ

200

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output Voltage in Undervoltage (VCC = 7.0 V, ISink = 1.0 mA)

ÁÁÁÁÁ

VO(UV)

ÁÁÁÁÁ

−

ÁÁÁÁÁ

0.01

ÁÁÁ

0.25

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LEADING EDGE BLANKING

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Bias Current

ÁÁÁÁÁ

Ibias

ÁÁÁÁÁ

−

ÁÁÁÁÁ

0.1

ÁÁÁ

0.5

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Threshold (as Offset from VCC) (VLEB Increasing)

ÁÁÁÁÁ

VLEB

ÁÁÁÁÁ

1.0

ÁÁÁÁÁ

2.25

ÁÁÁ

2.75

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Hysteresis (VLEB Decreasing)

ÁÁÁÁÁ

VH

ÁÁÁÁÁ

100

ÁÁÁÁÁ

270

ÁÁÁ

500

ÁÁÁ

mV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UNDERVOLTAGE LOCKOUT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Startup Threshold (VCC Increasing)

ÁÁÁÁÁ

Vth(on)

ÁÁÁÁÁ

11.5

ÁÁÁÁÁ

13

ÁÁÁ

14.5

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Minimum Operating Voltage After Turn−On (VCC Decreasing)

ÁÁÁÁÁ

VShutdown

ÁÁÁÁÁ

7.0

ÁÁÁÁÁ

8.5

ÁÁÁ

10

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Hysteresis

ÁÁÁÁÁ

VH

ÁÁÁÁÁ

−

ÁÁÁÁÁ

4.5

ÁÁÁ

−

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TIMER

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Watchdog Timer

ÁÁÁÁÁ

tDLY

ÁÁÁÁÁ

180

ÁÁÁÁÁ

385

ÁÁÁ

800

ÁÁÁ

ms

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Restart Timer Threshold

ÁÁÁÁÁ

Vth(restart)

ÁÁÁÁÁ

1.5

ÁÁÁÁÁ

2.3

ÁÁÁ

3.0

ÁÁÁ

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Restart Pin Output Current (Vrestart = 0 V, Vref = 5.0 V)

ÁÁÁÁÁ

Irestart

ÁÁÁÁÁ

3.1

ÁÁÁÁÁ

5.2

ÁÁÁ

7.1

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TOTAL DEVICE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Line Startup Current (VCC = 0 V, VLine = 50 V)

ÁÁÁÁÁ

ISU

ÁÁÁÁÁ

5.0

ÁÁÁÁÁ

16

ÁÁÁ

25

ÁÁÁ

mA

Line Operating Current (VCC = Vth(on), VLine = 50 V) IOP 3.0 12.9 20 mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

VCC Dynamic Operating Current (50 kHz, CL = 1.0 nF)

VCC Static Operating Current (IO = 0)

ÁÁÁÁÁ

ICC

ÁÁÁÁÁ

−

ÁÁÁÁÁ

5.3

3.0

ÁÁÁ

8.5

−

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Line Pin Leakage (VLine = 500 V)

ÁÁÁÁÁ

ILine

ÁÁÁÁÁ

−

ÁÁÁÁÁ

30

ÁÁÁ

80

ÁÁÁ

mA

ORDERING INFORMATION

Device Package Shipping†

MC33368DG SOIC−16

(Pb−Free)

48 Units / Rail

MC33368DR2G SOIC−16

(Pb−Free)

2500 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC33368

http://onsemi.com

5

VFB(OV), OVERVOLTAGE INPUT THRESHOLD (% V  ) VCS, CURRENT SENSE PIN 6 THRESHOLD (V)

6.0 V

-55

110

-0.12

0.08

10

100

-55

16

-0.2

1.6

θ, EXCESS PHASE (DEGREES)

5.0 ms/DIV

TA, AMBIENT TEMPERATURE (°C)

VM, MULTIPLIER PIN 5 INPUT VOLTAGE (V)

gm, TRANSCONDUCTANCE ( mho)μ

f, FREQUENCY (Hz)

VFB, VOLTAGE FEEDBACK THRESHOLDΔ

TA, AMBIENT TEMPERATURE (°C)

VCS, CURRENT SENSE PIN 6 THRESHOLD (V)

Figure 2. Current Sense Input Threshold

versus Multiplier Input

VM, MULTIPLIER PIN 5 INPUT VOLTAGE (V)

Figure 3. Current Sense Input Threshold

versus Multiplier Input, Expanded View

VCC = 14 V

TA = 25°C

Figure 4. Reference Voltage versus Temperature Figure 5. Overvoltage Comparator Input

Threshold versus Temperature

Figure 6. Error Amplifier Transconductance

and Phase versus Frequency

Figure 7. Error Amplifier Transient Response

VCC = 14 V

TA = 25°C

VCC = 14 V

VO = 2.0 to 4.0 V

RL = 10 kW

TA = 25°C

Phase

Transconductance

CHANGE (mV)

1.2

1.0

0.6

0.4

0.2

0

12

8.0

4.0

0

-4.0

80

60

40

20

0

-20

0.06

0.05

0.03

0.02

0.01

0

109

108

107

106

4.0 V

2.0 V

0 V

-1.0 V

0.04

0.07

0.8

1.4

0.6 1.4 2.2 3.0 -0.06 0 0.06 0.12 0.20

-25 0 25 50 75 125100 -25 0 25 50 75 100 12

5

100 1.0 k 10 k 100 k 1.0 M 10 M

0

30

60

90

120

150

180

VCC = 14 V

FB

VPin 4 = 4.0 V

= 3.0 V

= 2.75 V

= 2.5 V

= 2.25 V

= 2.0 V

= 3.75 V

= 3.5 V

= 3.25 V

VPin 4 = 4.0 V

= 3.0 V

= 2.75 V

= 2.5 V

= 2.25 V

= 2.0 V

MC33368

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6

0.01

1000

RJA(t), THERMAL RESISTANCE

°

t, TIME (s)

θ

JUNCTION-TO-AIR ( C/W)

100

10

0.1 1.0 10 100

400

2.0

6.0

-55

500

20

-55

1.80

OUTPUT VOLTAGE (V)

200 ms/DIV

ICC, SUPPLY CURRENT (mA)

VCC, SUPPLY VOLTAGE (V)

tDLY, WATCHDOG TIME DELAY ( s)

TA, AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

5.0 ms/DIV

Vchg, QUICKSTART CHARGE VOLTAGE (V)

TA, AMBIENT TEMPERATURE (°C)

Figure 8. Quickstart Charge Current

versus Temperature

Figure 9. Watchdog Timer Delay

versus Temperature

Figure 10. Drive Output Waveform Figure 11. Supply Current versus

Supply Voltage

Figure 12. Transient Thermal Resistance Figure 13. Low Load Detection

Response Waveform

VCC = 14 V

CL = 1000 pF

TA = 25°C

CO = 1000 pF

Pin 3, 6, 8= GND

Pin 5 = 1.0 k to GND

TA = 25°C

Voltage

Current

OUTPUT CURRENT (A)

Output

Voltage

Load

Current

Ichg, QUICKSTART CHARGE CURRENT (mA)

μ

VCC = 14 V VCC = 14 V

1.76

1.72

1.68

1.64

15

10

5.0

0

200

0

4.0

2.0

0

460

420

380

340

-25 0 25 50 75 100 125 -25 0 25 50 75 100 125

4.0 6.0 8.0 10 12 14

3.0

2.0

1.0

0

1.50

1.30

1.10

0.90

0.70

-5.0

Pulse tested with a 4.0 V peak, 50 kHz square

wave through a 22 k resistance into Pin 7.

MC33368

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7

FUNCTIONAL DESCRIPTION

INTRODUCTION

With the goal of exceeding the requirements of legislation

on line current harmonic content, there is an ever increasing

demand for an economical method of obtaining a unity

power factor. This data sheet describes a monolithic control

IC that was specifically designed for power factor control

with minimal external components. It offers the designer a

simple cost effective solution to obtain the benefits of active

power factor correction.

Most electronic ballasts and switching power supplies use

a bridge rectifier and a bulk storage capacitor to derive raw

dc voltage from the utility ac line, Figure 14.

Figure 14. Uncorrected Power Factor Circuit

Rectifiers Converter

Bulk

Storage

Capacitor

Load

AC

Line

This simple rectifying circuit draws power from the line

when the instantaneous ac voltage exceeds the capacitor

voltage. This occurs near the line voltage peak and results in

a high charge current spike, Figure 15. Since power is only

taken near the line voltage peaks, the resulting spikes of

current are extremely nonsinusoidal with a high content of

harmonics. This results in a poor power factor condition

where the apparent input power is much higher than the real

power. Power factor ratios of 0.5 to 0.7 are common.

Figure 15. Uncorrected Power Factor Input Waveforms

Rectified

DC

0

Vpk

Line Sag

AC Line

Voltage

AC Line

Current

0

Power factor correction can be achieved with the use of

either a passive or active input circuit. Passive circuits

usually contain a combination of large capacitors, inductors,

and rectifiers that operate at the ac line frequency. Active

circuits incorporate some form of a high frequency

switching converter for the power processing with the boost

converter being the most popular topology. Since active

input circuits operate at a frequency much higher than that

of the ac line, they are smaller, lighter in weight, and more

efficient than a passive circuit that yields similar results.

With proper control of the preconverter, almost any complex

load can be made to appear resistive to the ac line, thus

significantly reducing the harmonic current content.

Operating Description

The MC33368 contains many of the building blocks and

protection features that are employed in modern high

performance current mode power supply controllers.

Referring to the block diagram in Figure 16, note that a

multiplier has been added to the current sense loop and that

this device does not contain an oscillator. A description of

each of the functional blocks is given below.

Error Amplifier

An Error Amplifier with access to the inverting input and

output is provided. The amplifier is a transconductance type,

meaning that it has high output impedance with controlled

voltage−to−current gain (gm  50 mmhos). The noninverting

input is internally biased at 5.0 V ±2.0%. The output voltage

of the power factor converter is typically divided down and

monitored by the inverting input. The maximum input bias

current is −1.0 mA which can cause an output voltage error

that is equal to the product of the input bias current and the

value of the upper divider resistor R2. The Error Amplifier

output is internally connected to the Multiplier and is pinned

out (Pin 4) for external loop compensation. Typically, the

bandwidth is set below 20 Hz so that the amplifier’s output

voltage is relatively constant over a given ac line cycle. In

effect, the error amplifier monitors the average output voltage

of the converter over several line cycles resulting in a fixed

Drive Output on−time. The amplifier output stage can sink

and source 11.5 mA of current and is capable of swinging from

1.7 to 5.0 V, assuring that the Multiplier can be driven over its

entire dynamic range.

Note that by using a transconductance type amplifier, the

input is allowed to move independently with respect to the

output, since the compensation capacitor is connected to

ground. This allows dual usage of the Voltage Feedback pin

by the Error Amplifier and Overvoltage Comparator.

Overvoltage Comparator

An Overvoltage Comparator is incorporated to eliminate

the possibility of runaway output voltage. This condition

can occur during initial startup, sudden load removal, or

during output arcing and is the result of the low bandwidth

that must be used in the Error Amplifier control loop. The

Overvoltage Comparator monitors the peak output voltage

of the converter, and when exceeded, immediately

terminates MOSFET switching. The comparator threshold

is internally set to 1.08 Vref. In order to prevent false tripping

during normal operation, the value of the output filter

capacitor C3 must be large enough to keep the peak−to−peak

ripple less than 16% of the average dc output.

MC33368

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8

Multiplier

A single quadrant, two input multiplier is the critical

element that enables this device to control power factor. The

ac haversines are monitored at Pin 5 with respect to ground

while the Error Amplifier output at Pin 4 is monitored with

respect to the Voltage Feedback Input threshold. A graph of

the Multiplier transfer curve is shown in Figure 2. Note that

both inputs are extremely linear over a wide dynamic range,

0 to 3.2 V for Pin 5 and 2.5 to 4.0 V for Pin 4. The Multiplier

output controls the Current Sense Comparator threshold as

the ac voltage traverses sinusoidally from zero to peak line.

This has the effect of forcing the MOSFET on−time to track

the input line voltage, thus making the preconverter load

appear to be resistive.

Pin 6 Threshold [0.55 ǒVPin 4 –V

Pin 3ǓVPin 5

Zero Current Detector

The MC33368 operates as a critical conduction current

mode controller, whereby output switch conduction is

initiated by the Zero Current Detector and terminated when

the peak inductor current reaches the threshold level

established by the Multiplier output. The Zero Current

Detector initiates the next on−time by setting the RS Latch

at the instant the inductor current reaches zero. This critical

conduction mode of operation has two significant benefits.

First, since the MOSFET cannot turn−on until the inductor

current reaches zero, the output rectifier’s reverse recovery

time becomes less critical allowing the use of an inexpensive

rectifier. Second, since there are no deadtime gaps between

cycles, the ac line current is continuous thus limiting the

peak switch to twice the average input current

The Zero Current Detector indirectly senses the inductor

current by monitoring when the auxiliary winding voltage

falls below 1.2 V. To prevent false tripping, 200 mV of

hysteresis is provided. The Zero Current Detector input is

internally protected by two clamps. The upper 10 V clamp

prevents input overvoltage breakdown while the lower

−0.7 V clamp prevents substrate injection. An external

resistor must be used in series with the auxiliary winding to

limit the current through the clamps to 5.0 mA or less.

Current Sense Comparator and RS Latch

The Current Sense Comparator RS Latch configuration

used ensures that only a single pulse appears at the Drive

Output during a given cycle. The inductor current is

converted to a voltage by inserting a ground−referenced

sense resistor R7 in series with the source of output switch.

This voltage is monitored by the Current Sense Input and

compared to a level derived from the Multiplier output. The

peak inductor current under normal operating conditions is

controlled by the threshold voltage of Pin 6 where:

Ipk +Pin 6 Threshold

R7

Abnormal operating conditions occur when the

preconverter is running at extremely low line or if output

voltage sensing is lost. Under these conditions, the Current

Sense Comparator threshold will be internally clamped to

1.5 V. Therefore, the maximum peak switch current is:

Ipk(max) +1.5 V

R7

With the component values shown in Figure 16, the

Current Sense Comparator threshold, at the peak of the

haversine, varies from 110 mV at 90 Vac to 100 mV at

268 Vac. The Current Sense Input to Drive Output

propagation delay is typically 200 ns.

Timer

A watchdog timer function was added to the IC to

eliminate the need for an external oscillator when used in

stand alone applications. The Timer provides a means to

automatically start or restart the preconverter if the Drive

Output has been off for more than 385 ms after the inductor

current reaches zero.

Undervoltage Lockout and Quickstart

The MC33368 has a 5.0 V internal reference brought out

to Pin 1 and capable of sourcing 10 mA typically. It also

contains an Undervoltage Lockout (UVLO) circuit which

suppresses the Gate output at Pin 11 if the VCC supply

voltage drops below 8.5 V typical.

A Quickstart circuit has been incorporated to optimize

converter startup. During initial startup, compensation

capacitor C1 will be discharged, holding the Error Amplifier

output below the Multiplier’s threshold. This will prevent

Drive Output switching and delay bootstraping of capacitor

C4 by diode D6. If Pin 4 does not reach the multiplier

threshold before C4 discharges below the lower SMPS

UVLO threshold, the converter will hiccup and experience

a significant startup delay. The Quickstart circuit is designed

to precharge C1 to 1.7 V. This level is slightly below the

Pin 4 Multiplier threshold, allowing immediate Drive

Output switching.

Restart Delay

A restart delay pin is provided to allow hiccup mode fault

protection in case of a short circuit condition and to prevent

the SMPS from repeatedly trying to restart after the input

line voltage has been removed. When power is first applied,

there is no startup delay, but subsequent cycling of the VCC

voltage will result in delay times that are programmed by an

external resistor and capacitor. The Restart Delay, Pin 2, is

a high impedance, so that an external capacitor can provide

delay times as long as several seconds.

If the SMPS output is short circuited, the transformer

winding, which provides the VCC voltage to the control IC

and the MC33368, will be unable to sustain VCC to the

control circuits. The restart delay capacitor at Pin 2 of the

MC33368 prevents the high voltage startup transistor within

the IC from maintaining the voltage on C4. After VCC drops

below the UVLO threshold in the SMPS, the SMPS

switching transistors are held off for the time programmed

by the values of the restart capacitor (C9) and resistor (R8).

MC33368

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9

In this manner, the SMPS switching transistors are operated

at very low duty cycles, preventing their destruction. If the

short circuit fault is removed, the power supply system will

turn on by itself in a normal startup mode after the restart

delay has timed out.

Output Switching Frequency Clamp

In normal operation, the MC33368 operates the boost

inductor in the critical mode. That is, the inductor current

ramps to a peak value, ramps down to zero, then

immediately begins ramping positive again. The peak

current is programmed by the multiplier output within the

IC. As the input voltage haversine declines to near zero, the

output switch on−time becomes constant, rather than going

to zero because of the small integrated dc voltage at Pin 5

caused by C2, R3 and R5. Because of this, the average line

current does not exactly follow the line voltage near the zero

crossings. The Output Switching Frequency Clamp

remedies this situation to improve power factor and

minimize EMI generated in this operating region. The

values of R10 and C7, as shown in Figure 16, program a

minimum off−time in the frequency clamp which overrides

the zero current detect signal, forcing a minimum off−time.

This allows discontinuous conduction operation of the boost

inductor in the zero crossing region, and the average line

current more nearly follows the voltage. The Output

Switching Frequency Clamp function can be disabled by

connecting the FC input, Pin 13, to the VCC supply Pin 12.

For best results, the minimum off−time, determined by the

values of R10 and C7, should be chosen so that ts(min) = t(on)

+ t(off)fc. Output drive is inhibited when the voltage at the

frequency clamp input is less than 2.0 V. When the output

drive is high, C7 is discharged through an internal 100 mA

current source. When the output drive switches low, C7 is

charged through R10. The drive output is inhibited until the

voltage across C7 reaches 2.0 V, establishing a minimum

off−time where:

t(off)fc +*R10 C7 logeƪ1*ǒ2

VCCǓƫ

Output

The IC contains a CMOS output driver that was

specifically designed for direct drive of power MOSFETs.

The Gate Output is capable of up to ±1500 mA peak current

with a typical rise and fall time of 50 ns with a 1.0 nF load.

Additional internal circuitry has been added to keep the Gate

Output in a sinking mode whenever the Undervoltage

Lockout is active. This characteristic eliminates the need for

an external gate pull−down resistor. The totem−pole output

has been optimized to minimize cross−conduction current

during high speed operation.

MC33368

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10

Table 1. Design Equations

Calculation Formula Notes

Converter Output Power PO+VOIOCalculate the maximum required output power.

Peak Indicator Current

IL(pk) +

22

ǸPO

hVac(LL)

Calculated at the minimum required ac line voltage for

output regulation. Let the efficiency η = 0.92 for low line

operation.

Inductance

LP+

tǒVO

2

Ǹ–Vac(LL)ǓhVac(LL)2

2

ǸVOPO

Let the switching cycle t = 40 ms for universal input (85

to 265 Vac) operation and 20 ms for fixed input (92 to

138 Vac, or 184 to 276 Vac) operation.

Switch On−Time

t(on) +

2P

OLP

hVac2

In theory, the on−time t(on) is constant. In practice, t(on)

tends to increase at the ac line zero crossings due to

the charge on capacitor C5. Let Vac = Vac(LL) for initial

t(on) and t(off) calculations.

Switch Off−Time

t(off) +

t(on)

VO

2

ǸVac ŤSin qŤ–1

The off−time t(off) is greatest at the peak of the ac line

voltage and approaches zero at the ac line zero

crossings. Theta (q) represents the angle of the ac line

voltage.

Minimum Switch

Off−Time t(off)min +

LPIL(pk)

VO

The off−time is at a minimum at ac line crossings. This

equation is used to calculate t(off) as Theta approaches

zero.

Delay Time

td+–R10C7 lnǒVCC –2

VCC ǓThe delay time is used to override the minimum

off−time at the ac line zero crossings by programming

the Frequency Clamp with C7 and R10.

Switching Frequency

f+1

t(on) )t(off)

The minimum switching frequency occurs at the peak of

the ac line voltage. As the ac line voltage traverses

from peak to zero, t(off) approaches zero producing an

increase in switching frequency.

Peak Switch Current

R7 +

VCS

IL(pk)

Set the current sense threshold VCS to 1.0 V for

universal input (85 to 265 Vac) operation and to 0.5 V

for fixed input (92 to 138 Vac, or 184 to 276 Vac)

operation. Note that VCS must be less than 1.4 V.

Multiplier Input Voltage

VM+Vac 2

Ǹ

ǒR5

R3 )1Ǔ

Set the multiplier input voltage VM to 3.0 V at high line.

Empirically adjust VM for the lowest distortion over the

ac line voltage range while guaranteeing startup at

minimum line.

Converter Output

Voltage VO+Vref ǒR2

R1 )1Ǔ–I

IB R1 The IIB R1 error term can be minimized with a divider

current in excess of 100 mA.

Converter Output

Peak−to−Peak

Ripple Voltage DVO(pp) +IL(pk) ǒ1

2pfac C3Ǔ2

)ESR2

ǸThe calculated peak−to−peak ripple must be less than

16% of the average dc output voltage to prevent false

tripping of the Overvoltage Comparator. Refer to the

Overvoltage Comparator Text. ESR is the equivalent

series resistance of C3.

Error Amplifier

Bandwidth BW +gm

2pC1

The bandwidth is typically set to 20 Hz. When operating

at high ac line, the value of C1 may need to be

increased.

NOTE: The following converter characteristics must be chosen:

VO = Desired output voltage. Vac(LL) = AC RMS minimum required operating line voltage for output regulation.

IO = Desired output current. DVO = Converter output peak−to−peak ripple voltage.

Vac = AC RMS operating line voltage.

MC33368

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11

Multiplier

8

C1

0.68

Figure 16. 80 W Power Factor Controller

Vrms Pin PF Ifund THD 2 3 5 7 VO(pp) VOIOPOn(%)

90 79.7 0.999 0.89 0.5 0.15 0.09 0.06 0.09 3.0 244.4 0.31 76.01 95.4

100 79.3 0.998 0.79 0.5 0.14 0.09 0.08 0.10 3.0 242.9 0.31 75.54 95.3

110 78.9 0.997 0.72 0.5 0.16 0.13 0.08 0.10 3.0 242.9 0.31 75.30 95.4

120 78.5 0.996 0.66 0.5 0.15 0.12 0.08 0.13 3.0 243.0 0.31 75.57 96.3

130 78.1 0.994 0.60 0.5 0.14 0.12 0.07 0.14 3.0 243.0 0.31 75.57 96.7

138 77.8 0.991 0.57 0.5 0.15 0.14 0.08 0.14 3.0 243.0 0.31 75.57 97.1

Power Factor Controller Test Data

Frequency

Clamp

R

SQ

R

S

Timer R Zero

Current

Detect

Vref

Leading Edge

Blanking

Low

Load Detect

Comp FB

6

LEB

13

PGND

Gate

ZCD

VCC

Line

RD

AGND

MC33368

16

12

7

11

10

FC

9

314

Quickstart

1.08 x Vref

Overvoltage

Comparator

Set Dominant

15 V

Q

5.0 V

Reference

VO

D5

MUR130

C3

220

MTP8N50E

Q1

D6

1N4934

C4

100

T

R4

22 k

EMI

Filter

92 to

270

Vrms

R7

0.1

0.25 W

C5

1.0

R5

1.3 M

R3

20 k

C2

0.01

R1

10 k

R2

470 k

R8

10 k

C9

330 mF

D1 D3

D2 D4

R11

10

15 V

C6

0.1

13/8.0

UVLO

1.2/1.0

R13

51

D8

Not Used: D7, C8, R6, R9

1N4744

1N4006

320 mH

RS Latch

Vref

CS

To VCC

Pin 12

2

5

Mult

1.5 V

AC Line Input

Current Harmonic Distortion (% Ifund)

DC Output

R10

10

C7

10 pF

T: Coilcraft N2881−A

Primary = 62 turns of #22 AWG

Secondary = 5 turns of #22 AWG

Core = Coilcraft PT2510, EE25

Gap = 0.072″ total for a primary inductance (Lp) of 320 mH

Heatsink = AAVID Engineering Inc., 590302B03600, or 593002B03400

MC33368

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12

Figure 17. 175 W Universal Input Power Factor Controller

Not Used: D7, C7, C8, R6, R9, R10

T: Coilcraft N2880−A

L = 870 mHy

Primary: 78 turns of #16 AWG

Secondary: 6 turns of #18 AWG

Core: Coilcraft PT4215, EE42−15

Gap: 0.104″ total

Vrms Pin PF Ifund THD 2 3 5 7 VO(pp) VOIOPOn(%)

90 190.4 0.995 2.11 5.8 0.16 0.32 0.24 0.80 3.6 398.0 0.44 175.9 92.4

120 192.1 0.997 1.60 3.2 0.08 0.17 0.07 0.30 3.6 398.9 0.44 177.1 92.2

138 192.7 0.997 1.40 0.9 0.08 0.24 0.03 0.15 3.6 402.3 0.45 179.0 92.9

180 194.3 0.995 1.08 0.9 0.04 0.18 0.04 0.08 3.6 409.1 0.45 182.9 94.1

240 189.3 0.983 0.80 0.7 0.08 0.21 0.08 0.06 3.6 407.0 0.45 181.1 95.7

268 186.3 0.972 0.71 0.6 0.11 0.32 0.10 0.10 3.6 406.2 0.44 180.4 96.8

AC Line Input

Current Harmonic Distortion (% Ifund)

DC Output

Multiplier

8

C1

2.2

Frequency

Clamp

R

SQ

R

S

Timer R Zero

Current

Detect

Vref

Leading Edge

Blanking

Low

Load Detect

Comp FB

6

LEB

13

PGND

Gate

ZCD

VCC

Line

RD

AGND

MC33368

16

12

7

11

10

FC

9

314

Quickstart

1.08 x Vref

Overvoltage

Comparator

Set Dominant

1.5 V

15 V

Q

5.0 V

Reference

VO

D5

MUR460

C3

330

MTW20N50E

Q1

D6

1N4934

C4

100

T

R4

22 k

EMI

Filter

92 to

2

70 Vrms

R7

0.1

C5

1.0

R5

1.3 M

R3

10 k

C2

0.01

R1

10 k

R2

820 k

R8

1.0 M

C9

2.2

D1 D3

D2 D4

R11

10

15 V

C6

0.1

13/8.0

UVLO

1.2/1.0

R13

51

D8

1N4744

1N5406

RS Latch

Vref

CS

2

5

Mult

Power Factor Controller Test Data

6.9 V

To VCC

Pin 12

Heatsink = AAVID Engineering Inc., 590302B03600

MC33368

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13

Figure 18. Power Factor Test Setup

10

AC Power

Analyzer

PM 1000

A V

Voltech

EMI Filter

T

2X Step-up

Isolation

Transformer

Autoformer

115 Vrms

Input

Line

Neutral

0 to 270 Vac

Output to

Power Factor

Correction

Circuit

HI HI

L.O. L.O.

0.1 1.0

WVAPFV

rms Arms

VDAcf Ainst Freq HARM

An RFI filter is required for best performance when connecting the preconverter directly to the ac line. The filter attenuates the level of high

frequency switching that appears on the ac line current waveform. Figures 16 and 17 work well with commercially available two stage filters

such as the Delta Electronics 03DPCG6. Shown above is a single stage test filter that can easily be constructed with four ac line rated

capacitors and a common−mode transformer. Coilcraft CMT3−28−2 was used to test Figures 16 and 17. It has a minimum inductance of 28 mH

and a maximum current rating of 2.0 A. Coilcraft CMT4−17−9 was used to test Figure 20. It has a minimum inductance of 17 mH and a

maximum current rating of 9.0 A. Circuit conversion efficiency η (%) was calculated without the power loss of the RFI filter.

Figure 19. On/Off Control

Multiplier

8

C1

22

Frequency

Clamp

R

SQ

R

S

Timer R

Vref

Leading Edge

Blanking

Low

Load Detect

Comp FB

6

LEB

13

PGND

Gate

ZCD

VCC

Line

RD

AGND

MC33368

16

12

7

11

10

FC

9

314

Quickstart

Overvoltage

Comparator

Set Dominant

1.5 V

15 V

Q

5.0 V

Reference

DC

Out

D5

C3

330

MTW14N50E

Q1

D6

C4

100

T

R4

22 k

EMI

Filter

92 to

270 Vrms

R7

0.1

C5

1.0

R5

1.3 M

R3

10 k

C2

0.01

R1

10 k

R2

820 k

R8

10 k

C9

330 mF

D1 D3

D2 D4

R11

10

15 V

C6

0.1

13/8.0

UVLO

1.2/1.0

R13

51

D8

RS Latch

Vref

CS

2

5

Mult

VCC

6.9 V

1.0 k

10 k

1.0 k

2N3904

1N4148

On/Off

Input

Zero

Current

Detect

1.08 x Vref

5.0 V Off

0 V On

MC33368

http://onsemi.com

14

Figure 20. 400 W Power Factor Controller

Multiplier

8

C1

1.0

Frequency

Clamp

R

SQ

R

S

Timer R

Vref

Leading Edge

Blanking

Low

Load Detect

Comp FB

6

LEB

13

PGND

Gate

ZCD

VCC

Line

RD

AGND

MC33368

16

12

7

11

10

FC

9

314

Quickstart

Overvoltage

Comparator

Set Dominant

1.5 V

15 V

Q

5.0 V

Reference

400 V

MUR460

D5

C3

330

MTW20N50E

Q1

D6

C4

100

T

R4

22 k

EMI

Filter

92 to

270

Vac

R7

0.1

C5

1.0

R5

1.3 M

R3

10.5 k

C2

0.01

R1

10 k

R2

820 k

R8

1.0 M

C9

330 mF

D1 D3

D2 D4

R11

10

15 V

C6

0.1

13/8.0

UVLO

1.2/1.0

R13

51

D8

RS Latch

Vref

CS

2

5

Mult

1.5 V

Zero

Current

Detect

1.08 x Vref

1N5406

R10

10 k

C7

470 pF

Vref

C8

0.001

R9

10

1N4744

1N4934

MC33368

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15

ÎÎÎÎÎÎ

ÏÏÏÏ

Figure 21. Printed Circuit Board and Component Layout

(Circuits of Figures 16 and 17)

DC Output

C6 R3 C2 D1

D3

AC Input

C5

Transformer

D5

DGS

D8

J

R10

C7

C9

R2

R8 C1

R4

C8

D6

R6

D2 D4

R5

R1

D7

IC1

R11

R9

J

R13

R7 C4

Q1

(Top View)

(Bottom View)

4.5″

3.0″

MC33368

C3

J = Jumper

MC33368

http://onsemi.com

16

PACKAGE DIMENSIONS

SO−16

D SUFFIX

CASE 751K−01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005)

TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

DIM

A

MIN MAX MIN MAX

INCHES

9.80 10.00 0.368 0.393

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

18

9

16

G

P

C

K14 X D

SEATING

PLANE

J

R_

M_

−A−

−B−

M

0.25 (0.010) B S

F

X 45

−T−

S

A

M

0.25 (0.010) B S

T

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

MC33368/D

GreenLine is a trademark of Motorola, Inc.

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