S34ML16G2
General Description
SkyHigh S34ML16G2 16-Gb NAND is offered in 3.3 VCC
with ×8 I/O interface. This document contains information for
the
S34ML16G2 device, which is a quad-die stack of four S34ML04G2 die. For detailed specifications, please refer to the discrete die
data sheet:
S34ML01G2_04G2.
Distinctive Characteristics
Density
– 16-Gb (4-Gb 4)
Architecture (For each 4-Gb device)
– Input / Output Bus Width: 8-bits
– Page Size: (2048 + 128) bytes; 128-byte spare area
– Block Size: 64 Pages or (128k + 8k) bytes
– Plane Size
– 2048 Blocks per Plane or (256M + 16M) bytes
–Device Size
– 2 Planes per Device or 512 Mbyte
NAND Flash Interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply Voltage
– 3.3 V device: Vcc = 2.7 V ~ 3.6 V
Security
– One Time Programmable (OTP) area
– Serial number (unique ID)
– Hardware program/erase disabled during power transition
Additional Features
– Supports Multiplane Program and Erase commands
– Supports Copy Back Program
– Supports Multiplane Copy Back Program
– Supports Read Cache
Electronic Signature
– Manufacturer ID: 01h
Operating Temperature
– Industrial: 40 °C to 85 °C
Performance
Page Read / Program
– Random access: 30 µs (Max)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 300 µs (Typ)
Block Erase / Multiplane Erase
– Block Erase time: 3.5 ms (Typ)
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes)
– 10 Year Data retention (Typ)
– Blocks zero and one are valid and will be valid for at least
1000
program-erase cycles with ECC
Package Options
– Lead Free and Low Halogen
– 48-Pin TSOP 12 20 1.2 mm
– 63-Ball BGA 9 11 1.2 mm
16 Gb, 3 V, 4-bit ECC, x8 I/O, SLC NAND
Flash Memory for Embedded
SkyHigh Memory Limited
Document Number: 001-98528 Rev. *G
Suite 4401-02, 44/F One Island East,
18 Westlands Road Hong Kong
www.skyhighmemory.com
Revised May 09, 2019
S34ML16G2
Contents
General Description ............................................................. 1
Distinctive Characteristics .................................................. 1
Performance.......................................................................... 1
Connection Diagram1. .................................................... 3
2. Pin Description............................................................. 4
3. Block Diagrams............................................................ 5
4. Addressing ................................................................... 7
5. Read Status Enhanced ................................................ 7
6. Read ID.......................................................................... 8
6.1 Read Parameter Page ................................................... 9
7. Electrical Characteristics ........................................... 12
7.1 Valid Blocks .................................................................. 12
7.2 DC Characteristics........................................................ 12
7.3 Pin Capacitance............................................................ 12
Power Consumptions and Pin Capacitance7.4
for Allowed Stacking Configurations ............................. 13
Physical Interface8. ....................................................... 14
Physical Diagram............................................8.1 .............. 14
Ordering Information9. .................................................. 16
Document History10. ....................................................... 17
Document Number: 001-98528 Rev. *G
Page 2 of 17
S34ML16G2
1. Connection Diagram
Figure 1.1 48-Pin TSOP1 Contact x8 Device (2 CE#, 16 Gb)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 1.2 63-BGA Contact, x8 Device (Balls Down, Top View)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
NC
NC
NC
NC
NC
R/B2#
R/B1#
RE#
CE1#
CE2#
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
VSS
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC
NC
VCC
VSS
NC
VCC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
VSS
12
13
37
36
25
481
24
NAND Flash
TSOP1
(x8)
(1)
(1)
(1)
(1)
Document Number: 001-98528 Rev. *G
Page 3 of 17
S34ML16G2
2. Pin Description
Notes:
1. A 0.1 µF capacitor sho uld be connect ed b etween t he V CC Supply Volt age pin and the VSS Ground pin to decouple the current surges fr om the power supply. The PCB
track widths must be sufficient to carry the current s required during program and erase operations.
2. An internal voltage detector disabl es all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.
Pin Description
Pin Name Description
I/O0 - I/O7 Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
CLE Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising edge of Write Enable
(WE#).
ALE Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising edge of Write Enable (WE#).
CE# Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
WE# Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
RE# Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling
edge of RE# which also increments the internal column address counter by one.
WP# Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
R/B# Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit prevents the insertion of
Commands when VCC is less than VLKO.
VSS Ground.
NC Not Connected.
Document Number: 001-98528 Rev. *G
Page 4 of 17
S34ML16G2
3. Block Diagrams
Figure 3.1 Functional Block Diagram — 16 Gb
Figure 3.2 Block Diagram — 16 Gb (4 Gb x 4) 48-Pin TSOP with 2 CE# (Two Chip Enable Signals)
Address
Register/
Counter
Controller
Command
Interface
Logic
Command
Register
Data
Register
RE#
I/O Buffer
Y Decoder
Page Buffer
X
D
E
C
O
D
E
R
NAND Flash
Memory Array
WP#
CE#
WE#
CLE
ALE
I/O0~I/O7
Program Erase
HV Generation
16 Gb Device (4 Gb x 4)
IO0~IO7
CE2#
CE#
RB#WE#
RB2#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7
CE#
RB#WE#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7
CE#
RB#WE#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7IO0~IO7
CE1#
CE#
WE#
RB#WE#
RB1#
RE#
RE#
VSS
VSS
ALE
ALE
VCC
VCC
CLE
CLE
WP#
WP#
4 Gb x8
NAND Flash
Memory #3
4 Gb x8
NAND Flash
Memory #4
4 Gb x8
NAND Flash
Memory #1
4 Gb x8
NAND Flash
Memory #2
Document Number: 001-98528 Rev. *G
Page 5 of 17
S34ML16G2
Figure 3.3 Block Diagram — 16 Gb (4 Gb x 4) 63-Ball BGA with 1 CE# (One Chip Enable Signal)
IO0~IO7
CE#
RB#WE#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7
CE#
RB#WE#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7
CE#
RB#WE#
RE#
VSS
ALE
VCC
CLE
WP#
IO0~IO7IO0~IO7
CE#
CE#
WE#
RB#WE#
RB#
RE#
RE#
VSS
VSS
ALE
ALE
VCC
VCC
CLE
CLE
WP#
WP#
4 Gb x8
NAND Flash
Memory#3
4 Gb x8
NAND Flash
Memory#4
4 Gb x8
NAND Flash
Memory#1
4 Gb x8
NAND Flash
Memory#2
Document Number: 001-98528 Rev. *G
Page 6 of 17
S34ML16G2
4. Addressing
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. A31 for 16 Gb (4 Gb x 4 - QDP)
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A31: block address
5. Read Status Enhanced
Read Status Enhanced is used to retrieve the status value for a previous operation in the following cases:
In the case of concurrent operations on a multi-die stack.
When four dies are stacked to form a quad-die package (QDP), it is possible to run one operation on the first die, then activate a
different operation on the second die, for example: Erase while Read, Read while Program, etc.
In the case of multiplane operations in the same die.
Address Cycle Map
I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0Bus Cycle
A5 (CAA4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)1st / Col. Add. 1 A7 (CA7)A6 (CA6)5)
LLowLowLowA11 (CA11)A10 (CA10)A9 (CA9)A8 (CA8)2nd / Col. Add. 2 ow
A1A16 (PA4)A15 (PA3)A14 (PA2)A13 (PA1)A12 (PA0)3rd / Row Add. 1 A19 (BA0)A18 (PLA0)7 (PA5)
A2A24 (BA5)A23 (BA4)A22 (BA3)A21 (BA2)A20 (BA1)4th / Row Add. 2 A27 (BA8)A26 (BA7)5 (BA6)
5th / Row Add. 3(6) LowLowLowLowA31 (BA12)A30 (BA11)A29 (BA10)A28 (BA9)
Document Number: 001-98528 Rev. *G
Page 7 of 17
S34ML16G2
6. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00)
before Read Status command (0x70).
For the S34ML16G2 device, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and
5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 6.1 Read ID Operation Timing
Read ID for Supported Configurations
VOrgDensity CC 5th4th3rd2nd1st
56h95h90hDCh01h3.3Vx84 Gb
16 Gb
(4 Gb x 4 – QDP with one
CE#)
5Eh95hD2hD5h01h3.3Vx8
16 Gb
(4 Gb x 4 – QDP with two
CE#)
5Ah95hD1hD3h01h3.3Vx8
CE#
WE#
CLE
RE#
ALE
tWHR
tAR
tREA
Read ID
Command
Address 1
Cycle
Maker
Code
Device
Code
3rd Cycle 5th Cycle4th Cycle
I/Ox
01h
90h 00h 5Eh95hD2hD5h
Document Number: 001-98528 Rev. *G
Page 8 of 17
S34ML16G2
5th ID Data
Read ID Byte 5 Description
I/O1 I/O0I/O3 I/O2I/O6 I/O5 I/O4I/O7Description
ECC Level
1 bit / 512 bytes
2 bit / 512 bytes
4 bit / 512 bytes
8 bit / 512 bytes
0 0
0 1
1 0
1 1
Plane Number
1
2
4
8
0 0
0 1
1 0
1 1
Plane Size
(without spare area)
64 Mb
128 Mb
256 Mb
512 Mb
1 Gb
2 Gb
4 Gb
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Reserved 0
6.1
Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an
address input of 00h. The command register remains in Parameter
Page mode until further commands are issued to it.
Table
explains the parameter fields.
Note:
For 32nm SkyHigh NAND, for a particular condition, the Read Parameter Page command does not give the correct values.
To
overcome this issue, the host must issue a Reset
command before
the Read Parameter Page command. Issuance of Reset
before the Read Parameter Page command will provide
the correct values
and will not output 00h values.
Parameter Page Description
ValuesDescriptionO/MByte
Revision Information and Features Block
M0-3
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4Fh, 4Eh, 46h, 49h
M4-5
Revision number
Reserved (0)2-15
1 = supports ONFI version 1.01
0 Reserved (0)
02h, 00h
M6-7
Features supported
5-15 Reserved (0)
4 1 = supports odd to even page Copyback
3 1 = supports interleaved operations
2 1 = supports non-sequential page programming
1 1 = supports multiple LUN operations
0 1 = supports 16-bit data bus width
1Eh, 00h
M8-9
Optional commands supported
6-15 Reserved (0)
5 1 = supports Read Unique ID
4 1 = supports Copyback
3 1 = supports Read Status Enhanced
2 1 = supports Get Features and Set Features
1 1 = supports Read Cache commands
0 1 = supports Page Cache Program command
3Bh, 00h
Document Number: 001-98528 Rev. *G
Page 9 of 17
S34ML16G2
Reserved (0)10-31 00h
Manufacturer Information Block
Device manufacturer (12 ASCII characters)M32-43 53h, 50h, 41h, 4Eh, 53h, 49h, 4Fh, 4Eh,
20h, 20h, 20h, 20h
Device model (20 ASCII characters)M44-63
53h, 33h, 34h, 4Dh, 4Ch, 31h, 36h, 47h,
32h, 20h, 20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h
JEDEC manufacturer IDM64 01h
Date codeO65-66 00h
Reserved (0)67-79 00h
Memory Organization Block
00h, 08h, 00h, 00hNumber of data bytes per pageM80-83
80h, 00hNumber of spare bytes per pageM84-85
00h, 00h, 00h, 00Number of data bytes per partial pageM86-89 h
00h, 00hNumber of spare bytes per partial pageM90-91
40h, 00h, 00h, 00hNumber of pages per blockM92-95
Number of blocks per logical unit (LUN)M96-99 00h, 40h, 00h, 00h (1 CE#)
00h, 20h, 00h, 00h (2 CE#)
Number of logical units (LUNs)M100 01h (1 CE#)
02h (2 CE#)
M101
Number of address cycles
Column address cycles4-7
Row address cycles0-3
23h
Number of bits per cellM102 01h
Bad blocks maximum per LUNM103-104 47h, 01h (1 CE#)
A3h, 00h (2 CE#)
Block enduranceM105-106 01h, 05h
01hGuaranteed valid blocks at beginning of targetM107
01h, 03hBlock endurance for guaranteed valid blocksM108-109
04hNumber of programs per pageM110
M111
Partial programming attributes
Reserved5-7
1 = partial page layout is partial page data followed by4
partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
00h
04hNumber of bits ECC correctabilityM112
M113
Number of interleaved address bits
Reserved (0)4-7
Number of interleaved address bits0-3
01h
O114
Interleaved operation attributes
4-7 Reserved (0)
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
04h
Reserved (0)115-127 00h
Electrical Parameters Block
I/O pin capacitanceM128 0Ah
Parameter Page Description (Continued)
ValuesDescriptionO/MByte
Document Number: 001-98528 Rev. *G
Page 10 of 17
S34ML16G2
Note:
1. “O” Stands for Optional, “M” for Mandatory.
M129-130
Timing mode support
Reserved (0)6-15
1 = supports timing mode 55
1 = supports timing mode 44
1 = supports timing mode 33
1 = supports timing mode 22
1 = supports timing mode 11
1 = supports timing mode 0, shall be 10
1Fh, 00h
O131-132
Program cache timing mode support
Reserved (0)6-15
1 = supports timing mode 55
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0
1Fh, 00h
tM133-134 PROG BCh, 02hMaximum page program time (µs)
tM135-136 BERS 10h, 27hMaximum block erase time (µs)
tM137-138 R1Eh, 00hMaximum page read time (µs)
tM139-140 CCS C8h, 00hMinimum Change Column setup time (ns)
Reserved (0)141-163 00h
Vendor Block
00hVendor specific Revision numberM164-165
Vendor specific166-253 00h
Integrity CRCM254-255 6Fh, D9h (1CE#)
15h, 32h (2CE#)
Redundant Parameter Pages
Value of bytes 0-255M256-511 Repeat Value of bytes 0-255
Value of bytes 0-255M512-767 Repeat Value of bytes 0-255
FFhAdditional redundant parameter pagesO768+
Parameter Page Description (Continued)
ValuesDescriptionO/MByte
Document Number: 001-98528 Rev. *G
Page 11 of 17
S34ML16G2
7. Electrical Characteristics
7.1 Valid Blocks
Recommended Operating Conditions7.2
DC Characteristics7.3
Notes:
1. All VCC pins, and VSS pins respectively, are shorted together.
2. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking.
3. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
4. Standby current measurement can be performed after the device has completed the initialization process at power up.
Valid Blocks
UnitMaxTypMinSymbolDevice
NS34ML04G2 VB Blocks— 40964016
NS34ML16G2 (1 CE) VB Blocks— 1638416057
NS34ML16G2 (2 CE) VB Blocks— 1638416058
Recommended Operating Conditions
UnitsMaxTypMinSymbolParameter
V3.63.32.7VccVcc Supply Voltage
V000VssGround Supply Voltage
DC Characteristics and Operating Conditions (Values listed are for each 4 Gb NAND, 16 Gb (4 Gb x 4) will differ
accordingly)
UnitsMaxTypMinTest ConditionsSymbolParameter
IPower On Current CC0
FFh command input after
power on —— 50 per
device mA
Operating Current
ISequential Read CC1
tRC = tRC (min)
CE# = VIL, Iout = 0 mA mA— 3015
IProgram CC2
mA— 3015Normal
mA— 3015Cache
IErase CC3 mA—— 3015
IStandby Current, (TTL) CC4
CE# = VIH,
WP# = 0V/Vcc mA—— 1
IStandby Current, (CMOS) CC5
CE# = VCC-0.2,
WP# = 0/VCC
µA— 5010
IInput Leakage Current LI VIN = 0 to VCC µA—— ±10(max)
IOutput Leakage Current LO VOUT = 0 to VCC µA—— ±10(max)
VInput High Voltage IH —V
CC — Vx 0.8 CC V+ 0.3
VInput Low Voltage IL —— V-0.3 CC Vx 0.2
VOutput High Voltage OH IOH V——2.4= -400 µA
VOutput Low Voltage OL IOL V—— 0.4= 2.1 mA
IOutput Low Current (R/B#) OL(R/B#) VOL mA—108= 0.4V
VErase and Program Lockout Voltage LKO V——— 1.8
Document Number: 001-98528 Rev. *G
Page 12 of 17
S34ML16G2
Pin Capacitance7.4
Note:
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
7.5 Power Consumptions and Pin Capacitance for Allowed Stacking
Configurations
When multiple dies are stacked in the same package, the power consumption of the stack will increase according to the number of
chips. As an example, the standby current is the sum of the standby currents of all the chips, while the active power consumption
depends on the number of chips concurrently executing different operations.
When multiple dies are stacked in the same package the pin/ball capacitance for the single input and the single input/output of the
combo package must be calculated based on the number of chips sharing that input or that pin/ball.
Pin Capacitance (TA = 25°C, f = 1.0 MHz)
UnitMaxMinTest ConditionSymbolParameter
CInput IN VIN pF— 10= 0V
CInput / Output IO VIL pF— 10= 0V
Document Number: 001-98528 Rev. *G
Page 13 of 17
S34ML16G2
8. Physical Interface
8.1 Physical Diagram
8.1.1 48-Pin Thin Small Outline Package (TSOP1)
Figure 8.1 TS2 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
gs5039 -ts4 048-09.05.14
TS4 48PACKAGE
MO-142 (D) DDJEDEC
MAXNOMMINSYMBOL
1.20------A
0.15---0.05A1
1.051.000.95A2
0.230.200.17b1
0.270.220.17b
0.16---0.10c1
0.21---0.10c
20.2020.0019.80D
18.5018.4018.30D1
12.1012.0011.90E
0.50 BASICe
0.700.600.50L
O8---0˚
0.20---0.08R
48N
NOTES:
DIMENSIONS ARE IN MILLIMETERS (mm).1.
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994).
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm.
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM
THE SEATING PLANE.
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
Document Number: 001-98528 Rev. *G
Page 14 of 17
S34ML16G2
63-Ball BGA Package8.1.2
Figure 8.2 63-Ball BGA 9 x 11 x 1.2 mm
PACKAGE
JEDEC
D X E
SYMBOL
A
A1
D
E
D1
E1
MD
ME
n
O b
eE
eD
MIN.
---
0.25
0.40
A3-A8,B2-B8,C1,C2,C9,C10,D1,
D2,D9,D10,E1,E2,E9,E10,F1,F2,
F9,F10,G1,G2,G9,G10,H1,H2,H9,
H10,J1,J2,J9,J10,K1,K2,K9,K10,
L3-L8,M3-M8
TNA 063
MO-207(N)
11.00mm X 9.00mm PACKAGE
NOM.
---
---
11.00 BSC
9.00 BSC
8.80 BSC
7.20 BSC
12
10
63
0.45
0.80 BSC
0.80 BSC
MAX.
1.20
---
0.50
NOTE
PROFILE
BALL HEIGHT
BODY SIZE
BODY SIZE
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
BALL DIAMETER
BALL PITCH
BALL PITCH
SOLDER BALL PLACEMENT
SOLDER BALL PLACEMENT
0.40 BSCSD
gs5038-tna063-09.05.14
NOTES:
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
BALL P
OSITION DESIGNATION PER JEP 95, SECTION 3, SPP-020.
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL “MD” IS THE BALL MATRIX SIZE IN THE “D” DIRECTION.
SYMBOL “ME” IS THE BALL MATRIX SIZE IN THE “E” DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
DIMENSION “b” IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
“SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW
“SD” OR “SE” = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW
“SD” = eD/2 AND “SE” = eE/2.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALLIZED MARK INDENTATION OR OTHER MEANS.
“+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
1.
2.
3.
4.
5.
6.
7.
8.
9.
0.40 BSCSE
DEPOPULATED SOLDER BALLS
Document Number: 001-98528 Rev. *G
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S34ML16G2
9. Ordering Information
The ordering part number is formed by a valid combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Contact your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
020IFT02216GS34ML
Packing Type
0 = Tray
3 = 13” Tape and Reel
Model Number
00 = Standard Interface / ONFI (x8)
20 = Two Chip Enable with Standard ONFI (x8)
Temperature Range
I = Industrial (–40 °C to + 85 °C)
Materials Set
F = Lead (Pb)-free
H = Lead (Pb)-free and Low Halogen
Package
B = BGA
T = TSOP
Bus Width
00 = x8 NAND, single die
04 = x16 NAND, single die
01 = x8 NAND, dual die
02 = x8 NAND, quad die
05 = x16 NAND, dual die
Technology
2 =SkyHigh NAND Revision 2 (32 nm)
Density
01G = 1
Gb
02G = 2
Gb
04G = 4
Gb
08G = 8
Gb
16G = 16 Gb
Device Family
S34ML
SkyHigh SLC NAND Flash Memory for Embedded
Valid Combinations
TechnologyDensityDevice Family Bus
Width
Package
Type
Temperature
Range
Additional Ordering
Options Packing Type Package
Description
ITF/BH02216GS34ML TF – 20
BH – 00 0, 3 BGA
TSOP
Document Number: 001-98528 Rev. *G
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S34ML16G2
10. Document History
Document Title: S34ML16G2, 16-Gbit, 4-Bit ECC, ×8 I/O, 3 V VCC NAND Flash for Embedded
Document Number: 001-98528
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
–– Initial release (Spansion Publication Number: S3410/28/2014** ML16G2)
–– Performance: Corrected Package Options for 63-Bal06/10/2015*A l BGA to 9 x 11 x 1.2 mm
Connection Diagram: 63-BGA Contact, x8 Device (Balls Down, Top View) figure: added
Note
Physical Interface: 63-Ball BGA Package: corrected figure title to ‘63-Ball BGA 9 x 11 x
1.2 mm’
Read ID: Read ID for Supported Configurations table:08/19/2015 added 16 Gb (4 Gb x 4 – QDP
with two CE#)
Electrical Characteristics: Valid Blocks table: added S34ML16G2 (2 CE)
Updated to Cypress template.10/15/2015XILA4965191*B
Updated to new template.11/20/2015XILA5016364*C
Updated04/25/2016XILA5160512*D Read ID:
Updated Read Parameter Page:
Updated description.
Updated Electrical Characteristics:
Added Recommended Operating Conditions.
Updated DC Characteristics:
Replaced “VCC supply Voltage (erase and program lockout)” with “Erase and Program
Lockout voltage” in “Parameter” column corresponding to VLKO.
Updated to new template.
Updated logo and copyright.05/05/2017HARA5727817*E
Updated to new template.11/09/2018MNAD6379791*F
Completing Sunset Review.
*G MNAD 05/09/2019 Updated to SkyHigh format
Document Number: 001-98528 Rev. *G
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