$= XILINX XH4000EX HardWire Array Family Preliminary Product Specification Features * Mask-programmed versions of Programmable Logic Cell Arrays FPGA ~ Specifically designed for easy XC4000EX series FPGA conversions - Significant cost reduction for high volume applications Transparent conversion from FPGA device On-chip scan-path test registers High performance CMOS process ~ Meets XC4000EX series -3 speeds Supports all XC4000EX Select-RAM features ~ Low voltage versions available for 3.3 V operation * Easy conversion with guaranteed results No customer engineering resource required Fully pin-for-pin compatible Supports most popular package types Same specifications and architecture as programmable FPGA devices All nets and CLBs preserved FPGA Design File used to generate production ready prototypes Prototypes built on production fab line, fully tested to production specification - Geater than 95% fault coverage HardWire | Replacement} Speed Device FPGA XC4028EX | XC4028EX XH4036EX | XH4036EX XH4044EX | XH4044EX XH4028XL XH4036XL XH4044XL XH4052XL XH4062XL -3 3 XC4036XL XC4044XL XC4052XL XC4062XL v Description The XH4000EX Series HardWire Arrays are advanced mask-programmed versions of the XC4000 programmable devices. In high-volume applications where the design is stable, the programmable FPGA devices used for proto- typing and initial production can be replaced by their HardWire Array equivalents. This offers a significant cost reduction with virtually no risk or engineering resources required. , In a programmable FPGA device, the logic functions and interconnections are determined by the configuration pro- gram data, loaded and stored in internal static-memory cells. The HardWire device has the identical functional architecture as the programmed FPGA device it replaces. In the HardWire device, the logic is optimized for area but maintains the relative timing relationship. Xilinx manufactures the HardWire device using the infor- mation from the programmed FPGA design file. Since the HardWire device is both pinout and architecturally identi- Cal to the programmable FPGA device, it is easily created without all the costly and time-consuming customer engi- neering activity that other semicustom solutions would require no redesign time, no expensive and time-con- suming simulation runs, no place and route, no test-vector generation. Xilinx proprietary software checks the design and maintains timing relationships as well as automatically generating test vectors. The combination of the program- Packages Grade |PQ208 | PQ240| PG299 | HQ304| BG352 | PG411 | BG432 | PG475 v v 3-31XH4000EX HardWire Array Family mable FPGA device and the HardWire Array offers the fastest and easiest way to get a new product to market, while ensuring low cost, low risk, and high-volume cost reduction. The XH4000EX HardWire technology further optimizes silicon area by removing all unused logic in a CLB, and removing any unused CLBs and routing resources. In fact, allunused FPGA features are eliminated in the XH4000EX. However, using our DesignLock technology, the impie- mentation of the CLBs (including placement and routing) are maintained. This unique conversion process also eliminates the need for timing simulation. Timing is guar- anteed through our Design Review process with the aid of our proprietary software. See The Xilinx Dafa Book for more information on the XC4000 architecture. Interconnect User-defined interconnect resources in the device provide routing paths to connect inputs and outputs of the I/O and logic blocks into logic networks. The speed of the interconnect paths of the HardWire Array is significantly faster, since all interconnections are fixed metal connections. Architectural Enhancements Compared to older array families, XH4000EX HardWire arrays provide significant enhancements. Powerful system features, as listed below, are incorporated to improve system speed, device flexibility, and ease of use. JTAG Boundary Scan IEEE 1149.1 Boundary-scan * Select-RAM Memory: on chip RAM with: Synchronous write option Dual-port RAM option STARTUP The STARTUP User Logic block is completely supported in the XH4000EX. The input pins for GSR and GTS can be tied anywhere in the design. Each of these pins can also be inverted, as in the XC5200 FPGA. Refer to Figure 1 for a detaited block diagram of the STARTUP User Logic block. Xilinx recommends the use of the STARTUP block for FPGA designs. By utilizing the GSR pin, all flip-flops in the design may be cleared. It is further recommended that the GSR input be driven directly from a device pin rather than from internal logic. This permits the design to be fully reset from an external device pin, resulting in greater testability. XH4000EX GSR] STARTUP [a2 GTS | Q3 cu] Figure 1. STARTUP User Logic Block Similary, the GTS pin should also be connected to an external device pin so that the FPGA/HardWire may have all I/O pins at a three-state condition. This condition is often necessary for printed circuit board level manufacturing testing and is therefore a recommended design practice. Configuration Modes XC4OO00E devices have six configuration modes. XH4000EX devices have the same six modes, plus an additional configuration mode. These modes are selected by a 3-bit input code applied to the M2, M1, and MO inputs. These are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode, which is used primarily for daisy- chain devices. The seventh mode, called Express mode, is an additional slave mode that allows high-speed parallel configuration of the high-capacity XH4000EX devices. The coding for modes selection is shown in Table 1. Table 1. Configuration Modes Mode M2 Mt Mo | CCLK Data Master Serial 0 0 0 output Bit-Serial Slave Serial 1 1 1 input Bit-Serial Master 1 0 0 output | Byte-Wide, Parallel Up increment from 00000 Master 1 1 0 output | Byte-Wide, Parallel increment Down from 3FFFF Peripheral 0 1 1 input Byte-Wide Synchronous* Peripheral 1 0 1 output | Byte-Wide Asynchronous* Express 0 1 0 input Byte-Wide (XC4000EX only Reserved 0 0 4 a _ Note: * Peripheral Synchronous can be considered byte-wide Slave Parallel A detailed description of each configuration mode, with timing information, is included in the XC4000E data sheet. For more information on Configuration Emulation, refer to the Design Considerations section of this Data Book.>= XILINX Power Distribution Power for the HardWire Array is distributed through a grid to achieve high noise immunity and isolation between logic and W/O. Inside the device, dedicated Voc and ground rings surround the logic array and provide power to the VO drivers. An independent matrix of Vcc and ground lines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically a 0.1-~F capacitor connected near the Vcc and ground pins will provide adequate decoupling. Output buffers capable of driving the specified 12-mA/ 24-mA loads under worst-case conditions may be capable of driving many times that current in a best case. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direc- tion. It may also be beneficial to locate heavily loaded output buffers near the ground pads. The I/O Block output buffers Dedicated or Special Pins on XH4000EX HardWire Array have a slew-limited mode which should be used where output rise and fall times are not speed critical. Slew-limited outputs maintain their dc drive capability, but generate less external reflections and internal noise. A maximum total external capacitive load for simultaneous fast-mode switching in the same direction is 100 pF per power/ground pin pair. For slew- rate limited outputs this total is four times larger. XC4000EX-Family Pin Assignments Xilinx offers members of the XH4000EX family in a variety of surface-mount package types, with pin counts from 208 to 304. Each chip is offered in several package types to accommo- date the available PC-board space and manufacturing technology. Most package types are also offered with different chips to accommodate design changes without requiring PC-board changes. Pin Function Configuration Emulation Mode Pin Name During Configuration During Operation MO Mo User Input (1.2) M1 M1 User Output (1-2) M2 M2 User Input (1.2) CCLK Master: Output, Slave; Input HIGH - internal Pull-up PROGRAM | PROGRAM Input Global Reset Device - Reconfigure DONE DONE Output HIGH - Internal Pull-up HDC HDC Output User 0 LDC LOC Output User 1/0 INIT Master: INIT Input, Slave POR Output Open Drain DIN DIN Pin User I/O DOUT DOUT Pin User I/O Notes: 1. User Pin is only accessible through special schematic /O Macros X7110 2. Pin does not have an associated IOB register(s) Unrestricted User-Programmable V/O Pins. An I/O pin may be programmed by the user to be an Input or an Output pin following configuration. Before configuration is completed, these pins have an internal high-value pull-up resistor that defines the logic level as High. 3-33XH4000EX HardWire Array Family Production Test Methodology The Xilinx XH4000EX utilizes a Production Test Methodology which permits total testability of all testable faults. This is achieved through high fault coverage vectors generated by an Automatic Test Vector Generator (ATPG). The vectors are fed via both a serial and a parallet data path for the highest degree of fault observation. One major advantage of Xilinxs test methodology is that the customer is not required to generate any production test vectors. Since this can often consume a great deal of time, Xilinx HardWire can save valuable customer engineering resources. The user flip-flops in the design are converted into scannable elements. All flip-flops in the dedicated logic such as Configu- ration Emulation or Boundary Scan are also converted into scannable elements. These elements are then combined to form full-scan chains. Up to eight chains are used in order to reduce the total required test time. By using a combination of random and deterministic fault alogrithms, high fault cover- age is achieved resulting in total testability of all testable faults. ESD Considerations The XC5400 has similar ESD protection as the XC5200 FPGA, and is able to withstand ESD up to 2,000 volts. The HardWire is manufactured in CMOS process technology, and appropriate Electro-Static Discharge (ESD) handling precau- tions should be followed. 3 V/5 V Considerations The XC5400 HardWire Array can operate either as 5 volt only, or as a 3.3 volt device (part number XC4400L). 5 Volt Operation 3.3 Volt Operation Vil (max) | Vih (min) | Vol (max) | Voh (min) | Vil (max) | Vih (min) | Vol (max) | Voh (min) XH4000EX | 0.80 2.00 0.40 Vor 0.4 0.80 2.20 0.30 Voc 0.3 xT1I1 User User User Scan_in C> t Flip-Flop Flip-Flop rere ><] ns 0 Q D Qb-eip a User Data ] To User Logic User Tast Mode 4 -_f Oata b b User CLK1 scan_cux [>> X6788 User cixz2 | J Figure 2. XH4000EX Scan Chain 3-34