CS1600-FSZ - Cirrus Logic Inc

Cirrus Logic, Inc.

http://www.cirrus.com

CS1600

Low-cost PFC Controller for Electronic Ballasts

Features & Description

Lowest PFC System Cost for Electron ic Ballasts

Variable Frequency Discontinuo us Conduction Mode

Improved Efficiency Due to Variable Switching Frequency

EMI Signature Reduction from Digital Noise Shaping

Integrated Feedback Compensation

Overvoltage Protection with Hysteresis

Overpower Protection with Shutdown

UVLO with Wide Hysteresis

Thermal Shutdown with Hysteresis

Description

CS1600 is a high-performance Variable Frequency Discontinu-

ous Conduction Mode (VF - DCM), active Power Factor

Correction (PFC) con troller, optimized to del iver the lowest PFC

system cost for electronic ballast applications.

A variable ON time / variable frequency algorithm is used to

achieve near unity power factor. This algorithm spreads the EMI

frequency spectrum, which reduces the conducted EMI filtering

requirements. The feedback loop is closed through an integrated

compensation network within the IC, eliminating the need for

additional external components. Protection features such as

overvoltage, overcurrent, overpower, open- and short-circuit pro-

tection, overtemperature, and brownout help protect the device

during abnormal transient conditions.

Ordering Information

See page 13.

7 4

C1 C3 Regulated

DC Outp ut

Mains

BR 1

BR1

BR 1

BR1

CS1600 GD

IFB

GND

IAC

VDD

NOV ‘10

DS904F1

CS1600

2DS904F1

1. INTRODUCTION

Figure 1. CS1600 Block Diagram

The CS1600 digital power factor controller operates in variable

on-time, variable frequency, discontinuous conduction mode

(DCM). The CS1600 uses a proprietary digital algorithm to

maximize the efficiency and reduce the conductive EMI.

The analog-to-digital converter (ADC) shown in the CS1600

block diagram in Figure 9 is used to sense the PFC output

voltage ( Vlink ) and the rectified AC line voltage ( Vrect ) by

measuring currents through their respective resistors. The

magnitudes of these currents are measured as a proportion of a

reference current (IREF) that functions as the reference for the

ADCs. The digital signal is then processed in a control algorithm

which determines the behavior of the CS1600 during start-up,

normal operation, and under fault conditions, such as

overvoltage, and over-temperature conditions.

The CS1600 PFC switching frequency varies with the Vrect on

a cycle-by-cycle basis, and its digital algorithm calculates the

on-time accordingly for unity power factor. Unlike traditional

Critical Conduction Mode (CRM) PFC controller, CS1600

operates at its low switching frequency near the zero-crossing

point of the AC input voltage, and it operates at its high

switching frequency at the peak of its AC input voltage (this is

the opposite of the switching frequency profile for a CRM PFC

controller), thus CS1600 reduces switching losses e specially

under light-load conditions, spreads conducted EMI energy

peaks over a wide frequency band and increases overall

system efficiency.

The proprietary digital control engine optimizes the feedback

error signal using an adaptive control algorithm, improves

system stability and transient response. No external feedback

error signal compensation compon ents are required.

The CS1600s digital controller algorithm limits the ON time of

the Power MOSFET by the following equ ation:

Where Ton is the max time that th e power MOSFET is turned

on and Vrect is the rectified line voltage. In the event of a

sudden line surge or sporadic, high dv/dt line voltages, this

equation may not limit the ON time appropriately . For this type

of line disturbance, additional protection mechanisms such as

fusible resistors, fast-blow fuses, or other current-limiting

devices are recommended.

Under steady-state conditions, the voltage loop keeps PFC

output voltage close to its nominal value. Under light load

startup or feedback loop open conditions, the output voltage

may pass the overvoltage protection threshold. The digital

control engine initiates a fast response loop to shut down gate

driving signal to reduce the ene rgy delivered to the output for

PFC capacitor protection. When the link voltage drop below

VOVP –V

OVP(Hy), PFC resumes normal operation.

POR +

th(ST)

th(STP)

Voltage

Regulator 7

VDD

GND

IFB

ADC

IAC

ADC

15k

24k

15k

24k

Ton 0.001827VμS

Vrect

-------------------------------------

≤

CS1600

DS904F1 3

2. PIN DESCRIPTION

Table 1. Pin Descriptions

Pin Name Pin # I/O Description

NC 1,2,8 - NC — No connections

IAC 3IN

Rectifier Voltage Sense — A current proportional to the rectified line voltage (Vrect) is

fed into this pin. The current is measured with an A/D converter.

IFB 4IN

Link Vo ltage Sense — A current proportional to the output link voltage (Vlink) of the

PFC is fed into this pin. The current is measured with an A/D converter.

GND 5PWR

Ground — Current return for both the input signal portion of the IC and the gate driver.

GD 6OUT

Gate Driver Output — The totem pole stage is able to drive the power MOSFET with a

peak current of 0.5 A source and 1.0 A sink. The high -level voltage of this pin is

clamped at VZ to avoid excessive gate voltages.

VDD 7PWR

IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the

gate driver.

IFBLi nk Vol t age Sense

NCNo Connecti on

GND Ground

GD PF C G ate Driver

VDD IC Supply Vol t age

NC No Connecti on

NCNo Connecti on

IACRect i fi er Voltage Sense

8-l ead SOIC

Figure 2. CS1600 Pin Assignments

CS1600

4DS904F1

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 Electrical Characteristics

Typical characteristics conditions:

TA= 25º C, VDD = 13 V, GND = 0 V

All voltages are measured with respect to GND.

Unless otherwise specified, all currents are positive when

flowin g in to the IC.

Minimum/Maximum characteristics conditions:

TJ= -40º to +125º C, VDD = 10 V to 15 V, GND = 0 V

Notes: 1. Specifications guaranteed by design and are characterized and correlated using statistical process methods.

2. Specification are based upon a PFC system configured for AC input of 108-305 VAC (Sine), 45/65 Hz, Vlink=460V,

RIAC =3.45 MΩ, RIFB = 3.45 MΩ, C3 = 23.5 μF, LB= 380 μH, 115 W.

3. Overpower protection is scaled to rated power.

4. Normal operation mode, see 5.2 Start-up vs. Normal Operation Mode on page 8.

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Turn-on Threshold Voltage VDD Increasing VDD(on) 8.4 8.8 9.3 V

Turn-off Threshold Voltage (UVLO) VDD Decreasing VDD(off) 7.1 7.4 7.9 V

UVLO Hysteresis VHys -1.4-V

Zener Voltage IDD =20mA V

Z17.0 17.9 18.5 V

VDD Supply Current

Start-up Supply Current VDD =V

DD(on) IST -6880μA

Operating Supply Current CL=1nF, fsw=70kHz IDD -1.71.9mA

PFC Gate Drive

Output Source Resistance IGD =100mA,V

DD = 13V ROH -9-Ω

Output Sink Resistance IGD = -200mA,VDD = 13V ROL -6-Ω

Rising Time CL=1nF,VDD = 13V tr-3260ns

Falling Time CL=1nF,VDD = 13V tf-1530ns

Output Voltage Low State IGD = -200mA,VDD = 13V Vol - 0.9 1.3 V

Output Voltage High St ate IGD =100mA,V

DD = 13V Voh 11.3 11.8 - V

Overvoltage Protection (OVP) 2

Output Voltage at Startup Mode VO(startup) - 414 - V

Output Voltage at Normal Mode VO(nom) - 460 - V

OVP Threshold VOVP - 492 - V

OVP Hysteresis VOVP(Hy) -5-V

Thermal Protection 1

Thermal Shutdown Threshold TSD 130 143 155 ºC

Thermal Shutdown Hysteresis TSD(Hy) -9-ºC

CS1600

DS904F1 5

3.2 Absolute Maximum Ratings

Notes: 5. The CS1501 has an internal shunt regulator that controls the voltage on the VDD pin. VZ, the shunt regulation

voltage, can be a maximum of 20 V but may also be as low as 10 V.

6. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power

dissipation at the rate of 50 mW / ºC for variati on over temperature.

WARNING:

Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Pin Symbol Parameter Value Unit

DD IC Supply Voltage VZV

1,3,4,5 - Analo g Input Maximum Voltage -0.5 to VZV

1,3,4,5 - Analog Input Maximum Current 50 mA

GD Gate Drive Output Voltage -0.3 to VZV

GD Gate Drive Output Current -1.0 / +0.5 A

-P

DTotal Power Dissipation @ TA=50° C 600 mW

-θJA Junction-to-Ambient Thermal Impedance 107 ºC / W

-T

AOperating Ambient Temperature Range1-40 to +125 ºC

-T

JJunction Temperature Operating Range -40 to +125 ºC

-T

Stg Storage Temperature Range -65 to +150 ºC

All Pins ESD Electro static Discharge Capability Human Body Model

Machine Mode l

Charged Device Model

2000

200

500 V

CS1600

6DS904F1

4. TYPICAL ELECTRICAL PERFORMANCE

0.5

1.5

2.5

3.5

0123456789101112131415161718

(V)

(mA)

= 1 nF

= 70 kHz

= 25 °C

Falling

Rising

-50 0 50 100 150

TEMP (oC)

VDD (V)

Startup

UVLO

0.5

1.5

-50 0 50 100 150

TEMP (oC)

UVLO Hysteresis (V)

17.5

18.5

-50 0 50 100 150

TEMP (oC)

(V)

IDD = 20 mA

Figure 3. Supply Current vs. Sup pl y Voltage Figure 4. Start-up & UVLO vs. Temp

Figure 5. UVLO Hysteresis vs. Temp Figure 6. VDD Zener Voltage vs. Temp

CS1600

DS904F1 7

Frequency (kHz)

Min Freq

Max Freq

TEMP (oC)

100

-60 -40 -20 0 20 40 60 80 100 120 140

-60 -40 -20 0 40 100 120 140

Gate Resistor (R

, R

) Temp (oC)

Zout (Ohm)

Source

Sink

= 13 V

source

= 100 mA

sink

= 200 mA

20 60 80

-50 0 50 100 150

TEM P (oC)

Supply Current (mA)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Operating

= 13 V

= 1 nF

SW(max)

= 70 kHz

Start-up

420

430

440

450

460

470

480

490

500

-50 0 50 100 150

Temperature (°C)

link

(V)

OVP

Normal

Figure 7. Supply Current (ISB, IST, IDD) vs. Tem p Fi gure 8. Min/Max Operating Frequency vs. Temp

Fi g u r e 9 . Gate Resistance (ROH, ROL) vs. Temp Figure 10. OVP vs. Temp

CS1600

8DS904F1

5. GENERAL DESCRIPTION

The CS1600 offers numerous features, options, and

functional capabilities to the designer of switching power

converters. This digital PFC control IC is designed to replace

legacy analog PFC controllers with minimal design effort.

5.1 PFC Operation

One key feature of the CS1600 is its operating frequency

profile. Figure 1 1 illustrates how the frequency varies over half

cycle of the line voltage in steady-state operation. When

power is first applied to the CS1600, it examines the line

voltage and adapts its operating frequency to the line voltage

as shown in Figure 1 1. The operating frequency is varied from

the peak to the trough of the AC input. During start-up the

control algorithm’s goal is to generate maximum power while

maintaining DCM operation, providing an approximate

square-wave envelop current within every half line cycle by

adjusting the operating frequency for fast startup behavior.

Figure 11. Switching Frequency vs. Phase Angle

Figure 12 illustrates how the operating frequency (as a

percentage of maximum frequency) changes with output

power and the peak of the line voltage.

Figure 12. Max Switching Frequency vs. Output Power

When Po falls below 5% the CS1600 chang es to Burst Mode

(See 5.3 Burst Mode on page 8).

5.2 Start-up vs. Normal Operation Mode

CS1600 has two discrete operation modes: Start-up and

Normal. S tart-up mode will be activated when Vlink is less than

90% of nominal value and remains active until Vlink reaches

100% of nominal value, as shown in Figure 13. Startup mode

is activated during initial system power-up. Any Vlink drop to

less than 90% of nominal value, such as load change, can

cause the system to enter Start-up mode until Vlink is brought

back into regulation.

Figure 13. Start-up and Normal Modes

Startup mode is defined as a surge of current delivering

maximum power to the output regardless of th e load. During

every active switch cycle, the 'ON' time is calculated to drive a

constant peak current over the entire line cycle. However, the

'OFF' time is calculated based on the DCM/CCM boundary

equation.

5.3 Burst Mode

Burst mode is utilized to improve system efficiency when the

system output power (Po) is < 5% of nominal. Burst mode is

implemented by intermittently disabling the PFC over a full

half-line period cycle under li ght load cond itions, as shown in

Figure 14.

Figure 14. Burst Modes

100

120

04590135180

Rectified Line Voltage Phase (Deg.)

% of Max

Switching Freq. (% of Max.)

Line Voltage (% of Max.)

% P

O max

SW ma x

(kHz)

405

Burst Mode

060 80 100

Vi n > 156 VAC

Vi n < 182 VAC

t [ms]

Vlink

[V]

100%

90%

Startup Mode

Normal

Mode

Startup Mode

Normal

Mode

Vin

[V]

t [ms]

FET

Vgs

Burst Mode

Active

Vin

[W]

t [ms]

PFC

Disable

Burst Threshold

CS1600

DS904F1 9

5.4 Output Power and PFC Boost Inductor

In normal operating mode, the nominal output power is

estimated by the following equation.

where:

Porated output power of the system

ηefficiency of the boost converter (estimated as 100%

by the PFC algorithm)

Vin(min) minimum RMS line voltage is 108V, measured after

the rectifier and EMI fi lter

Vlink nominal PFC output voltage must be 460 V

fmax maximum switching frequency is 70 kHz

LBboost inductor specified by rated power requirement

αmargin factor to guarantee rated output power (Po)

against boost inductor tolerances.

Equation 1 is provided for explanation purposes only. Using

substituted required design values for Vlink and fmax gives the

following equation.

Changing values for appli cation-specific devices such as the

boost inductor or Vlink voltage is not recommended and

requires changing internal register values.

Solving Equation 2 for the PFC boost inductor LB gives the

following equation.:

If a value of the boost inductor other than that obtained from

Equation 3 above is used, the total output power capability as

well as the minimum input voltage threshold will differ

according to Equation 2.

Figure 15. Relative Effect s of Varying Boost Inductance

5.5 PFC Output Capacitor

The value of the PFC output capacitor should be chosen

based upon voltage ripple and hold-up requirements. To

ensure system stability with the digital controller, the

recommended value of the capacitor is within the range of

0.25 μF / watt to 0.5 μF/watt.

5.6 Output IFB Sense & Input IAC Sense

A current proportional to the PFC output voltage, Vlink, is

supplied to the IC on pin IFB and is used as a feedback control

signal. This current is compared against an internal fixed-

value current.

The ADC is used to measure the magnitude of the IFB current

through resistor RIFB. The magnitude of the IFB current is then

compared to an internal fixed-value current.

Figure 16. Feedb ack Input Pin Model

Resistor RIFB sets the feedback current and is calculated as

follows:

By using digital loop compensation, the voltage feedback

signal does not require an external compensation network.

A current proportional to the AC input voltage is supplied to the

IC on pin IAC and is used by the PFC control algorithm.

Figure 17. IAC Input Pin Model

Resistor RIAC sets the IAC current and is derived as follows:

For optimal performance, resistors RIAC & RIFB should use 1%

tolerance or better resistors.

oαη Vin min()

()×2

×Vlink Vin min() 2×()–

max LBVlink

×××

---------------------------------------------------------

×=[Eq.1]

oαη 108V()×2

×460V 108V 2×()–

270kHzL

B460V×××

-------------------------------------------------------------

×=[Eq.2]

LBαη 108V()×2

×460V 108V 2×()–

270kHzP

o460V×××

-------------------------------------------------------------

×=[Eq.3]

AC(rms)

108 305

o(max)

L > L

/α

L = L

L < L

/α

IFB

VDD

15k

link

CS1600

24k ADC

R3 R

IFB

RIFB Vlink Vdd

–

Ifixed

----------------------------460V Vdd

–

129μA

------------------------------

== [Eq.4]

R1 R

IAC

IA C

VDD

15k

rect

CS1600

24k ADC

RIAC RIFB

=[Eq.5]

CS1600

10 DS904F1

5.7 Brownout Protection

As an added protecti on to the PFC boost stage, the CS160 0

includes a failure mechanism that detects high average

currents that occur under abnormal brownout co nditio ns. Th e

brownout protection feature monitors the Vrect input signal and

suspends the gate-drive switching when a brownout threshold

breach is detected. Under normal conditions, the CS1600 will

never reach the brownout threshold, as the PFC stage is

automatically protected by the power limitation of Equatio n 2,

see section 5.4 Output Power and PFC Boost Inductor on

page 9. In the event that the boost inductor is significantly less

than the target value of L B, the browno ut protection threshol d

may be breached. However, under normal operating

conditions with proper boost inductance, this will not occur.

If a brownout event is detected, the CS1600 enters standby,

and upon recovery from brownout enters normal operation

mode. In order to avoid an erroneous brownout detection,

hysteresis and minimum detection time is implemented to

avoid brownout detection during input transients. Figure 5.8

illustrates the brownout entry and exit timing. If the input line

voltage is lower than the threshold for a fixed period of time, a

brownout is declared. The measured voltage decreases at a

rate of 5 V / half-line-cycle (~8 ms for 60 Hz line frequency).

The CS1600 triggers a timer when the measured voltage falls

below the lower brownout threshold. The IC asserts the

brownout protection and stops the gate-d rive switching only if

the timer reaches more than 56 ms, which is determined by

the minimum line frequency..

Figure 18. Brownout Sequence

During the brownout state, the device continues monitoring

the input line voltage. The device exits the brownout state

when the input voltage peak value exceeds the brownout

upper threshold for at least 56 ms.

The maximum response time of the brownout protection

normally happens at light-load conditions. It can be calculated

by the following equation:

5.8 Overvoltage Protection

The overvoltage protection (OVP) will trigger immediately and

stop the gate drive when the current into the IFB pin (IOVP)

exceeds 105% of the reference current value (Iref). The IC

resumes gate drive switching when the link voltage drops

below VOVP –V

OVP(HY).

5.9 Open/Short Loop Protection

If the PFC output sense resistor RIFB fails (open or short to

GND), the measured output voltage decre ases at a slew rate

of about 2V / μs, which is determined by ADC sampling rate.

The IC stops the gate drive when the measured output voltage

is lower than the measured line voltage. The IC resumes gate

drive switching when the current into the IFB pin becomes

larger than or equal to the current into the IAC pin and Vlink is

greater than the peak of the line voltage (Vrect(pk)). The

maximum response time of open/short loop protection for RIFB

is about 150 μs in the CS1600.

If the PFC input sense resistor RIAC fails (open or short to

GND), the current reference signal supplied to the IC on pin

IAC falls to zero.

56 m s

Start

Timer

Enter Standby Exit Standby

Upper

Lower

Brownout

Thresholds

Start Timer

Brownout

116.8 ms=

[Eq.6]

TBrownout 8ms 8ms

------------ 128V VBP th()

–()56ms++=

8=8

---128 95–()56++

CS1600

DS904F1 11

6. SUMMARY OF EQUATIONS

Eq. # Equation Variables/Recommended Values

Output Power (page 9)

Porated output power of the system

ηefficiency of the boost converter (estimated as

100% by the PFC algorithm)

Vin(min) minimum RMS line voltage is 108V, measured

after the rectifier and EMI filter

Vlink nominal PFC output voltage must be 460 V

fmax maximum switching frequency is 70 kHz

LBboost inductor specified by rated power

requirement

αmargin factor to guarantee rated output power

(Po) against boost inductor tolerances.

Output Power w/ required values (page 9)

Boost Inductor (page 9)

Output IFB Sense Resistor (page 9)

Input IAC Sense Resistor (page 9)

Boost Inductor Peak Current

Boost Inductor RMS Current

Vlink Voltage Ripple Cout Va lue of the output capacitor in microfarads.

fline(min) Minimum line frequency.

oαη Vin min()

()×2

×Vlink Vin min() 2×()–

max LBVlink

×××

---------------------------------------------------------

×=

oαη Vin min()

()×2

×460V Vin min() 2×()–

270kHzL

B460V×××

-------------------------------------------------------------

×=

LBαη Vin min()

()×2

×460V Vin min() 2×()–

270kHzP

o460V×××

-------------------------------------------------------------

×=

RIFB Vlink Vdd

–

Ifixed

----------------------------460V Vdd

–

129μA

------------------------------

RIAC RIFB

ILB pk()

ηV×in min() 2×

--------------------------------------------

ILB rms()

Vin min()

η×

------------------------------

ΔVlink rip()

2πfline min()

×460×Cout

----------------------------------------------------------------------

CS1600

12 DS904F1

7. SUMMARY OF TERMS

Variable Definition

ηThe efficiency factor.

αA margin factor to guarantee rated power against tolerances and transients.

fline(min) The minimum AC line frequency.

IAC The current generated by Vrect that flows into the IAC pin.

IFB The current generated by Vlink that flows into the IFB pin.

IFET(pk) The PFC MOSFET peak current, which is equal to the peak current in the PFC boost inductor.

Irms The magnitude of the RMS current.

Isat The boost inductor LB saturation current.

Ist The sum of the current into the IAC and IFB pins.

IST The startup current of the chip.

LBThe PFC boost inductor.

PoThe nominal output power from the CS1600 PFC circuit.

Po(max) The maximum value of the output power from the CS1600 PFC circuit.

RIAC The sense resistor u s ed to meas ure current into the IAC pin.

RIFB The sense resistor used to mea s ure curr ent into the IFB pin.

Vin(min) The minimum specified line voltage for proper operation (volts RMS).

Vlink The magnitude of the output voltage from the PFC.

Vlink(min) The magnitude of the output voltage from the PFC.

ΔVlink(rip) ΔVlink(rip), is the output voltage ripple requirement in volts peak-to-peak

Vrect The instantaneous value of the rectified line voltage (volts).

CS1600

DS904F1 13

8. PACKAGE DRAWING

9. ORDERING INFORMATION

10.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.053 0.069 1.35 1.75

A1 0.004 0.010 0.10 0.25

B 0.013 0.020 0.33 0.51

C 0.007 0.010 0.19 0.25

D 0.189 0.197 4.80 5.00

E 0.150 0.157 3.80 4.00

e 0.040 0.060 1.02 1.52

H 0.228 0.244 5.80 6.20

L 0.016 0.050 0.40 1.27

∝0° 8° 0° 8°

JEDEC # MS-012

8L SOIC (150 MIL BODY) PACKAGE DRAWING

∝

SEATING

PLANE

Part # Temperature Range Package Description

CS1600-FSZ -40 °C to +125 °C 8-lead SOIC, Lead (Pb) Free

Model Number Peak Reflow Temp MSL Ratinga

a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Max Floor Lifeb

b. Stored at 30 °C, 60% relative humidity.

CS1600-FSZ 260 °C 2 365 Days

CS1600

14 DS904F1

11.REVISION HISTORY

Revision Date Changes

A8 SEP 2010 Replaced typical connection, pinout, and block diagram.

F1 NOV 2010 Revised Brownout section. Finalized data sheet for QPL 1.

Contacting Cirrus Lo gic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to http://www.cirrus.com

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