S-8253A/B Series
www.ablicinc.com
BATTERY PROTECTION IC
FOR 2-SERIAL OR 3-SERIAL-CELL PACK
© ABLIC Inc., 2003-2010 Rev.5.0_01
1
The S-8253A/B Series are protection ICs for 2-serial or 3-serial cell lithium-ion rechargeable batteries and include high-
accuracy voltage detectors and delay circuits.
These ICs are suitable for protecting lithium-ion rechargeable battery packs from overcharge, overdischarge and overcurrent.
Features
(1) High-accuracy voltage detection for each cell
Overcharge detection voltage n (n 1 to 3) 3.9 V to 4.4 V (50 mV steps) Accuracy 25 mV
Overcharge release voltage n (n 1 to 3) 3.8 V to 4.4 V *1 Accuracy 50 mV
Overdischarge detection voltage n (n 1 to 3) 2.0 V to 3.0 V (100 mV steps) Accuracy 80 mV
Overdischarge release voltage n (n 1 to 3) 2.0 V to 3.4 V *2 Accuracy 100 mV
(2) Three-level overcurrent detection (Including load short circuiting detection)
Overcurrent detection voltage 1 0.05 V to 0.30 V (50 mV steps) Accuracy 25 mV
Overcurrent detection voltage 2 0.5 V (Fixed)
Overcurrent detection voltage 3 1.2 V (Fixed)
(3) Delay times (Overcharge, Overdischarge, Overcurrent) are generated by an internal circuit. (External capacitors
are unnecessary).
(4) Charge / discharge operation can be inhibited via the control pin.
(5) 0 V battery charge function available / unavailable are selectable.
(6) High-voltage withstand devices Absolute maximum rating 26 V
(7) Wide operating voltage range 2 V to 24 V
(8) Wide operating temperature range 40C to 85C
(9) Low current consumption
Operation mode 28 A max. (25C)
Power-down mode 0.1 A max. (25C)
(10) Lead-free, Sn100%, halogen-free*3
*1. Overcharge release voltage Overcharge detection voltage Overcharge hysteresis voltage
(Overcharge hysteresis voltage n (n 1 to 3) can be selected as 0 V or from a range of 0.1 V to 0.4 V in
50 mV steps.)
*2. Overdischarge release voltage Overdischarge detection voltage Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage n (n 1 to 3) can be selected as 0 V or from a range of 0.2 V to 0.7 V in
100 mV steps.)
*3. Refer to “Product Name Structure” for details.
Applications
Lithium-ion rechargeable battery packs
Lithium polymer rechargeable battery packs
Package
8-Pin TSSOP
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
2
Block Diagrams
1. S-8253A Series
COP
VDD
DOP
VMP 95 k
900 k
Oscillator, counter,
controller
200 nA
CTL
CTLH
CTLM
VC1
VC2
VSS
Remark All diodes shown in figure are parasitic diodes.
Figure 1
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
3
2. S-8253B Series
COP
VDD
DOP
VMP 95 k
900 k
Oscillator, counter,
controller
200 nA
CTL
CTLH
CTLM
VC1
VC2
VSS
Remark All diodes shown in figure are parasitic diodes.
Figure 2
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
4
Product Name Structure
1. Product Name
1. 1 Environmental code = U
S-8253 x xx T8T1 U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
T8T1: 8-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
Product series name
A: 2-cell
B: 3-cell
*1. Refer to the tape specifications.
*2. Refer to the “3. Product Name List”.
1. 2 Environmental code = G
S-8253 x xx T8T1 G Z
Environmental code
G: Lead-free (for details, please contact our sales office)
Package abbreviation and IC packing specifications*1
T8T1: 8-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
Product series name
A: 2-cell
B: 3-cell
Fixed
*1. Refer to the tape specifications.
*2. Refer to the “3. Product Name List”.
2. Package
Package Name Drawing Code
Package Tape Reel
8-Pin TSSOP Environmental code = G FT008-A-P-SD FT008-E-C-SD FT008-E-R-SD
Environmental code = U FT008-A-P-SD FT008-E-C-SD FT008-E-R-S1
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
5
3. Product Name List
Table 1 S-8253A Series (For 2-Serial Cell)
Model No.
Overcharge
detection voltage
[V
CU
]
Overcharge
release voltage
[V
CL
]
Overdischarge
detection voltage
[V
DL
]
Overdischarge
release voltage
[V
DU
]
Overcurrent
detection voltage 1
[V
IOV1
]
0 V battery
charge function
S-8253AAA-T8T1
4.350
0.025 V 4.050
0.050 V 2.40
0.080 V 2.70
0.100 V 0.300
0.025 V Available
S-8253AAB-T8T1
4.350
0.025 V 4.050
0.050 V 2.70
0.080 V 2.70
0.080 V 0.300
0.025 V Available
S-8253AAC-T8T1
4.350
0.025 V 4.050
0.050 V 2.40
0.080 V 2.70
0.100 V 0.080
0.025 V Available
S-8253AAD-T8T1
4.250
0.025 V 4.050
0.050 V 2.40
0.080 V 2.70
0.100 V 0.120
0.025 V Available
S-8253AAE-T8T1
4.350
0.025 V 4.050
0.050 V 2.80
0.080 V 3.00
0.100 V 0.300
0.025 V Available
S-8253AAF-T8T1
4.350
0.025 V 4.050
0.050 V 2.40
0.080 V 2.60
0.100 V 0.300
0.025 V Unavailable
S-8253AAG-T8T1
4.280
0.025 V 4.080
0.050 V 2.40
0.080 V 2.70
0.100 V 0.150
0.025 V Unavailable
S-8253AAH-T8T1
4.350
0.025 V 4.150
0.050 V 2.30
0.080 V 2.30
0.080 V 0.090
0.025 V Available
Table 2 S-8253B Series (Fo r 3-Serial Cell)
Model No.
Overcharge
detection voltage
[V
CU
]
Overcharge
release voltage
[V
CL
]
Overdischarge
detection voltage
[V
DL
]
Overdischarge
release voltage
[V
DU
]
Overcurrent
detection voltage 1
[V
IOV1
]
0 V battery
charge function
S-8253BAA-T8T1
4.350
0.025 V 4.050
0.050 V 2.40
0.080 V 2.70
0.100 V 0.300
0.025 V Available
S-8253BAB-T8T1
4.325
0.025 V 4.075
0.050 V 2.20
0.080 V 2.90
0.100 V 0.200
0.025 V Unavailable
S-8253BAC-T8T1
4.350
0.025 V 4.050
0.050 V 2.40
0.080 V 2.70
0.100 V 0.080
0.025 V Available
S-8253BAD-T8T1
4.250
0.025 V 4.050
0.050 V 2.40
0.080 V 2.70
0.100 V 0.120
0.025 V Available
S-8253BAE-T8T1
4.350
0.025 V 4.150
0.050 V 2.20
0.080 V 2.40
0.100 V 0.100
0.025 V Available
S-8253BAF-T8T1
4.280
0.025 V 4.180
0.050 V 2.20
0.080 V 2.50
0.100 V 0.190
0.025 V Unavailable
S-8253BAG-T8T1
4.280
0.025 V 4.180
0.050 V 2.20
0.080 V 2.50
0.100 V 0.125
0.025 V Unavailable
S-8253BAH-T8T1
4.350
0.025 V 4.150
0.050 V 2.20
0.080 V 2.40
0.100 V 0.250
0.025 V Available
S-8253BAI-T8T1
4.350
0.025 V 4.150
0.050 V 2.20
0.080 V 2.40
0.100 V 0.160
0.025 V Available
Remark 1. Please contact the ABLIC Inc. marketing department for the products with the detection voltage value other
than those specified above.
2. : GZ or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
6
Pin Configuration
DOP
COP
VMP
CTL
VDD
VC1
VC2
VSS
8-Pin T SSO P
Top view
1
2
3
4
8
7
6
5
Table 3 S-8253A Series
Pin No. Symbol Description
1 DOP
Connection pin for discharge control FET gate
(CMOS output)
2 COP
Connection pin for charge control FET gate
(Nch open-drain output)
Figure 3 3 VMP
Pin for voltage detection between VDD and VMP
(Detection pin for overcurrent)
4 CTL
Input pin for charge / discharge control signal,
Pin for shortening test time
( L : Normal operation,
H : inhibit charge / discharge
M (VDD 1 / 2) : shorten test time)
5 VSS
Input pin for negative power supply ,
Connection pin for negative voltage of battery 2
6 VC2 No connection
*1
7 VC1
Connection pin for negative voltage of battery 1,
for positive voltage of battery 2
8 VDD Input pin for positive power supply ,
Connection pin for positive voltage of battery 1
*1. No connection is electrically open. This pin can be connected to VDD or
VSS.
Remark Refer to the package drawings for the external views.
Table 4 S-8253B Series
Pin No. Symbol Description
1 DOP
Connection pin for discharge control FET gate
(CMOS output)
2 COP
Connection pin for charge control FET gate
(Nch open-drain output)
3 VMP
Pin for voltage detection between VDD and VMP
(Detection pin for overcurrent)
4 CTL
Input pin for charge / discharge control signal,
pin for shortening test time
( L : Normal operation,
H : inhibit charge / discharge,
M (VDD 1 / 2) : shorten test time)
5 VSS
Input pin for negative power supply ,
Connection pin for negative voltage of battery 3
6 VC2
Connection pin for negative voltage of battery 2,
for positive voltage of battery 3
7 VC1
Connection pin for negative voltage of battery 1,
for positive voltage of battery 2
8 VDD Input pin for positive power supply ,
Connection pin for positive voltage of battery 1
Remark Refer to the package drawings for the external views.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
7
Absolute Maximum Ratings
Table 5 (Ta 25C unless otherwise specified)
Item Symbol Applicable Pins Absolute Maximum Ratings Unit
Input voltage between VDD and VSS VDS VSS 0.3 to VSS 26 V
Input pin voltage VIN VC1, VC2 VSS 0.3 to VDD 0.3 V
VMP pin input voltage VVMP VMP VSS 0.3 to VSS 26 V
DOP pin output voltage VDOP DOP VSS 0.3 to VDD 0.3 V
COP pin output voltage VCOP COP VSS 0.3 to VVMP 0.3 V
CTL input pin voltage VINCTL CTL VSS 0.3 to VDD 0.3 V
Power dissipation PD 300 (When not mounted on board) mW
700*1 mW
Operating ambient temperature Topr 40 to 85 C
Storage temperature Tstg 40 to 125 C
*1. When mounted on board
[Mounted board]
(1) Board size : 114.3 mm 76.2 mm t1.6 mm
(2) Board name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding w h ich the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
0 50 100 150
600
400
200
0
Power Dissipation (P
D
) [mW]
Ambient Temperature (Ta) [C]
500
300
100
700
800
Figure 4 Power Dissipation of Package (When Mounted on Board)
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
8
Electrical Characteristics
1. Except Detection Delay Time Table 6 (1 / 2) (Ta 25C unless otherwise specified)
Item Symbol Conditions Min. Typ. Max. Unit
Test
condi-
tion
Test
circuit
DETECTION VOLTAGE
Overcharge detection voltage n V
CUn
3.90 V to 4.40 V, Adjustable V
CUn
0.025 V
CUn
V
CUn
0.025 V 1 1
Overcharge release voltage n V
CLn
3.80 V to 4.40 V,
Adjustable
V
CL
V
CU
V
CLn
0.05 V
CLn
V
CLn
0.05 V 1 1
V
CL
V
CU
V
CLn
0.025 V
CLn
V
CLn
0.025 V 1 1
Overdischarge detection voltage n V
DLn
2.0 V to 3.0 V, Adjustable V
DLn
0.080 V
DLn
V
DLn
0.080 V 1 1
Overdischarge release voltage n V
DUn
2.0 V to 3.40 V,
Adjustable
V
DL
V
DU
V
DUn
0.10 V
DUn
V
DUn
0.10 V 1 1
V
DL
V
DU
V
DUn
0.08 V
DUn
V
DUn
0.08 V 1 1
Overcurrent detection voltage 1 V
IOV1
0.05 V to 0.30 V, Adjustable
Based on V
DD
V
IOV1
0.025 V
IOV1
V
IOV1
0.025 V 2 1
Overcurrent detection voltage 2 V
IOV2
Based on V
DD
0.40 0.50 0.60 V 2 1
Overcurrent detection voltage 3 V
IOV3
Based on V
DD
0.9 1.2 1.5 V 2 1
Temperature coefficient 1
*1
T
COE1
Ta
0°C to 50°C
*3
1.0 0 1.0 mV /
C
Temperature coefficient 2
*2
T
COE2
Ta
0°C to 50°C
*3
0.5 0 0.5 mV /
C
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage V
0CHA
0 V battery charging available
0.8 1.5 V 12 5
0 V battery charge inhibition battery
voltage V
0INH
0 V battery charging unavailable 0.4 0.7 1.1 V 12 5
INTERNAL RESISTANCE
Resistance between VMP and VDD R
VMD
V1
V2
V3
*4
3.5 V, V
VMP
V
SS
70 95 120
k
6 2
Resistance between VMP and VSS R
VMS
V1
V2
V3
*4
1.8 V, V
VMP
V
DD
450 900 1800 k
6 2
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
9
Table 6 (2 / 2) (Ta 25C unless otherwise specified)
Item Symbol Conditions Min. Typ. Max. Unit
Test
condi-
tion
Test
circuit
INPUT VOLTAGE
Operating voltage
between VDD and VSS V
DSOP
Output voltage of DOP and COP fixed 2
24 V
CTL input voltage “H” V
CTLH
V
DD
0.5
V 7 1
CTL input voltage “L” V
CTLL
V
SS
0.5 V 7 1
INPUT CURRENT
Current consumption on operation I
OPE
V1
V2
V3
*4
3.5 V
14 28
A 5 2
Current consumption at power down I
PDN
V1
V2
V3
*4
1.5 V
0.1
A 5 2
VC1 pin current I
VC1
V1
V2
V3
*4
3.5 V
0.3 0 0.3
A 9 3
VC2 pin current I
VC2
V1
V2
V3
*4
3.5 V
0.3 0 0.3
A 9 3
CTL pin current “H” I
CTLH
V1
V2
V3
*4
3.5 V, V
CTL1
V
DD
0.1
A 8 3
CTL pin current “L” I
CTLL
V1
V2
V3
*4
3.5 V, V
CTL1
V
SS
0.4 –0.2
A 8 3
OUTPUT CURRENT
COP pin leakage current I
COH
V
COP
24 V
0.1
A 10 4
COP pin sink current I
COL
V
COP
V
SS
0.5 V 10
A 10 4
DOP pin source current I
DOH
V
DOP
V
DD
0.5 V 10
A 11 4
DOP pin sink current I
DOL
V
DOP
V
SS
0.5 V 10
A 11 4
*1. Voltage temperature coefficient 1 : Overcharge detection voltage
*2. Voltage temperature coefficient 2 : Overcurrent detection voltage 1
*3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
*4. Because S-8253A Series are the protection ICs for 2-serial cell, there is no V3 for them.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
10
2. Detection Delay Time
(1) S-8253AAA, S-8253AAB, S-8253AAC, S-8253AAD, S-8253AAE, S-8253AAF, S-8253AAG, S-8253BAA,
S-8253BAC, S-8253BAD, S-8253BAE, S-8253BAH
Table 7
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
tCU
0.92 1.15 1.38 s 3 1
Overdischarge detection delay time
tDL
115 144 173 ms 3 1
Overcurrent detection delay time 1
tIOV1
7.2 9 10.8 ms 4 1
Overcurrent detection delay time 2
tIOV2
3.6 4.5 5.4 ms 4 1
Overcurrent detection delay time 3
tIOV3
220 300 380
s
4 1
(2) S-8253BAB, S-8253BAF, S-8253BAG, S-8253BAI
Table 8
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
tCU
0.92 1.15 1.38 s 3 1
Overdischarge detection delay time
tDL
115 144 173 ms 3 1
Overcurrent detection delay time 1
tIOV1
3.6 4.5 5.4 ms 4 1
Overcurrent detection delay time 2
tIOV2
0.89 1.1 1.4 ms 4 1
Overcurrent detection delay time 3
tIOV3
220 300 380
s
4 1
(3) S-8253AAH
Table 9
Item Symbol Condition Min. Typ. Max. Unit
Test
Condition Test
Circuit
DELAY TIME (Ta = 25°C)
Overcharge detection delay time
tCU
0.92 1.15 1.38 s 3 1
Overdischarge detection delay time
tDL
115 144 173 ms 3 1
Overcurrent detection delay time 1
tIOV1
14.5 18 22 ms 4 1
Overcurrent detection delay time 2
tIOV2
3.6 4.5 5.4 ms 4 1
Overcurrent detection delay time 3
tIOV3
220 300 380
s
4 1
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
11
Test Circuits
1. Overcharge Detection Voltage 1, Overcharge Release Voltage 1, Overdischarge Detection Voltage 1,
Overdischarge Release Voltage 1
(Test Condition 1, Test Circuit 1)
Confirm that V1 V2 3.5 V (S-8253A Series), V1 V2 V3 3.5 V (S-8253B Series), V4 0 V, V5 0 V, and the
COP and DOP pins are “L” (VDD 0.1 V or lower) (this status is referred to as the initial status).
1. 1 Overcharge Detection Voltage 1 (VCU1), Overcharge Release Voltage 1 (VCL1)
Overcharge detection voltage 1 (VCU1) is the voltage of V1 when the voltage of the COP pin is “H” (VDD 0.9 V or
more) after the V1 voltage has been gradually increased starting at the initial status. Overcharge release voltage
1 (VCL1) is the voltage of V1 when the voltage at the COP pin is low after the V1 voltage has been gradually
decreased.
1. 2 Overdischarge Detection Voltage 1 (VDL1), Overdischarge Release Voltage 1 (VDU1)
Overdischarge detection voltage 1 (VDL1) is the voltage of V1 when the voltage of the DOP pin is high after the V1
voltage has been gradually decreased starting at the initial status. Overdischarge release voltage 1 (VDU1) is the
voltage of V1 when the voltage at the DOP pin is low after the V1 voltage has been gradually increased.
By changing Vn (n 2: S-8253A Series, n 2, 3: S-8253B Series) the overcharge detection voltage (VCUn),
overcharge release voltage (VCLn), overdischarge detection voltage (VDLn), and overdischarge release voltage (VDUn)
can be measured in the same way as when n 1.
2. Overcurrent Detection Voltage 1, Ov ercurrent Detection Voltage 2, Overcurrent Detection Voltage 3
(Test Condition 2, Test Circuit 1)
Confirm that V1 V2 3.5 V (S-8253A Series), V1 V2 V3 3.5 V (S-8253B Series), V4 0 V, V5 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
2. 1 Overcurrent Detection Voltage 1 (VIOV1)
Overcurrent detection voltage 1 (VIOV1) is the voltage of V5 when the voltages of the COP pin and DOP pin are
high after the V5 voltage has been gradually increased starting at the initial status.
2. 2 Overcurrent Detection Voltage 2 (VIOV2)
Overcurrent detection voltage 2 (VIOV2) is the voltage of V5 when the voltages of the COP pin and DOP pin are
high within the minimum and maximum values of overcurrent detection time 2 (tIOV2) after the voltage of V5 was
instantaneously increased (within 10 s) starting at the initial status.
2. 3 Overcurrent Detection Voltage 3 (VIOV3)
Overcurrent detection voltage 3 (VIOV3) is the voltage of V5 when the voltages of the COP pin and DOP pin are
high within the minimum and maximum values of overcurrent detection time 3 (tIOV3) after the voltage of V5 was
instantaneously increased (within 10 s) starting at the initial status.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
12
3. Overcharge Detection Delay Time, Overdischarge Detection Delay Time
(Test Condition 3, Test Circuit 1)
Confirm that V1 V2 3.5 V (S-8253A Series), V1 V2 V3 3.5 V (S-8253B Series), V4 0 V, V5 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
3. 1 Overcharge Detection Delay Time (tCU)
The overcharge detection delay time (tCU) is the time it takes for the voltage of the COP pin to change from low to
high after the voltage of V1 is instantaneously changed from overcharge detection voltage 1 (VCU1) 0.2 V to
overcharge detection voltage 1 (VCU1) 0.2 V (within 10 s) starting at the initial status.
3. 2 Overdischarge Detection Delay Time (tDL)
The overdischarge detection delay time (tDL) is the time it takes for the voltage of the DOP pin to change from low
to high after the voltage of V1 is instantaneously changed from overdischarge detection voltage 1 (VDL1) 0.2 V to
overdischarge detection voltage 1 (VDL1) 0.2 V (within 10 s) starting at the initial status.
4. Overcurrent Detection Delay Time 1, Detection Delay Time 2, Detection Delay Time 3
(Test Condition 4, Test Circuit 1)
Confirm that V1 V2 3.5 V (S-8253A Series), V1 V2 V3 3.5 V (S-8253B Series), V4 0 V, V5 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
4. 1 Overcurrent Detection Delay Time 1 (tIOV1)
Overcurrent detection delay time 1 (tIOV1) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 0.35 V (within 10 s) starting at the initial status.
4. 2 Overcurrent Detection Delay Time 2 (tIOV2)
Overcurrent detection delay time 2 (tIOV2) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 0.7 V (within 10 s) starting at the initial status.
4. 3 Overcurrent Detection Delay Time 3 (tIOV3)
Overcurrent detection delay time 3 (tIOV3) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 1.6 V (within 10 s) starting at the initial status.
5. Consumption on Operation, Power Consumption at Power-down
(Test Condition 5, Test Circuit 2)
5. 1 Power Consumption on Operation (IOPE)
The power consumption during operation (IOPE) is the current of the VSS pin (ISS) when V1 V2 3.5 V (S-8253A
Series), V1 V2 V3 3.5 V (S-8253B Series), S1 ON, and S2 OFF.
5. 2 Power Consumption at Power-down (IPDN)
The power consumption at power-down (IPDN) is the current of the VSS pin (ISS) when V1 V2 1.5 V (S-8253A
Series), V1 V2 V3 1.5 V (S-8253B Series), S1 OFF, and S2 ON.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
13
6. Resistance between VMP and VDD, Resistance between VMP and VSS
(Test Condition 6, Test Circuit 2)
Confirm that V1 V2 3.5 V (S-8253A Series), V1 V2 V3 3.5 V (S-8253B Series), S1 ON, and S2 OFF (this
status is referred to as the initial status).
6. 1 Resistance between VMP and VDD (RVMD)
The resistance between VMP and VDD (RVMD) is determined based on the current of the VMP pin (IVMD) after S1
and S2 are switched to OFF and ON, respectively, starting at the initial status.
S-8253A Series : RVMD (V1 V2) / IVMD
S-8253B Series : RVMD (V1 V2 V3) / IVMD
6. 2 Resistance between VMP and VSS (RVMS)
The resistance between VMP and VSS (RVMS) is determined based on the current of the VMP pin (IVMS) after V1
V2 1.8 V (S-8253A Series) or V1 V2 V3 1.8 V (S-8253B Series) are set starting at the initial status.
S-8253A Series : RVMS (V1 V2) / IVMS
S-8253B Series : RVMS (V1 V2 V3) / IVMS
7. CTL Pin Input Voltage “H”
(Test Condition 7, Test Circuit 1)
Confirm that V1 V2 3.5 V (S-8253A Series), V1 V2 V3 3.5 V (S-8253B Series), V4 0 V, V5 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
7. 1 CTL Pin Input Voltage “H” (VCTLH)
The CTL pin input voltage “H” (VCTLH) is the voltage of V4 when the voltages of the CO P pin and DOP pin are high
after the voltage of V4 has been gradually increased starting at the initial status.
8. CTL Pin Input Voltage “L”
(Test condition 7, Test circuit 1)
Confirm that V1 V2 3.5 V (S-8253A Series), V1 V2 V3 3.5 V (S-8253B Series), V4 0 V, V5 0.35 V, and
the COP pin and DOP pin are high (this status is referred to as the initial status).
8. 1 CTL Pin Input Voltage “L” (VCTLL)
The CTL pin input voltage “L” (VCTLL) is the voltage of V4 when the voltages of the COP pin and DOP pin are low
after the voltage of V4 has been gradually increased starting at the initial status.
9. CTL Pin Current “H”, CTL Pin Current “L”
(Test Condition 8, Test Circuit 3)
9. 1 CTL Pin Current “H” (ICTLH), CTL Pin Current “L” (ICTLL)
The CTL pin current “H” (ICTLH) is the current that flows through the CTL pin when V1 V2 3.5 V (S-8253A
Series), V1 V2 V3 3.5 V (S-8253B Series), and S3 ON, S4 OFF. The CTL current “L” (ICTLL) is the
current that flows through the CTL pin when S3 OF F and S4 ON after that.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
14
10. VC1 Pin Current, VC2 Pin Current
(Test Condition 9, Test Circuit 3)
10. 1 VC1 Pin Current (IVC1), VC2 Pin Current (IVC2)
The VC1 pin current (IVC1) is the current that flows through the VC1 pin when V1 V2 3.5 V (S-8253A Series),
V1 V2 V3 3.5 V (S-8253B Series), and S3 OFF, S4 ON. Similarly, the VC2 pin current (IVC2) is the
current that flows through the VC2 pin under these conditions (S-8253B Series only).
11. COP Pin Leakage Current, COP Pin Sink Current
(Test Condition 10, Test Circuit 4)
11. 1 COP Pin Leakage Cu rrent (ICOH)
The COP pin leakage current (ICOH) is the current that flows through the COP pin when V1 V2 12 V (S-8253A
Series), V1 V2 V3 8 V (S-8253B Series), S6 S7 S8 OFF, and S5 ON.
11. 2 COP Pin Sink Current (ICOL)
The COP pin sink current (ICOL) is the current that flows through the COP pin when V1 V2 3.5 V (S-8253A
Series), V1 V2 V3 3.5 V (S-8253B Series), V6 0.5 V, S5 S7 S8 OFF, and S6 ON.
12. DOP Pin Source Current, DOP Pin Sink Current
(Test Condition 11, Test Circuit 4)
12. 1 DOP Pin Source Curren t (IDOH)
The DOP pin source current (IDOH) is the current that flows through the DOP pin when V1 V2 1.8 V (S-8253A
Series), V1 V2 V3 1.8 V (S-8253B Series), V7 0.5 V, S5 S6 S8 OFF, and S7 ON.
12. 2 DOP Pin Sink Current (IDOL)
The DOP pin sink current (IDOL) is the current that flows through the DOP pin when V1 V2 3.5 V (S-8253A
Series), V1 V2 V3 3.5 V (S-8253B Series), V8 0.5 V, S5 S6 S7 OFF, and S8 ON.
13.
0 V Battery Charge Starting Battery Charger Voltage (Product with 0 V Battery Charge Function),
0 V Battery Charge Inhibition Battery Voltage (Product with 0 V Battery Charge Inhibition Function)
(Test Condition 12, Test Circuit 5)
13. 1 0 V Battery Charge Starting Battery Charger Voltage (V0CHA) (Product with 0 V Battery Charge
Function)
The COP pin voltage should be lower than V0CHA max. 1 V when V1 V2 0 V (S-8253A Series), V1 V2 V3
0 V (S-8253B Series), and V9 VVMP V0CHA max.
13. 2 0 V Battery Charge Inhibition Battery Voltage (V0INH) (Product with 0 V Battery Charge Inhibition
Function)
The COP pin voltage should be higher than VVMP 1 V when V1 V2 V0INH min. (S-8253A Series), V1 V2
V3 V0INH min. (S-8253B Series), and V9 VVMP 24 V.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
15
V5
1 M DOP 1
COP 2
VMP 3
CTL 4
8VDD
7VC1
6VC2
5VSS
V
V
1 F
V2
V4
V1
S-8253A
V5
1 M
V V
1 F
V2
V4
V1
DOP
1
COP 2
VMP 3
CTL 4
8VDD
7VC1
6VC2
5 VSS
S-8253B
V3
Figure 5 Test Circuit 1
S1
DOP 1
COP 2
VMP 3
CTL 4
8 VDD
7 VC1
6 VC2
5VSS
A 1 F
V2
S2
V1
S-8253A
A
S1
DOP 1
COP 2
VMP 3
CTL 4
8VDD
7VC1
6VC2
5VSS
A
1 F
V2
S2
V1
S-8253B
A
V3
Figure 6 Test Circuit 2
S3
DOP 1
COP 2
VMP 3
CTL 4
8 VDD
7 VC1
6 VC2
5VSS
A
1 F
V2
S4
V1
S-8253A
A
S3
DOP 1
COP 2
VMP 3
CTL 4
8VDD
7VC1
6VC2
5VSSA
1 F
V2
S4
V1
S-8253B
A
A V3
Figure 7 Test Circuit 3
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
16
S5
DOP
1
COP
2
VMP
3
CTL
4
8VDD
7VC1
6VC2
5VSS
A
1 F
V2
S6
V1
S-8253A
A
V8
S7
S8
V6
V7
S5
DOP
1
COP
2
VMP
3
CTL
4
8VDD
7VC1
6VC2
5VSS
A
1 F
V2
S6
V1
S-8253B
A
V8
S7
S8
V6
V7
V3
Figure 8 Test Circuit 4
1 M
DOP
1
COP
2
VMP
3
CTL
4
8
VDD
7
VC1
6
VC2
5VSS
V
1 F
V2
V9
V1
S-8253A
1 M
DOP
1
COP
2
VMP
3
CTL
4
8
VDD
7
VC1
6
VC2
5VSS
V
1 F
V2
V9
V1
S-8253B
V3
Figure 9 Test Circuit 5
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
17
Operation
Remark Refer to “ Battery Protection IC Connection Example”.
1. Normal Status
When all of the battery voltages are in the range from VDLn to VCUn and the discharge current is lower than the
specified value (the VMP pin voltage is higher than VDD VIOV1), the charging and discharging FETs are turned on.
This condition is called the normal status, and in this condition charging and discharging can be carried out freely.
Caution When the battery is connected for the first time, discharging may not be enabled. In this case,
short the VMP pin and VDD pin or connect the ch arger to restore the normal status.
2. Overcharge Status
When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP
pin becomes high impedance. Because the COP pin is pulled up to the EB pin voltage by an external resistor, the
charging FET is turned off to stop charging. This is called the overcharge status. The overcharge status is
released when one of the following two conditions holds.
(1) All battery voltages become VCLn or lower.
(2) All of the battery voltages are VCUn or lower, and the VMP pin voltage is VDD VIOV1 or lower (since the
discharge current flows through the body diode of the charging FET immediately after discharging is started
when the charger is removed and a load is connected, the VMP pin voltage momentarily decreases by
approximately 0.6 V from the VDD pin voltage. T he IC detects this voltage and releases the overcharging
status).
3. Overdischarge Status
When any one of the battery voltages becomes lower than VDLn and the state continues for tDL or longer, the DOP pin
voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is called the
overdischarging status. After discharging is stopped due to the overdischarge status, the S-8253A/B Series enters
the power-down status.
4. Power-down Status
When discharging has stopped due to the overdischarge status, the VMP pin is pulled down to the VSS level by the
RVMS resistor. When the VMP pin voltage is lower than Typ. 0.8 V, the S-8253A/B Series enters the power-down
status. In the power-down status, almost all the circuits of the S-8253A/B Series stop and the current consumption is
IPDN or lower. The conditions of each output pin are as follows.
(1) COP pin : High-Z
(2) DOP pin : VDD
The power-down status is releas ed when the following condition holds.
(1) The VMP pin voltage is Typ. 0.8 V or higher.
The overdischarging status is released when the following two conditions hold.
(1) All battery voltage is released at VDUn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the
VMP pin voltage is lower than VDD.
(2) All battery voltage is released at VDLn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the
VMP pin voltage is VDD or higher (when a charger is connected and VMP pin voltage is VDD or higher,
overdischarge hysteresis is released and electric discharge control FET is turned on at VDLn).
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
18
5. Overcurrent Status
The S-8253A/B Series has three overcurrent detection levels (VIOV1, VIOV2, and VIOV3) and three overcurrent detection
delay times (tIOV1, tIOV2, and tIOV3) corresponding to each overcurrent detection level. When the discharging current
becomes higher than the specified value (the difference of the voltages of the VMP pin and VDD pin is greater than
VIOV1) and the state continues for tIOV1 or longer, the S-8253A/B Series enters the overcurrent status, in which the
DOP pin voltage becomes VDD level to turn off the discharging FET to stop discharging, the COP pin becomes high
impedance and is pulled up to the EB pin voltage to turn off the charging FET to stop charging, and the VMP pin is
pulled up to the VDD voltage by the internal resistor (RVMD). Operation of overcurrent detection levels 2, 3 (VIOV2,
VIOV3) and overcurrent detection delay times 2, 3 (tIOV2, tIOV3) are the same as for VIOV1 and tIOV1.
The overcurrent status is released when the following condition holds.
(1) The VMP pin voltage is VDD VIOV1 or higher because a charger is connected or the load is released.
Caution The impedance that enables automatic restoration varies depending on the battery voltage and set
value of overcurrent detection voltage 1.
6. 0 V Battery Charge Function
Regarding the charging of a self-discharged battery (0 V battery), the S-8253A/B Series has two functions from which
one should be selected.
(1) 0 V battery charging is allowed (0 V battery charging is available.)
When the charger voltage is higher than V0CHA, the 0 V battery can be charged.
(2) 0 V battery charging is prohibited (0 V battery charging is unavailable.)
When one of the battery voltages is lower than V0INH, the 0 V battery cannot be charged.
Caution When the VDD pin voltage is lower than the minimum value of VDSOP, the operation of the S-
8253A/B Series is not guaranteed.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
19
7. Delay Circuit
The following detection delay times are determined by dividing a clock of approximately 3.57 kHz by the counter.
(Example) Oscillator clock cycle (TCLK) : 280 s
Overcharge detection delay time (tCU) : 1.15 s
Overdischarge detection delay time (tDL) : 144 ms
Overcurrent detection delay time 1 (tIOV1) : 9 ms
Overcurrent detection delay time 2 (tIOV2) : 4.5 ms
Remark The overcurrent detection delay time 2 (tIOV2) and overcurrent detection delay time 3 (tIOV3) start when the
overcurrent detection voltage 1 (VIOV1) is detected. As soon as the overcurrent detection voltage 2 (VIOV2)
or overcurrent detection voltage 3 (VIOV3) is detected over the detection delay time for overcurrent 2 (tIOV2)
or overcurrent 3 (tIOV3) after the detection of overcurrent 1 (VIOV1), the S-8253A/B turns the discharging
control FET off within tIOV2 or tIOV3 of each detection.
VDD
DOP pin voltage
VSS
Overcurr ent detection
delay time 2 (t
IOV2
)
VIOV1
Time
VDD
VMP pin voltage
VSS Time
VIOV2
VIOV3
t
D
0
t
D
t
IOV2
Figure 10
8. CTL Pin
The S-8253A/B Series has a control pin for charge / discharge control and shortening the test time. The levels, “L”,
“H”, and “M”, of the voltage input to the CTL pin determine the status of the S-8253A/B Series: normal operation,
charge / discharge inhibition, or test time shortening. The CTL pin takes precedence over the battery protection
circuit. During normal use, short the CTL pin and VSS pin.
Table 10 Conditions Set by CTL Pin
CTL Pin Potential Status of IC COP Pin DOP Pin
Open Charge / discharge inhibited status High-Z VDD
High (VCTL VCTLH) Charge / discharge inhibited status High-Z VDD
Middle (VCTLL VCTL VCTLH) Delay time-shortening status *1 (
*2) (*2)
Low (VCTLL VCTL) Normal status (*2) (*2)
*1. In this status, delay times are shortened in 1 / 60 to 1 / 30 scale.
*2. The pin status is controlled by the voltage detection circuit.
Caution 1. If the potential of the CTL pin is middle, overcu rrent detection voltage 1 (VIOV1) does not
operate.
2. If you use the middle potential of the CTL pin, contact ABLIC Inc. marketing department.
3. Please note unexpected behavior might occur when electrical potential difference between the
CTL pin (“L” level) and VSS is generated through the external filter (RVSS and CVSS) as a result
of input voltage fluctuations.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
20
Timing Chart
1. Overcharge Detection and Overdischarge Detection
(n = 1 to 3)
V
CUn
V
DUn
V
DLn
V
CLn
Battery
voltage
High-Z
V
SS
COP
pin voltage
V
DD
DOP
pin voltage
V
SS
Charger
connection
Load
connection
Status
*1
Overcharge detection
delay time ( t
CU
)
< 1 > < 2 > < 1 > < 4 > < 1 >
V
IOV1
V
SS
VMP
pin voltage
V
DD
V
EB
V
EB
V
HC
V
HD
High-Z
0.8 V
< 3 >
Overdischarge detection
delay time ( t
DL
)
*1. < 1 > : Normal status
< 2 > : Overcharge status
< 3 > : Overdischarge status
< 4 > : Power-down status
Remark The charger is assumed to charge with a constant current. VEB indicates the open voltage of the
charger.
Figure 11
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
21
2. Overcurrent Detection
V
CUn
V
DUn
V
DLn
(n = 1 to 3)
V
CLn
Battery
voltage
V
HC
V
HD
V
DD
DOP
pin voltage
V
SS
High-Z
V
EB
V
SS
COP
pin voltage
High-Z
High-Z
V
DD
V
SS
VMP
pin voltage V
IOV3
Load
connection
Status
*1
Overcurrent detection
delay time 1 ( t
IOV1
)
< 1 > < 2 > < 1 > < 1 >
Overcurrent detection
delay time 2 ( t
IOV2
) Overcurrent detection
delay time 3 ( t
IOV3
)
< 2 > < 1 > < 2 >
V
IOV2
V
V
IOV1
*1. < 1 > : Normal status
< 2 > : Overcurrent status
Remark The charger is assumed to charge with a constant current. VEB indicates the open voltage of the
charger. Figure 12
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
22
Battery Protection IC Connection Example
1. S-8253A Series
EB
RCOP
RVMP
RDOP
RCTL
EB
1 DOP
2 COP
3 VMP
4 CTL
8 VDD 7 VC1 6 VC2 5 VSS
S-8253A
RVC1
CVSS
CVC1
RVSS
Charging
FET Discharging
FET
CTL
Figure 13
2. S-8253B Series
EB
RCOP
RVMP
RDOP
RCTL
EB
1 DOP
2 COP
3 VMP
4 CTL
8 VDD 7 VC1 6 VC2 5 VSS
S-8253B
RVC1
CVC2
CVSS
CVC1 RVC2
RVSS
Charging
FET Discharging
FET
CTL
Figure 14
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
23
Table 11 Constants for External Components
No. Symbol Typ. Range Unit
1 RVC1 1 0.51 to 1*1 k
2 RVC2 1 0.51 to 1*1 k
3 RDOP 5.1 2 to 10 k
4 RCOP 1 0.1 to 1 M
5 RVMP 5.1 1 to 10 k
6 RCTL 1 1 to 100 k
7 RVSS 51 5.1 to 51*1
8 CVC1 0.1 0.1 to 0.47*1 F
9 CVC2 0.1 0.1 to 0.47*1 F
10 CVSS 2.2 1 to 10*1 F
*1. Please set up a filter constant to be RVSS CVSS 51 F and to be
RVC1 CVC1 RVC2 CVC2 RVSS CVSS.
Caution 1. The above constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant do
not guarantee proper operation. Perform through evaluation using the actual application to set the
constant.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
24
Precautions
In case of designing a circuit by using the CTL pin, as seen in
Figure 15
, note that discharging may stop during connecting a battery
pack and the device.
Remark If you are cautious about this condition, please consider to use the S-8253C/D Series.
[Cause]
This is because the overcurrent detection voltage 3 (V
IOV3
) is detected due to the rush current which flows into the device while a
battery pack is in the delay time-shortening status.
[Mechanism]
As seen in
Figure 15
, before a battery pack is connected to the device, the battery pack may be in the charge / discharge
inhibited status in which the CTL pin is inter nally pulled-up. From this status, if connecting the batter y pack to the device, the CTL
pin will be pulled-down in a time-constant C1
(R1 + R
PD
) by a pull-down resistor in the device. If the CTL’s potential reaches
V
CTLL
V
CTL
V
CTLH
, the battery pack goes in the delay time-shortening status so that it rel eases charging and discharging, hence it
starts charging a parasitic capacitor in the device. In this case, if the rush current, which makes the S-8253A/B Series to detect
the overcurrent detection voltage 3 (V
IOV3
), flows into the device, the overcurr ent detection delay time 3 ( t
IOV3
= 300
s typ.) will be
shortened. So that the battery pack goes in the overcur rent status in several 10
s. However, the battery pack goes in the normal
status by connecting the device to the charger.
S-8253A/B
Discharging
C1
Pull-down
resistor
R
PD
CTL
CTL
VMP
COP
DOPVDD
R1
EB−
EB+
200 nA
Parasitic
capacitor
Rush current
Battery pack Device
Figure 15
CTLM
DOP
VMP
CTL
Connect charger
<1> : Normal status
<2> : Overcurrent status
<3> : Charge / discharge inhibit status
<4> : Delay time-shortening status
(enable to charge / discharge)
<3>
CTL = H CTL = L
ON OFF ONOFF
Connect battery pack to device
t
IOV3
<4> <2> <1>
Status
Rush current
Figure 16
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
25
The application conditions for the input voltage, output voltage, and load current should not exceed the package
power dissipation.
Batteries can be connected in any order, however, there may be cases when discharging cannot be performed when
a battery is connected. In this case, short the VMP pin and VDD pin or connect the battery charger to return to the
normal mode.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
26
Characteristics (Typical Data)
1. Current Consumption
1. 1 IOPE vs. VDD
0 5 10 15 20
40
35
30
25
20
15
10
5
0
I
OPE
[A]
(S-8253A
A
A)
V
DD
[V]
0 5 10 15 20
40
35
30
25
20
15
10
5
0
(S-8253BAA)
I
OPE
[A]
V
DD
[V]
1. 2 IOPE vs. Ta
40 25 0 25 50 75 85
40
35
30
25
20
15
10
5
0
IOPE [A]
Ta [C]
(S-8253AAA)
40 25 0 25 50 75 85
40
35
30
25
20
15
10
5
0
I
OPE
[A]
Ta [C]
(S-8253BAA)
1. 3 IPDN vs. VDD
0 5 10 15 20
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
I
PDN
[A]
V
DD
[V]
(S-8253AAA)
0 5 10 15 20
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
I
PDN
[A]
(S-8253B
A
A
)
V
DD
[V]
1. 4 IPDN vs. Ta
40 25 0 25 50 75 85
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
I
PDN
[A]
(S-8253AAA)
Ta [C]
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
(S-8253BAA)
I
PDN
[A]
Ta [C]
40 25 0 25 50 75 85
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
27
2. Overcharge Detection / Release Voltage, Overdischarge Detection / Release Voltage, Overcurrent
Detection Voltage, and Delay Times (S-8253AAA, S-8253BAA)
2. 1 VCU vs. Ta 2. 2 VCL vs. Ta
4.375
4.370
4.365
4.360
4.355
4.350
4.345
4.340
4.335
4.330
4.325
40 25 0 25 50 75 85
V
CU
[A]
Ta [C]
4.10
4.09
4.08
4.07
4.06
4.05
4.04
4.03
4.02
4.01
4.00
VCL [A]
40 25 0 25 50 75 85
Ta [C]
2. 3 VDU vs. Ta 2. 4 VDL vs. Ta
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
2.64
2.62
2.60
V
DU
[A]
40 25 0 25 50 75 85
Ta [C]
2.48
2.46
2.44
2.42
2.40
2.38
2.36
2.34
2.32
V
DL
[A]
40 25 0 25 50 75 85
Ta [C]
2. 5 tCU vs. Ta 2. 6 tDL vs. Ta
1320
1220
1120
1020
920
1380
t
CU
[ms]
40 25 0 25 50 75 85
Ta [C]
165
155
145
135
125
115
173
t
DL
[ms]
40 25 0 25 50 75 85
Ta [C]
2. 7 VIOV1 vs. VDD 2. 8 VIOV1 vs. Ta
0.325
0.320
0.315
0.310
0.305
0.300
0.295
0.290
0.285
0.280
0.275 7 8 10 11 12 9 13
V
IOV1
[V]
V
DD
[V]
0.325
0.320
0.315
0.310
0.305
0.300
0.295
0.290
0.285
0.280
0.275
40 25 0 25 50 75 85
Ta [C]
V
IOV1
[V]
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series Rev.5.0_01
28
2. 9 VIOV2 vs. VDD 2. 10 VIOV2 vs. Ta
0.60
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
0.42
0.40
7 8 10 11 12 9 13
V
IOV2
[V]
V
DD
[V]
0.60
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
0.42
0.40
V
IOV2
[V]
40 25 0 25 50 75 85
Ta [C]
2. 11 VIOV3 vs. VDD 2. 12 VIOV3 vs. Ta
1.5
1.4
1.3
1.2
1.1
1.0
0.9 7 8 10 11 12 9 13
V
IOV3
[V]
V
DD
[V]
1.5
1.4
1.3
1.2
1.1
1.0
0.9
V
IOV3
[V]
40 25 0 25 50 75 85
Ta [C]
2. 13 tIOV1 vs. VDD 2. 14 tIOV1 vs. Ta
10.8
10.4
10.0
9.6
9.2
8.8
8.4
8.0
7.6
7.2
7 8 10 11 12 9 13
V
DD
[V]
t
IOV1
[ms]
10.8
10.4
10.0
9.6
9.2
8.8
8.4
8.0
7.6
7.2
t
IOV1
[ms]
40 25 0 25 50 75 85
Ta [C]
2. 15 tIOV2 vs. VDD 2. 16 tIOV2 vs. Ta
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
t
IOV2
[ms]
7 8 10 11 12 9 13
V
DD
[V]
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
t
IOV2
[ms]
40 25 0 25 50 75 85
Ta [C]
NOT RECOMMENDED FOR NEW DESIGN
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
Rev.5.0_01 S-8253A/B Series
29
2. 17 tIOV3 vs. VDD 2. 18 tIOV3 vs. Ta
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
tIOV3 [ms]
7 8 10 11 12 9 13
VDD [V]
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
t
IOV3
[ms]
40 25 0 25 50 75 85
Ta [C]
3. COP / DOP Pin (S-8253AAA, S-8253BAA)
3. 1 ICOH vs. VCOP 3. 2 ICOL vs. VCOP
0.08
0.06
0.04
0.02
0 0 4 12 16 20 8 24
I
COH
[A]
V
COP
[V]
0.10
14
12
10
8
6
4
2
0 0 3. 10.5 7.0
ICOL [m
A
]
VCOP [V]
3. 3 IDOH vs. VDOP 3. 4 IDOL vs. VDOP
0.5
1.0
1.5
2.0
2.5 0 1.8 5.4 3.6
I
DOH
[m
A
]
V
DOP
[V]
0
14
12
10
8
6
4
2
0 0 3.5 10.5
7.0
I
DOL
[m
A
]
V
DOP
[V]
NOT RECOMMENDED FOR NEW DESIGN
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
TSSOP8-E-PKG Dimensions
No. FT008-A-P-SD-1.2
FT008-A-P-SD-1.2
0.17±0.05
3.00 +0.3
-0.2
0.65
0.2±0.1
14
5
8
mm
NOT RECOMMENDED FOR NEW DESIGN
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
ø1.55±0.05
2.0±0.05
8.0±0.1 ø1.55 +0.1
-0.05
(4.4)
0.3±0.05
1
45
8
4.0±0.1
Feed direction
TSSOP8-E-Carrier Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
6.6
mm
NOT RECOMMENDED FOR NEW DESIGN
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
Enlarged drawing in the central part
No. FT008-E-R-SD-1.0
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
3,000
QTY.
TSSOP8-E-Reel
FT008-E-R-SD-1.0
mm
NOT RECOMMENDED FOR NEW DESIGN
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
Enlarged drawing in the central part
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
4,000
QTY.
TSSOP8-E-Reel
FT008-E-R-S1-1.0
mm
No. FT008-E-R-S1-1.0
NOT RECOMMENDED FOR NEW DESIGN
Disclaimers (Handling Precautions)
1. All the information described herein
(product data,
specifications,
figures,
tables,
programs,
algorithms and application
circuit examples,
etc.)
is current as of publishing date of this document and is subject to change without notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5. When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9. Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
2.0-2018.01
www.ablicinc.com
NOT RECOMMENDED FOR NEW DESIGN
