To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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H8S/2626 Group, H8S/2623 Group,
H8S/2626F-ZTATTM,
H8S/2623F-ZTATTM
Hardware Manual
16
User’s Manual
Rev.5.00 2006.01
Renesas 16-Bit Single-Chip
Microcomputer
H8S Family/H8S/2600 Series
H8S/2626 HD6432626
HD64F2626
H8S/2625 HD6432625
H8S/2623 HD6432623
HD64F2623
H8S/2622 HD6432622
H8S/2621 HD64F2621
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Rev. 5.00 Jan 10, 2006 page ii of xxiv
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
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a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
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4. When using any or all of the information contained in these materials, including product data,
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contained therein.
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 5.00 Jan 10, 2006 page iii of xxiv
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through cu rrent f lows internally, and a malfunction may occur.
3. Processing befo re Initialization
Note: When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.
Rev. 5.00 Jan 10, 2006 page iv of xxiv
Rev. 5.00 Jan 10, 2006 page v of xxiv
Preface
The H8S/2626 Group and H8S/2623 Group are series of high-performance microcontrollers with a
32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for system
configuration.
The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general r egisters with a 32-bit in ternal co nfiguration, and a concise and optimized instructio n set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*), and mask ROM versions are available,
providing a quick and flexib le response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), watchdog timer (WDT), serial communication interface (SCI), controller area
network (HCAN), A/D converter, D/A converter (H8S/2626 Group only), and I/O ports.
In addition, d a ta tr ansfer contr oller (DTC) is provid ed, enabling high-speed data transfer without
CPU intervention.
Use of the H8S/2626 Group or H8S/2623 Group enables easy implementation of compact, high-
performance systems capable of processing large volumes of data.
This manual describes the hardware of the H8S/2626 Group and H8S/2623 Group. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the
instructio n set.
Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp.
Rev. 5.00 Jan 10, 2006 page vi of xxiv
Rev. 5.00 Jan 10, 2006 page vii of xxiv
Main Revisions in This Edition
Item Page Revision (See Manual for Details)
All — • All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and
other Hitachi brand names changed to Renesas Technology Corp.
• Designation for categories changed from “series” to “group”
19.13 Flash
Memory
Programming
and Erasing
Precautions
Figure 19.26
Power-On/Off
Timing (Boot
Mode)
682 Figure 19.26 amended
Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
φ
VCC
FWE
t
OSC1
Min 0 µs
t
MDS*3
t
MDS*3
MD2 to MD0
*1
RES
SWE1 bit
SWE1 set SWE1 cleared
Program-
ming/
erasing
possible
Wait time:
xWait time:
100 µs
Min 0 µs
Rev. 5.00 Jan 10, 2006 page viii of xxiv
Item Page Revision (See Manual for Details)
19.13 Flash
Memory
Programming
and Erasing
Precautions
Figure 19.27
Power-On/Off
Timing (User
Program Mode)
683 Figure 19.27 amended
Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
φ
VCC
FWE
t
OSC1
Min 0 µs
MD2 to MD0
*1
RES
SWE1 bit
SWE1 set SWE1 cleared
Program-
ming/
erasing
possible
Wait time:
xWait time:
100 µs
tMDS*3
Figure 19.28
Mode
Transition
Timing
(Example: Boot
Mode → User
Mode ↔ User
Program Mode)
684 Figure 19.28 amended
Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
φ
VCC
FWE
t
OSC1
Min 0µs
t
MDS
t
MDS*2
t
MDS
t
RESW
MD2 to MD0
RES
SWE1 bit
Mode
change
*1
User
mode
Boot
mode User program mode
SWE1 set SWE1
cleared
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Programming/
erasing possible
Wait time: x
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Wait time: 100 µs
Mode
change
*1
User
mode User program
mode
Rev. 5.00 Jan 10, 2006 page ix of xxiv
Contents
Section 1 Overview............................................................................................................. 1
1.1 Overview........................................................................................................................... 1
1.2 Internal Block Diagram..................................................................................................... 6
1.3 Pin Descriptions................................................................................................................ 8
1.3.1 Pin Arrangement.................................................................................................. 8
1.3.2 Pin Functions in Each Operating Mode............................................................... 10
1.3.3 Pin Functions ....................................................................................................... 18
Section 2 CPU...................................................................................................................... 23
2.1 Overview........................................................................................................................... 23
2.1.1 Features................................................................................................................ 23
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 24
2.1.3 Differences from H8/300 CPU ............................................................................ 25
2.1.4 Differences from H8/300H CPU.......................................................................... 25
2.2 CPU Operating Modes...................................................................................................... 26
2.3 Address Space................................................................................................................... 31
2.4 Register Configuration...................................................................................................... 32
2.4.1 Overview.............................................................................................................. 32
2.4.2 General Registers................................................................................................. 33
2.4.3 Control Registers ................................................................................................. 34
2.4.4 Initial Register Values.......................................................................................... 36
2.5 Data Formats..................................................................................................................... 37
2.5.1 General Register Data Formats............................................................................ 37
2.5.2 Memory Data Formats......................................................................................... 39
2.6 Instruction Set................................................................................................................... 40
2.6.1 Overview.............................................................................................................. 40
2.6.2 Instructions and Addressing Modes..................................................................... 41
2.6.3 Table of Instructions Classified by Function ....................................................... 42
2.6.4 Basic Instruction Formats.................................................................................... 51
2.7 Addressing Modes and Effective Address Calculation..................................................... 53
2.7.1 Addressing Mode................................................................................................. 53
2.7.2 Effective Address Calculation ............................................................................. 56
2.8 Processing States............................................................................................................... 60
2.8.1 Overview.............................................................................................................. 60
2.8.2 Reset State............................................................................................................ 61
2.8.3 Exception-Handling State.................................................................................... 62
2.8.4 Program Execution State...................................................................................... 65
Rev. 5.00 Jan 10, 2006 page x of xxiv
2.8.5 Bus-Released State............................................................................................... 65
2.8.6 Power-Down State............................................................................................... 65
2.9 Basic Timing..................................................................................................................... 66
2.9.1 Overview.............................................................................................................. 66
2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 66
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 68
2.9.4 On-Chip HCAN Module Access Timing............................................................. 70
2.9.5 External Address Space Access Timing .............................................................. 72
2.10 Usage Note................................................................................................................. ....... 72
2.10.1 TAS Instruction.................................................................................................... 72
Section 3 MCU Operating Modes .................................................................................. 73
3.1 Overview........................................................................................................................... 73
3.1.1 Operating Mode Selection ................................................................................... 73
3.1.2 Register Configuration......................................................................................... 74
3.2 Register Descriptions....................................................................................................... .75
3.2.1 Mode Control Register (MDCR) ......................................................................... 75
3.2.2 System Control Register (SYSCR)...................................................................... 75
3.2.3 Pin Function Control Register (PFCR)................................................................ 77
3.3 Operating Mode Descriptions........................................................................................... 79
3.3.1 Mode 4................................................................................................................. 79
3.3.2 Mode 5................................................................................................................. 79
3.3.3 Mode 6................................................................................................................. 79
3.3.4 Mode 7................................................................................................................. 79
3.4 Pin Functions in Each Operating Mode ............................................................................ 80
3.5 Address Map in Each Operating Mode............................................................................. 80
Section 4 Exception Handling ......................................................................................... 85
4.1 Overview........................................................................................................................... 85
4.1.1 Exception Handling Types and Priority............................................................... 85
4.1.2 Exception Handling Operation............................................................................. 86
4.1.3 Exception Vector Table ....................................................................................... 86
4.2 Reset.................................................................................................................................. 88
4.2.1 Overview.............................................................................................................. 88
4.2.2 Reset Sequence.................................................................................................... 88
4.2.3 Interrupts after Reset............................................................................................ 90
4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 90
4.3 Traces................................................................................................................................ 91
4.4 Interrupts........................................................................................................................... 92
4.5 Trap Instruction............................................................................................................ ..... 93
4.6 Stack Status after Exception Handling.............................................................................. 94
Rev. 5.00 Jan 10, 2006 page xi of xxiv
4.7 Notes on Use of the Stack................................................................................................. 95
Section 5 Interrupt Controller.......................................................................................... 97
5.1 Overview........................................................................................................................... 97
5.1.1 Features................................................................................................................ 97
5.1.2 Block Diagram..................................................................................................... 98
5.1.3 Pin Configuration ................................................................................................. 99
5.1.4 Register Configuration......................................................................................... 99
5.2 Register Descriptions....................................................................................................... . 100
5.2.1 System Control Register (SYSCR)...................................................................... 100
5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 101
5.2.3 IRQ Enable Register (IER).................................................................................. 103
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 104
5.2.5 IRQ Status Register (ISR).................................................................................... 105
5.3 Interrupt Sources............................................................................................................... 106
5.3.1 External Interrupts ............................................................................................... 106
5.3.2 Internal Interrupts................................................................................................. 108
5.3.3 Interrupt Exception Handling Vector Table......................................................... 108
5.4 Interrupt Operation............................................................................................................ 112
5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 112
5.4.2 Interrupt Control Mode 0..................................................................................... 116
5.4.3 Interrupt Control Mode 2..................................................................................... 118
5.4.4 Interrupt Exception Handling Sequence .............................................................. 120
5.4.5 Interrupt Response Times.................................................................................... 121
5.5 Usage Notes...................................................................................................................... 122
5.5.1 Contention between Interrupt Generation and Disabling..................................... 122
5.5.2 Instructions that Disable Interrupts...................................................................... 123
5.5.3 Times when Interrupts are Disabled .................................................................... 123
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 124
5.6 DTC Activation by Interrupt............................................................................................. 124
5.6.1 Overview.............................................................................................................. 124
5.6.2 Block Diagram..................................................................................................... 125
5.6.3 Operation ............................................................................................................. 125
Section 6 PC Break Controller (PBC)........................................................................... 127
6.1 Overview........................................................................................................................... 127
6.1.1 Features................................................................................................................ 127
6.1.2 Block Diagram..................................................................................................... 128
6.1.3 Register Configuration......................................................................................... 129
6.2 Register Descriptions....................................................................................................... . 129
6.2.1 Break Address Register A (BARA)..................................................................... 129
Rev. 5.00 Jan 10, 2006 page xii of xxiv
6.2.2 Break Address Register B (BARB)...................................................................... 130
6.2.3 Break Control Register A (BCRA)...................................................................... 130
6.2.4 Break Control Register B (BCRB)....................................................................... 132
6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 132
6.3 Operation .......................................................................................................................... 133
6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 133
6.3.2 PC Break Interrupt Due to Data Access............................................................... 134
6.3.3 Notes on PC Break Interrupt Handling................................................................ 134
6.3.4 Operation in Transitions to Power-Down Modes ................................................ 135
6.3.5 PC Break Operation in Continuous Data Transfer............................................... 136
6.3.6 When Instruction Execution is Delayed by One State......................................... 137
6.3.7 Additional Notes.................................................................................................. 138
Section 7 Bus Controller ................................................................................................... 139
7.1 Overview........................................................................................................................... 139
7.1.1 Features................................................................................................................ 139
7.1.2 Block Diagram..................................................................................................... 140
7.1.3 Pin Configuration ................................................................................................. 141
7.1.4 Register Configuration......................................................................................... 142
7.2 Register Descriptions....................................................................................................... . 143
7.2.1 Bus Width Control Register (ABWCR)............................................................... 143
7.2.2 Access State Control Register (ASTCR) ............................................................. 144
7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 145
7.2.4 Bus Control Register H (BCRH).......................................................................... 149
7.2.5 Bus Control Register L (BCRL) .......................................................................... 151
7.2.6 Pin Function Control Register (PFCR)................................................................ 152
7.3 Overview of Bus Control.................................................................................................. 154
7.3.1 Area Partitioning.................................................................................................. 154
7.3.2 Bus Specifications................................................................................................ 155
7.3.3 Memory Interfaces............................................................................................... 156
7.3.4 Interface Specifications for Each Area ................................................................ 157
7.4 Basic Bus Interface ........................................................................................................... 158
7.4.1 Overview.............................................................................................................. 158
7.4.2 Data Size and Data Alignment............................................................................. 158
7.4.3 Valid Strobes........................................................................................................ 160
7.4.4 Basic Timing........................................................................................................ 161
7.4.5 Wait Control ........................................................................................................ 169
7.5 Burst ROM Interface......................................................................................................... 171
7.5.1 Overview.............................................................................................................. 171
7.5.2 Basic Timing........................................................................................................ 171
7.5.3 Wait Control ........................................................................................................ 173
Rev. 5.00 Jan 10, 2006 page xiii of xxiv
7.6 Idle Cycle.......................................................................................................................... 174
7.6.1 Operation ............................................................................................................. 174
7.6.2 Pin States in Idle Cycle........................................................................................ 176
7.7 Write Data Buffer Function .............................................................................................. 177
7.8 Bus Release....................................................................................................................... 178
7.8.1 Overview.............................................................................................................. 178
7.8.2 Operation ............................................................................................................. 178
7.8.3 Pin States in External Bus Released State............................................................ 179
7.8.4 Transition Timing................................................................................................ 180
7.8.5 Usage Note........................................................................................................... 181
7.9 Bus Arbitration.................................................................................................................. 181
7.9.1 Overview.............................................................................................................. 181
7.9.2 Operation ............................................................................................................. 181
7.9.3 Bus Transfer Timing............................................................................................ 182
7.10 Resets and the Bus Controller........................................................................................... 182
Section 8 Data Transfer Controller (DTC)................................................................... 183
8.1 Overview........................................................................................................................... 183
8.1.1 Features................................................................................................................ 183
8.1.2 Block Diagram..................................................................................................... 184
8.1.3 Register Configuration......................................................................................... 185
8.2 Register Descriptions....................................................................................................... . 186
8.2.1 DTC Mode Register A (MRA) ............................................................................ 186
8.2.2 DTC Mode Register B (MRB)............................................................................. 188
8.2.3 DTC Source Address Register (SAR).................................................................. 189
8.2.4 DTC Destination Address Register (DAR).......................................................... 189
8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 190
8.2.6 DTC Transfer Count Register B (CRB)............................................................... 190
8.2.7 DTC Enable Registers (DTCER)......................................................................... 191
8.2.8 DTC Vector Register (DTVECR)........................................................................ 192
8.2.9 Module Stop Control Register A (MSTPCRA) ................................................... 193
8.3 Operation .......................................................................................................................... 193
8.3.1 Overview.............................................................................................................. 193
8.3.2 Activation Sources............................................................................................... 195
8.3.3 DTC Vector Table................................................................................................ 197
8.3.4 Location of Register Information in Address Space............................................ 200
8.3.5 Normal Mode....................................................................................................... 201
8.3.6 Repeat Mode........................................................................................................ 202
8.3.7 Block Transfer Mode........................................................................................... 203
8.3.8 Chain Transfer ..................................................................................................... 205
8.3.9 Operation Timing................................................................................................. 206
Rev. 5.00 Jan 10, 2006 page xiv of xxiv
8.3.10 Number of DTC Execution States........................................................................ 207
8.3.11 Procedures for Using DTC................................................................................... 209
8.3.12 Examples of Use of the DTC............................................................................... 210
8.4 Interrupts........................................................................................................................... 213
8.5 Usage Notes...................................................................................................................... 213
Section 9 I/O Ports.............................................................................................................. 215
9.1 Overview........................................................................................................................... 215
9.2 Port 1................................................................................................................................. 219
9.2.1 Overview.............................................................................................................. 219
9.2.2 Register Configuration......................................................................................... 220
9.2.3 Pin Functions ....................................................................................................... 222
9.3 Port 4................................................................................................................................. 234
9.3.1 Overview.............................................................................................................. 234
9.3.2 Register Configuration......................................................................................... 235
9.3.3 Pin Functions ....................................................................................................... 235
9.4 Port 9................................................................................................................................. 236
9.4.1 Overview.............................................................................................................. 236
9.4.2 Register Configuration......................................................................................... 237
9.4.3 Pin Functions ....................................................................................................... 237
9.5 Port A................................................................................................................................ 237
9.5.1 Overview.............................................................................................................. 237
9.5.2 Register Configuration......................................................................................... 238
9.5.3 Pin Functions ....................................................................................................... 242
9.5.4 MOS Input Pull-Up Function............................................................................... 245
9.6 Port B................................................................................................................................ 246
9.6.1 Overview.............................................................................................................. 246
9.6.2 Register Configuration......................................................................................... 247
9.6.3 Pin Functions ....................................................................................................... 249
9.6.4 MOS Input Pull-Up Function............................................................................... 258
9.7 Port C................................................................................................................................ 259
9.7.1 Overview.............................................................................................................. 259
9.7.2 Register Configuration......................................................................................... 260
9.7.3 Pin Functions ....................................................................................................... 263
9.7.4 MOS Input Pull-Up Function............................................................................... 268
9.8 Port D................................................................................................................................ 269
9.8.1 Overview.............................................................................................................. 269
9.8.2 Register Configuration......................................................................................... 270
9.8.3 Pin Functions ....................................................................................................... 272
9.8.4 MOS Input Pull-Up Function............................................................................... 273
9.9 Port E ................................................................................................................................ 274
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9.9.1 Overview.............................................................................................................. 274
9.9.2 Register Configuration......................................................................................... 275
9.9.3 Pin Functions ....................................................................................................... 277
9.9.4 MOS Input Pull-Up Function............................................................................... 278
9.10 Port F................................................................................................................................. 279
9.10.1 Overview.............................................................................................................. 279
9.10.2 Register Configuration......................................................................................... 280
9.10.3 Pin Functions....................................................................................................... 282
Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 285
10.1 Overview........................................................................................................................... 285
10.1.1 Features................................................................................................................ 285
10.1.2 Block Diagram..................................................................................................... 289
10.1.3 Pin Configuration................................................................................................. 290
10.1.4 Register Configuration......................................................................................... 292
10.2 Register Descriptions........................................................................................................ 294
10.2.1 Timer Control Register (TCR)............................................................................. 294
10.2.2 Timer Mode Register (TMDR)............................................................................ 299
10.2.3 Timer I/O Control Register (TIOR)..................................................................... 301
10.2.4 Timer Interrupt Enable Register (TIER).............................................................. 314
10.2.5 Timer Status Register (TSR)................................................................................ 316
10.2.6 Timer Counter (TCNT)........................................................................................ 320
10.2.7 Timer General Register (TGR)............................................................................ 320
10.2.8 Timer Start Register (TSTR)................................................................................ 321
10.2.9 Timer Synchro Register (TSYR) ......................................................................... 321
10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... 322
10.3 Interface to Bus Master..................................................................................................... 323
10.3.1 16-Bit Registers ................................................................................................... 323
10.3.2 8-Bit Registers ..................................................................................................... 323
10.4 Operation .......................................................................................................................... 325
10.4.1 Overview.............................................................................................................. 325
10.4.2 Basic Functions.................................................................................................... 326
10.4.3 Synchronous Operation........................................................................................ 331
10.4.4 Buffer Operation.................................................................................................. 334
10.4.5 Cascaded Operation............................................................................................. 338
10.4.6 PWM Modes........................................................................................................ 340
10.4.7 Phase Counting Mode.......................................................................................... 345
10.5 Interrupts........................................................................................................................... 351
10.5.1 Interrupt Sources and Priorities............................................................................ 351
10.5.2 DTC Activation.................................................................................................... 353
10.5.3 A/D Converter Activation.................................................................................... 353
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10.6 Operation Timing.............................................................................................................. 354
10.6.1 Input/Output Timing............................................................................................ 354
10.6.2 Interrupt Signal Timing........................................................................................ 358
10.7 Usage Notes...................................................................................................................... 362
Section 11 Programmable Pulse Generator (PPG) .................................................... 373
11.1 Overview........................................................................................................................... 373
11.1.1 Features................................................................................................................ 373
11.1.2 Block Diagram..................................................................................................... 374
11.1.3 Pin Configuration................................................................................................. 375
11.1.4 Registers............................................................................................................... 376
11.2 Register Descriptions........................................................................................................ 377
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 377
11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 378
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 379
11.2.4 Notes on NDR Access.......................................................................................... 379
11.2.5 PPG Output Control Register (PCR).................................................................... 381
11.2.6 PPG Output Mode Register (PMR)...................................................................... 383
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 385
11.2.8 Module Stop Control Register A (MSTPCRA) ................................................... 386
11.3 Operation .......................................................................................................................... 387
11.3.1 Overview.............................................................................................................. 387
11.3.2 Output Timing...................................................................................................... 388
11.3.3 Normal Pulse Output............................................................................................ 389
11.3.4 Non-Overlapping Pulse Output............................................................................ 391
11.3.5 Inverted Pulse Output .......................................................................................... 394
11.3.6 Pulse Output Triggered by Input Capture............................................................ 395
11.4 Usage Notes...................................................................................................................... 396
Section 12 Watchdog Timer............................................................................................. 399
12.1 Overview........................................................................................................................... 399
12.1.1 Features................................................................................................................ 399
12.1.2 Block Diagram..................................................................................................... 400
12.1.3 Pin Configuration................................................................................................. 402
12.1.4 Register Configuration......................................................................................... 402
12.2 Register Descriptions........................................................................................................ 403
12.2.1 Timer Counter (TCNT)........................................................................................ 403
12.2.2 Timer Control/Status Register (TCSR)................................................................ 404
12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 408
12.2.4 Pin Function Control Register (PFCR)................................................................ 410
12.2.5 Notes on Register Access..................................................................................... 410
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12.3 Operation .......................................................................................................................... 412
12.3.1 Watchdog Timer Operation ................................................................................. 412
12.3.2 Interval Timer Operation ..................................................................................... 415
12.3.3 Timing of Setting Overflow Flag (OVF)............................................................. 415
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)......................... 416
12.4 Interrupts........................................................................................................................... 417
12.5 Usage Notes...................................................................................................................... 417
12.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 417
12.5.2 Changing Value of PSS and CKS2 to CKS0 ....................................................... 418
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 418
12.5.4 System Reset by WDTOVF Signal...................................................................... 418
12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 418
12.5.6 OVF Flag Clearing in Interval Timer Mode........................................................ 419
Section 13 Serial Communication Interface (SCI) .................................................... 421
13.1 Overview........................................................................................................................... 421
13.1.1 Features................................................................................................................ 421
13.1.2 Block Diagram..................................................................................................... 423
13.1.3 Pin Configuration................................................................................................. 424
13.1.4 Register Configuration......................................................................................... 425
13.2 Register Descriptions........................................................................................................ 426
13.2.1 Receive Shift Register (RSR) .............................................................................. 426
13.2.2 Receive Data Register (RDR).............................................................................. 426
13.2.3 Transmit Shift Register (TSR)............................................................................. 427
13.2.4 Transmit Data Register (TDR)............................................................................. 427
13.2.5 Serial Mode Register (SMR)................................................................................ 428
13.2.6 Serial Control Register (SCR).............................................................................. 431
13.2.7 Serial Status Register (SSR) ................................................................................ 435
13.2.8 Bit Rate Register (BRR) ...................................................................................... 439
13.2.9 Smart Card Mode Register (SCMR).................................................................... 447
13.2.10 Module Stop Control Register B (MSTPCRB).................................................... 448
13.3 Operation .......................................................................................................................... 450
13.3.1 Overview.............................................................................................................. 450
13.3.2 Operation in Asynchronous Mode....................................................................... 452
13.3.3 Multiprocessor Communication Function............................................................ 463
13.3.4 Operation in Clocked Synchronous Mode........................................................... 471
13.4 SCI Interrupts.................................................................................................................... 480
13.5 Usage Notes...................................................................................................................... 482
Section 14 Smart Card Interface ..................................................................................... 491
14.1 Overview........................................................................................................................... 491
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14.1.1 Features................................................................................................................ 491
14.1.2 Block Diagram..................................................................................................... 492
14.1.3 Pin Configuration................................................................................................. 493
14.1.4 Register Configuration......................................................................................... 494
14.2 Register Descriptions........................................................................................................ 495
14.2.1 Smart Card Mode Register (SCMR).................................................................... 495
14.2.2 Serial Status Register (SSR) ................................................................................ 496
14.2.3 Serial Mode Register (SMR)................................................................................ 498
14.2.4 Serial Control Register (SCR).............................................................................. 500
14.3 Operation .......................................................................................................................... 501
14.3.1 Overview.............................................................................................................. 501
14.3.2 Pin Connections................................................................................................... 501
14.3.3 Data Format ......................................................................................................... 503
14.3.4 Register Settings .................................................................................................. 505
14.3.5 Clock.................................................................................................................... 507
14.3.6 Data Transfer Operations..................................................................................... 509
14.3.7 Operation in GSM Mode ..................................................................................... 516
14.3.8 Operation in Block Transfer Mode...................................................................... 517
14.4 Usage Notes...................................................................................................................... 518
Section 15 Controller Area Network (HCAN)............................................................ 523
15.1 Overview........................................................................................................................... 523
15.1.1 Features................................................................................................................ 523
15.1.2 Block Diagram..................................................................................................... 524
15.1.3 Pin Configuration................................................................................................. 525
15.1.4 Register Configuration......................................................................................... 526
15.2 Register Descriptions........................................................................................................ 528
15.2.1 Master Control Register (MCR)........................................................................... 528
15.2.2 General Status Register (GSR) ............................................................................ 530
15.2.3 Bit Configuration Reg ister (BCR) ....................................................................... 53 1
15.2.4 Mailbox Configuration Register (MBCR) ........................................................... 534
15.2.5 Transmit Wait Register (TXPR).......................................................................... 535
15.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 536
15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 537
15.2.8 Abort Acknowledge Register (ABACK) ............................................................. 538
15.2.9 Receive Complete Register (RXPR).................................................................... 539
15.2.10 Remote Request Register (RFPR)........................................................................ 540
15.2.11 Interrupt Register (IRR)....................................................................................... 541
15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 545
15.2.13 Interrupt Mask Register (IMR)............................................................................ 546
15.2.14 Receive Error Counter (REC).............................................................................. 549
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15.2.15 Transmit Error Counter (TEC)............................................................................. 549
15.2.16 Unread Message Status Register (UMSR)........................................................... 550
15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 551
15.2.18 Message Control (MC0 to MC15)....................................................................... 553
15.2.19 Message Data (MD0 to MD15) ........................................................................... 557
15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 559
15.3 Operation .......................................................................................................................... 560
15.3.1 Hardware and Software Resets ............................................................................ 560
15.3.2 Initialization after Hardware Reset...................................................................... 563
15.3.3 Transmit Mode..................................................................................................... 568
15.3.4 Receive Mode...................................................................................................... 574
15.3.5 HCAN Sleep Mode.............................................................................................. 579
15.3.6 HCAN Halt Mode................................................................................................ 582
15.3.7 Interrupt Interface................................................................................................ 583
15.3.8 DTC Interface...................................................................................................... 584
15.4 CAN Bus Interface............................................................................................................ 585
15.5 Usage Notes...................................................................................................................... 585
Section 16 A/D Converter................................................................................................. 589
16.1 Overview........................................................................................................................... 589
16.1.1 Features................................................................................................................ 589
16.1.2 Block Diagram..................................................................................................... 590
16.1.3 Pin Configuration................................................................................................. 591
16.1.4 Register Configuration......................................................................................... 592
16.2 Register Descriptions........................................................................................................ 593
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 593
16.2.2 A/D Control/Status Register (ADCSR) ............................................................... 594
16.2.3 A/D Control Register (ADCR) ............................................................................ 597
16.2.4 Module Stop Control Register A (MSTPCRA) ................................................... 598
16.3 Interface to Bus Master..................................................................................................... 599
16.4 Operation .......................................................................................................................... 600
16.4.1 Single Mode (SCAN = 0) .................................................................................... 600
16.4.2 Scan Mode (SCAN = 1)....................................................................................... 602
16.4.3 Input Sampling and A/D Conversion Time ......................................................... 604
16.4.4 External Trigger Input Timing............................................................................. 605
16.5 Interrupts........................................................................................................................... 606
16.6 Usage Notes...................................................................................................................... 607
Section 17 D/A Converter [Provided in the H8S/2626 Group only].................... 613
17.1 Overview........................................................................................................................... 613
17.1.1 Features................................................................................................................ 613
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17.1.2 Block Diagram..................................................................................................... 614
17.1.3 Pin Configuration................................................................................................. 615
17.1.4 Register Configuration......................................................................................... 615
17.2 Register Descriptions........................................................................................................ 616
17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3) ................................................. 616
17.2.2 D/A Control Register 23 (DACR23).................................................................... 616
17.2.3 Module Stop Control Register C (MSTPCRC).................................................... 618
17.3 Operation .......................................................................................................................... 618
Section 18 RAM .................................................................................................................. 621
18.1 Overview........................................................................................................................... 621
18.1.1 Block Diagram..................................................................................................... 621
18.1.2 Register Configuration......................................................................................... 622
18.2 Register Descriptions........................................................................................................ 622
18.2.1 System Control Register (SYSCR)...................................................................... 622
18.3 Operation .......................................................................................................................... 623
18.4 Usage Notes...................................................................................................................... 623
Section 19 ROM (Preliminary)........................................................................................ 625
19.1 Features............................................................................................................................. 625
19.2 Overview........................................................................................................................... 626
19.2.1 Block Diagram..................................................................................................... 626
19.2.2 Mode Transitions................................................................................................. 627
19.2.3 On-Board Programming Modes........................................................................... 628
19.2.4 Flash Memory Emulation in RAM ...................................................................... 630
19.2.5 Differences between Boot Mode and User Program Mode ................................. 631
19.2.6 Block Configuration ............................................................................................ 632
19.3 Pin Configuration.............................................................................................................. 632
19.4 Register Configuration...................................................................................................... 633
19.5 Register Descriptions........................................................................................................ 633
19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 633
19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 637
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 638
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 638
19.5.5 RAM Emulation Register (RAMER)................................................................... 639
19.5.6 Flash Memory Power Control Register (FLPWCR)............................................ 641
19.5.7 Serial Control Register X (SCRX)....................................................................... 641
19.6 On-Board Programming Modes........................................................................................ 642
19.6.1 Boot Mode........................................................................................................... 643
19.6.2 User Program Mode............................................................................................. 647
19.7 Flash Memory Programming/Erasing............................................................................... 649
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19.7.1 Program Mode ..................................................................................................... 651
19.7.2 Program-Verify Mode.......................................................................................... 652
19.7.3 Erase Mode.......................................................................................................... 656
19.7.4 Erase-Verify Mode .............................................................................................. 656
19.8 Protection.......................................................................................................................... 658
19.8.1 Hardware Protection............................................................................................ 658
19.8.2 Software Protection.............................................................................................. 659
19.8.3 Error Protection.................................................................................................... 660
19.9 Flash Memory Emulation in RAM ................................................................................... 662
19.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 664
19.11 Flash Memory Programmer Mode.................................................................................... 664
19.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 665
19.11.2 Programmer Mode Operation.............................................................................. 667
19.11.3 Memory Read Mode............................................................................................ 668
19.11.4 Auto-Program Mode............................................................................................ 672
19.11.5 Auto-Erase Mode................................................................................................. 674
19.11.6 Status Read Mode................................................................................................ 676
19.11.7 Status Polling....................................................................................................... 677
19.11.8 Programmer Mode Transition Time .................................................................... 677
19.11.9 Notes on Memory Programming.......................................................................... 678
19.12 Flash Memory and Power-Down States............................................................................ 679
19.12.1 Note on Power-Down States................................................................................ 679
19.13 Flash Memory Programming and Erasing Precautions..................................................... 680
19.14 Note on Switching from F-ZTAT Version to Mask ROM Version.................................. 685
Section 20 Clock Pulse Generator.................................................................................. 687
20.1 Overview........................................................................................................................... 687
20.1.1 Block Diagram..................................................................................................... 688
20.1.2 Register Configuration......................................................................................... 688
20.2 Register Descriptions........................................................................................................ 689
20.2.1 System Clock Control Register (SCKCR)........................................................... 689
20.2.2 Low-Power Control Register (LPWRCR) ........................................................... 690
20.3 Oscillator........................................................................................................................... 691
20.3.1 Connecting a Crystal Resonator........................................................................... 691
20.3.2 External Clock Input............................................................................................ 694
20.4 PLL Circuit ....................................................................................................................... 696
20.5 Medium-Speed Clock Divider .......................................................................................... 696
20.6 Bus Master Clock Selection Circuit.................................................................................. 697
20.7 Subclock Oscillator (H8S/2626 Group Only)................................................................... 697
20.8 Subclock Waveform Shaping Circuit (H8S/2626 Group Only)........................................ 698
20.9 Note on Crystal Resonator................................................................................................ 698
Rev. 5.00 Jan 10, 2006 page xxii of xxiv
Section 21A Power-Down Modes [H8S/2623 Group]............................................. 699
21A.1 Overview....................................................................................................................... 699
21A.1.1 Register Configuration.................................................................................. 702
21A.2 Register Descriptions..................................................................................................... 702
21A.2.1 Standby Control Register (SBYCR)............................................................. 702
21A.2.2 System Clock Control Register (SCKCR).................................................... 704
21A.2.3 Low-Power Control Register (LPWRCR).................................................... 705
21A.2.4 Module Stop Control Register (MSTPCR)................................................... 706
21A.3 Medium-Speed Mode.................................................................................................... 707
21A.4 Sleep Mode.................................................................................................................... 708
21A.4.1 Sleep Mode................................................................................................... 708
21A.4.2 Exiting Sleep Mode ...................................................................................... 708
21A.5 Module Stop Mode........................................................................................................ 708
21A.5.1 Module Stop Mode....................................................................................... 708
21A.5.2 Usage Notes.................................................................................................. 710
21A.6 Software Standby Mode................................................................................................ 710
21A.6.1 Software Standby Mode................................................................................ 710
21A.6.2 Clearing Software Standby Mode................................................................. 710
21A.6.3 Setting Oscillation Stabilizat ion Time after Clearing Software
Standby Mode............................................................................................... 711
21A.6.4 Software Standby Mode Application Example ............................................. 712
21A.6.5 Usage Notes.................................................................................................. 713
21A.7 Hardware Standby Mode............................................................................................... 713
21A.7.1 Hardware Standby Mode.............................................................................. 713
21A.7.2 Hardware Standby Mode Timing.................................................................. 714
21A.8 φ Clock Output Disabling Function............................................................................... 714
Section 21B Power-Down Modes [H8S/2626 Group].............................................. 715
21B.1 Overview....................................................................................................................... 715
21B.1.1 Register Configuration .................................................................................. 719
21B.2 Register Descriptions..................................................................................................... 719
21B.2.1 Standby Control Register (SBYCR)............................................................. 719
21B.2.2 System Clock Control Register (SCKCR).................................................... 721
21B.2.3 Low-Power Control Register (LPWRCR).................................................... 722
21B.2.4 Timer Control/Status Register (TCSR)......................................................... 725
21B.2.5 Module Stop Control Register (MSTPCR)................................................... 726
21B.3 Medium-Speed Mode.................................................................................................... 727
21B.4 Sleep Mode.................................................................................................................... 728
21B.4.1 Sleep Mode................................................................................................... 728
21B.4.2 Exiting Sleep Mode ...................................................................................... 728
21B.5 Module Stop Mode........................................................................................................ 728
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21B.5.1 Module Stop Mode....................................................................................... 728
21B.5.2 Usage Notes.................................................................................................. 730
21B.6 Software Standby Mode................................................................................................ 730
21B.6.1 Software Standby Mode................................................................................ 730
21B.6.2 Clearing Software Standby Mode................................................................. 730
21B.6.3 Settin g Oscillation Stabilization Time after Clearing Software
Standby Mode............................................................................................... 731
21B.6.4 Software Standby Mode Application Example ............................................. 732
21B.6.5 Usage Notes.................................................................................................. 733
21B.7 Hardware Standby Mode............................................................................................... 733
21B.7.1 Hardware Standby Mode.............................................................................. 733
21B.7.2 Hardware Standby Mode Timing.................................................................. 734
21B.8 Watch Mode.................................................................................................................. 734
21B.8.1 Watch Mode.................................................................................................. 734
21B.8.2 Exiting Watch Mode..................................................................................... 735
21B.8.3 Notes............................................................................................................. 735
21B.9 Sub-Sleep Mode............................................................................................................ 736
21B.9.1 Sub-Sleep Mode............................................................................................ 736
21B.9.2 Exiting Sub-Sleep Mode............................................................................... 736
21B.10 Sub-Active Mode.......................................................................................................... 737
21B.10.1 Sub-Active Mode......................................................................................... 737
21B.10.2 Exiting Sub-Active Mode............................................................................ 737
21B.11 Direct Transitions.......................................................................................................... 738
21B.11.1 Overview of Direct Transitions.................................................................... 738
21B.12 φ Clock Output Disabling Function .............................................................................. 738
21B.13 Usage Notes................................................................................................................... 739
Section 22 Electrical Characteristics (Preliminary)................................................... 741
22.1 Absolute Maximum Ratings ............................................................................................. 741
22.2 DC Characteristics ............................................................................................................ 742
22.3 AC Characteristics ............................................................................................................ 745
22.3.1 Clock Timing....................................................................................................... 746
22.3.2 Control Signal Timing ......................................................................................... 747
22.3.3 Bus Timing .......................................................................................................... 749
22.3.4 Timing of On-Chip Supporting Modules............................................................. 756
22.4 A/D Conversion Characteristics........................................................................................ 760
22.5 D/A Conversion Characteristics........................................................................................ 760
22.6 Flash Memory Characteristics........................................................................................... 761
22.7 Usage Note................................................................................................................. ....... 762
Rev. 5.00 Jan 10, 2006 page xxiv of xxiv
Appendix A Instruction Set.............................................................................................. 763
A.1 Instruction List.................................................................................................................. 763
A.2 Instruction Codes.............................................................................................................. 787
A.3 Operation Code Map......................................................................................................... 802
A.4 Number of States Required for Instruction Execution...................................................... 806
A.5 Bus States during Instruction Execution........................................................................... 817
A.6 Condition Code Modification ........................................................................................... 831
Appendix B Internal I/O Register................................................................................... 837
B.1 Address ............................................................................................................................. 837
B.2 Functions........................................................................................................................... 852
Appendix C I/O Port Block Diagrams......................................................................... 1008
C.1 Port 1 Block Diagrams.................................................................................................... 1008
C.2 Port 4 Block Diagram ..................................................................................................... 1014
C.3 Port 9 Block Diagram ..................................................................................................... 1014
C.4 Port A Block Diagrams................................................................................................... 1015
C.5 Port B Block Diagram..................................................................................................... 1020
C.6 Port C Block Diagrams ................................................................................................... 1021
C.7 Port D Block Diagram..................................................................................................... 1025
C.8 Port E Block Diagram..................................................................................................... 1026
C.9 Port F Block Diagrams.................................................................................................... 1027
Appendix D Pin States...................................................................................................... 1036
D.1 Port States in Each Mode................................................................................................ 1036
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode............................................................................................. 1039
Appendix F Product Code Lineup................................................................................ 1040
Appendix G Package Dimensions................................................................................. 1041
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 1 of 1042
REJ09B0275-0500
Section 1 Overview
1.1 Overview
The H8S/2626 Group and H8S/2623 Group are series of microcomputers (MCUs) that integrate
peripheral functions required for system configuration together with an H8S/2600 CPU employing
an original Renesas architecture.
The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU in structions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include a data transfer controller
(DTC) bus master, ROM and RAM, a16-bit timer-pulse unit (TPU), programmable pulse
generator (PPG), watchdog timer (WDT), serial communication interface (SCI), controller area
network (HCAN), A/D converter, D/A converter (H8S/2626 Group only), and I/O ports.
The on-chip ROM is 256-kbyte flash memory (F-ZTAT™)* or 256-, 128-, or 64-kbyte mask
ROM. The ROM is connected to the CPU by a 16-bit d ata bus, enabling both byte and word data
to be accessed in one state. Instruction fetching has been speeded up, and processing speed
increased.
Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or
external expansion mode.
The features of the H8S/2626 Group and H8S/2623 Group are shown in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 2 of 1042
REJ09B0275-0500
Table 1.1 Overview
Item Specifications
CPU • General-register machine
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers or eight 32-bit registers)
• High-speed operation suitable for realtime control
Maximum operating frequency: 20 MHz
High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 50 ns
16 × 16-bit register-register multiply: 200 ns
16 × 16 + 42-bit multiply and accumulate: 200 ns
32 ÷ 16-bit register-register divide: 1000 ns
• Instruction set suitable for high-speed operation
69 basic instructions
8/16/32-bit move/arithmetic and logic instructions
Unsigned/signed multiply and divide instructions
Multiply-and accumulate instruction
Powerful bit-manipu lati on instructions
• Two CPU operating modes
Normal mode: 64-kbyte address space
(Not available in the H8S/2626 Group or H8S/2623 Group)
Advanced mode: 16-Mbyte address space
Bus controller • Address space divided into 8 areas, with bus specific ations settable
independently for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• External bus release function
PC break
controller • Supports debugging functions by means of PC break interrupts
• Two break channels
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 3 of 1042
REJ09B0275-0500
Item Specifications
Data transfer
controller (DTC) • Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation
source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
16-bit timer-pulse
unit (TPU) • 6-channel 16-bit timer
• Pulse input/output processing capability for up to 16 pins
• Automatic 2-phase encoder count capability
Programmable
pulse generator
(PPG)
• Maximum 8-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or invers e output set tin g
Watchdog timer
(WDT), 2 channels
(H8S/2626 Group)
• Watchdog tim er or interva l timer selectable
• Subclock operation possible (one channel only)
Watchdog timer
(WDT), 1 channel
(H8S/2623 Group)
• Watchdog tim er or interva l timer selectable
Serial communi-
cation interface
(SCI), 3 channels
(SCI0 to SCI2)
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function
Controller area
network (HCAN), 1
channel
• CAN: Ver. 2.0B compliant
• Buffer size: 15 transmit/receive buffers, one transmit-only buffer
• Receive message filtering
A/D converter • Resolution: 10 bits
• Input: 16 channe ls
• 13.3 µs minimum conversion time (at 20 MHz operation)
• Single or scan mode selectable
• Sample-and-hold function
• A/D conversion can be activated by external trigger or timer trigger
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 4 of 1042
REJ09B0275-0500
Item Specifications
D/A converter
(H8S/2626 Group
only)
• Resolution: 8 bits
• Output: 2 channels
I/O ports
(H8S/2626 Group) • 51 input/output pins, 17 input-only pins
I/O ports
(H8S/2623 Group) • 53 input/output pins, 17 input-only pins
Memory • Flash memory or masked ROM
• High-speed static RAM
Product Name ROM RAM
H8S/2626, H8S/ 2623 256 kbytes 12 kbytes
H8S/2625, H8S/ 2622 128 kbytes 8 kbytes
H8S/2624, H8S/ 2621 64 kbytes 4 kbytes
Interrupt controller • Seven external interrupt pins (NMI, IRQ0 to IRQ5)
• Internal interrupt sources
H8S/2626: 48
H8S/2623: 47
• Eight priority lev el s settable
Power-down state • Medium-speed mode
• Sleep mode
• Module stop mode
• Software standb y mode
• Hardware stan dby mode
• Subclock operation (H8S/2626 Group only)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 5 of 1042
REJ09B0275-0500
Item Specifications
Operating modes • Four MCU operating modes
External Data Bus
Mode
CPU
Operating
Mode Description On-Chip
ROM Initial
Width Max.
Width
4 Advanced On-chip ROM disabled
expansion mode Disabled 16 bits 16 bits
5 On-chip ROM disabled
expansion mode Disabled 8 bits 16 bits
6 On-chip ROM enabled
expansion mode Enabled 8 bits 16 bits
7 Single-c hi p mode Enabled — —
Clock pulse
generator • Built-in PLL circuit (×1, ×2, ×4)
• Input clock frequency: 2 to 20 MHz
Package • 100-pin plastic QFP (FP-100B)
Product lineup Model
Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Package
HD6432626
HD6432623 HD64F2626
HD64F2623 256 k/12 k FP-100B
HD6432625
HD6432622 — 128 k/8 k FP-100B
HD6432624
HD6432621 — 64 k/4 k FP-100B
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 6 of 1042
REJ09B0275-0500
1.2 Internal Block Diagram
Figures 1.1 and 1.2 show internal block diagrams of the H8S/2623 Group and H8S/2626 Group.
Internal data bus
Peripheral data bus
Peripheral address bus
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Port D
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
PVCC1
PVCC2
PVCC3
PVCC4
VCC
VCC
VSS
VSS
VSS
VSS
VSS
PA5
PA4
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
4
PC1/A1/RxD0
PC0/A0/TxD0
P97/AN15
P96/AN14
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
HRxD
HTxD
Vref
AVCC
AVSS
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2/IRQ1
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1/IRQ0
P13/PO11/TIOCD0/TCLKB/A23
P12/PO10/TIOCC0/TCLKA/A22
P11/PO9/TIOCB0/A21
P10/PO8/TIOCA0/A20
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/WAIT/BREQO
PF1/BACK
PF0/BREQ/IRQ2
ROM
(Mask ROM,
flash memory)
PC break controller
(2 channels)
RAM
WDT × 1 channel
TPU
SCI × 3 channels
HCAN × 1 channel
A/D converter
PPG
MD2
MD1
MD0
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
STBY
RES
WDTOVF
NMI
FWE
*
H8S/2600 CPU
DTC
Interrupt controller
Port 4Port 1
Internal address bus
Note: * The FWE pin is used only in the flash memory version.
Port E
Port APort BPort CPort 9
Bus controller
Clock pulse
generator
PLL
Port F
Figure 1.1 Internal Block Diagram (H8S/2623 Group)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 7 of 1042
REJ09B0275-0500
Internal data bus
Peripheral data bus
Peripheral address bus
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Port D
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
PVCC1
PVCC2
PVCC3
PVCC4
VCC
VCC
VSS
VSS
VSS
VSS
VSS
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
4
PC1/A1/RxD0
PC0/A0/TxD0
P97/AN15/DA3
P96/AN14/DA2
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
HRxD
HTxD
Vref
AVCC
AVSS
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2/IRQ1
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1/IRQ0
P13/PO11/TIOCD0/TCLKB/A23
P12/PO10/TIOCC0/TCLKA/A22
P11/PO9/TIOCB0/A21
P10/PO8/TIOCA0/A20
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/WAIT/BREQO
PF1/BACK
PF0/BREQ/IRQ2
ROM
(mask ROM or
flash memory)
PC break controller
(2 channels)
RAM
WDT × 2 channels
TPU
SCI × 3 channels
HCAN × 1 channel
A/D converter
PPG
MD2
MD1
MD0
OSC1
OSC2
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
STBY
RES
WDTOVF
NMI
FWE*
H8S/2600 CPU
DTC
Interrupt controller
Port 4Port 1
Internal address bus
Note: * The FWE pin is provided in the flash memory version only.
Port E
D/A converter
PLL
Port APort BPort CPort 9
Port F
Clock pulse
generator
Bus controller
Figure 1.2 Internal Block Diagram (H8S/2626 Group)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 8 of 1042
REJ09B0275-0500
1.3 Pin Descriptions
1.3.1 Pin Arrangement
Figures 1.3 and 1.4 show pin arrangements of the H8S/2623 Group and H8S/2626 Group.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Top view
(FP-100B)
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/IRQ1
P17/PO15/TIOCB2/TCLKD
VCC
HTxD
VSS
HRxD
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE4/D4
VSS
PE5/D5
PVCC1
PE6/D6
PE7/D7
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PA4
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PVCC2
PB1/A9/TIOCB3
VSS
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
4
PC1/A1/RxD0
PC0/A0/TxD0
PD7/D15
PD6/D14
PF0/BREQ/IRQ2
PF1/BACK
PF2/WAIT/BREQO
PF3/LWR/ADTRG/IRQ
3
PF4/HWR
PF5/PD
PF6/AS
PF7/φ
FWE
EXTAL
VSS
XTAL
VCC
STBY
NMI
RES
PLLVCC
PLLCAP
PLLVSS
MD2
MD1
VSS
MD0
PVCC3
PA5
AVCC
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14
P97/AN15
AVSS
VSS
WDTOVF
PVCC4
P10/PO8/TIOCA0/A20
P11/PO9/TIOCB0/A21
P12/PO10/TIOCC0/TCLKA/A22
Figure 1.3 Pin Arrangement (FP-100B: Top View) (H8S/2623 Group)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 9 of 1042
REJ09B0275-0500
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Top view
(FP-100B)
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/IRQ1
P17/PO15/TIOCB2/TCLKD
VCC
HTxD
VSS
HRxD
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE4/D4
VSS
PE5/D5
PVCC1
PE6/D6
PE7/D7
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
OSC1
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PVCC2
PB1/A9/TIOCB3
VSS
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
PC1/A1/RxD0
PC0/A0/TxD0
PD7/D15
PD6/D14
PF0/BREQ/IRQ2
PF1/BACK/BUZZ
PF2/WAIT/BREQO
PF3/LWR/ADTRG/IRQ
PF4/HWR
PF5/PD
PF6/AS
PF7/φ
FWE
EXTAL
VSS
XTAL
VCC
STBY
NMI
RES
PLLVCC
PLLCAP
PLLVSS
MD2
MD1
VSS
MD0
PVCC3
OSC2
AVCC
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14/DA2
P97/AN15/DA3
AVSS
VSS
WDTOVF
PVCC4
P10/PO8/TIOCA0/A20
P11/PO9/TIOCB0/A21
P12/PO10/TIOCC0/TCLKA/A22
Figure 1.4 Pin Arrangement (FP-100B: Top View) (H8S/2626 Group)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 10 of 1042
REJ09B0275-0500
1.3.2 Pin Functions i n Each Operating Mode
Tables 1.2 and 1.3 show the pin functions in each of the operating modes of the H8S/2623 Group
and H8S/2626 Group.
Table 1.2 Pin Functions in Each Operat ing Mode
Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
1 P13/PO11/TIOCD0/
TCLKB/A23 P13/PO11/TIOCD0/
TCLKB/A23 P13/PO11/TIOCD0/
TCLKB/A23 P13/PO11/TIOCD0/
TCLKB
2 P14/PO12/TIOCA1/
IRQ0 P14/PO12/TIOCA1/
IRQ0 P14/PO12/TIOCA1/
IRQ0 P14/PO12/TIOCA1/
IRQ0
3 P15/PO13/TIOCB1/
TCLKC P15/PO13/TIOCB1/
TCLKC P15/PO13/TIOCB1/
TCLKC P15/PO13/TIOCB1/
TCLKC
4 P16/PO14/TIOCA2/
IRQ1 P16/PO14/TIOCA2/
IRQ1 P16/PO14/TIOCA2/
IRQ1 P16/PO14/TIOCA2/
IRQ1
5 P17/PO15/TIOCB2/
TCLKD P17/PO15/TIOCB2/
TCLKD P17/PO15/TIOCB2/
TCLKD P17/PO15/TIOCB2/
TCLKD
6 VCC VCC VCC VCC
7 HTxD HTxD HTxD HTxD
8 VSS VSS VSS VSS
9 HRxD HRxD HRxD HRxD
10 PE0/D0 PE0/D0 PE0/D0 PE0
11 PE1/D1 PE1/D1 PE1/D1 PE1
12 PE2/D2 PE2/D2 PE2/D2 PE2
13 PE3/D3 PE3/D3 PE3/D3 PE3
14 PE4/D4 PE4/D4 PE4/D4 PE4
15 VSS VSS VSS VSS
16 PE5/D5 PE5/D5 PE5/D5 PE5
17 PVCC1 PVCC1 PVCC1 PVCC1
18 PE6/D6 PE6/D6 PE6/D6 PE6
19 PE7/D7 PE7/D7 PE7/D7 PE7
20 D8 D8 D8 PD0
21 D9 D9 D9 PD1
22 D10 D10 D10 PD2
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 11 of 1042
REJ09B0275-0500
Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
23 D11 D11 D11 PD3
24 D12 D12 D12 PD4
25 D13 D13 D13 PD5
26 D14 D14 D14 PD6
27 D15 D15 D15 PD7
28 A0 A0 PC0/A0/TxD0 PC0/TxD0
29 A1 A1 PC1/A1/RxD0 PC1/RxD0
30 A2 A2 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4
31 A3 A3 PC3/A3/TxD1 PC3/TxD1
32 A4 A4 PC4/A4/RxD1 PC4/RxD1
33 A5 A5 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5
34 A6 A6 PC6/A6 PC6
35 A7 A7 PC7/A7 PC7
36 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/TIOCA3
37 VSS VSS VSS VSS
38 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/TIOCB3
39 PVCC2 PVCC2 PVCC2 PVCC2
40 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/TIOCC3
41 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/TIOCD3
42 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/TIOCA4
43 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/TIOCB4
44 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/TIOCA5
45 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/TIOCB5
46 PA0/A16 PA0/A16 PA0/A16 PA0
47 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2
48 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2
49 PA3/A19/SCK2 PA3/A19/SCK2 PA3/A19/SCK2 PA3/SCK2
50 PA4 PA4 PA4 PA4
51 PA5 PA5 PA5 PA5
52 PVCC3 PVCC3 PVCC3 PVCC3
53 MD0 MD0 MD0 MD0
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 12 of 1042
REJ09B0275-0500
Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
54 VSS VSS VSS VSS
55 MD1 MD1 MD1 MD1
56 MD2 MD2 MD2 MD2
57 PLLVSS PLLVSS PLLVSS PLLVSS
58 PLLCAP PLLCAP PLLCAP PLLCAP
59 PLLVCC PLLVCC PLLVCC PLLVCC
60 RES RES RES RES
61 NMI NMI NMI NMI
62 STBY STBY STBY STBY
63 VCC VCC VCC VCC
64 XTAL XTAL XTAL XTAL
65 VSS VSS VSS VSS
66 EXTAL EXTAL EXTAL EXTAL
67 FWE FWE FWE FWE
68 PF7/φPF7/φPF7/φPF7/φ
69 AS AS AS PF6
70 RD RD RD PF5
71 HWR HWR HWR PF4
72 PF3/LWR/ADTRG/
IRQ3 PF3/LWR/ADTRG/
IRQ3 PF3/LWR/ADTRG/
IRQ3 PF3/ADTRG/
IRQ3
73 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2
74 PF1/BACK PF1/BACK PF1/BACK PF1
75 PF0/BREQ/IRQ2 PF0/BREQ/IIRQ2 PF0/BREQ/IIRQ2 PF0/IRQ2
76 AVCC AVCC AVCC AVCC
77 Vref Vref Vref Vref
78 P40/AN0 P40/AN0 P40/AN0 P40/AN0
79 P41/AN1 P41/AN1 P41/AN1 P41/AN1
80 P42/AN2 P42/AN2 P42/AN2 P42/AN2
81 P43/AN3 P43/AN3 P43/AN3 P43/AN3
82 P44/AN4 P44/AN4 P44/AN4 P44/AN4
83 P45/AN5 P45/AN5 P45/AN5 P45/AN5
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 13 of 1042
REJ09B0275-0500
Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
84 P46/AN6 P46/AN6 P46/AN6 P46/AN6
85 P47/AN7 P47/AN7 P47/AN7 P47/AN7
86 P90/AN8 P90/AN8 P90/AN8 P90/AN8
87 P91/AN9 P91/AN9 P91/AN9 P91/AN9
88 P92/AN10 P92/AN10 P92/AN10 P92/AN10
89 P93/AN11 P93/AN11 P93/AN11 P93/AN11
90 P94/AN12 P94/AN12 P94/AN12 P94/AN12
91 P95/AN13 P95/AN13 P95/AN13 P95/AN13
92 P96/AN14 P96/AN14 P96/AN14 P96/AN14
93 P97/AN15 P97/AN15 P97/AN15 P97/AN15
94 AVSS AVSS AVSS AVSS
95 VSS VSS VSS VSS
96 WDTOVF WDTOVF WDTOVF WDTOVF
97 PVCC4 PVCC4 PVCC4 PVCC4
98 P10/PO8/TIOCA0/
A20 P10/PO8/TIOCA0/
A20 P10/PO8/TIOCA0/
A20 P10/PO8/TIOCA0
99 P11/PO9/TIOCB0/
A21 P11/PO9/TIOCB0/
A21 P11/PO9/TIOCB0/
A21 P11/PO9/TIOCB0
100 P12/PO10/TIOCC0/
TCLKA/A22 P12/PO10/TIOCC0/
TCLKA/A22 P12/PO10/TIOCC0/
TCLKA/A22 P12/PO10/TIOCC0/
TCLKA
Note: NC pins should be connected to VSS or left open.
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 14 of 1042
REJ09B0275-0500
Table 1.3 Pin Functions in Each Operat ing Mode
Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
1 P13/PO11/TIOCD0/
TCLKB/A23 P13/PO11/TIOCD0/
TCLKB/A23 P13/PO11/TIOCD0/
TCLKB/A23 P13/PO11/TIOCD0/
TCLKB
2 P14/PO12/TIOCA1/
IRQ0 P14/PO12/TIOCA1/
IRQ0 P14/PO12/TIOCA1/
IRQ0 P14/PO12/TIOCA1/
IRQ0
3 P15/PO13/TIOCB1/
TCLKC P15/PO13/TIOCB1/
TCLKC P15/PO13/TIOCB1/
TCLKC P15/PO13/TIOCB1/
TCLKC
4 P16/PO14/TIOCA2/
IRQ1 P16/PO14/TIOCA2/
IRQ1 P16/PO14/TIOCA2/
IRQ1 P16/PO14/TIOCA2/
IRQ1
5 P17/PO15/TIOCB2/
TCLKD P17/PO15/TIOCB2/
TCLKD P17/PO15/TIOCB2/
TCLKD P17/PO15/TIOCB2/
TCLKD
6 VCC VCC VCC VCC
7 HTxD HTxD HTxD HTxD
8 VSS VSS VSS VSS
9 HRxD HRxD HRxD HRxD
10 PE0/D0 PE0/D0 PE0/D0 PE0
11 PE1/D1 PE1/D1 PE1/D1 PE1
12 PE2/D2 PE2/D2 PE2/D2 PE2
13 PE3/D3 PE3/D3 PE3/D3 PE3
14 PE4/D4 PE4/D4 PE4/D4 PE4
15 VSS VSS VSS VSS
16 PE5/D5 PE5/D5 PE5/D5 PE5
17 PVCC1 PVCC1 PVCC1 PVCC1
18 PE6/D6 PE6/D6 PE6/D6 PE6
19 PE7/D7 PE7/D7 PE7/D7 PE7
20 D8 D8 D8 PD0
21 D9 D9 D9 PD1
22 D10 D10 D10 PD2
23 D11 D11 D11 PD3
24 D12 D12 D12 PD4
25 D13 D13 D13 PD5
26 D14 D14 D14 PD6
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Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
27 D15 D15 D15 PD7
28 A0 A0 PC0/A0/TxD0 PC0/TxD0
29 A1 A1 PC1/A1/RxD0 PC1/RxD0
30 A2 A2 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4
31 A3 A3 PC3/A3/TxD1 PC3/TxD1
32 A4 A4 PC4/A4/RxD1 PC4/RxD1
33 A5 A5 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5
34 A6 A6 PC6/A6 PC6
35 A7 A7 PC7/A7 PC7
36 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/TIOCA3
37 VSS VSS VSS VSS
38 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/TIOCB3
39 PVCC2 PVCC2 PVCC2 PVCC2
40 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/TIOCC3
41 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/TIOCD3
42 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/TIOCA4
43 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/TIOCB4
44 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/TIOCA5
45 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/TIOCB5
46 PA0/A16 PA0/A16 PA0/A16 PA0
47 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2
48 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2
49 PA3/A19/SCK2 PA3/A19/SCK2 PA3/A19/SCK2 PA3/SCK2
50 OSC1 OSC1 OSC1 OSC1
51 OSC2 OSC2 OSC2 OSC2
52 PVCC3 PVCC3 PVCC3 PVCC3
53 MD0 MD0 MD0 MD0
54 VSS VSS VSS VSS
55 MD1 MD1 MD1 MD1
56 MD2 MD2 MD2 MD2
57 PLLVSS PLLVSS PLLVSS PLLVSS
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Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
58 PLLCAP PLLCAP PLLCAP PLLCAP
59 PLLVCC PLLVCC PLLVCC PLLVCC
60 RES RES RES RES
61 NMI NMI NMI NMI
62 STBY STBY STBY STBY
63 VCC VCC VCC VCC
64 XTAL XTAL XTAL XTAL
65 VSS VSS VSS VSS
66 EXTAL EXTAL EXTAL EXTAL
67 FWE FWE FWE FWE
68 PF7/φPF7/φPF7/φPF7/φ
69 AS AS AS PF6
70 RD RD RD PF5
71 HWR HWR HWR PF4
72 PF3/LWR/ADTRG/
IRQ3 PF3/LWR/ADTRG/
IRQ3 PF3/LWR/ADTRG/
IRQ3 PF3/ADTRG/
IRQ3
73 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2
74 PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BUZZ
75 PF0/BREQ/IRQ2 PF0/BREQ/IIRQ2 PF0/BREQ/IIRQ2 PF0/IRQ2
76 AVCC AVCC AVCC AVCC
77 Vref Vref Vref Vref
78 P40/AN0 P40/AN0 P40/AN0 P40/AN0
79 P41/AN1 P41/AN1 P41/AN1 P41/AN1
80 P42/AN2 P42/AN2 P42/AN2 P42/AN2
81 P43/AN3 P43/AN3 P43/AN3 P43/AN3
82 P44/AN4 P44/AN4 P44/AN4 P44/AN4
83 P45/AN5 P45/AN5 P45/AN5 P45/AN5
84 P46/AN6 P46/AN6 P46/AN6 P46/AN6
85 P47/AN7 P47/AN7 P47/AN7 P47/AN7
86 P90/AN8 P90/AN8 P90/AN8 P90/AN8
87 P91/AN9 P91/AN9 P91/AN9 P91/AN9
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Pin No. Pin Name
FP-100B Mode 4 Mode 5 Mode 6 Mode 7
88 P92/AN10 P92/AN10 P92/AN10 P92/AN10
89 P93/AN11 P93/AN11 P93/AN11 P93/AN11
90 P94/AN12 P94/AN12 P94/AN12 P94/AN12
91 P95/AN13 P95/AN13 P95/AN13 P95/AN13
92 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2
93 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3
94 AVSS AVSS AVSS AVSS
95 VSS VSS VSS VSS
96 WDTOVF WDTOVF WDTOVF WDTOVF
97 PVCC4 PVCC4 PVCC4 PVCC4
98 P10/PO8/TIOCA0/
A20 P10/PO8/TIOCA0/
A20 P10/PO8/TIOCA0/
A20 P10/PO8/TIOCA0
99 P11/PO9/TIOCB0/
A21 P11/PO9/TIOCB0/
A21 P11/PO9/TIOCB0/
A21 P11/PO9/TIOCB0
100 P12/PO10/TIOCC0/
TCLKA/A22 P12/PO10/TIOCC0/
TCLKA/A22 P12/PO10/TIOCC0/
TCLKA/A22 P12/PO10/TIOCC0/
TCLKA
Note: NC pins should be connected to VSS or left open.
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1.3.3 Pin Functions
Table 1.4 summarizes the pin functions.
Table 1.4 Pin Functions
Type Symbol I/O Pin Name Function
Power supply VCC Input Power supply For connection to the power supply.
Connect all VCC pins to the system
power supply.
PVCC1 Input Port power supply
PVCC2 Input Port power supply
PVCC3 Input Port power supply
PVCC4 Input Port power supply
Port power supply pins. Connect all
these pins to the same power supply.
VSS Input Ground For connection to the power supply
(0 V). Connect all VSS pins to the
system power supply (0 V).
Clock PLLVCC Input PLL power supply On-chip PLL oscillator power supply
PLLVSS Input PLL ground On-chip PLL oscillator ground
PLLCAP Input PLL capacitance On-chip PLL oscillator external
capacitance pin
XTAL Input Crystal For connection to a crystal resonator.
For examples of crystal resonator
connect ion and ext erna l cloc k inpu t,
see section 20, Clock Pulse
Generator.
EXTAL Input External cloc k For connection to a crystal resonator.
For examples of crystal resonator
connect ion and ext erna l cloc k inpu t,
see section 20, Clock Pulse
Generator.
OSC1*1Input Subclock For connection to a recommended
32.768 kHz resonator. For examples
of crystal resonator connection, see
section 20, Clock Pulse Generator.
OSC2*1Input Subclock For connection to a recommended
32.768 kHz resonator. For examples
of crystal resonator connection, see
section 20, Clock Pulse Generator.
φOutput System clock Suppl ies the system clo ck to extern al
devices.
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Type Symbol I/O Pin Name Function
Operating
mode control MD2 to
MD0 Input Mode pins These pins set the operating mode.
The relation between the settings of
pins MD2 to MD0 and the operating
mode is shown below. Inputs at these
pins should not be changed during
operation.
MD2 MD1 MD0 Operating Mode
000—
1 —
10—
1 —
100Mode 4
1 Mode 5
1 0 Mode 6
1 Mode 7
System
control RES Input Reset input When this pin is driven low, the chip is
reset.
STBY Input Standby When this pin is driven low, a
transition is made to hardware standby
mode.
BREQ Input Bus request Used by an external bus master to
issue a bus request to the chip.
BREQO Output Bus request
output External bus request signal used when
an internal bus master accesses
external space in the external bus-
released state.
BACK Output Bus request
acknowledge Indicates that the bus has been
released to an external bus master.
FWE Input Flash write enable Pin for use by flash memory
Interrupts NMI Input Nonmaskable
interrupt Requests a nonmaskable interrupt. If
this pin is not used, it should be fixed
high.
IRQ5 to
IRQ0 Input Interrupt request
5 to 0 These pins request a maskable
interrupt.
Address bus A23 to A0 Output Address bus These pins output address signals.
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Type Symbol I/O Pin Name Function
Data bus D15 to D0 Input/
output Data bus Bidirectional data bus
Bus control AS Output Address strobe Goes low to indicate valid address
output on the address bus.
RD Output Read Goes low to indicate reading from the
external addr es s spac e.
HWR Output High write Strobe signal indicating writing to the
external address space; indicates valid
data on the upper data bus (D15 to
D8).
LWR Output Low write Strobe signal indicating writing to the
external address space; indicates valid
data on the lower data bus (D7 to D0).
WAIT Input Wait Requests ins erti on of wait sta tes in
bus cycles during access to 3-state
external addr es s spac e.
TCLKD to
TCLKA Input Clock input
D to A These pins input an external clock.16-bit timer-
pulse unit
(TPU) TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
Input/
output Input capture/
output compare
match A0 to D0
The TGR0A to TGR0D input capture
input/out put com pare output/PWM
output pins
TIOCA1,
TIOCB1 Input/
output Input capture/
output compare
match A1 and B1
The TGR1A and TGR1B input capture
input/out put com pare output/PWM
output pins
TIOCA2,
TIOCB2 Input/
output Input capture/
output compare
match A2 and B2
The TGR2A and TGR2B input capture
input/out put com pare output/PWM
output pins
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
Input/
output Input capture/
output compare
match A3 to D3
The TGR3A to TGR3D input capture
input/out put com pare output/PWM
output pins
TIOCA4,
TIOCB4 Input/
output Input capture/
output compare
match A4 and B4
The TGR4A and TGR4B input capture
input/out put com pare output/PWM
output pins
TIOCA5,
TIOCB5 Input/
output Input capture/
output compare
match A5 and B5
The TGR5A and TGR5B input capture
input/out put com pare output/PWM
output pins
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Type Symbol I/O Pin Name Function
Programmable
pulse
generator
(PPG)
PO15 to
PO8 Output Pulse output
15 to 8 Pulse output pins
Watchdog
timer (WDT) WDTOVF Output Watchdog timer
overflow The counter overflow signal output pin
in watchdog timer mode
TxD2,
TxD1,
TxD0
Output Transmit data Data output pinsSerial
communication
interface (SCI)/
smart card
interface RxD2,
RxD1,
RxD0
Input Receive data Data input pins
SCK2,
SCK1,
SCK0
Input/
output Serial clock Clock input/output pins
HTxD Output HCAN transmit
data The CAN bus transmission pinController
area network
(HCAN) HRxD Input HCAN receiv e
data The CAN bus reception pin
A/D converter AN15 to
AN0 Input Analog 15 to 0 Analog input pins
ADTRG Input A/D conversion
external trigg er
input
Pin for input of an external trigger to
start A/D conversion
D/A converter
pin DA3, DA2 Output Analog output D/A converter analog output pins
A/D converter/
D/A converter AVCC Input Analog power
supply The power supply pin for the A/D and
D/A converters. When the A/D and
D/A converters are not used, connect
this pin to the system power supply
(+5 V).
AVSS Input Analog ground The ground pin and reference voltage
for the A/D and D/A converters.
Connect this pin to the system power
supply (0 V).
Vref Input Analog reference
power supply The reference voltage input pin for the
A/D and D/A converters. When the
A/D and D/A converters are not used,
connect this pin to the system power
supply (+5 V).
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Type Symbol I/O Pin Name Function
I/O ports P17 to
P10 Input/
output Port 1 Eight input/output pin s. Input or output
can be selected for each pin in the
port 1 data direction register (P1DDR).
P47 to
P40 Input Port 4 Eight input pins
P97 to
P90 Input Port 9 Eight input pins
PA5 to
PA0*2Input/
output Port A Six input/output pins. Input or output
can be selected for each pin in the
port A data direction register
(PADDR).
PB7 to
PB0 Input/
output Port B Eight input/output pin s. Input or output
can be selected for each pin in the
port B data direction register
(PBDDR).
PC7 to
PC0 Input/
output Port C Eight input/out put pin s. Input or output
can be selected for each pin in the
port C data direction regi ster
(PCDDR).
PD7 to
PD0 Input/
output Port D Eight input/out put pin s. Input or output
can be selected for each pin in the
port D data direction regi ster
(PDDDR).
PE7 to
PE0 Input/
output Port E Eight input/output pin s. Input or output
can be selected for each pin in the
port E data direction register
(PEDDR).
PF7 to
PF0 Input/
output Port F Eight input/output pins. Input or output
can be selected for each pin in the
port F data direction register (PFDDR).
Notes: 1. Applies to the H8S/2626 Group only.
2. PA3 to PA0 in the H8S/2626 Group.
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Section 2 CPU
2.1 Overview
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is
ideal for realtim e contr ol.
2.1.1 Features
The H8S/2600 CPU has the following features.
• Upward-compatible with H8 /300 and H8/300H CPUs
Can execute H8/300 and H8/300 H object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
• Sixty-nine basic instructions
8/16/32-b it ar ithmetic and logic in str uctions
Multiply and divide instructio ns
Powerful bit-manipulation instructions
Multiply-and-accumulate instr uction
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @( d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx: 16, or #xx: 3 2]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes (4 Gbytes architecturally)
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• High-speed operation
All frequently-u sed instructions execute in one or two states
Maximum clock rate: 20 MHz
8/16/32-bit register-register add/subtract: 50 ns
8 × 8-bit register-reg ister multiply: 150 ns
16 ÷ 8-bit register-register divide: 600 ns
16 × 16-bit register-register multiply: 200 ns
32 ÷ 16-bit register-register divide: 1000 ns
• Two CPU operating modes
Normal mode*
Advanced mode
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions is different in each
CPU.
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
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In addition, there are differences in addr ess space, CCR and EXR register fun ctions, power-down
modes, etc., depending on the model.
2.1.3 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide in structions have be en added.
A multiply-and-accumulate in struction has been added.
Two-bit shift instructions have been added.
Instructio ns for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
2.1.4 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.
• Additional control register
One 8-bit and two 32-bit control registers have been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
A multiply-and-accumulate in struction has been added.
Two-bit shift instructions have been added.
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Instructio ns for saving and r e storing multiple registers have be en added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
2.2 CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for
program and data areas combined). The mode is selected by the mode pins of the microcontroller.
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
CPU operating modes
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Normal mode*
Advanced mode
Maximum 64 kbytes, program
and data areas combined
Maximum 16-Mbytes for
program and data areas
combined
Figure 2.1 CPU Operating Modes
(1) Normal Mode (Not Available in the H8S/2626 Group or H8S/2623 Group)
The exception vector table and stack have the same structure as in the H8/300 CPU.
Address Space: A maximum address space of 64 kbytes can be accessed.
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain
any value, even when the corresponding general register (Rn) is used as an address register. If the
general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn)
Section 2 CPU
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or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (E n) will be affected.
Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of
effective addresses (EA) are valid.
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details
of the exception vector table, see section 4, Exception Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
Manual reset exception vector*
Exception vector 1
Exception vector 2
Exception
vector table
(Reserved for system use)
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in th e instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-
bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.
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Stack Structure: When the program counter (PC) is pushed onto the stack in a subrou tine call,
and the PC, co ndition-code register (CCR), and extended control register ( EXR) are pushed onto
the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is
not pushed onto the stack. For details, see section 4, Exception Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(16 bits) EXR*1
Reserved*1 *3
CCR
CCR*3
PC
(16 bits)
SP SP
Notes: 1.
2.
3.
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
Ignored when returning.
(SP )
*2
Figure 2.3 Stack Structure in Normal Mode
(2) Advanced Mode
Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally
a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4
Gbytes for program and data areas combined).
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers or address registers.
Instruction Set: All instructions and addressing modes can be used.
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top
area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32
bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4).
For details of the exception vector table, see section 4, Exception Handling.
H'00000000
H'00000003
H'00000004
H'0000000B
H'0000000C
Exception vector table
Reserved
Reset exception vector
(Reserved for system use)
Reserved
Exception vector 1
Reserved
Manual reset exception vector*
H'00000010
H'00000008
H'00000007
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Figure 2.4 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in th e instruction code to specify a memory operand that
contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing
a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area th at is regarded as
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H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the
first part of th is r ange is also the exception vector table.
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a
subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR)
are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When
EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(24 bits)
EXR*1
Reserved*1 *3
CCR
PC
(24 bits)
SP SP
Notes: 1.
2.
3.
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
Ignored when returning.
(SP )
*2
Reserved
Figure 2.5 Stack Structure in Advanced Mode
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2.3 Address Space
Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.
(b) Advanced Mode
H'0000
H'FFFF
H'00000000
H'FFFFFFFF
H'00FFFFFF
(a) Normal Mode*
Data area
Program area
Cannot be
used by the
H8S/2626
Group or
H8S/2623
Group
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Figure 2.6 Memory Map
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2.4 Register Configuration
2.4.1 Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general
registers and control registers.
T
————
I2 I1 I0EXR 76543210
PC
23 0
15 07 07 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
General Registers (Rn) and Extended Registers (En)
Control Registers (CR)
Legend: Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit*
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Note: * Cannot be used as an interrupt mask bit in the H8S/2626 Group or H8S/2623 Group.
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
I
UI
HUNZVCCCR 76543210
Sign extension
63 32
41
031
MAC MACL
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Multiply-accumulate register
H:
U:
N:
Z:
V:
C:
MAC:
MACH
Figure 2.7 CPU Registers
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2.4.2 General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a data
register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used
as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, prov iding a maximum sixteen 8-bit
registers.
Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
Section 2 CPU
Rev. 5.00 Jan 10, 2006 page 34 of 1042
REJ09B0275-0500
Free area
Stack area
SP (ER7)
Figure 2.9 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),
8-bit condition - code register (CCR), and 6 4-bit multiply-accumulate register (MAC).
(1) Program Counter (PC)
This 24-b it coun ter indicates th e address of the next instruction the CPU will execute. Th e length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is re garded as 0. )
(2) Extended Control Register (EXR)
This 8-bit register contains the trace bit (T) and three interr upt mask bits (I2 to I0).
Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed
in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is
executed.
Bits 6 to 3—Reserved: They are always read as 1.
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate th e interrupt mask level (0 to
7). For details, ref e r to section 5, Interrupt Controller.
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instruction s. All in ter r upts, including NMI , are disabled for three states after one of th ese
instructions is executed, except for STC.
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REJ09B0275-0500
(3) Condition-Code Register (CCR)
This 8-bit r egister contains internal CPU statu s in formation , including an interrupt ma sk bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start o f an exception-
handling sequence. For details, refer to section 5, Interrupt Controller.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by sof twar e u sin g the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details, r e f e r to section 5, Interrupt Con tr oller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is ex ecuted, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is ex ecuted, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instru ctions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to sto r e the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to appendix A.1, Instruction List.
Section 2 CPU
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REJ09B0275-0500
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
(4) Multiply - A ccumulate Register (MAC)
This 64-b it register stores the results of multiply -and-accumulate operation s. It consists of two 32-
bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.
2.4.4 Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the genera l r egisters ar e not initialized. In par ticular, the stack pointer (ER7 ) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
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2.5 Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions op erate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-b it
BCD data.
2.5.1 General Register Data Formats
Figure 2.10 shows the data formats in general registers.
76543210 Don’t care
70
Don’t care 76543210
43
70
70
Don’t careUpper Lower
LSB
MSB LSB
Data Type Register Number Data Format
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
RnH
RnL
RnH
RnL
RnH
RnL
MSB
Don’t care Upper Lower
43
70
Don’t care
70
Don’t care 70
Figure 2.10 General Register Data Formats
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REJ09B0275-0500
0
MSB LSB
15
Word data
Word data
Rn
En
0
LSB
15
16
MSB
31
En Rn
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Legend:
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
0
MSB LSB
15
Longword data ERn
Data Type Register Number Data Format
Figure 2.10 General Register Data Formats (cont)
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REJ09B0275-0500
2.5.2 Memory Data Formats
Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data
in memory, but word or longword data must begin at an even address. If an attempt is made to
access word or longword data at an odd address, no address error occurs bu t the least significant
bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to
instructio n fetches.
76543210
70
MSB LSB
MSB
LSB
MSB
LSB
Data Type Data Format
1-bit data
Byte data
Word data
Longword data
Address
Address L
Address L
Address 2M
Address 2M + 1
Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
Figure 2.11 Memory Data Formats
When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.
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REJ09B0275-0500
2.6 Instruction Set
2.6.1 Overview
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
Data transfer MOV BWL 5
POP*1, PUSH*1WL
LDM, STM L
MOVFPE*3, MOVTPE*3B
ADD, SUB, CMP, NEG BWL 23Arithmetic
operations ADDX, SUBX, DAA, DAS B
INC, DEC BWL
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS BW
EXTU, EXTS WL
TAS*4B
MAC, LDMAC, STMAC, CLRMAC —
Logic operations AND, OR, XOR, NOT BWL 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8
Bit manipulati on BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR B14
Branch Bcc*2, JMP, BSR, JSR, RTS — 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9
Block data transfer EEPMOV — 1
Total: 69
Legend: B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Not available in the H8S/2626 Group or H8S/2623 Group.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Section 2 CPU
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REJ09B0275-0500
2.6.2 Instructions and Addressing Mo des
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Table 2.2 Combinations of Instructions and Addressing Modes
Addressing Modes
Function Instruction
#xx
Rn
@ERn
@(d:16,ERn)
@(d:32,ERn)
@–ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
—
MOV BWL BWL BWL BWL BWL BWL B BWL —BWL ————Data
transfer POP, PUSH —————————————WL
LDM, STM ————————————— L
MOVEPE*1,
MOVTPE*1———————B——————
ADD, CMP BWL BWL ————————————
Arithmetic
operations SUB WL BWL ————————————
ADDX, SUBX B B ————————————
ADDS, SUBS — L ————————————
INC, DEC —BWL ————————————
DAA, DAS — B ————————————
MULXU, DIVXU —BW ————————————
MULXS, DI VXS —BW ————————————
NEG —BWL ————————————
EXTU, EXTS —WL ————————————
TAS*2——B———————————
MAC ————— ————————
CLRMAC —————————————
LDMAC, STMAC — L ————————————
AND, OR, XOR BWL BWL ————————————Logic
operations NOT — BWL ————————————
Shift —BWL ————————————
Bit manipulation —BB———BB— B ————
Branch Bcc, BSR —————————— ——
JMP, JSR ———————— ——— —
RTS —————————————
TRAPA —————————————System
control RTE —————————————
SLEEP —————————————
LDC B B W W W W — W — W ————
STC —BWWWW— W — W ————
ANDC, ORC,
XORC B—————————————
NOP —————————————
Block data transfer —————————————BW
Legend: B: Byte
W: Word
L: Longword
Notes: 1. Not available in the H8S/2626 Group or H8S/2623 Gr oup.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Section 2 CPU
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REJ09B0275-0500
2.6.3 Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The no tation used in table 2.3
is defined below.
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
MAC Multiply-accumulate register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control r egi ster
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
–Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Logical exclusive OR
→Move
¬NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Table 2.3 Instructions Classified by Function
Type Instruction Size*1Function
Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead)
Moves data between two general registers or between a
general register and memory, or moves immediate data
to a general register.
MOVFPE B Cannot be used in the H8S/2626 Group or H8S/2623
Group.
MOVTPE B Cannot be used in the H8S/2626 Group or H8S/2623
Group.
POP W/L @SP+ → Rn
Pops a register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a register onto the stack. PUSH.W Rn is
identical to MOV.W Rn, @–SP. PUSH.L ERn is identical
to MOV.L ERn, @–SP.
LDM L @SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM L Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
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Type Instruction Size*1Function
Arithmetic
operations ADD
SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register. (Immediate byte data cannot be subtracted
from byte data in a general register. Use the SUBX or
ADD instruction.)
ADDX
SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on
byte data in two general registers, or on immediate data
and data in a general register.
INC
DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
ADDS
SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a
32-bit register.
DAA
DAS B Rd decimal adjust → Rd
Decimal-a dju st s an additi on or subtrac t io n result in a
general register by referring to the CCR to produce 4-bit
BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
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Type Instruction Size*1Function
Arithmetic
operations DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-
bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the resul t.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of
data in a general register .
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
TAS B @ERd – 0, 1 → (<bit 7> of @ERd)*2
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
MAC — (EAs) × (EAd) + MAC → MAC
Performs signed mu ltiplication on memory contents and
adds the result to the multiply-accumulate register. The
following oper atio ns can be performe d:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC —0 → MAC
Clears the multiply-accumulate register to zero.
LDMAC
STMAC LRs → MAC, MAC → Rd
Transfers data between a general register and a
multiply-a ccum u late regi ster .
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Type Instruction Size*1Function
Logic
operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one's complement of general register
contents.
Shift
operations SHAL
SHAR B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
SHLL
SHLR B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
ROTL
ROTR B/W/L Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
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Type Instruction Size*1Function
Bit-
manipulation
instructions
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
BTST B ¬ (<bit-No .> of <EAd>) → Z
Tests a specified bit in a general register or memory
operand and sets or clears the Z flag accordingly. The
bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
BAND
BIAND
B
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
BIOR
B
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Type Instruction Size*1Function
Bit-
manipulation
instructions
BXOR
BIXOR
B
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-O Rs the carry flag with a specif ied bit in a
general register or memory operand and stores the
result in the carry flag.
C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a
specified bit in a general register or memory operand
and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
BILD
B
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag.
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general
register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
BIST
B
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a
general register or memory operand.
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a
specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
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Type Instruction Size*1Function
Branch
instructions Bcc —Branches to a specified address if a specified condition
is true. The branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (true) Always
BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC(BHS) Carry clear
(high or same) C = 0
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP —Branches unconditionally to a specified address.
BSR —Branches to a subroutine at a specified address.
JSR —Branches to a subroutine at a specified address.
RTS —Returns from a subroutine
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Type Instruction Size*1Function
TRAPA —Starts trap-instruction exception handling.
RTE —Returns from an exception-handling routine.
System
control
instructions SLEEP —Causes a transition to a power-down state.
LDC B/W (EAs) → CCR, (EAs) → EXR
Moves the sour ce opera nd cont ents or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit
registers, word-size transfers are performed between
them and memory. The upper 8 bits are valid.
STC B/W CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general regis ter or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with
immediate data.
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate
data.
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data.
NOP —PC + 2 → PC
Only increments the program counter.
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Type Instruction Size*1Function
Block data
transfer
instruction
EEPMOV.B
EEPMOV.W
—
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block according to parameters set in
general registers R4L or R4, ER5, and ER6.
R4L or R4: si ze of block (bytes)
ER5: starting source address
ER6: starting destination address
Execution of the next instruction begins as soon as the
transfer is completed.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
2.6.4 Basic Instruction Formats
The H8S/2626 Group and H8S/2623 Group instructions consist of 2-byte (1-word) units. An
instruction consists of an operation field (op field), a register field (r field), an effective address
extension (EA field), and a condition field (cc).
(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the
operation to be carried out on the operand. The operation field always includes the first four bits of
the instruction. Some instructions have two operation fields.
(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data
registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register
field.
(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
(4) Condition Field: Specifies the branching con dition of Bcc instru ctions.
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Figure 2.12 shows examples of instruction formats.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
rn rm
op
EA (disp)
(4) Operation field, effective address extension, and condition field
op cc EA (disp) BRA d:16, etc.
Figure 2.12 Instruction Formats (Examples)
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2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Mode
The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of
these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-coun ter
relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit nu mber in the operand.
Table 2.4 Addressing Mo des
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement @ERn+
@–ERn
5 Absolute addres s @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
(1) Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
(2) Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
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(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or
longword transfer instruction, the register value should be even.
• Register indirect with pre-decrem ent—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instru ction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer
instruction, or 4 for longword transfer instruction. For word or longword transfer instruction,
the register value should be even.
(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit abso lute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a prog ram instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.5 indicates the accessible absolute address ranges.
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Table 2.5 Absolute Address Access Ranges
Absolute Address Normal Mode*Advanced Mode
Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32) H'000000 to H'FFFFFF
Program instruction
address 24 bits (@aa:24)
Note: *Not available in the H8S/2626 Group or H8S/2623 Group.
(6) Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions con tain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits ar e all assumed to be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
(8) Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode*
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode
the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00).
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Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
(a) Normal Mode*(b) Advanced Mode
Branch address
Specified
by @aa:8 Specified
by @aa:8 Reserved
Branch address
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Figure 2.13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
2.7.2 Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal
mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: * Cannot be set in the H8S/2626 Group or H8S/2623 Group.
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Table 2.6 Effective Address Calculation
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
1 Register direct (Rn)
op rm rn Operand is general register contents.
Register indirect (@ERn)2
Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
3
• Register indirect with pre-decrement @–ERn
4
General register contents
General register contents
Sign extension disp
General register contents
1, 2, or 4
General register contents
1, 2, or 4
Byte
Word
Longword
1
2
4
Operand Size Value added
31 0
31 0
31 0
31 0
31 0 31 0
31 0
31 0
31 0
op r
r
op
op r
rop
disp
24 23
Don’t care
24 23
Don’t care
24 23
Don’t care
24 23
Don’t care
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5
@aa:8
Absolute address
@aa:16
@aa:32
6Immediate #xx:8/#xx:16/#xx:32
31 08 7
Operand is immediate data.
No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
@aa:24
31 0
16 15
31 0
24 23
31 0
op abs
op abs
abs
op
op
abs
op IMM
H'FFFF
Don’t care
24 23
Don’t care
24 23
Don’t care
24 23
Don’t care Sign extension
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31
0
0
0
7Program-counter relative
@(d:8, PC)/@(d:16, PC)
8Memory indirect @@aa:8
• Normal mode*
• Advanced mode
0
No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
23
23
31 8 7
0
15
0
31 8 7
0
disp
H'000000
abs
H'000000
31 0
24 23
31 0
16 15
31 0
24 23
op disp
op abs
op abs
Sign
extension
PC contents
abs
Memory contents
Memory contents
H'00
Don’t care
24 23
Don’t care
Don’t care
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
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2.8 Processing States
2.8.1 Overview
The CPU has five main processing states: the reset state, exception handling state, program
execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the
processing states. Figure 2.15 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Power-down state
CPU operation is stopped
to conserve power.*
Sleep mode
Software standby
mode
Hardware standby
mode
Processing
states
Note:
*The power-down state also includes a medium-speed mode, module stop mode,
subactive mode, subsleep mode, and watch mode. Subclock functions (subactive
mode, subsleep mode, and watch mode) are not available in the H8S/2623 Group,
but are available in the H8S/2626 Group.
Figure 2.14 Processing States
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Exception handling state
Bus-released state
Hardware standby mode
*
2
Software standby mode
Reset state
*
1
Sleep mode
Power-down state
*
3
Program execution state
End of bus request
Bus request
Interrupt request
External interrupt request
RES= High
Request for exception handling
STBY= High, RES= Low
End of bus
request
Bus request
SLEEP
instruction
with
SSBY = 0
SLEEP
instruction
with
SSBY = 1
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode in the
H8S/2626 Group. See section 21B, Power-Down Modes [H8S/2626 Group].
End of exception
handling
Reset state
Figure 2.15 State Transitions
2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrup ts ar e masked in the reset state. Reset exceptio n handlin g starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,
Watchdog Timer.
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2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing f low due to a reset, interrupt, or trap instr uction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7
indicates the types of exception handling and their priority. Trap instruction exception handling is
always accepted, in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7 Exception Handling Types and Prio rity
Priority Type of Exception Detection Timing Start of Exception Handling
High Reset Synchronized with clock Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
Trace End of instruction execution
or end of exception-handling
sequence*1
When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence
Interrupt End of instruction execution
or end of exception-handling
sequence*2
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Low
Trap instruction When TRAPA instruction
is exec uted Exception handling starts when
a trap (TRAPA) instruction is
executed*3
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not
executed at the end of the RTE instruction.
2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
3. Trap instruction exception handling is always accepted, in the program execution state.
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(2) Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, wh en RES pin goes high
again, reset exception handling starts. The CPU enters the reset state when the RES is low. When
reset exception handling starts the CPU fetches a start address (vector) from the ex ception vector
table and starts program execution from that address. All interrupts, including NMI, are disabled
during reset ex ception handling and after it ends.
(3) Traces
Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR
is set to 1. When trace mode is established, trace exception handling starts at the end of each
instruction.
At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode
is cleared. Interrupt masks are no t affected.
The T bit saved on th e stack retains its value of 1, and when the RTE instruction is executed to
return from the trace exception-handling routine, trace mode is entered again. Trace exception-
handling is not executed at the end of the RTE instruction.
Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.
(4) Interrupt Exception Ha ndling and Trap Inst ruction Exception Ha ndling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the contro l register s. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2.16 shows the stack after exception handling ends.
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(c) Interrupt control mode 0 (d) Interrupt control mode 2
CCR
PC
(24 bits)
SP
CCR
PC
(24 bits)
SP
EXR
Reserved
*1
(a) Interrupt control mode 0 (b) Interrupt control mode 2
CCR
CCR
*1
PC
(16 bits)
SP
CCR
CCR
*1
PC
(16 bits)
SP
EXR
Reserved
*1
Normal mode
*2
Advanced mode
Notes: 1. Ignored when returning.
2. Not available in the H8S/2626 Group or H8S/2623 Group.
Figure 2.16 Stack Structure after Exception Handling (Examples)
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2.8.4 Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5 Bus- Released Sta t e
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. Wh ile the bus is released, th e CPU halts operatio ns.
Bus masters other than the CPU are data transfer controller (DTC).
For further details, refer to section 7, Bus Controller.
2.8.6 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode*, and watch mode*. There are
also three other power-down modes: medium-speed mode, module stop mode, and subactive
mode*. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock.
Module stop mode permits halting of the operation of individual modules, other than the CPU.
Subactive mode*, subsleep mode*, and watch mode* are power-down states using subclock input.
For details, refer to section 21B, Power-Down Modes [H8S/2626 Group].
Note: * Supported only in the H8S/2626 Group; not available in the H8S/2623 Group.
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2.9 Basic Timing
2.9.1 Overview
The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The period from one
rising edge of φ to the next is referr ed to as a "state." The memory cycle or bus cycle consists of
one, two, or three states. Different methods are used to access on-chip memory, on-chip
supporting modules, and the external address space.
2.9.2 On-Chip Memo ry (ROM, RAM)
On-chip memory is accessed in one state. Th e data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows
the pin states.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
φ
Bus cycle
T1
Address
Read data
Write data
Read
access
Write
access
Figure 2.17 On-Chip Memory Access Cycle
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Bus cycle
T1
RetainedAddress bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 2.18 Pin States during On-Chip Memory Access
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2.9.3 On-Chip Supporting Module Acces s Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the
access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
Bus cycle
T1 T2
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Internal address bus
φ
Figure 2.19 On-Chip Supporting Module Access Cycle
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Bus cycle
T1 T2
Retained
Address bus
AS
RD
HWR, LWR
Data bus
φ
High
High
High
High-impedance state
Figure 2.20 Pin States during On-Chip Supporting Module Access Cycle
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2.9.4 On-Chip HCAN Module Access Timing
On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait
states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access
timing is shown in figures 2.21 and 2.22, and the pin states in figure 2.23.
Internal address bus
HCAN read signal
Internal data bus
HCAN write signal
Internal data bus
φ
Bus cycle
T1
Address
Read
Write
Read data
Write data
T3
T2 T4
Figure 2.21 On-Chip HCAN Module Access Cy cle (No Wait State)
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Internal address bus
HCAN read signal
Internal data bus
HCAN write signal
Internal data bus
φ
Bus cycle
T1
Address
Read
Write
T3
T2 Tw
Read data
Write data
Tw T4
Figure 2.22 On-Chip HCAN Module Access Cy cle (Wait States Inserted)
T1 T3
T2 T4
Bus cycle
AS
RD
HWR, LWR
Data bus
φ
High
High
High
RetainedAddress bus
High-impedance state
Figure 2.23 Pin States in On-Chip HCAN Module Access
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2.9.5 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 7, Bus Controller.
2.10 Usage Note
2.10.1 TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers.
If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0,
ER1, ER4, or ER5 is used.
Section 3 MCU Operating Modes
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Section 3 MCU Operati ng Mo des
3.1 Overview
3.1.1 Operating Mode Selectio n
The H8S/2626 Group and H8S/2623 Group have four operating modes (modes 4 to 7). These
modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the
initial bus width setting, by setting the mode pins (MD2 to MD0) .
Table 3.1 lists the MCU operating modes.
Table 3.1 MCU Operating Mode Selection
External Data Bus
MCU
Operating
Mode MD2 MD1 MD0
CPU
Operating
Mode Description On-Chip
ROM Initial
Width Max.
Width
0*000— — — —
1*1—
2*10
3*1
4 1 0 0 Advanced Disabled 16 bits 16 bits
51
On-chip ROM disabled,
expanded mode 8 bits 16 bits
6 1 0 On-chip ROM enabled,
expanded mode Enabled 8 bits 16 bits
7 1 Single-chip mode —
Note: *Not available in the H8S/2626 Group or H8S/2623 Group.
The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2626 Group and
H8S/2623 Group actually access a maximum of 16 Mbytes.
Modes 4 to 6 are externally expanded modes that allow access to external memo ry and peripheral
devices.
The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program
execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus
controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit
access is selected for all areas, 8-bit bus mode is set.
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Note that the functions of each pin depend on the operating mode.
The H8S/2626 Group and H8S/2623 Group can be used only in modes 4 to 7. This means that the
mode pins must be set to select one of these modes. Do not change the inputs at the mode pins
during operation.
3.1.2 Register Configuration
The H8S/2626 Group and H8S/2623 Group have a mode control register (MDCR) that indicates
the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls
the operation of the H8S/2626 Group or H8S/2623 Group chip. Table 3.2 summarizes these
registers.
Table 3.2 MCU Registers
Name Abbreviation R/W Initial Value Address*
Mode control register MDCR R/W Undetermined H'FDE7
System control register SYSCR R/W H'01 H'FDE5
Pin function control register PFCR R/W H'0D/H'00 H'FDEB
Note: *Lower 16 bits of the address.
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3.2 Register Descriptions
3.2.1 Mode Control Register (MDCR)
7
—
1
R/W
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
MDS2
—*
R
1
MDS1
—*
R
Note: * Determined by pins MD2 to MD0.
Bit
Initial value
R/W
:
:
:
MDCR is an 8-bit register that indicates the current operating mode of the H8S/2626 Group or
H8S/2623 Group chip.
Bit 7—Reserved: Only 1 should be written to this bit.
Bits 6 to 3—Reserved: These bits are always read as 0 and cannot be modified.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0.
MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input
levels are latched into these bits when MDCR is read. These latches are canceled by a reset.
3.2.2 System Control Register (SYSCR)
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
—
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and
enables or disables on-chip RAM.
SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in
software standby mode.
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Bit 7—MAC Saturation (MACS): Selects either saturating or non-satur a ting calculation for the
MAC instructio n.
Bit 7
MACS Description
0 Non-saturating calculation for MAC instruction (Initial value
)
1 Saturating calculation for MAC instruction
Bit 6—Reserved: This bit is always read as 0 and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and I nterr upt Operation.
Bit 5 Bit 4
INTM1 INTM0 Interrupt
Control Mode Description
0 0 0 Control of interrupts by I bit (Initial value)
1 — Setting prohibited
1 0 2 Control of interrupts by I2 to I0 bits and IPR
1 — Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG Description
0 An interrupt is requested at the falling edge of NMI input (Initial value
)
1 An interrupt is requested at the rising edge of NMI input
Bit 2—Reserved: Only 0 should be written to this bit.
Bit 1—Reserved: This bit is always read as 0 and cannot be modified.
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Bit 0—RA M Enable ( R AME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value
)
Note: When the DTC is used, the RAME bit must be set to 1.
3.2.3 Pin Function Control Register (PFCR)
7
—
0
R/W
6
—
0
R/W
5
BUZZE
0
R/W
4
—
0
R/W
3
AE3
1/0
R/W
0
AE0
1/0
R/W
2
AE2
1/0
R/W
1
AE1
0
R/W
Bit
Initial value
R/W
:
:
:
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous
state in software standby mode.
Bits 7 to 4—Reserved: Only 0 should be written to these bits.
Bit 5—BUZZE Ou tput Enable (BUZZE): This bit is for use only in the H8S/2626. Only 0
should be writtn to this bit.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or
disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When
a pin is enabled for address output, the address is output regardless of the corresponding DDR
setting. When a pin is disabled fo r address output, it becomes an output port when the
corresponding DDR bit is set to 1.
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Bit 3 Bit 2 Bit 1 Bit 0
AE3 AE2 AE1 AE0 Description
0000A8–A23 address output disabled (Initial value*)
1 A8 address output enabled; A9–A23 address output disabled
1 0 A8, A9 address output enabled; A10–A23 address output
disabled
1A8–A10 address output enab led ; A11–A23 address output
disabled
100A8–A11 address output enabled ; A12–A23 addr ess output
disabled
1A8–A12 address output enab led ; A13–A23 address output
disabled
10A8–A13 address output enab led ; A14–A23 address output
disabled
1A8–A14 address output enab led ; A15–A23 address output
disabled
1000A8–A15 address output enabled ; A16–A23 addr ess output
disabled
1A8–A16 address output enab led ; A17–A23 address output
disabled
10A8–A17 address output enab led ; A18–A23 address output
disabled
1A8–A18 address output enab led ; A19–A23 address output
disabled
100A8–A19 address output enabled ; A20–A23 addr ess output
disabled
1A8–A20 address output enab led ; A21–A23 address output
disabled (Initial value*)
10A8–A21 address output enabled; A22, A23 address output
disabled
1A8–A23 address output enab led
Note: *In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR
bits to 1.
Section 3 MCU Operating Modes
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3.3 Operating Mode Descriptions
3.3.1 Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of
port F carries bus control signals.
The initial bus mod e after a reset is 16 bits, with 1 6 - bit access to all areas. However, note that if 8-
bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.2 Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of
port F carries bus control signals.
The initial bus mod e after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16 -
bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
3.3.3 Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. Th e on-chip ROM is enabled.
Ports 1, A, B, and C, function as input port pins immediately after a reset. Address output can be
performed by setting the corresponding DDR (data direction register) bits to 1.
Port D function as a data bus, and part of port F carries data bus signals.
The initial bus mod e after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16 -
bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
3.3.4 Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. Th e on-chip ROM is enabled,
but external addresses cannot be accessed.
Section 3 MCU Operating Modes
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All I/O ports are available for use as input-output ports.
3.4 Pin Functions in Each Operating Mode
The pin functions of ports 1 and A to F vary depending on the operating mode. Table 3.3 shows
their functions in each operating mode.
Table 3.3 Pin Functions in Each Mode
Port Mode 4 Mode 5 Mode 6 Mode 7
Port 1 P10 A A P*/A P
P11 to P13 P*/A P*/A P*/A P
Port A PA4 to PA0 A A P*/A P
Port B A A P*/A P
Port C A A P*/A P
Port D DDDP
Port E P/D*P*/D P*/D P
Port F PF7 P/C*P/C*P/C*P*/C
PF6 to PF4 C C C P
PF3 P/C*P*/C P*/C
PF2 to PF0 P*/C P*/C P*/C
Legend:
P: I/O port
A: Address bus output
D: Data bus I/O
C: Control signals, clo ck I/O
Note: *After reset
3.5 Address Map in Each Operating Mode
An address map of the H8S/2623 and H8S/2626 is shown in figure 3.1, and an address map of the
H8S/2622, and H8S/2625 in figure 3.2, and an address map of the H8S/2621 and H8S/2624 in
figure 3.3.
The address space is 16 Mbytes in modes 4 to 7 (advanced modes).
The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus
Controller.
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External address
space On-chip ROM On-chip ROM
Internal I/O registers
Reserved area
On-chip RAM*
On-chip RAM*
External area
External area
Internal I/O registers
Internal I/O registers
Reserved area
On-chip RAM*
Internal I/O registers
On-chip RAM
On-chip RAM*
External area
External area
On-chip RAM
Internal I/O registers Internal I/O registers
External address
space
H'000000 H'000000 H'000000
H'FFB000
H'FFC000
H'FFEFC0
H'FFFFC0
H'FFFFFF
H'FFFF40
H'FFFF60
H'FFF800
H'FFB000
H'040000
H'FFC000
H'FFEFC0
H'FFFFC0
H'FFFFFF
H'FFFF40
H'FFFF60
H'FFF800
H'FFC000
H'FFEFBF
H'FFFFC0
H'FFFFFF
H'FFFF3F
H'FFFF60
H'FFF800
H'03FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
Mode 7
(advanced single-chip mode)
Figure 3.1 Memory Map in Each Operating Mode in the H8S/2623 and H8S/2626
Section 3 MCU Operating Modes
Rev. 5.00 Jan 10, 2006 page 82 of 1042
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External address
space
On-chip ROM On-chip ROM
Internal I/O registers
Reserved area
On-chip RAM*
On-chip RAM*
External area
External area
Internal I/O registers
Internal I/O registers
Reserved area
Reserved area
On-chip RAM*
Internal I/O registers
On-chip RAM
On-chip RAM*
External area
External area
On-chip RAM
Internal I/O registers Internal I/O registers
External address
space
H'000000 H'000000
H'020000
H'000000
H'FFB000
H'FFD000
H'FFEFC0
H'FFFFC0
H'FFFFFF
H'FFFF40
H'FFFF60
H'FFF800
H'FFB000
H'040000
H'FFD000
H'FFEFC0
H'FFFFC0
H'FFFFFF
H'FFFF40
H'FFFF60
H'FFF800
H'FFD000
H'FFEFBF
H'FFFFC0
H'FFFFFF
H'FFFF3F
H'FFFF60
H'FFF800
H'01FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
Mode 7
(advanced single-chip mode)
Figure 3.2 Memory Map in Ea ch Operating Mode in the H8S/2622 and H8S/2625
Section 3 MCU Operating Modes
Rev. 5.00 Jan 10, 2006 page 83 of 1042
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External address
space
On-chip ROM On-chip ROM
Internal I/O registers
Reserved area
On-chip RAM*
On-chip RAM*
External area
External area
Internal I/O registers
Internal I/O registers
Reserved area
Reserved area
On-chip RAM*
Internal I/O registers
On-chip RAM
On-chip RAM*
External area
External area
On-chip RAM
Internal I/O registers Internal I/O registers
External address
space
H'000000 H'000000
H'010000
H'000000
H'FFB000
H'FFE000
H'FFEFC0
H'FFFFC0
H'FFFFFF
H'FFFF40
H'FFFF60
H'FFF800
H'FFB000
H'040000
H'FFE000
H'FFEFC0
H'FFFFC0
H'FFFFFF
H'FFFF40
H'FFFF60
H'FFF800
H'FFE000
H'FFEFBF
H'FFFFC0
H'FFFFFF
H'FFFF3F
H'FFFF60
H'FFF800
H'00FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
Mode 7
(advanced single-chip mode)
Figure 3.3 Memory Map in Each Operating Mode in the H8S/2621 and H8S/2624
Section 3 MCU Operating Modes
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Section 4 Exception Handling
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Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the RES pin, or
when the watchdog timer overflows. The CPU enters the reset
state when the RES pin is low.
Trace*1Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Direct transition Starts when a direction transition occurs as the result of SLEEP
instruct ion exe cution.
Interrupt Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued*2
Low Trap instruction
(TRAPA)*3Started by execution of a trap instructio n (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed afte r execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution stat e.
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4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC), condition code register (CCR), and extended register (EXR) are
pushed onto the stack.
2. The interr upt ma sk bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are
assigned to different exception sources.
Table 4.2 lists the exception sources and their vector addresses.
Exception
sources
Reset
Trace
Interrupts
Trap instruction
Reset
Manual reset*1
External interrupts: NMI, IRQ5 to IRQ0
Internal interrupts: 47 interrupt sources*2 in
on-chip supporting modules
Notes: 1.
2. Not available in the H8S/2626 Group or H8S/2623 Group.
48 interrupt sources in the H8S/2626 Group.
Figure 4.1 Exception Sources
Section 4 Exception Handling
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Table 4.2 Exception Vector Table
Vector Address*1
Exception Source Vector Number Advanced Mode
Reset 0 H'0000 to H'0003
Manual reset*31 H'0004 to H'0007
Reserved 2 H'0008 to H'000B
3 H'000C to H'000F
4 H'0010 to H'0013
Trace 5 H'0014 to H'0017
Direct transitions*4 (H8S/2626 only) 6 H'0018 to H'001B
External interrupt NMI 7 H'001C to H'001F
Trap instruction (4 sources) 8 H'0020 to H'0023
9 H'0024 to H'0027
10 H'0028 to H'002B
11 H'002C to H'002F
Reserved 12 H'0030 to H'0033
13 H'0034 to H'0037
14 H'0038 to H'003B
15 H'003C to H'003F
External interrupt IRQ0 16 H'0040 to H'0043
IRQ1 17 H'0044 to H'0047
IRQ2 18 H'0048 to H'004B
IRQ3 19 H'004C to H'004F
IRQ4 20 H'0050 to H'0053
IRQ5 21 H'0054 to H'0057
Reserved 22 H'0058 to H'005B
23 H'005C to H'005F
Internal interrupt*224
127
H'0060 to H'0063
H'01FC to H'01 FF
Notes: 1. Lower 16 bits of the address.
2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling
Vector Table.
3. Not available in the H8S/2626 Group or H8S/2623 Group.
4. See section 21B.11, Direct Transitions, for details.
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4.2 Reset
4.2.1 Overview
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and the H8S/2626 Group or H8S/2623 Group
enters the reset state. A reset initializes the internal state of the CPU and th e registers of on-c hip
supporting modules. Immediately after a reset, interrupt control mode 0 is set.
Reset exception handling begins when the RES pin changes from low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer.
4.2.2 Reset Sequence
The chip enters the reset state when the RES pin goes low.
To ensure th at the chip is r eset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 20 states.
When the RES pin goes high after being held lo w for the necessary time, the chip starts re set
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, the T bit is clear ed to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.2 and 4.3 show examples of the reset sequence.
Section 4 Exception Handling
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Address bus
Vector fetch Internal
processing Prefetch of first
program instruction
(1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002)
(2) (4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2) (4))
(6) First program instruction
φ
RES
(1) (5)
High
(2) (4)
(3)
(6)
RD
HWR, LWR
D15 to D0
*
Note: * Three program wait states are inserted.
**
Figure 4.2 Reset Sequence (Modes 4 and 5)
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φ
RES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
Vector fetch
(1) (3) (5)
High
Internal
processing
Prefetch of
first program
instruction
(2) (4)
(1) (3) Reset exception handling vector address (when reset, (1) = H'000000,
(3) = H'000002)
(2) (4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2) (4))
(6) First program instruction
(6)
Figure 4.3 Reset Sequence (Modes 6 and 7)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC an d
CCR will not be saved correctly , leadin g to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state en ds, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.2.4 St ate of On-Chip Sup porting Modules after Reset Relea se
After reset release, MSTPC RA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, re sp ectively,
and all modules except the DTC enter module stop mode. Consequently, on-chip supporting
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module registers cannot be read or written to. Register reading and writing is enabled when
module stop mode is exited.
4.3 Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction.
Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.
Table 4.3 shows the state of CCR and EXR after execution of trace exception handling.
Interrupts are accepted even within the trace exception handling routine.
The T bit saved on th e stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instr uction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Table 4.3 Status of CCR and EXR after Trace Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 Trace exception handling cannot be used.
21——0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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4.4 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and
internal sources (H8S/2626 Group: 48, H8S/2623 Group: 47) in the on-chip supporting modules.
Figure 4.4 classifies the interrupt sources and the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller
(DTC), PC break controller (PBC), controller area network (HCAN), and A/D converter. Each
interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts ar e controlled by the interrupt contro ller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
eight prio r ity/mask levels to enab le multip lexed interrupt contr ol.
For details of interrupts, see section 5, Interrupt Contr oller.
Interrupts
External
interrupts
Internal
interrupts
NMI (1)
IRQ5 to IRQ0 (6)
WDT* H8S/2626 Group (2), H8S/2623 Group (1)
TPU (26)
SCI (12)
DTC (1)
PBC (1)
HCAN (5)
A/D converter (1)
Numbers in parentheses are the numbers of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
request at each counter overflow.
Notes:
Figure 4.4 Interrupt Sources and Number of Interrupts
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4.5 Trap Instruction
Trap instruction exception handling starts when a TRAPA instructio n is executed. Trap instru ction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 sho w s the status of CCR and EXR af ter execution of trap instruction exception handling.
Table 4.4 Sta tus of CCR and EXR after Trap Instruction Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
01———
21—— 0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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4.6 Stack Status after Exception Handling
Figures 4.5 (1 ) and 4.5 (2) show the stack after completion of trap instruction exception handling
and interrupt exception handling.
SP
SP CCR
CCR*
PC
(16 bits)
CCR
CCR*
PC
(16 bits)
Reserved*
EXR
(a) Interrupt control mode 0 (b) Interrupt control mode 2
Note: * Ignored on return.
Figure 4.5 (1) Stack Status after Exception Handling
(Normal Modes: Not Available in the H8S/2626 Group or H8S/2623 Group)
SP
SP CCR
PC
(24 bits)
CCR
PC
(24 bits)
Reserved*
EXR
(a) Interrupt control mode 0 (b) Interrupt control mode 2
Note: * Ignored on return.
Figure 4.5 (2) Stack Status after Exception Handling
(Advanced Modes)
Section 4 Exception Handling
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4.7 Notes on Use of the Stack
When accessing word data or longword data, the H8S/2626 Group or H8S/2623 Group assumes
that the lowest address bit is 0. The stack should always be accessed by word transfer instruction
or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be
kept even. Use the following instructions to save registers:
PUSH.W Rn (or MOV.W Rn, @-SP)
PUSH.L ERn (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what
happens when the SP value is odd.
SP
Legend:
Note: This diagram illustrates an example in which the interrupt control mode
is 0, in advanced mode.
SP
SP
CCR
PC
R1L
PC
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
MOV.B R1L, @–ER7
SP set to H'FFFEFF
TRAP instruction executed
Data saved above SP Contents of CCR lost
CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Figure 4.6 Operation when SP Value is Odd
Section 4 Exception Handling
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Section 5 Interrupt Controller
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Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The H8S/2626 Group and H8S/2623 Group control interrupts by means of an interrupt controller.
The interrupt controller has the following features:
• Two interrupt control modes
Any of two interr upt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR).
• Priorities settable with IPR
An interru pt priority register ( I PR) is provided for setting interrupt prio r ities. Eight priority
levels can be set for each module for all interrupts except NMI.
NMI is assigned the highest priority level of 8, and can be accepted at all times.
• Independent vect or address es
All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be id entified in the interrupt handling routine.
• Seven external interrupts
NMI is the highest-p riority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI.
Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5
to IRQ0.
• DTC control
DTC activation is performed by means of interrupts.
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5.1.2 Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
SYSCR
NMI input
IRQ input
Internal interrupt
request
SWDTEND to
SLE0
INTM1 INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
IPR
Interrupt controller
Priority
determination
Interrupt
request
Vector
number
I
I2 to I0 CCR
EXR
CPU
ISCR
IER
ISR
IPR
SYSCR
: IRQ sense control register
: IRQ enable register
: IRQ status register
: Interrupt priority register
: System control register
Legend:
Figure 5.1 Block Diagram of Interrupt Controller
Section 5 Interrupt Controller
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5.1.3 Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Interrupt Controller Pins
Name Symbol I/O Function
Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or
falling edge can be selected
External interrupt
requests 5 to 0 IRQ5 to IRQ0 Input Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected
5.1.4 Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2 Interrupt Controller Registers
Name Abbreviation R/W Initial Value Address*1
System control register SYSCR R/W H'01 H'FDE5
IRQ sense control register H ISCRH R/W H'00 H'FE12
IRQ sense control register L ISCRL R/W H'00 H'FE13
IRQ enable register IER R/W H'00 H'FE14
IRQ status register ISR R/(W)*2H'00 H'FE15
Interrupt priority register A IPRA R/W H'77 H'FEC0
Interrupt priority register B IPRB R/W H'77 H'FEC1
Interrupt priority register C IPRC R/W H'77 H'FEC2
Interrupt priority register D IPRD R/W H'77 H'FEC3
Interrupt priority register E IPRE R/W H'77 H'FEC4
Interrupt priority register F IPRF R/W H'77 H'FEC5
Interrupt priority register G IPRG R/W H'77 H'FEC6
Interrupt priority register H IPRH R/W H'77 H'FEC7
Interrupt priority register I IPRI R/W H'77 H'FEC8
Interrupt priority register J IPRJ R/W H'77 H'FEC9
Interrupt priority register K IPRK R/W H'77 H'FECA
Interrupt priority register M IPRM R/W H'77 H'FECC
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
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5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
—
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
SYSCR is an 8-bit readable/writab le r egister that selects the inter r upt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control
Register (SYSCR).
SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrup t contr ol modes for the interrupt controller.
Bit 5 Bit 4 Interrupt
INTM1 INTM0 Control Mode Description
0 0 0 Interrupts are contr oll ed by I bit (Initi al val ue
)
1 — Setting prohibited
1 0 2 Interrupts are contr olled by bits I2 to I0, and IPR
1 — Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG Description
0 Interrupt request generated at falling edge of NMI input (Initial value
)
1 Interrupt request generated at rising edge of NMI input
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5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)
7
—
0
—
6
IPR6
1
R/W
5
IPR5
1
R/W
4
IPR4
1
R/W
3
—
0
—
0
IPR0
1
R/W
2
IPR2
1
R/W
1
IPR1
1
R/W
Bit
Initial value
R/W
:
:
:
The IPR registers are twelve 8-bit readable/writable reg ister s that set priorities ( levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a r e set and in hardware standby mode.
They are not initialized in software standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
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Table 5.3 Correspondence between Interrupt Sources and IPR Settings
Bits
Register 6 to 4 2 to 0
IPRA IRQ0 IRQ1
IPRB IRQ2
IRQ3 IRQ4
IRQ5
IPRC —*1DTC
IPRD WDT0 —*1
IPRE PC break A/D converter, WDT1*2
IPRF TPU channel 0 TPU channel 1
IPRG TPU channel 2 TPU channel 3
IPRH TPU channel 4 TPU channel 5
IPRI —*1—*1
IPRJ —*1SCI channel 0
IPRK SCI channel 1 SCI channel 2
IPRM HCAN —*1
Notes: 1. Reserved bits. These bits are always read as 1 and cannot be modified.
2. Valid only in the H8S/2626 Group.
As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range
from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding
interrup t. The lo west p riority level, level 0, is assigned by setting H'0, and the highest priority
level, level 7, by settin g H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority
levels set in the IPR r egisters is selected. This interrup t lev e l is then compared with the interrupt
mask level set b y the interrupt m a sk bits ( I2 to I0) in the extend r egister (EXR) in the CPU, an d if
the prior ity level of the interrupt is hig her than the set mask level, an interrupt request is issued to
the CPU.
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5.2.3 IRQ Enable Register (IER)
7
—
0
R/W
6
—
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
Bit
Initial value
R/W
:
:
:
IER is an 8-bit readable/writable reg ister th at controls enabling and disabling of interrupt requests
IRQ5 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ5 to
IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0 IRQn interrupts disabled (Initial value
)
1 IRQn interrupts enabled
(n = 5 to 0)
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5.2.4 IRQ Sense Control Reg isters H a nd L (ISCRH, ISCRL)
ISCRH
15
—
0
R/W
14
—
0
R/W
13
—
0
R/W
12
—
0
R/W
11
IRQ5SCB
0
R/W
8
IRQ4SCA
0
R/W
10
IRQ5SCA
0
R/W
9
IRQ4SCB
0
R/W
Bit
Initial value
R/W
:
:
:
ISCRL
7
IRQ3SCB
0
R/W
6
IRQ3SCA
0
R/W
5
IRQ2SCB
0
R/W
4
IRQ2SCA
0
R/W
3
IRQ1SCB
0
R/W
0
IRQ0SCA
0
R/W
2
IRQ1SCA
0
R/W
1
IRQ0SCB
0
R/W
Bit
Initial value
R/W
:
:
:
The ISCR registers ar e 16-bit read able/writable registers that select r isin g edge, falling ed ge, or
both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0.
The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 15 to 12—Reserved: Only 0 should be written to these bits.
Bits 11 to 0: IRQ7 Sense Control A and B (IRQ5SCA, IRQ5SCB) to IRQ0 Sense Control A and
B (IRQ0SCA, IRQ0SCB)
Bits 11 to 0
IRQ5SCB to
IRQ0SCB IRQ5SCA to
IRQ0SCA Description
0 0 Interrupt request generated at IRQ5 to IRQ0 input low level
(Initial value)
1 Interrupt request generated at falling edge of IRQ5 to IRQ0 input
1 0 Interrupt request generated at rising edge of IRQ5 to IRQ0 input
1 Interrupt request generated at both falling and rising edges of
IRQ5 to IRQ0 input
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5.2.5 IRQ Status Register (ISR)
7
—
0
R/(W)*
6
—
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
0
IRQ0F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
Bit
Initial value
R/W
Note: * Only 0 can be written, to clear the flag.
:
:
:
ISR is an 8-bit r eadable/writable register that in dicates the status of IRQ5 to I RQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in h a rdware stan dby mode.
They are not initialized in software standby mode.
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bits 5 to 0—IRQ5 to IRQ0 flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
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Bit n
IRQnF Description
0 [Clearing conditions] (Initial value)
• Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
• When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
• When IRQn interrupt exception handling is executed when falling, rising, or both-
edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
• When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
1 [Setting conditions]
• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
• When a falling edge occurs in IRQn input when falli ng edge dete cti on is set
(IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1) (n = 5 to 0)
5.3 Interrupt Sources
Interrupt sou r ces comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts (48
sources: H8S/2626 Group, 47 sources: H8S/2623 Group).
5.3.1 External Interrupts
There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to
restore the H8S/2626 Group or H8S/2623 Group chip from software standby mode.
NMI Interrupt : NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. Th e NMI E G
bit in SYSCR can be used to select wheth er an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
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IRQ5 to IRQ0 Inte r rupts: Inter r upts I RQ5 to IRQ0 are requested by an input signal at pins IRQ5
to IRQ0. Interrupts IRQ5 to IRQ0 have the following features:
• Using ISCR, it is p ossible to select whether an interrupt is generated by a low level, fallin g
edge, rising edge, or both edges, at pins IRQ5 to IRQ0.
• Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER.
• The interrupt pr iority level can be set with IPR.
• The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5.2.
IRQn
interrupt
request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge/level
detection circuit
IRQnSCA, IRQnSCB
IRQn
input
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0
Figure 5.3 shows the timing of setting IRQnF.
φ
IRQn
input pin
IRQnF
Figure 5.3 Timing of Setting IRQnF
The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16.
Section 5 Interrupt Controller
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Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
5.3.2 Internal Interrupts
There are 48 sources for internal interrupts from on-chip supporting modules in the H8S/2626
Group, and 47 in the H8S/2623 Group.
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular in ter rupt source, an interrupt reque st is issued to the interrupt controller.
• The interrupt pr iority level can be set by means o f IPR.
• The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the
DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits ar e not
affected.
5.3.3 Interrupt Ex ception Handling Vector Table
Table 5.4 shows in terrupt exception ha ndling sources, vector add r esses, and interrupt prio rities.
For default priorities, the lower the vector number, the high e r the prio r ity.
Priorities among modules can be set by means of the IPR. The situation when two or more
modules are set to the same priority, and priorities within a module, are fixed as shown in
table 5.4.
Section 5 Interrupt Controller
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector
Address*
Interrupt Source
Origin of
Interrupt
Source Vector
Number Advanced
Mode IPR Priority
NMI 7 H'001C High
IRQ0
External
pin 16 H'0040 IPRA6 to 4
IRQ1 17 H'0044 IPRA2 to 0
IRQ2
IRQ3 18
19 H'0048
H'004C IPRB6 to 4
IRQ4
IRQ5 20
21 H'0050
H'0054 IPRB2 to 0
Reserved —22
23 H'0058
H'005C IPRC6 to 4
SWDTEND (software activation
interrupt end) DTC 24 H'0060 IPRC2 to 0
WOVI0 (interval timer) Watchdog
timer 0 25 H'0064 IPRD6 to 4
Reserved —26 H'0068 IPRD2 to 0
PC break PC break 27 H'006C IPRE6 to 4
ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to 0
WOVI1 (interval timer)
(H8S/2626 Group only) Watchdog
timer 1 29 H'0074
Reserved —30
31 H'0078
H'007C
TGI0A (TGR0A input capture/
compare match)
TGI0B (TGR0B input capture/
compare match)
TGI0C (TGR0C input capture/
compare match)
TGI0D (TGR0D input capture/
compare match)
TCI0V (overflow 0)
TPU
channel 0 32
33
34
35
36
H'0080
H'0084
H'0088
H'008C
H'0090
IPRF6 to 4
Reserved —37
38
39
H'0094
H'0098
H'009C Low
Section 5 Interrupt Controller
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Vector
Address*
Interrupt Source
Origin of
Interrupt
Source Vector
Number Advanced
Mode IPR Priority
TGI1A (TGR1A input capture/
compare match)
TGI1B (TGR1B input capture/
compare match)
TCI1V (overflow 1)
TCI1U (underflow 1)
TPU
channel 1 40
41
42
43
H'00A0
H'00A4
H'00A8
H'00AC
IPRF2 to 0 High
TGI2A (TGR2A input capture/
compare match)
TGI2B (TGR2B input capture/
compare match)
TCI2V (overflow 2)
TCI2U (underflow 2)
TPU
channel 2 44
45
46
47
H'00B0
H'00B4
H'00B8
H'00BC
IPRG6 to 4
TGI3A (TGR3A input capture/
compare match)
TGI3B (TGR3B input capture/
compare match)
TGI3C (TGR3C input capture/
compare match)
TGI3D (TGR3D input capture/
compare match)
TCI3V (overflow 3)
TPU
channel 3 48
49
50
51
52
H'00C0
H'00C4
H'00C8
H'00CC
H'00D0
IPRG2 to 0
Reserved —53
54
55
H'00D4
H'00D8
H'00DC
TGI4A (TGR4A input capture/
compare match)
TGI4B (TGR4B input capture/
compare match)
TCI4V (overflow 4)
TCI4U (underflow 4)
TPU
channel 4 56
57
58
59
H'00E0
H'00E4
H'00E8
H'00EC
IPRH6 to 4
Low
Section 5 Interrupt Controller
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Vector
Address*
Interrupt Source
Origin of
Interrupt
Source Vector
Number Advanced
Mode IPR Priority
TGI5A (TGR5A input capture/
compare match)
TGI5B (TGR5B input capture/
compare match)
TCI5V (overflow 5)
TCI5U (underflow 5)
TPU
channel 5 60
61
62
63
H'00F0
H'00F4
H'00F8
H'00FC
IPRH2 to 0 High
Reserved —64
65
66
H'0100
H'0104
H'0108
IPRI6 to 4
67 H'010C
68
69
70
H'0110
H'0114
H'0118
IPRI2 to 0
71 H'011C
72
73
74
75
H'0120
H'0124
H'0128
H'012C
IPRJ6 to 4
76
77
78
79
H'0130
H'0134
H'0138
H'013C
ERI0 (receive error 0)
RXI0 (reception com ple ted 0)
TXI0 (transmit data empty 0)
TEI0 (transmission end 0)
SCI
channel 0 80
81
82
83
H'0140
H'0144
H'0148
H'014C
IPRJ2 to 0
ERI1 (receive error 1)
RXI1 (reception com ple ted 1)
TXI1 (transmit data empty 1)
TEI1 (transmission end 1)
SCI
channel 1 84
85
86
87
H'0150
H'0154
H'0158
H'015C
IPRK6 to 4
ERI2 (receive error 2)
RXI2 (reception com ple ted 2)
TXI2 (transmit data empty 2)
TEI2 (transmission end 2)
SCI
channel 2 88
89
90
91
H'0160
H'0164
H'0168
H'016C
IPRK2 to 0
Low
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Vector
Address*
Interrupt Source
Origin of
Interrupt
Source Vector
Number Advanced
Mode IPR Priority
ERS0
OVR0
RM0
RM1
HCAN 104
105
106
107
H'01A0
H'01A4
H'01A8
H'01AC
IPRM6 to 4 High
SLE0 108 H'01B0 IPRM2 to 0 Low
Note: *Lower 16 bits of the start address.
5.4 Interrupt Operation
5.4.1 Interrupt Control Modes and Interrupt Operation
Interrupt operations in the H8S/2626 Group and H8S/2623 Group differ depending on the
interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module in terrupts, an enable bit is provided for
each interrupt. Clearing an en able bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 ar e controlled by the interrupt controller.
Table 5.5 shows the interrup t control modes.
The interrupt con troller performs interrupt contro l accord ing to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and th e m a sking state indicated
by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.
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Table 5.5 Interrupt Control Modes
SYSCR
Interrupt
Control Mode INTM1 INTM0 Priority Setting
Registers Interrupt
Mask Bits Description
000—I Interrupt mask control is
performed by the I bit.
— 1 ——Setting prohibited
2 1 0 IPR I2 to I0 8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set
with IPR.
— 1 ——Setting prohibited
Figure 5.4 shows a block diagram of the priority decision circuit.
Interrupt
acceptance
control
8-level
mask control
Default priority
determination Vector number
Interrupt control mode 2
IPR
Interrupt source
I2 to I0
Interrupt
control
mode 0 I
Figure 5.4 Block Diagram of Interrupt Control Operation
Section 5 Interrupt Controller
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(1) Interrupt Acceptance Control
In interrup t control mode 0 , interrupt acceptance is con tr olled by the I bit in CCR.
Table 5.6 shows the interrupts selected in each interrupt control mode.
Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Mask Bits
Interrupt Control Mode I Selected Interrupts
0 0 All interrupts
1 NMI interrupts
2*All interrupts
*: Don't care
(2) 8-Level Control
In interrupt control mode 2, 8-level mask lev e l determination is per for med for the selected
interrupts in interrupt acceptance control according to the interrupt priority level (IPR).
The interrupt sou r ce selected is the interrupt with the highest priority level, and whose pr iority
level set in IPR is higher than the mask level.
Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2)
Interrupt Control Mode Selected Interrupts
0 All interrupts
2 Highest-pri orit y-le ve l (IPR) interrupt who se prior ity le vel is great er
than the mask level (IPR > I2 to I0).
Section 5 Interrupt Controller
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(3) Default Priority Determination
When an inter r upt is selected by 8-level con trol, its p r iority is determined and a vector number is
generated.
If the same value is set for IPR, acceptance of multip le interrupts is enabled, and so only the
interrupt source with the highest priority according to the p reset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.8 shows operations and control signal functions in each interrupt control mode.
Table 5.8 Operations and Control Sig nal Functions in Each Interrupt Control Mode
Setting Interrupt
Acceptance Control 8-Level Control
Interrupt
Control
Mode INTM1 INTM0 I I2 to I0 IPR
Default Priori ty
Determination T
(Trace)
000 IM X ——
*2—
210X—*1IM PR T
Legend:
: Interrupt operation control performe d
X : No operation. (All interrupts enabled)
IM : Used as interrupt mask bit
PR: Sets priority.
—: Not used.
Notes: 1. Set to 1 when interrupt is accepted.
2. Keep the initial setting.
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5.4.2 Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1.
Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt r equ est is sent to the interrupt controller.
[2] T he I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
[5] The PC and CCR ar e saved to the stack area by interrupt exception handling. Th e PC saved on
the stack shows the address of the first in struction to be executed after returning from th e
interrup t handling routine.
[6] Next, the I bit in CCR is set to 1. This ma sks all interrupts except NMI.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Section 5 Interrupt Controller
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Program execution status
Interrupt generated?
NMI
IRQ0
IRQ1
SLE0
I = 0
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
No
Yes
Yes
No
Hold pending
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
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5.4.3 Interrupt Control Mode 2
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by comparin g th e interrupt mask lev e l set by bits I2 to I0 of EXR in th e CPU with IPR.
Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt r equ est is sent to the interrupt controller.
[2] When interr upt requests are sent to the interrupt controller, the interrupt with th e highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
[3] Next, the priority of the selected interrupt request is co mpared with the interrupt m a sk level set
in EXR. An interr upt request with a priority no higher than the mask leve l set at th at time is
held pending, and only an interrupt request with a priority higher than the in ter rup t m ask level
is accepted.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
[5] T he PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interru pt handling routine.
[6] The T bit in EXR is clear ed to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
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Yes
Program execution status
Interrupt generated?
NMI
Level 6 interrupt?
Mask level 5
or below?
Level 7 interrupt?
Mask level 6
or below?
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Hold pending
Level 1 interrupt?
Mask level 0?
Yes
Yes
No Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Contro l Mode 2
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5.4.4 Int errupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip m emor y.
(14)(12)(10)(8)
(6)(4)(2)
(1) (5)
(7) (9) (11) (13)
Interrupt service
routine instruction
prefetch
Internal
operation
Vector fetchStack
Instruction
prefetch Internal
operation
Interrupt
acceptance
Interrupt level determination
Wait for end of instruction
Interrupt
request signal
Internal
address bus
Internal
read signal
Internal
write signal
Internal
data us
φ
(3)
(1)
(2) (4)
(3)
(5)
(7)
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP-2
SP-4
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (vector
address contents)
Interrupt handling routine start address ((13) = (10) (12))
First instruction of interrupt handling routine
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
Figure 5.7 Interrupt Exception Handling
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5.4.5 Interrupt Response Times
The H8S/2626 Group and H8S/2623 Group are capable of fast word transfer to on-chip memory,
and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-
speed processing.
Table 5.9 shows interrupt response times - the interval between generation of an interrupt request
and execution of th e f ir st in str uction in the interrupt handling routine. The execution status
symbols used in table 5.9 are explained in table 5.10.
Table 5.9 Interrupt Response Times
Normal Mode*5Advanced Mode
No. Execution Status INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1
1 Interrupt priority determination*133 33
2 Number of wait states until
executing instruction ends *21 to
(19+2·SI)1 to
(19+2·SI)1 to
(19+2·SI)1 to
(19+2·SI)
3 PC, CCR, EXR st ack save 2·SK3·SK2·SK3·SK
4 Vector fetch SISI2·SI2·SI
5 Instruction fetch*32·SI2·SI2·SI2·SI
6 Internal processing*422 22
Total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
5. Not available in the H8S/2626 Group or H8S/2623 Group.
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Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus 16 Bit Bus
Symbol Internal
Memory 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI1 4 6+2m 2 3+m
Branch address read SJ
Stack manipulation SK
Legend:
m: Number of wait states in an external device ac cess.
5.5 Usage Notes
5.5.1 Contention between Int errupt Generatio n a nd Disabling
When an inter r upt enable bit is cleared to 0 to disab le in ter rupts, the disabling becomes eff ective
after execution of the instruction.
In other word s, when an interrupt enable bit is cleared to 0 by an instr uction such as BCLR or
MOV, if an interrupt is generated during execution of the in struction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will b e ex ecuted on co mpletio n of the instruction. However, if there is an interrupt
request of high e r prio r ity than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower - prio r ity inter rupt will be ignored.
The same also applies when an interrup t source flag is cleared to 0.
Figure 5.8 shows an example in which the TCIEV bit in the TPU’s TIER0 register is cleared to 0.
Section 5 Interrupt Controller
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Internal
address bus
Internal
write signal
φ
TCIEV
TCFV
TCIV
interrupt signal
TIER0 write cycle by CPU TCIV exception handling
TIER0 address
Figure 5.8 Contention between Interrupt Generation and Disabling
The above contention will n ot occur if an enable bit or interrupt source flag is cleared to 0 while
the interru pt is masked.
5.5.2 Instructions that Disable Interrupts
Instructions that disable in terrupts are LDC, ANDC, ORC, and XORC. After any o f these
instruction s is ex ecuted, all interrupts in clu ding NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.5.3 Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the in terrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
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5.5.4 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an in ter rupt request (in c luding NMI) issued during the transfer
is not accepted until the mo v e is completed.
With the EEPMOV.W ins tr uction, if an interr upt r e quest is issued d u ring the transfer, interrup t
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
5.6 DTC Activation by Interrupt
5.6.1 Overview
The DTC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation req uest to DTC
• Selection of a number of the above
For details of interrupt requests that can b e used with to activate the DTC, see section 8 , Data
Transfer Controller (DTC).
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5.6.2 Block Diagram
Figure 5.9 shows a block diagram of the DTC interrupt controller.
Selection
circuit
DTCER
DTVECR
Control logic
Determination of
priority CPU
DTC
DTC activation
request vector
number
Clear signal
CPU interrupt
request vector
number
Select
signal
Interrupt
request
Interrupt source
clear signal
IRQ
interrupt
On-chip
supporting
module
Clear signal
Interrupt controller I, I2 to I0
SWDTE
clear signal
Figure 5.9 Interrupt Control for DTC
5.6.3 Operation
The interrupt controller has three main functions in DTC con trol.
(1) Selection of Interrupt Source
Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means
of the DTCE bit of DTCERA to D TCERG in the DT C.
After a DTC data transf er , the DTCE bit can be cleared to 0 and an interrupt request sen t to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value
is zero, the DTCE bit is clear ed to 0 and an interrupt request is sent to the CPU after the DTC data
transfer.
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(2) Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 8.3.3, DTC Vector Table, for the respective
priorities.
(3) Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC
data transfer is performed first, follo wed by CPU interrupt exception handling.
Table 5.11 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERG in th e DTC, and the DISEL bit of MRB
in the DTC.
Table 5.11 Interrupt Source Selection and Clearing Control
Settings
DTC Interrupt Source Selection/Clearing Control
DTCE DISEL DTC CPU
0*X∆
10 ∆X
1O∆
Legend:
∆: The relevant interrupt is use d. Interru pt sourc e clear ing is perfo rm ed.
(The CPU should clear the source flag in the interrupt handling routine.)
O: The relevant interrupt is used. The interrupt source is not cleared.
X: The relevant bit cannot be used.
*:Don’t care
(4) Notes on Use
SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the
prescribed register.
Section 6 PC Break Controll er (PBC)
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Section 6 PC Break Controller (PBC)
6.1 Overview
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:
instruction fetch, data read, data write, and data read/write.
6.1.1 Features
The PC break controller has the following features:
• Two break channels (A and B)
• The following can be set as break compare conditions:
24 address bits
Bit masking possible
Bus cycle
Instruction fetch
Data access: data read, data write, data read/write
Bus master
Either CPU or CPU/DTC can be selected
• The timing of PC break exception handling after the occurrence of a break condition is as
follows:
Immediately before execution of the instruction fetched at the set address (instruction
fetch)
Immediately after execution of the instruction that accesses data at the set address (data
access)
• Module stop mode can be set
The initial setting is fo r PBC operation to b e halted . Register access is enabled by clearing
module stop mode.
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6.1.2 Block Diagram
Figure 6.1 shows a block diagram of th e PC break controller.
Output control
Mask control
Output control
Match signal
PC break
interrupt
Match signal
Mask control
BARA BCRA
BARB BCRB
Comparator Control
logic
Comparator Control
logic
Internal address
Access
status
Figure 6.1 Block Diagram of PC Break Controller
Section 6 PC Break Controll er (PBC)
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6.1.3 Register Configuration
Table 6.1 shows the PC break controller registers.
Table 6.1 PC Break Controller Registers
Initial Value
Name Abbreviation R/W Reset Manual Reset*3Address*1
Break address register A BARA R/W H'000000 Retained H'FE00
Break address register B BARB R/W H'000000 Retained H'FE04
Break control register A BCRA R/(W)*2H'00 Retained H'FE08
Break control register B BCRB R/(W)*2H'00 Retained H'FE09
Module stop contro l
register C MSTPCRC R/W H'FF Retained H'FDEA
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
3. Not available in the H8S/2626 Group or H8S/2623 Group.
6.2 Register Descriptions
6.2.1 Break Address Register A (BARA)
Bit
Initial value
R/W —
—
31
Unde-
fined —
—
24
Unde-
fined R/W
BAA
23
23
0
R/W
BAA
22
22
0
R/W
BAA
21
21
0
R/W
BAA
20
20
0
R/W
BAA
19
19
0
R/W
BAA
18
18
0
R/W
BAA
17
17
0
R/W
BAA
16
16
0
R/W
0
BAA
7
7
R/W
0
BAA
6
6
R/W
0
BAA
5
5
R/W
0
BAA
4
4
R/W
0
BAA
3
3
R/W
0
BAA
2
2
R/W
0
BAA
1
1
R/W
0
BAA
0
0
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
BARA is a 32-bit readable/writable register that specifies the channel A break address.
BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode.
Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.
Bits 23 to 0—Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC
break address.
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6.2.2 Break Address Register B (BARB)
BARB is the channel B break addr ess register. The bit configuration is the same as for BARA.
6.2.3 Break Control Register A (BCRA)
Bit
Initial value
R/W
Note: * Only 0 can be written, for flag clearing.
R/(W)*
0
CMFA
7
R/W
0
CDA
6
R/W
0
BAMRA2
5
R/W
0
BAMRA1
4
R/W
0
BAMRA0
3
R/W
0
CSELA1
2
R/W
0
CSELA0
1
R/W
0
BIEA
0
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) sp ecif ies bits subject to address comparison maskin g, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set f or ch annel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA Description
0 [Clearing cond iti on]
When 0 is written to CMFA after reading CMFA = 1 (Initial value)
1 [Setting condition]
When a condition set for channel A is satisfied
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break cond ition bus
master.
Bit 6
CDA Description
0 PC break is performed when CPU is bus master (Initial value)
1 PC break is performed when CPU or DTC is bus master
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Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits
specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked.
Bit 5 Bit 4 Bit 3
BAMRA2 BAMRA1 BAMRA0 Description
000All BARA bits are unmasked and included in break conditions
(Initial value)
1 BAA0 (lowest bit) is masked, and not included in break
conditions
1 0 BAA1–0 (lower 2 bits) are masked, and not included in break
conditions
1 BAA2–0 (lower 3 bits) are masked, and not included in break
conditions
1 0 0 BAA3–0 (lower 4 bits) are masked, and not included in break
conditions
1 BAA7–0 (lower 8 bits) are masked, and not included in break
conditions
1 0 BAA11–0 (lower 12 bits) are masked, and not included in break
conditions
1 BAA15–0 (lower 16 bits) are masked, and not included in break
conditions
Bits 2 and 1—Brea k Condition Select A (CSELA1, CSE LA0 ) : These bits select an instruction
fetch, data read, data write, or da ta read/write cy cle as the channel A break condition.
Bit 2 Bit 1
CSELA1 CSELA0 Description
0 0 Instruction fetch is used as break condition (Initial value)
1 Data read cycle is used as break condition
1 0 Data write cycle is used as break condition
1 Data read/write cycle is used as break condition
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Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.
Bit 0
BIEA Description
0 PC break interrupts are disabled (Initial value)
1 PC break interrupts are enabled
6.2.4 Break Control Register B (BCRB)
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.2.5 Module Stop Control Register C (MSTPCRC)
7
MSTPC7
1
R/W
Bit
Initial value
R/W
6
MSTPC6
1
R/W
5
MSTPC5
1
R/W
4
MSTPC4
1
R/W
3
MSTPC3
1
R/W
2
MSTPC2
1
R/W
1
MSTPC1
1
R/W
0
MSTPC0
1
R/W
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus
cycle, and module stop mode is entered. Register read/write accesses are not possible in module
stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode.
MSTPCRC is initialized to H'FF by a power on reset and in hardware standby mode. It is not
initialized in software standby mode.
Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.
Bit 4
MSTPC4 Description
0 PC break controller module stop mode is cleared
1 PC break controller module stop mode is set (Initial value)
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6.3 Operation
The operation flow from break condition setting to PC break interrupt exception handling is
shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch and 6.3.2, PC Break Interrupt
Due to Data Access, taking the example of ch annel A.
6.3.1 PC Break Interrupt Due to Instruction Fetch
(1) Initial setting s
Set the break address in BARA. For a PC break caused by an instruction fetch, set the
address of the first instruction byte as the break address.
Set the break cond itions in BCRA.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.
BCRA bits 2, 1 (CSELA1, 0): Set 00 to specify an instruction fetch as the break condition.
BCRA bit 0 (BIEA): Set to 1 to enable break in terru p ts.
(2) Satisfaction of b reak condition
When the instruction at the set address is fetched, a PC break request is generated
immediately b efore execution of the fetched instr uction, and the condition m a tch flag
(CMFA) is set.
(3) Interrupt handling
After prior ity determination by the interrupt controller, PC break inter r upt exception
handling is started.
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6.3.2 PC Break Interrupt Due to Data Access
(1) Initial setting s
Set the break address in BARA. For a PC break caused by a data access, set the target
ROM, RAM, I/O, or external address space address as the break address. Stack operations
and branch address reads are included in data accesses.
Set the break cond itions in BCRA.
BCRA bit 6 (CDA): Select the bus master.
BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.
BCRA bits 2, 1 (CSELA1, 0): Set 01, 10, or 11 to specify data access as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break in terru p ts.
(2) Satisfaction of b reak condition
After execution of the instruction that performs a data access on the set address, a PC break
request is g enerated and the cond ition match flag (CMFA) is set.
(3) Interrupt handling
After prior ity determination by the interrup t controller, PC break interrupt ex ception
handling is started.
6.3.3 Notes on PC Break Interrupt Handling
(1) The PC break interrupt is shared by channels A and B. The channel from which the request
was issued must be determined by the interrupt handler.
(2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB
after first readin g the f lag while it is set to 1. If the flag is left set to 1 , anoth e r interr upt will be
requested after interrupt handling ends.
(3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has
been transferred to th e CPU by the bus controller.
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6.3.4 Operation in Transitions to Power-Down Modes
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
(1) When the SLEEP instruction causes a transition from high-speed (mediu m-speed) mode to
sleep mode, or from subactive mode to subsleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode, and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)).
(2) When the SLEEP instruction causes a transition from high-speed (mediu m-speed) mode to
subactive mode:
After execution of the SLEEP instruction, a transition is made to subactive mode via direct
transition ex ception handling. After the transition, PC br eak inter r upt h a ndling is executed,
then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (B))
(Supported only in the H8S/2626 Group).
(3) When the SLEEP instruction causes a transition from subactive mode to high-speed (medium-
speed) mode:
After execution of the SLEEP instruction, and following the clock oscillation settling time, a
transition is made to high-speed (medium-speed) mode via direct transition ex ception
handling. After the transition, PC br eak interrupt handling is execu ted, then the instruction at
the address after the SLEEP instruction is executed (figure 6.2 (C)) (Supported only in the
H8S/2626 Group).
(4) When the SLEEP instruction causes a transition to software standby mode or watch mode:
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2
(D)).
Section 6 PC Break Controll er (PBC)
Rev. 5.00 Jan 10, 2006 page 136 of 1042
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SLEEP instruction
execution
High-speed
(medium-speed)
mode
SLEEP instruction
execution
Subactive
mode
System clock
→ subclock
Direct transition
exception handling
PC break exception
handling
Execution of instruction
after sleep instruction
Subclock →
system clock,
oscillation settling time
SLEEP instruction
execution
Transition to
respective mode
Direct transition
exception handling
PC break exception
handling
Execution of instruction
after sleep instruction
PC break exception
handling
Execution of instruction
after sleep instruction
Note: * Supported only in the H8S/2626 Group.
(A)
(B)*(C)*
(D)
SLEEP instruction
execution
Figure 6.2 Operation in Power-Down Mode Transitions
6.3.5 PC Break Operation in Continuous Data Transfer
If a PC break interrupt is generated when the following operations are being performed, exception
handling is executed on completion of the specified transfer.
(1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction:
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
(2) When a PC break interrupt is generated at a DTC transfer address:
PC break exception handling is executed after the DTC has completed the specified number of
data transfer s, or after data for which the DISEL b it is set to 1 has been transferr ed.
Section 6 PC Break Controll er (PBC)
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6.3.6 When Instruction Execution is Delay e d by One State
Caution is required in the followin g cases, as instruction execution is one state later than usual.
(1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a
one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on-
chip ROM or RAM is always delayed by one state.
(2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
RAM space, and that address is used for data access, the instruction that executes the data
access is one state later than in normal operation.
(3) When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, and that address is
used for data access, the instruction will be one state later than in normal operation.
@ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC),
@(d:16,PC), @@aa:8
(4) When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has
#xx,Rn as its addressing mode, and that instruction is located in on -chip ROM or RAM, the
instruction will be one state later than in nor mal operation.
Section 6 PC Break Controll er (PBC)
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6.3.7 Additional Notes
(1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP,
TRAPA, RTE, or RTS instruction:
Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS
instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the
instruction fetch at the next address.
(2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC br eak interrupt
becomes valid two states after the end of the executing instruction. If a PC break interrupt is
set for the in str uction following one of these instructions, since interrupts, includ in g NMI, ar e
disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction
is always executed. For details, see section 5, Interrupt Controller.
(3) When a PC break is set for an instruction fetch at the address following a Bcc instruction:
A PC break interrupt is generated if the instruction at the next address is executed in
accordance with the branch conditio n , but is not generated if the instruction at the next address
is not executed.
(4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc
instruction:
A PC break interrupt is generated if the in struction at the branch destination is executed in
accordance with the branch condition, but is not generated if the instruction at the branch
destination is not executed.
Section 7 Bus Controller
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Section 7 Bus Controller
7.1 Overview
The H8S/2626 Group and H8S/2623 Group have an on-chip bu s controller (BSC) that manages
the external address space divided into eight areas. The bus specifications, such as bus width and
number of access states, can b e set independently for each area, enabling multiple memories to be
connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU and data transfer controller (DTC).
7.1.1 Features
The features of the bus contro ller are listed below.
• Manages external address space in area units
Manages the external space as 8 areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM interface can be set
• Basic bus interface
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Burst ROM interface
Burst ROM interface can be set for area 0
Choice of 1- or 2-state burst access
• Idle cycle insertio n
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted in case of an external write cycle immediately after an
external read cycle
• Write buffer functions
External write cycle and internal access can be executed in parallel
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC
• Other features
External bus release function
Section 7 Bus Controller
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7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the bus controller.
Area decoder
Bus
controller
ABWCR
ASTCR
BCRH
BCRL
Internal
address bus
External bus control signals
Legend:
ABWCR: Bus width control register
ASTCR: Access state control register
BCRH: Bus control register H
BCRL: Bus control register L
WCRH: Wait control register H
WCRL: Wait control register L
BREQ
BACK
BREQO
Internal control
signals
Wait
controller WCRH
WCRL
Bus mode signal
Bus arbiter
CPU bus request signal
DTC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
WAIT
Internal data bus
Figure 7.1 Block Diagram of Bus Controller
Section 7 Bus Controller
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7.1.3 Pin Configuration
Table 7.1 summarizes the pins of the bus contro ller.
Table 7.1 Bus Controller Pins
Name Symbol I/O Function
Address strobe AS Output Strobe signal indicating that address output on address
bus is enabled .
Read RD Output Strobe signal indicatin g that extern al spa ce is bein g
read.
High write HWR Output Strobe signal ind icatin g that extern al spa ce is to be
written, and upper half (D15 to D8) of data bus is
enabled.
Low write LWR Output Strobe signal indicating that extern al spa ce is to be
written, and lower half (D7 to D0) of data bus is
enabled.
Wait WAIT Input Wait request signal when accessing external 3-state
access space.
Bus request BREQ Input Request signal that releases bus to external device.
Bus request
acknowledge BACK Output Acknowledge signal indicating that bus has been
released.
Bus request
output BREQO Output External bus request signal used when internal bus
master accesses external space when external bus is
released.
Section 7 Bus Controller
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7.1.4 Register Configuration
Table 7.2 summarizes the registers of the bus controller.
Table 7.2 Bus Controller Registers
Initial Value
Name Abbreviation R/W Reset Manual Reset*3Address*1
Bus width control register ABWCR R/W H'FF/H'00*2Retained H'FED0
Access state control register ASTCR R/W H'FF Retained H'FED1
Wait control register H WCRH R/W H'FF Retained H'FED2
Wait control regi ster L WCRL R/W H'FF Retained H'FED3
Bus control register H BCRH R/W H'D0 Retained H'FED4
Bus control register L BCRL R/W H'08 Retained H'FED5
Pin function control register PFCR R/W H'0D/H'00 Retained H'FDEB
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode.
3. Not available in the H8S/2623 Group.
Section 7 Bus Controller
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7.2 Register Descriptions
7.2.1 Bus Width Contro l Register (ABWCR)
7
ABW7
1
R/W
0
R/W
6
ABW6
1
R/W
0
R/W
5
ABW5
1
R/W
0
R/W
4
ABW4
1
R/W
0
R/W
3
ABW3
1
R/W
0
R/W
0
ABW0
1
R/W
0
R/W
2
ABW2
1
R/W
0
R/W
1
ABW1
1
R/W
0
R/W
Bit :
Initial value :
Modes 5 to 7
Mode 4
:R/W
Initial value :
:R/W
ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or
16-bit access.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7, and to
H'00 in mode 4. It is not initialized in software standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the
corresponding area is to be designated for 8-bit access or 16-bit access.
Bit n
ABWn Description
0 Area n is designated for 16-bit access
1 Area n is designated for 8-bit access
(n = 7 to 0)
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7.2.2 Access State Control Register (ASTCR)
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
0
AST0
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
Bit
Initial value
R/W
:
:
:
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access
space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is to be designated as a 2-state access space or a 3-state access space.
Wait state insertion is enabled or disabled at the same time.
Bit n
ASTn Description
0 Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
1 Area n is designated for 3-state access (Initial value
)
Wait state insertion in area n external space is enabled
(n = 7 to 0)
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7.2.3 Wait Control Reg isters H a nd L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
Program waits are not inserted in the case of on-chip memory or internal I/O registers.
WCRH and WC RL ar e initialized to H'FF by a r e set and in hardware stan dby mode. They are not
initialized in software standby mode.
(1) WCRH
7
W71
1
R/W
6
W70
1
R/W
5
W61
1
R/W
4
W60
1
R/W
3
W51
1
R/W
0
W40
1
R/W
2
W50
1
R/W
1
W41
1
R/W
Bit
Initial value
R/W
:
:
:
Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of
program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set
to 1.
Bit 7 Bit 6
W71 W70 Description
0 0 Program wait not inserted when external space area 7 is accessed
1 1 program wait state inserted when external space area 7 is accessed
1 0 2 program wait states inserted when external space area 7 is accessed
1 3 program wait states inserted when external space area 7 is accessed
(Initial value)
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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of
program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set
to 1.
Bit 5 Bit 4
W61 W60 Description
0 0 Program wait not inserted when external space area 6 is accessed
1 1 program wait state inserted when external space area 6 is accessed
1 0 2 program wait states inserted when external space area 6 is accessed
1 3 program wait states inserted when external space area 6 is accessed
(Initial value)
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of
program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set
to 1.
Bit 3 Bit 2
W51 W50 Description
0 0 Program wait not inserted when external space area 5 is accessed
1 1 program wait state inserted when external space area 5 is accessed
1 0 2 program wait states inserted when external space area 5 is accessed
1 3 program wait states inserted when external space area 5 is accessed
(Initial value)
Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of
program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set
to 1.
Bit 1 Bit 0
W41 W40 Description
0 0 Program wait not inserted when external space area 4 is accessed
1 1 program wait state inserted when external space area 4 is accessed
1 0 2 program wait states inserted when external space area 4 is accessed
1 3 program wait states inserted when external space area 4 is accessed
(Initial value)
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(2) WCRL
7
W31
1
R/W
6
W30
1
R/W
5
W21
1
R/W
4
W20
1
R/W
3
W11
1
R/W
0
W00
1
R/W
2
W10
1
R/W
1
W01
1
R/W
Bit
Initial value
R/W
:
:
:
Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of
program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set
to 1.
Bit 7 Bit 6
W31 W30 Description
0 0 Program wait not inserted when external space area 3 is accessed
1 1 program wait state inserted when external space area 3 is accessed
1 0 2 program wait states inserted when external space area 3 is accessed
1 3 program wait states inserted when external space area 3 is accessed
(Initial value)
Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of
program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set
to 1.
Bit 5 Bit 4
W21 W20 Description
0 0 Program wait not inserted when external space area 2 is accessed
1 1 program wait state inserted when external space area 2 is accessed
1 0 2 program wait states inserted when external space area 2 is accessed
1 3 program wait states inserted when external space area 2 is accessed
(Initial value)
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3 Bit 2
W11 W10 Description
0 0 Program wait not inserted when external space area 1 is accessed
1 1 program wait state inserted when external space area 1 is accessed
1 0 2 program wait states inserted when external space area 1 is accessed
1 3 program wait states inserted when external space area 1 is accessed
(Initial value)
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1 Bit 0
W01 W00 Description
0 0 Program wait not inserted when external space area 0 is accessed
1 1 program wait state inserted when external space area 0 is accessed
1 0 2 program wait states inserted when external space area 0 is accessed
1 3 program wait states inserted when external space area 0 is accessed
(Initial value)
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7.2.4 Bus Control Register H (BCRH)
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
—
0
R/W
2
—
0
R/W
1
—
0
R/W
Bit
Initial value
R/W
:
:
:
BCRH is an 8-bit readable/writab le r egister that selects enablin g or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a r e set and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1 Description
0 Idle cycle not inserted in case of successive external read cycles in different areas
1 Idle cycle inserted in case of successive external read cycles in different areas
(Initial value
)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0 Description
0 Idle cycle not inserted in case of successive external read and external write cycles
1 Idle cycle inserted in case of successive external read and external write cycles
(Initial value
)
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Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface.
Bit 5
BRSTRM Description
0 Area 0 is basic bus interface (Initial value
)
1 Area 0 is burst ROM interface
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1 Description
0 Burst cy cle com pri ses 1 state
1 Burst cycle com p ri se s 2 stat es (Initial val ue
)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0 Description
0 Max. 4 words in burst access (Initial value
)
1 Max. 8 words in burst access
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
Section 7 Bus Controller
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7.2.5 Bus Control Reg ister L (BCRL)
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
—
0
—
4
—
0
R/W
3
—
1
R/W
0
WAITE
0
R/W
2
—
0
R/W
1
WDBE
0
R/W
Bit
Initial value
R/W
:
:
:
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'08 by a reset an d in hardware standby mode. I t is not in itialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE Description
0 External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O
ports. (Initial value
)
1 External bus release is enabled.
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE Description
0BREQO output disabled. BREQO can be used as I/O port. (Initial value)
1BREQO output enabled.
Bit 5—Reserved: This bit cannot be modified and is always read as 0.
Bit 4—Reserved: Only 0 should be written to this bit.
Bit 3—Reserved: Only 1 should be written to this bit.
Bit 2—Reserved: Only 0 should be written to this bit.
Section 7 Bus Controller
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Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is
used for an external write cycle.
Bit 1
WDBE Description
0 Write data buffer function not used (Initial value)
1 Write data buffer function used
Bit 0—WAI T Pi n Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE Description
0 Wait input by WAIT pin disabl ed. WAIT pin can be used as I/O port. (Initial value
)
1 Wait input by WAIT pin enabled
7.2.6 Pin Function Control Register (PFCR)
7
—
0
R/W
6
—
0
R/W
5
BUZZE
0
R/W
4
—
0
R/W
3
AE3
1/0
R/W
0
AE0
1/0
R/W
2
AE2
1/0
R/W
1
AE1
0
R/W
Bit
Initial value
R/W
:
:
:
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous
state in software standby mode.
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bit 5—BUZZ Output Enab le (BUZZE): Enables or disables BUZZ output from the PF1 pin. For
details, see section 12.2.4, Pin Function Control Register (PFCR).
Bit 4—Reserved: Only 0 should be written to this bit.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or
disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When
a pin is enabled for address output, the address is output regardless of the corresponding DDR
Section 7 Bus Controller
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setting. When a pin is disabled fo r address output, it becomes an output port when the
corresponding DDR bit is set to 1.
Bit 3 Bit 2 Bit 1 Bit 0
AE3 AE2 AE1 AE0 Description
0000A8–A23 address output disabled (Initial value*)
1 A8 address output enabled; A9–A23 address output disabled
1 0 A8, A9 address output enabled; A10–A23 address output
disabled
1A8–A10 address output enab led ; A11–A23 address output
disabled
100A8–A11 address output enabled ; A12–A23 addr ess output
disabled
1A8–A12 address output enab led ; A13–A23 address output
disabled
10A8–A13 address output enab led ; A14–A23 address output
disabled
1A8–A14 address output enab led ; A15–A23 address output
disabled
1000A8–A15 address output enabled ; A16–A23 addr ess output
disabled
1A8–A16 address output enab led ; A17–A23 address output
disabled
10A8–A17 address output enab led ; A18–A23 address output
disabled
1A8–A18 address output enab led ; A19–A23 address output
disabled
100A8–A19 address output enabled ; A20–A23 addr ess output
disabled
1A8–A20 address output enab led ; A21–A23 address output
disabled (Initial value*)
10A8–A21 address output enabled; A22, A23 address output
disabled
1A8–A23 address output enab led
Note: *In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR
bits to 1.
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7.3 Overview of Bus Control
7.3.1 Area Partitioning
In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to
7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it
controls a 64-kbyte address space comprising part of area 0. Figure 7.2 shows an outline of the
memory map.
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Area 0
(2 Mbytes)
H'000000
H'FFFFFF
(1) (2)
H'0000
H'1FFFFF
H'200000 Area 1
(2 Mbytes)
H'3FFFFF
H'400000 Area 2
(2 Mbytes)
H'5FFFFF
H'600000 Area 3
(2 Mbytes)
H'7FFFFF
H'800000 Area 4
(2 Mbytes)
H'9FFFFF
H'A00000 Area 5
(2 Mbytes)
H'BFFFFF
H'C00000 Area 6
(2 Mbytes)
H'DFFFFF
H'E00000 Area 7
(2 Mbytes)
H'FFFF
Advanced mode Normal mode*
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Figure 7.2 Overview of Area Partitioning
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7.3.2 Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and number of program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
(1) Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an
8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is
selected functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit
access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is
always set.
(2) Number of Access States: Two or three access states can be selected with ASTCR. An area
for which 2-state access is selected functions as a 2-state access space, and an area for which 3-
state access is selected functions as a 3-state access space.
With the burst ROM interface, the number of access states may be determined without regard to
ASTCR.
When 2-state access space is designated, wait insertion is disabled.
(3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of progr am wait states to be inserted automatically is selected with W CRH and WCRL.
From 0 to 3 program wait states can be selected.
Table 7.3 shows the bus specifications for each basic bus interface area.
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Table 7.3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH, WCRL Bus Specifications (Basic Bus Interface)
ABWn ASTn Wn1 Wn0 Bus Width Access States Program Wait
States
00—— 16 2 0
100 3 0
11
10 2
13
10—— 82 0
100 3 0
11
10 2
13
7.3.3 Memory Interfaces
The H8S/2626 Group and H8S/2623 Group memory interfaces comprise a basic bus interface that
allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct
connection of burst ROM. The memory interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, and an area for
which the burst ROM interface is designated functions as burst ROM space.
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7.3.4 Interface Specifications for Each Area
The initial state of each area is b a sic bus interface, 3-state access space. The initial bu s width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (7.4, Basic Bus Interface, and 7.5, Burst ROM
Interface) should be referred to for further details.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space.
Only the basic bus interface can be used for areas 1 to 6.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,
the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
Only the basic bus interface can be used for the area 7.
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7.4 Basic Bus Interface
7.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table
7.3).
7.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 7.3 illustrates data alig nment control for the 8-bit access sp ace. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word transfer instruction is performed as two
byte accesses, and a longword transfer instruction, as four byte accesses.
D15 D8 D7 D0
Upper data bus
Lower data bus
Byte size
Word size 1st bus cycle
2nd bus cycle
Longword size 1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
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16-Bit Access Space: Figure 7.4 illustrates data alig nment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword transfer instruction is executed as two word tr ansfer instructions.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
D15 D8 D7 D0
Upper data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
• Even address
Byte size • Odd address
Lower data bus
Figure 7.4 Access Sizes and Data Alignment Control (16-Bit Access Space)
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7.4.3 Valid Strobes
Table 7.4 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 7.4 Data Buses Used and Valid Strobes
Area Access
Size Read/
Write Address Valid
Strobe Upper Data Bus
(D15 to D8) Lower data bus
(D7 to D0)
Byte Read —RD Valid Invalid
8-bit access
space Write —HWR Hi-Z
Byte Read Even RD Valid Invalid16-bit access
space Odd Invalid Valid
Write Even HWR Valid Hi-Z
Odd LWR Hi-Z Valid
Word Read —RD Valid Valid
Write —HWR, LWR Valid Valid
Notes: Hi-Z: High impedance.
Invalid: Input state; input value is ignored.
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7.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 7.5 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 High impedance
Write
High
Figure 7.5 Bus Timing for 8-Bit 2-State Access Space
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8-Bit 3-State Access Space: Figure 7.6 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states can be inserted.
Bus cycle
T1T2
Address bus
φ
AS
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 High impedance
Write
High
T3
Figure 7.6 Bus Timing for 8-Bit 3-State Access Space
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16-Bit 2-State Access Space: Figures 7.7 to 7.9 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 High impedance
Write
High
Figure 7.7 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
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Bus cycle
T
1
T
2
Address bus
φ
AS
RD
D15 to D8 Invalid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 High impedance
D7 to D0 Valid
Write
High
Figure 7.8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
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Bus cycle
T
1
T
2
Address bus
φ
AS
RD
D15 to D8 Valid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 Valid
Write
Figure 7.9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
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16-Bit 3-State Access Space: Figures 7.10 to 7.12 show bus timings for a 16-bit 3-state access
space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states can be inserted.
Bus cycle
T1T2
Address bus
φ
AS
RD
D15 to D8 Valid
D7 to D0 Invalid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 High impedance
Write
High
T3
Figure 7.10 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
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Bus cycle
T
1
T
2
Address bus
φ
AS
RD
D15 to D8 Invalid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 High impedance
D7 to D0 Valid
Write
High
T
3
Figure 7.11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
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Bus cycle
T
1
T
2
Address bus
φ
AS
RD
D15 to D8 Valid
D7 to D0 Valid
Read
HWR
LWR
D15 to D8 Valid
D7 to D0 Valid
Write
T
3
Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
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7.4.5 Wait Control
When accessing external space, the H8S/2626 Group or H8S/2623 Group can extend the bus cycle
by inserting one or more wait states (Tw). There are two ways of inserting wait states: program
wait insertion and pin wait insertio n using the WAIT pin.
Program Wait Insertion
From 0 to 3 wait states can b e inserted automatically between the T2 state and T3 state on an
individu a l area basis in 3-state access space, accordin g to the settings of WCRH and WCRL.
Pin Wait Insertion
Setting th e WA ITE bit in BCRL to 1 enables wait insertion by me ans of the WAIT pin. Program
wait insertion is first carried o ut according to the settings in WCRH and WCRL. Then , if the
WAIT pin is low at the falling edge of φ in the last T2 or Tw state, a Tw state is inserted. If the
WAIT pin is held low, Tw states are inserted until it goes high.
This is useful when inserting four or more Tw states, or when changing the number of Tw states for
different external devices.
The WAITE bit setting applies to all areas.
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Figure 7.13 shows an example of wait state insertion timing.
By program wait
T
1
Address bus
φ
AS
RD
Data bus Read data
Read
HWR, LWR
Write data
Write
Note: indicates the timing of WAIT pin sampling.
WAIT
Data bus
T
2
T
w
T
w
T
w
T
3
By WAIT pin
Figure 7.13 Example of Wait State Insertion Timing
The settings after a reset are: 3-state access, 3 program wait state insertion, and WAIT input
disabled.
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7.5 Burst ROM Interface
7.5.1 Overview
With the H8S/2626 Group and H8S/2623 Group, external space area 0 can be designated as burst
ROM space, and burst ROM interfacing can be performed. The bu rst ROM space interface enables
16-bit conf ig uration ROM with bur st access capability to be accessed at high speed.
Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.
Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
7.5.2 Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordan ce
with the setting of the AST0 bit in ASTCR. Also, wh en the AST0 bit is set to 1, wait state
insertion is p ossible. One or two states can be selected for the burst cycle, according to the setting
of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst
ROM space, it becomes 16-bit access space rega rdless of the setting of the ABW0 bit in ABWCR.
When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 7.14 (a) and (b). The timing
shown in figure 7.14 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and
that in figure 7.14 (b) is for the case where both these bits are cleared to 0.
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T1
Address bus
φ
AS
Data bus
T2T3T1T2T1
Full access
T2
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 7.14 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
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T1
Address bus
φ
AS
Data bus
T2T1T1
Full access
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 7.14 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
7.5.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4 . 5, Wait
Control.
Wait states cannot be inserted in a burst cycle.
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7.6 Idle Cycle
7.6.1 Operation
When the H8S/2626 Group or H8S/2623 Group accesses external space , it can insert a 1-state idle
cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different
areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By
inserting an id le cycle it is possible, for example, to avoid data collisions between ROM, with a
long output floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occu r while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7.15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B Bus cycle A Bus cycle B
Long output
floating time
Data
collision
(a) Idle cycle not inserted
(ICIS1 = 0) (b) Idle cycle inserted
(Initial value ICIS1 = 1)
T
1
Address bus
φ
RD
Data bus
T
2
T
3
T
I
T
1
T
2
C
S* (area A)
C
S* (area B)
CS* (area A)
CS* (area B)
Note: * The CS signals are generated off-chip.
Figure 7.15 Example of Idle Cycle Operation (1)
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(2) Write after Read
If an e xternal write occurs after a n external r e ad w hile the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 7.16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In ( b), an idle cycle is inserted, and a data collisio n is prevented.
T1
Address bus
φ
RD
Bus cycle A
T2T3T1T2
Bus cycle B
T1
Address bus
φ
RD
Bus cycle A
T2T3TIT1
Bus cycle B
T2
C
S* (area A)
C
S* (area B)
CS* (area A)
CS* (area B)
(a) Idle cycle not inserted
(ICIS1 = 0) (b) Idle cycle inserted
(Initial value ICIS1 = 1)
Note: * The CS signals are generated off-chip.
Possibility of overlap between
CS (area B) and RD
Figure 7.16 Example of Idle Cycle Operation (2)
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7.6.2 Pin States in Idle Cycle
Table 7.5 shows pin states in an idle cycle.
Table 7.5 Pin States in Idle Cycle
Pins Pin State
A23 to A0 Contents of next bus cycle
D15 to D0 High impedance
AS High
RD High
HWR High
LWR High
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7.7 Write Data Buffer Function
The H8S/2626 Group and H8S/2623 Group have a write data buffer function in the external data
bus. Using the write data buffer function enables external writes to b e execu ted in parallel with
internal accesses. The write data b uffer function is made available by setting the WDBE bit in
BCRL to 1.
Figure 7.17 sh ows an example of the timing when the write data buffer function is u sed . When this
function is used, if an external write continues for 2 states or longer, and there is an internal access
next, only an external write is executed in the first state, but from the next state onward an internal
access (on-chip memory or internal I/O register read /write) is executed in parallel with the external
write rather than waiting until it ends.
T1
Internal address bus
A23 to A0
External write cycle
HWR, LWR
T2TWTWT3
On-chip memory read Internal I/O register read
Internal read signal
D15 to D0
External address
Internal memory
External
space
write
Internal I/O register address
Figure 7.17 Example of Timing when Write Data Buffer Function is Used
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7.8 Bus Release
7.8.1 Overview
The H8S/2626 Group and H8S/2623 Group can release the external bus in response to a bus
request from an external device. In the external bus released state, the internal bus master
continues to operate as long as there is no external access.
If an internal bus master wants to make an external access in the external bus released state, it can
issue a bus request off-chip.
7.8.2 Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Dr iving the BREQ pin low issues an external bus request to the H8S/2626 Group or
H8S/2623 Group. When the BREQ pin is sampled, at the prescrib ed timing the BACK pin is
driven low, and the address bus, data bus, and bus control signals are placed in the high-
impedance state, establishing the external bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped.
If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to m ake a n externa l
access in the external bus released state, the BREQO pin is driven low and a request can be made
off-chip to drop the bus request.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and internal bus master external access occur simultaneously, the
order of prio rity is as follows:
(High) External bus release > Internal bus master external access (Low)
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7.8.3 Pin States in External Bus Released State
Table 7.6 shows pin states in the external bus released state.
Table 7.6 Pin States in Bus Released State
Pins Pin State
A23 to A0 High impedance
D15 to D0 High impedance
AS High impedance
RD High impedance
HWR High impedance
LWR High impedance
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7.8.4 Transition Timi ng
Figure 7. 18 shows the timing for transition to th e bus- r e leased state.
CPU
cycle
External bus released stateCPU cycle
Address
T
0
T
1
T
2
φ
Address bus
Data bus
AS
HWR, LWR
BREQ
BACK
High impedance
Minimum
1 state
BREQO*
[1] [2] [3] [4] [5] [6]
[1]
[2]
[3]
[4]
[5]
[6]
Note: * Output only when BREQOE is set to 1.
Low level of BREQ pin is sampled at rise of T
2
state.
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
BREQO signal goes high 1.5 clocks after BACK signal goes high.
High impedance
High impedance
High impedance
RD High impedance
Figure 7.18 Bus-Released State Transition Timing
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7.8.5 Usage Note
If MSTPCR is set to H'FFFFFF or H'EFFFFF and a transition is made to sleep mode, the external
bus release function will halt. Therefore, these values should not be set in MSTPCR if the external
bus release function is to be used in sleep mode.
7.9 Bus Arbitration
7.9.1 Overview
The H8S/2626 Group and H8S/2623 Group have a bus arbiter that arbitrates bus master
operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter d e termin es priorities at the prescrib ed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes po ssession of the bus and
begins its operation.
7.9.2 Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledg e signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until th at sig nal is canceled.
The order of pr iority of the bus masters is as follows:
(High) DTC > CPU (Low)
An internal bus access by an intern al bus master, and external bus release, can be executed in
parallel.
In the event of simultaneous external bus release request, and internal bus master external access
request generation, the order of priority is as follows:
(High) External bus release > Internal bus master external access (Low)
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7.9.3 Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to th e bus master that issued the request. The timing for transfer of
the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations. See appendix A.5, Bus States During Instruction Execution, for timings at
which the bus is not transferred.
• If the CPU is in sleep mode, it transfers the bus immediately.
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data tran sfer, or a register information write (3 states).
7.10 Resets and the Bus Controller
In a reset, the H8S/2626 Group or H8S/2623 Group, including the bus controller, enters the reset
state at that point, and an executing bus cycle is discontinued.
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Section 8 Data Transfer Controller (DTC)
8.1 Overview
The H8S/2626 Group and H8S/2623 Group include a data transfer controller (DTC). The DTC can
be activated by an interrupt or software, to transfer data.
8.1.1 Features
The features of the DTC are:
• Transfer possible over any number of channels
Transfer information is stored in me mor y
One activation source can trigger a number of data transfers (chain transfer)
• Wide range of tr ansfer modes
Normal, repeat, and block tran sfer modes available
Incrementing, decrementing, and fixing of source and destination addresses can be selected
• Direct specification of 16-Mbyte address space possible
24-bit transfer source and destination addresses can be specified
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
An interrupt request can be issued to the CPU after one data transfer ends
An interrupt request can be issued to the CPU after the specified data transfers have
completely ended
• Activation by software is possible
• Module stop mode can be set
The initial setting enables DTC registers to be accessed. DTC operation is halted by setting
module stop mode.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 184 of 1042
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8.1.2 Block Diagram
Figure 8.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on- chip RAM*. A 32-b it bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state read ing and writing of the DTC register
information.
Note: * When the DTC is used, th e RAME bit in SYSCR mu st be set to 1.
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC service
request
Control logic
Register information
MRA MRB
CRA
CRB
DAR
SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERG
DTVECR
DTCERA
to
DTCERG
DTVECR
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to G
: DTC vector register
Figure 8.1 Block Diagram of DTC
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 185 of 1042
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8.1.3 Register Configuration
Table 8.1 summarizes the DTC registers.
Table 8.1 DTC Registers
Name Abbreviation R/W Initial Value Address*1
DTC mode register A MRA —*2Undefined —*3
DTC mode register B MRB —*2Undefined —*3
DTC source address register SAR —*2Undefined —*3
DTC destination address register DAR —*2Undefined —*3
DTC transfer count register A CRA —*2Undefined —*3
DTC transfer count register B CRB —*2Undefined —*3
DTC enable registers DTCER R/W H'00 H'FE16 to H'FE1C
DTC vector register DTVECR R/W H'00 H'FE1F
Module stop control register MSTPCRA R/W H'3F H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot
be located in external memory space. When the DTC is used, the RAME bit in SYSCR
must be set to 1.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 186 of 1042
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8.2 Register Descriptions
8.2.1 DTC Mode Register A (MRA)
7
SM1 6
SM0 5
DM1 4
DM0 3
MD1 0
Sz
2
MD0 1
DTS
Bit
Initial value
:
:
—
Unde-
fined
R/W : —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7 Bit 6
SM1 SM0 Description
0 — SAR is fixed
1 0 SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1 SAR is de cremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a da ta tr ansfer.
Bit 5 Bit 4
DM1 DM0 Description
0 — DAR is fixed
1 0 DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1 DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 187 of 1042
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Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3 Bit 2
MD1 MD0 Description
0 0 Normal mode
1 Repeat mode
1 0 Block transfer mode
1 —
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1
DTS Description
0 Destination side is repeat area or block area
1 Source side is repeat area or block area
Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0
Sz Description
0 Byte-size transfer
1 Word-size transfer
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 188 of 1042
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8.2.2 DTC Mode Register B (MRB)
7
CHNE 6
DISEL 5
—4
—3
—0
—
2
—1
—
Bit
Initial value
:
:
R/W : —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined —
Unde-
fined
MRB is an 8-bit register that contr ols the DTC oper ating m ode.
Bit 7—DTC C hain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a
number of data transfers can be performed consecutively in response to a single transfer request.
In data tran sf er with CHNE set to 1, determination of the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of DTCER is not performed.
Bit 7
CHNE Description
0 End of DTC data transfer (activation waiting state is entered)
1 DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL Description
0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2626 Group and
H8S/2623 Group, and should always be written with 0.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 189 of 1042
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8.2.3 DTC Source Address Register (SAR)
23 22 21 20 19 43210
Bit
Initial value
:
:
—
Unde-
fined
R/W : —
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4 DTC Destina t ion Address Register (DAR)
23 22 21 20 19 43210
Bit
Initial value
:
:
—
Unde-
fined
R/W : —
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 190 of 1042
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8.2.5 DTC Transfer Count Register A (CRA)
15 14 13 12 11109876543210
CRAH CRAL
Bit
Initial value
:
:
—
Unde-
fined
R/W : —
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
—
Unde-
fined
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
8.2.6 DTC Transfer Count Register B (CRB)
15 14 13 12 11109876543210
Bit
Initial value
:
:
————————————————
Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined Unde-
fined
Unde-
fined Unde-
fined
R/W :
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 191 of 1042
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8.2.7 DTC Enable Registers (DTCER)
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
0
DTCE0
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
Bit
Initial value
R/W
:
:
:
The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to
DTCERG, with bits corresponding to the interrupt sources that can control enabling and disabling
of DTC activation. These bits enable or disable DTC service for the corresponding interrupt
sources.
The DTC enable reg ister s ar e initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn Description
0 DTC activation by this interrupt is disabled (Initial value
)
[Clearing cond iti ons ]
• When the DISEL bit is 1 and the data transfer has ended
• When the specified number of transfers have ended
1 DTC activation by this interrupt is enabled
[Holding cond iti on]
When the DISEL bit is 0 and the specified number of transfers have not ended
(n = 7 to 0)
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 8.4, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. If all interrupts are masked, multiple activation sour ces can be set at one time by writing
data after executing a dummy read on the relevant register.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 192 of 1042
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8.2.8 DTC Vector Register (DTVECR)
7
SWDTE
0
R/(W)*1
6
DTVEC6
0
R/(W)*2
5
DTVEC5
0
R/(W)*2
4
DTVEC4
0
R/(W)*2
3
DTVEC3
0
R/(W)*2
0
DTVEC0
0
R/(W)*2
2
DTVEC2
0
R/(W)*2
1
DTVEC1
0
R/(W)*2
Notes: 1. Only 1 can be written to the SWDTE bit.
2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
Bit
Initial value
R/W
:
:
:
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE Description
0 DTC software activation is disabled (Initial value
)
[Clearing cond iti ons ]
• When the DISEL bit is 0 and the specified number of transfers have not ended
• When 0 s written to the DISEL bit after a software-activated data transfer end
interrupt (SWDTEND) request has been sent to the CPU
1 DTC software activation is enabled
[Holding cond iti ons ]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activati on
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number fo r DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 193 of 1042
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8.2.9 Module Stop Control Register A (MSTPCRA)
7
MSTPA7
0
R/W
Bit
Initial value
R/W
6
MSTPA6
0
R/W
5
MSTPA5
1
R/W
4
MSTPA4
1
R/W
3
MSTPA3
1
R/W
2
MSTPA2
1
R/W
1
MSTPA1
1
R/W
0
MSTPA0
1
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operatio n stops at the end of the bus
cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6
bit while the DTC is operating. For details, see sections 21A.5, 21 B.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset an d in hardware standby mode. It is not initialized in
software standby mode.
Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode.
Bit 6
MSTPA6 Description
0 DTC module stop mode cle ared (Initial value
)
1 DTC module stop mode set
8.3 Operation
8.3.1 Overview
When activated, the DTC reads register information that is already stored in memory and transfers
data on the basis of that register information. After the data transfer, it writes updated register
inform ation back to memory. Pre-storage of register information in memory makes it possible to
transfer da ta over any r e quir ed number of channels. Setting th e CHNE bit to 1 make s it possib le to
perform a number of transfers with a single activation.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 194 of 1042
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Figure 8.2 shows a flowchart of DTC operation.
Start
Read DTC vector Next transfer
Read register information
Data transfer
Write register information
Clear an activation flag
CHNE=1
End
No
No
Yes
Yes
Transfer Counter = 0
or DISEL = 1
Clear DTCER
Interrupt exception
handling
Figure 8.2 Flowchart of DTC Operation
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 8.2 outlines the functions of the DTC.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 195 of 1042
REJ09B0275-0500
Table 8.2 DTC Functions
Address Registers
Transfer Mode Activation Source Transfer
Source Transfer
Destination
• Normal mode
One transfer request transfers one
byte or one word
Memory addres ses are incremented
or decremented by 1 or 2
Up to 65,536 transfers possible
• Repeat mode
One transfer request transfers one
byte or one word
Memory addres ses are incremented
or decremented by 1 or 2
After the specified number of
transfers (1 to 256), the initial state
resumes and operation continues
• Block transfer mode
One transfer request transfers a
block of the specified size
Block size is from 1 to 256 bytes or
words
Up to 65,536 transfers possible
A block area can be designated at
either the source or destination
• IRQ
• TPU TGI
• SCI TXI or RXI
• A/D converter ADI
• Software
• HCAN RM0
24 bits 24 bits
8.3.2 Activation Sources
The DTC operates wh en activated by an interrupt or by a write to DTVECR b y software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. An interr upt b ecomes a DTC activation sour ce when the corresponding bit is set to 1, and a
CPU interrupt source when the bit is cleared to 0.
At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. Table 8.3 shows activation source and
DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag
of SCI0.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 196 of 1042
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Table 8.3 Activation Source and DTCER Clearance
Activation Source
When the DISEL Bit Is 0 and
the Specified Number of
Transfers Have Not Ended
When the DISEL Bit Is 1, or when
the Specified Number of Transfers
Have Ended
Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1
An interrupt is issued to the CPU
Interrupt activation The corresponding DTCER bit
remains set to 1
The activation source flag is
cleared to 0
The corresponding DTCER bit is cleared
to 0
The activation source flag remains set to 1
A request is issued to the CPU for the
activation source interrupt
Figure 8.3 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
On-chip
supporting
module
IRQ interrupt
DTVECR
Selection circuit
Interrupt controller CPU
DTC
DTCER
Clear
controller
Select
Interrupt
request
Source flag cleared
Clear
Clear request
Interrupt mask
Figure 8.3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 197 of 1042
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8.3.3 DTC Vector Table
Figure 8.4 shows the correspondence between DTC vector addresses and register information.
Table 8.4 shows the correspondence between activation and vector addresses. When the DTC is
activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where
<< 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
The DTC reads the start address of the register information from the vector address set for each
activation source, and then reads the register information from that start address. The register
information can be placed at predetermined addresses in the on-chip RAM. The start address of
the register in f orm ation should be an integral multiple of four.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes sp ecify the lower bits of the address in the on-chip
RAM.
Note: * Not available in the H8S/2626 Group or H8S/2623 Group.
Register information
start address Register information
Chain transfer
DTC vector
address
Figure 8.4 Correspondence between DTC Vector Address and Register Information
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 198 of 1042
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Table 8.4 Interrupt Sources, DTC Vector Addresse s, and Corresponding DTCEs
Interrupt Source
Origin of
Interrupt
Source Vector
Number Vector
Address DTCE*Priority
Write to DTVECR Software DTVECR H'0400+
(DTVECR
[6:0] <<1)
—High
IRQ0 External pin 16 H'0420 DTCEA7
IRQ1 17 H'0422 DTCEA6
IRQ2 18 H'0424 DTCEA5
IRQ3 19 H'0426 DTCEA4
IRQ4 20 H'0428 DTCEA3
IRQ5 21 H'042A DTCEA2
Reserved 22 H'042C DTCEA1
23 H'042E DTCEA0
ADI (A/D conversion end) A/D 28 H'0438 DTCEB6
TGI0A (GR0A compare match/
input capture) TPU
channel 0 32 H'0440 DTCEB5
TGI0B (GR0B compare match/
input capture) 33 H'0442 DTCEB4
TGI0C (GR0C compare match/
input capture) 34 H'0444 DTCEB3
TGI0D (GR0D compare match/
input capture) 35 H'0446 DTCEB2
TGI1A (GR1A compare match/
input capture) TPU
channel 1 40 H'0450 DTCEB1
TGI1B (GR1B compare match/
input capture) 41 H'0452 DTCEB0
TGI2A (GR2A compare match/
input capture) TPU
channel 2 44 H'0458 DTCEC7
TGI2B (GR2B compare match/
input capture) 45 H'045A DTCEC6 Low
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 199 of 1042
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Interrupt Source
Origin of
Interrupt
Source Vector
Number Vector
Address DTCE*Priority
TGI3A (GR3A compare match/
input capture) TPU
channel 3 48 H'0460 DTCEC5 High
TGI3B (GR3B compare match/
input capture) 49 H'0462 DTCEC4
TGI3C (GR3C compare match/
input capture) 50 H'0464 DTCEC3
TGI3D (GR3D compare match/
input capture) 51 H'0466 DTCEC2
TGI4A (GR4A compare match/
input capture) TPU
channel 4 56 H'0470 DTCEC1
TGI4B (GR4B compare match/
input capture) 57 H'0472 DTCEC0
TGI5A (GR5A compare match/
input capture) TPU
channel 5 60 H'0478 DTCED5
TGI5B (GR5B compare match/
input capture) 61 H'047A DTCED4
Reserved —64 H'0480 DTCED3
65 H'0482 DTCED2
68 H'0488 DTCED1
69 H'048A DTCED0
72 H'0490 DTCEE7
73 H'0492 DTCEE6
74 H'0494 DTCEE5
75 H'0496 DTCEE4
RXI0 (reception complete 0) 81 H'04A2 DTCEE3
TXI0 (transmit data empty 0) SCI
channel 0 82 H'04A4 DTCEE2
RXI1 (reception complete 1) 85 H'04AA DTCEE1
TXI1 (transmit data empty 1) SCI
channel 1 86 H'04AC DTCEE0
RXI2 (reception complete 2) 89 H'04B2 DTCEF7
TXI2 (transmit data empty 2) SCI
channel 2 90 H'04B4 DTCEF6
RM0 HCAN 106 H'04D4 DTCEG5 Low
Note: *DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 200 of 1042
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8.3.4 Location of Register Information in Address Space
Figure 8.5 shows how the register information should be located in the address space.
Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, fr om the start address
of the register information (contents of the vector address). In the case of chain transfer, register
information should be located in consecutive areas.
Locate the register in for mation in the on-chip RAM (ad dresses: H'FFEBC0 to H'FFEF BF).
Register
information
start address
Chain
transfer Register information
for 2nd transfer in
chain transfer
MRA SAR
MRB DAR
CRA CRB
4 bytes
Lower address
CRA CRB
Register information
MRA
0123
SAR
MRB DAR
Figure 8.5 Location of Register Information in Address Space
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 201 of 1042
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8.3.5 Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 8.5 lists the register information in normal mode and figure 8.6 shows memory mapping in
normal mode.
Table 8.5 Register Information in Normal Mode
Name Abbreviation Function
DTC source address register SAR Designates source address
DTC destination address register DAR Designates destination address
DTC transfer count register A CRA Designates transfer count
DTC transfer count register B CRB Not used
Transfer
SAR DAR
Figure 8.6 Memory Mapping in Normal Mode
Section 8 Data Transfer Controller (DTC)
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8.3.6 Repeat Mode
In repeat mode, one operation transfers on e byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial state of the transfer counter and the address register specified as the repeat area is restored ,
and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and
therefore CPU interrupts cannot be requested when DISEL = 0.
Table 8.6 lists the register information in repeat mode and figu re 8.7 shows memory mapping in
repeat mode.
Table 8.6 Register Information in Repeat Mode
Name Abbreviation Function
DTC source address register SAR Designates source addres s
DTC destination address register DAR Designates destination address
DTC transfer count register AH CRAH Holds number of transfers
DTC transfer count register AL CRAL Designates transfer count
DTC transfer count register B CRB Not used
Transfer
SAR or
DAR DAR or
SAR
Repeat area
Figure 8.7 Memory Mapping in Repeat Mode
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 203 of 1042
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8.3.7 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area.
The block size is 1 to 2 56. When the transfer of on e block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremen ted, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrup t is requested.
Table 8.7 lists the register information in block transfer mode and figure 8.8 shows memory
mapping in block transfer mode.
Table 8.7 Register Information in Block Transfer Mode
Name Abbreviation Function
DTC source address register SAR Designates source addres s
DTC destination address register DAR Designates destination address
DTC transfer count regi ster AH CRAH Holds block size
DTC transfer count register AL CRAL Designates block size count
DTC transfer count register B CRB Transfer count
Section 8 Data Transfer Controller (DTC)
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Transfer
SAR or
DAR DAR or
SAR
Block area
First block
Nth block
·
·
·
Figure 8.8 Memory Mapping in Block Transfer Mode
Section 8 Data Transfer Controller (DTC)
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8.3.8 Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8.9 shows the memory map for chain transfer.
Source
Source
Destination
Destination
DTC vector
address Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Figure 8.9 Chain Transfer Memory Map
In the case of transf er with CHNE set to 1, an interrupt r equest to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Section 8 Data Transfer Controller (DTC)
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8.3.9 Operation Timing
Figures 8.10 to 8.12 show an example of DTC operation timing.
DTC activation
request
DTC
request
Address
Vector read
Transfer
information read Transfer
information write
Data transfer
Read Write
φ
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
Read Write Read Write
Data transfer
Transfer
information write
Transfer
information read
Vector read
φ
DTC activation
request
DTC request
Address
Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 207 of 1042
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Read Write Read Write
Address
φ
DTC activation
request
DTC
request Data transfer Data transfer
Transfer
information
write
Transfer
information
write
Transfer
information
read
Transfer
information
read
Vector read
Figure 8.12 DTC Operation Timing (Example of Chain Transfer)
8.3.10 Number of DTC Execution States
Table 8.8 lists execution statuses for a single DTC data transfer, and table 8.9 shows the number of
states required for each execution status.
Table 8.8 DTC Execution Statuses
Mode Vector Read
I
Register Information
Read/Write
JData Read
KData Write
L
Internal
Operations
M
Normal1 6 113
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
N: Block size (initial setting of CRAH and CRAL)
Section 8 Data Transfer Controller (DTC)
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Table 8.9 Number of States Required for Each Execution Status
Object to be Accessed On-
Chip
RAM
On-
Chip
ROM
On-Chip I/O
Registers External Devices
Bus width 3216816 8 16
Access states 11222323
Vector read SI— 1 —— 46+2m2 3+m
Register
information
read/write
SJ1———————
Byte data read SK112223+m23+m
Word data read SK114246+2m23+m
Byte data write SL112223+m23+m
Word data write SL114246+2m23+m
Execution
status
Internal operation SM1
The number of execution states is calculated from the formula below. No te that Σ means the sum
of all transfer s activated by one activation even t ( th e number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · (SI + 1) + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is tran sferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 14 states. The time from activation to the end of the data write is 11 states.
Section 8 Data Transfer Controller (DTC)
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8.3.11 Procedures for Using DTC
Activation by Interrupt: Th e procedure for using the DTC with inter rupt activation is as fo llows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
[5] After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is r equested. If the DTC is to contin u e
transferrin g data, set the DTCE bit to 1.
Activatio n by Software: The procedu re for using the DTC with sof twar e activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Check that the SWDTE bit is 0 .
[4] Write 1 to SWDTE bit and the vector number to DTVECR.
[5] Check the vector number wr itten to DTVECR.
[6] After the end of one d ata tr ansfer , if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE b it
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interru pt is requested.
Section 8 Data Transfer Controller (DTC)
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8.3.12 Examples of Use of the DTC
(1) Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
[1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by on e interr upt ( CHNE = 0, DI SEL = 0). Set th e
SCI RDR address in SAR, the start addr ess of the RAM area where the d a ta will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
[2] Set the start address of the register information at the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
[5] E ach time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. Th e RDRF flag is
automatically cleared to 0.
[6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0 , and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
Section 8 Data Transfer Controller (DTC)
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(2) Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG’s NDR is performed in the first half o f the chain
transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of tran sfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
[1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
[2] Perform settings for tran sf er to the TPU’s TGR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 =
MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address
in DAR, and the data table size in CRA. CRB can b e set to any value.
[3] Locate the TPU transfer register information consecutively after th e NDR transfer register
information.
[4] Set the start address of the NDR transfer register information to the DTC vector address.
[5] Set the b it corresponding to TGI A in DTCER to 1.
[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
[7] Set the in itial output valu e in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match
to be used as the output trigger.
[8] Set the CST b it in TSTR to 1, and start the TCNT count oper ation.
[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and
the set value of the next output trigger period is transferred to TGRA. The activation source
TGFA flag is cleared.
[10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt req uest is sent to
the CPU. Termination processing should be performed in the interrupt handling routine.
Section 8 Data Transfer Controller (DTC)
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(3) Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
[2] Set the start address of the register information at the DTC vector address (H'04C0).
[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
[4] Write 1 to the SWDTE bit and th e vector number (H'60) to DTVECR. The write data is H'E0.
[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
[6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
[7] After the transfer , an SWDTEND inter rupt occurs. The interrup t handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
Section 8 Data Transfer Controller (DTC)
Rev. 5.00 Jan 10, 2006 page 213 of 1042
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8.4 Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL b it was set to 1. In the case of interrupt activation,
the interru pt set as the activation sour ce is generated. These interrupts to the CPU are subject to
CPU mask level an d interrupt controller priority lev e l contr ol.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers
have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or dur in g data transfer even if the SWDTE bit is set to 1.
8.5 Usage Notes
Module Stop: When the MSTPA6 bit in MSTPCRA is set to 1, th e DTC clo c k stops, and the
DTC enters the module stop state. However, 1 cannot be written in the MSTPA6 bit while the
DTC is operating.
On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip
RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.
DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR. If all interrupts are masked, multiple activation sources can be set at on e time by writing
data after executing a dummy read on the relevant register.
Section 8 Data Transfer Controller (DTC)
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Section 9 I/O Ports
Rev. 5.00 Jan 10, 2006 page 215 of 1042
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Section 9 I/O Ports
9.1 Overview
The H8S/2626 Group and H8S/2623 Group have seven I/O ports (ports 1 and A to F), and two
input-only ports (ports 4 and 9).
Table 9.1 summarizes the port functions. The pins of each port also have other functions.
Each I/O port includes a data direction register (DDR) that controls input/output, a data register
(DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only
ports do not have a DR or DDR register.
Ports A to E hav e a built- in pull-up MOS functio n, and in addition to DR and DDR, h ave a MOS
input pull-up control register (PCR) to control the on/off state of MOS input pull-up.
Ports A to C include an open-drain control register (ODR) that controls the on/off state of the
output buffer PMOS.
Ports 10 to 13, A0 to A3, and B to E can drive a single TTL load and 50 pF capacitive load when
used as expansion bus control signal output pins. In other cases these ports, together with ports 14
to 17 and 3, can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a
Darlington transistor when in output mode. Ports 1, A, B, and C can drive an LED (10 mA sink
current).
See appendix C, I/O Port Block Diagrams, for a block diagram of each port.
Section 9 I/O Ports
Rev. 5.00 Jan 10, 2006 page 216 of 1042
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Table 9.1 Port Functions
Port Descri p ti on Pins Mode 4 Mode 5 Mode 6 Mode 7
Port 1 •8-bit I/O
port
•Schmitt-
triggered
input (P16
and P14)
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2/IRQ1
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1/IRQ0
P13/PO11/TIOCD0/
TCLKB/A23
P12/PO10/TIOCC0/
TCLKA/A22
P11/PO9/TIOCB0/A21
P10/PO8/TIOCA0/A20
8-bit I/O port also functioning as TPU I/O
pins (TCLKA, TCLKB, TCLKC, TCLKD,
TIOCA0, TIOCB0, TIOCC0, TIOCD0,
TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG
output pins (PO15 to PO8), interrupt input
pins (IRQ0, IRQ1), and address outputs
(A20 to A23)
8-bit I/O port
also function-
ing as TPU
I/O pins
(TCLKA,
TCLKB,
TCLKC,
TCLKD,
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0,
TIOCA1,
TIOCB1,
TIOCA2,
TIOCB2),
PPG output
pins (PO15 to
PO8), and
interrupt i nput
pins (IRQ0,
IRQ1)
Port 4 • 8-bit input
port P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
8-bit input port also funct i oni ng as A/D converter analog
inputs (AN7 to AN0)
Port 9 • 8-bit input
port P97/AN15/DA3*1
P96/AN14/DA2*1
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
8-bit input port also funct i oni ng as A/D converter analog
inputs (AN15 to AN8) and D/A converter analog out puts
(DA3, DA2)
Section 9 I/O Ports
Rev. 5.00 Jan 10, 2006 page 217 of 1042
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Port Descri p ti on Pins Mode 4 Mode 5 Mode 6 Mode 7
Port A
*2•6-bit I/O
port
• Built-in
MOS input
pull-up
• Open-drain
output
capability
PA5
PA4
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
6-bit I/O port also functioni ng as SCI
(channel 2) I/O pins (TxD2, RxD2, SCK2),
and address outputs (A19 to A16)
6-bit I/O port
also function-
ing as SCI
(channel 2)
I/O pins
(TxD2, RxD2,
SCK2)
Port B •8-bit I/O
port
• Built-in
MOS input
pull-up
• Open-drain
output
capability
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
8-bit I/O port also functioning as TPU I/O
pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4,
TIOCD3, TIOCC3, TIOCB3, TIOCA3) and
address outputs (A 15 to A8)
8-bit I/O port
also function-
ing as TPU
I/O pins
(TIOCB5,
TIOCA5,
TIOCB4,
TIOCA4,
TIOCD3,
TIOCC3,
TIOCB3,
TIOCA3)
Port C •8-bit I/O
port
• Built-in
MOS input
pull-up
• Open-drain
output
capability
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ4
PC1/A1/RxD0
PC0/A0/TxD0
Address out put (A7 to A0) 8-bit I/ O port
also function-
ing as SCI
(channel 0, 1)
I/O pins
(TxD0, RxD0,
SCK0, TxD1,
RxD1, SCK1),
interrupt i nput
pins (IRQ4,
IRQ5), and
address
outputs (A7 to
A0)
8-bit I/O port
also function-
ing as SCI
(channel 0, 1)
I/O pins
(TxD0, RxD0,
SCK0, TxD1,
RxD1, SCK1)
and interrupt
input pins
(IRQ4, IRQ5)
Port D • 8-bit I/O
port
• Built-in
MOS input
pull-up
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Data bus input/output I/O port
Section 9 I/O Ports
Rev. 5.00 Jan 10, 2006 page 218 of 1042
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Port Descri p ti on Pins Mode 4 Mode 5 Mode 6 Mode 7
Port E •8-bit I/O
port
• Built-in
MOS input
pull-up
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
In 8-bit bus mode: I/O port
In 16-bit bus mode: data bus input/output I/O port
Port F •8-bit I/O
port PF7/φWhen DDR = 0: input port
When DDR = 1 (after reset): φ output When DDR =
0 (after reset):
input port
When DDR =
1: φ output
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
AS, RD, HWR, LWR output
ADTRG, IRQ3 input I/O port
ADTRG,
IRQ3 input
PF2/WAIT/BREQO When WAITE = 0 and BREQOE = 0 (after
reset): I/O port
When WAITE = 1 and BREQOE = 0:
WAIT input
When WAITE = 0 and BREQOE = 1:
BREQO input
I/O port
PF1/BACK/BUZZ*3
PF0/BREQ/IRQ2
When BRLE = 0 (after reset): I/O port
When BRLE = 1: BREQ input, BACK output,
BUZZ output, IRQ2 input
I/O port,
BUZZ output,
IRQ2 input
Notes: 1. DA3 and DA2 are outputs in the H8S/2626 Group only.
2. In the H8S/2626 Group, PA5 and PA4 are OSC2 and OSC1, respectively.
3. BUZZ output pin in the H8S/2626 Group only.
Section 9 I/O Ports
Rev. 5.00 Jan 10, 2006 page 219 of 1042
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9.2 Port 1
9.2.1 Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O
pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1,
TIOCB1, TIOCA2, and TIOCB2), external interrupt pins (IRQ0 and IRQ1), and address bus
output pins (A23 to A20). Port 1 pin functions change according to the operating mode.
Figure 9.1 shows the port 1 pin configuration.
P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input)
P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input)
P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input)
P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input)
P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) / A23 (output)
P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) / A22 (output)
P11 (I/O) / PO9 (output) / TIOCB0 (I/O) / A21 (output)
P10 (I/O) / PO8 (output) / TIOCA0 (I/O) / A20 (output)
Port 1
Port 1 pins
Pin functions in modes 4 to 6
P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input)
P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input)
P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input)
P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input)
P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input)
P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input)
P11 (I/O) / PO9 (output) / TIOCB0 (I/O)
P10 (I/O) / PO8 (output) / TIOCA0 (I/O)
Pin functions in mode 7
Figure 9.1 Port 1 Pin Functions
Section 9 I/O Ports
Rev. 5.00 Jan 10, 2006 page 220 of 1042
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9.2.2 Register Configuration
Table 9.2 shows the port 1 register configuration.
Table 9.2 Port 1 Registers
Name Abbreviation R/W Initial Value Address*
Port 1 data direction register P1DDR W H'00 H'FE30
Port 1 data register P1DR R/W H'00 H'FF00
Port 1 register PORT1 R Undefined H'FFB0
Note: *Lower 16 bits of the address .
Port 1 Data Direction Register (P1DDR)
Bit:76543210
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value:00000000
R/W:WWWWWWWW
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined valu e will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P1DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its pr ior state in
software standby mode.
Section 9 I/O Ports
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Port 1 Data Register (P1DR)
Bit:76543210
P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).
P1DR is initia lized to H'00 by a reset, and in hardware standby m ode . I t retains its prior state in
software standby mode.
Port 1 Register (PORT1)
Bit:76543210
P17 P16 P15 P14 P13 P12 P11 P10
Initial value : —*—*—*—*—*—*—*—*
R/W:RRRRRRRR
Note: *Determined by state of pins P17 to P10.
PORT1 is an 8-b it read-only register that shows the pin states. I t cannot be written to. Writing of
output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1
read is performed while P1DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as
P1DDR and P1DR are initialized. PORT1 retains its prior state in software standby mode.
Section 9 I/O Ports
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9.2.3 Pin Functions
Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB,
TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and
TIOCB2), exter nal interrupt input p ins (IRQ0 and IRQ1), and address bus output pins (A23 to
A20). Port 1 pin functions are shown in table 9.3.
Table 9.3 Port 1 Pin Functions
Pin Selection Method and Pin Functions
P17/PO15/
TIOCB2/TCLKD The pin function is switched as shown below according to the combination of
the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0
in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in
TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR.
TPU Channel
2 Setting Table Below (1) Table Below (2)
P17DDR —011
NDER15 ——01
Pin function TIOCB2 output P17
input P17
output PO15
output
TIOCB2 input *1
TCLKD input *2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 =
1.
2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2
to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting
mode.
TPU Channel
2 Setting (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
—B'xx00 Other than B'xx00
CCLR1,
CCLR0 ————Other
than B'10 B'10
Output
function —Output
compare
output
——
PWM
mode 2
output
—
x: Don’t care
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
P16/PO14/
TIOCA2/IRQ1 The pin function is switched as shown below according to the combination of
the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0
in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and
bit P16DDR.
TPU Channel
2 Setting Table Below (1) Table Below (2)
P16DDR —011
NDER14 ——01
Pin function TIOCA2 output P16
input P16
output PO14
output
TIOCA2 input *1
IRQ1 input
TPU Channel
2 Setting (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR1,
CCLR0 ————Other
than B'01 B'01
Output
function —Output
compare
output
—PWM
mode 1
output *2
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 =
1.
2. TIOCB2 output is disabled.
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
P15/PO13/
TIOCB1/TCLKC The pin function is switched as shown below according to the combination of
the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0
in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in
TCR0, TCR2, TCR4, and TCR5, bi t NDER13 in NDERH, and bit P15DDR.
TPU Channel
1 Setting Table Below (1) Table Below (2)
P15DDR —011
NDER13 ——01
Pin function TIOCB1 output P15
input P15
output PO13
output
TIOCB1 input *1
TCLKC input *2
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3
to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2
to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is
TPSC2 to TPSC0 = B'101.
TCLKC input when channels 2 and 4 are set to phase counting
mode.
TPU Channel
1 Setting (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
—B'xx00 Other than B'xx00
CCLR1,
CCLR0 ————Other
than
B'10
B'10
Output
function —Output
compare
output
——PWM
mode 2
output
—
x: Don’t care
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
P14/PO12/
TIOCA1/IRQ0 The pin function is switched as shown below according to the combination of
the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0
in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and
bit P14DDR.
TPU Channel
1 Setting Table Below (1) Table Below (2)
P14DDR —011
NDER12 ——01
Pin function TIOCA1 output P14
input P14
output PO12
output
TIOCA1 input *1
IRQ0 input
TPU Channel
1 Setting (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other
than
B'xx00
Other than B'xx00
CCLR1,
CCLR0 ————Other
than B'01 B'01
Output
function —Output
compare
output
—PWM
mode 1
output*2
PWM
mode 2
output
—
x: Don't care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to
IOA0 = B'10xx.
2. TIOCB1 output is disabled.
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
P13/PO11/
TIOCD0/TCLKB/
A23
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),
bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, bit
NDER11 in NDERH, and bit P13DDR.
Operating
mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1110 B'1111
TPU Channel
0 Setting Table
Below (1) Table Below (2) —
P13DDR —011—
NDER11 —— 01—
Pin function TIOCD0
output P13 input P13 output PO11
output A23 output
TIOCD0 input *1
TCLKB input *2
Operating
mode Mode 7
AE3 to AE0 —
TPU Channel
0 Setting Table
Below (1) Table Below (2)
P13DDR —011
NDER11 —— 01
Pin function TIOCD0
output P13 input P13 output PO11 output
TIOCD0 input *1
TCLKB input *2
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 =
B'10xx.
2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to
TPSC0 = B'101.
TCLKB input when channels 1 and 5 are set to phase counting
mode.
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Pin Selection Method and Pin Functions
TPU Channel
0 Setting (2) (1) (2) (2) (1) (2)
P13/PO11/
TIOCD0/TCLKB/
A23 (cont) MD3 to MD0 B'0000 B'0010 B'0011
IOD3 to IOD0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
—B'xx00 Other than B'xx00
CCLR2 to
CCLR0 ————
Other
than
B'110
B'110
Output
function —Output
compare
output
——PWM
mode 2
output
—
x: Don’t care
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
P12/PO10/
TIOCC0/TCLKA/
A22
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),
bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, bit
NDER10 in NDERH, and bit P12DDR.
Operating
mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1110 B'1111
TPU Channel
0 Setting Table
Below (1) Table Below (2) —
P12DDR —011—
NDER10 —— 01—
Pin function TIOCC0
output P12
input P12
output PO10
output A22 output
TIOCC0 input *1
TCLKA input *2
Operating
mode Mode 7
AE3 to AE0 —
TPU Channel
0 Setting Table
Below (1) Table Below (2)
P12DDR —011
NDER10 —— 01
Pin function TIOCC0
output P12 input P12 output PO10 output
TIOCC0 input*1
TCLKA input*2
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
TPU Channel
0 Setting (2) (1) (2) (1) (1) (2)
P12/PO10/
TIOCC0/TCLKA/
A22 (cont) MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR2 to
CCLR0 ————
Other
than
B'101
B'101
Output
function —Output
compare
output
—PWM
mode 1
output*3
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =
B'10xx.
2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to
TPSC0 = B'100.
TCLKA input when channels 1 and 5 are set to phase counting
mode.
3. TIOCD0 output is disabled.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and
setting (2) applies.
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Pin Selection Method and Pin Functions
P11/PO9/TIOCB0/
A21 The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, and bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in
TCR0, bits AE3 to AE0 in PFCR, bit NDER9 in NDERH, and bit P11DDR.
Operating
mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1101 B'1110 to
B'1111
TPU Channel
0 Setting Table
Below (1) Table Below (2) —
P11DDR —011—
NDER9 —— 01—
Pin function TIOCB0
output P11
input P11
output PO9
output A21 output
TIOCB0 input*
Operating
mode Mode 7
AE3 to AE0 —
TPU Channel
0 Setting Table
Below (1) Table Below (2)
P11DDR —011
NDER9 —— 01
Pin function TIOCB0
output P11 input P11 output PO9 output
TIOCB0 input*
Note: *TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 =
B'10xx.
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
TPU Channel
0 Setting (2) (1) (2) (2) (1) (2)
P11/PO9/TIOCB0/
A21 (cont)
MD3 to MD0 B'0000 B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
—B'xx00 Other than B'xx00
CCLR2 to
CCLR0 ————
Other
than
B'010
B'010
Output
function —Output
compare
output
——PWM
mode 2
output
—
x: Don’t care
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
P10/PO8/TIOCA0/
A20 The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0),
bits AE3 to AE0 in PFCR, bit NDER8 in NDERH, and bit P10DDR.
Operating
mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1110 B'1101 to
B'1111
TPU Channel
0 Setting Table
Below (1) Table Below (2) —
P10DDR —011—
NDER8 —— 01—
Pin function TIOCA0
output P10
input P10
output PO8
output A20 output
TIOCA0 input*1
Operating
mode Mode 7
AE3 to AE0 —
TPU Channel
0 Setting Table
Below (1) Table Below (2)
P10DDR —011
NDER8 —— 01
Pin function TIOCA0
output P10 input P10 output PO8 output
TIOCA0 input*1
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
TPU Channel
0 Setting (2) (1) (2) (1) (1) (2)
P10/PO8/TIOCA0/
A20 (cont)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR2 to
CCLR0 ————
Other
than
B'001
B'001
Output
function —Output
compare
output
—PWM
mode 1
output*2
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 =
B'10xx.
2. TIOCB0 output is disabled.
Section 9 I/O Ports
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9.3 Port 4
9.3.1 Overview
Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins
(AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 9.2 shows the port
4 pin configuration.
P47
P46
P45
P44
P43
P42
P41
P40
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
AN7 (input)
AN6 (input)
AN5 (input)
AN4 (input)
AN3 (input)
AN2 (input)
AN1 (input)
AN0 (input)
Port 4 pins
Port 4
Figure 9.2 Port 4 Pin Functions
Section 9 I/O Ports
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9.3.2 Register Configuration
Table 9.4 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a
data direction register or data register.
Table 9.4 Port 4 Registers
Name Abbreviation R/W Initial Value Address*
Port 4 register PORT4 R Undefined H'FFB3
Note: *Lower 16 bits of the address .
Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.
Bit:76543210
P47 P46 P45 P44 P43 P42 P41 P40
Initial value : —*—*—*—*—*—*—*—*
R/W:RRRRRRRR
Note: *Determined by state of pins P47 to P40.
9.3.3 Pin Functions
Port 4 pins also function as A/D converter analog input pins (AN0 to AN7).
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9.4 Port 9
9.4.1 Overview
Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins
(AN8 to AN15) and D/A converter analog output pins (DA3, DA2). Port 9 pin functions are the
same in all operating modes. Figure 9.3 shows the port 9 pin configuration.
P97
P96
P95
P94
P93
P92
P91
P90
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
AN15 (input) / DA3 (output)*
AN14 (input) / DA2 (output)*
AN13 (input)
AN12 (input)
AN11 (input)
AN10 (input)
AN9 (input)
AN8 (input)
Port 9 pins
Port 9
Note: * DA3 and DA2 are outputs in the H8S/2626 Group only.
Figure 9.3 Port 9 Pin Functions
Section 9 I/O Ports
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9.4.2 Register Configuration
Table 9.5 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a
data direction register or data register.
Table 9.5 Port 9 Registers
Name Abbreviation R/W Initial Value Address*
Port 9 register PORT9 R Undefined H'FFB8
Note: *Lower 16 bits of the address .
Port 9 Register (PORT9): The pin states are always read when a port 9 read is performed.
Bit:76543210
P97 P96 P95 P94 P93 P92 P91 P90
Initial value : —*—*—*—*—*—*—*—*
R/W:RRRRRRRR
Note: *Determined by state of pins P97 to P90.
9.4.3 Pin Functions
Port 9 pins also function as A/D converter analog input pins (AN8 to AN15) and D/A converter
analog output pins (DA3, DA2).
9.5 Port A
9.5.1 Overview
Port A is a 6-bit I/O port. Port A pins also function as address bus outputs and SCI2 I/O pins
(SCK2, RxD2, and TxD2). The pin functions change according to the operating mode.
Port A has a built-in MOS input pull-up function that can be controlled by software.
Figure 9.4 shows the port A pin configuration.
Section 9 I/O Ports
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PA5*
PA4*
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
Port A pins
Pin functions in mode 7
PA5 (I/O)
PA4 (I/O)
PA3 (I/O) / A19 (output) / SCK2 (I/O)
PA2 (I/O) / A18 (output) / RxD2 (input)
PA1 (I/O) / A17 (output) / TxD2 (output)
PA0 (I/O) / A16 (output)
Pin functions in modes 4 to 6
PA5 (I/O)
PA4 (I/O)
PA3 (I/O) / SCK2 (output)
PA2 (I/O) / RxD2 (input)
PA1 (I/O) / TxD2 (output)
PA0 (I/O)
Port A
Note: * In the H8S/2626 Series, PA5 and PA4 are OSC2 and OSC1, respectively.
Figure 9.4 Port A Pin Functions
9.5.2 Register Configuration
Table 9.6 shows the port A register configuration.
Table 9.6 Port A Registers
Name Abbreviation R/W Initial Value*2Address*1
Port A data direction register PADDR W H'0 H'FE39
Port A data register PADR R/W H'0 H'FF09
Port A register PORTA R Undefined H'FFB9
Port A MOS pull-up control register PAPCR R/W H'0 H'FE40
Port A open-drain control register PAODR R/W H'0 H'FE47
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
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Port A Data Direction Register (PADDR)
Bit:76543210
——
PA5DDR*PA4DDR*PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : Undefined Undefined 000000
R/W : ——WWWWWW
Note: *In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
read.
PADDR is an 8-bit write-o nly register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 and 6 ar e r e ser ved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode. The OPE bit in SBYCR is used to select whether the addr ess
output pins retain their output state or become high-impedance when a transition is made to
software standby mode.
• Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, ir respective of the value of bits PA5DDR to PA0DDR. When pin s are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PADDR bit to 1 mak es the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Port A Data Register (PADR)
Bit:76543210
——PA5DR*PA4DR*PA3DR PA2DR PA1DR PA0DR
Initial value : Undefined Undefined 000000
R/W : ——R/W R/W R/W R/W R/W R/W
Note: *In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
read.
Section 9 I/O Ports
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PADR is an 8-b it r eadable/writable register that sto res output data for the port A pins (PA5 to
PA0).
Bits 7 and 6 are reserved; they return an undeterm ined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 5 to 0 ) by a reset, and in hardware standby mode. It re tains its
prior state in software standby mode.
Port A Register (PORTA)
Bit:76543210
——PA5*2PA4*2PA3 PA2 PA1 PA0
Initial value : Undefined Undefined —*1—*1—*1—*1—*1—*1
R/W : ——RRRRRR
Notes: 1. Determined by state of pins PA5 to PA0.
2. In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
read.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA5 to PA0) must always be performed on PADR.
Bits 7 and 6 are reserved; they return an undeterm ined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as
PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.
Port A MOS Pull-Up Control Register (PAPCR)
Bit:76543210
——
PA5PCR*PA4PCR*PA3PCR PA2PCR PA1PCR PA0PCR
Initial value : Undefined Undefined 000000
R/W : ——R/W R/W R/W R/W R/W R/W
Note: *In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
read.
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
Section 9 I/O Ports
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Bits 7 and 6 are r e ser ved; they return an undetermined valu e if read, and cannot be modif ied . In
modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
PAPCR is initialized to H'0 (bits 5 to 0) by a reset, and in har dware standby mode. It retains its
prior state in software standby mode.
Port A Open Drain Control Register (PAODR)
Bit:76543210
——
PA5ODR*PA4ODR*PA3ODR PA2ODR PA1ODR PA0ODR
Initial value : Undefined Undefined 000000
R/W : ——R/W R/W R/W R/W R/W R/W
Note: *In the H8S/2626 Group bits 5 and 4 are reserved, and will return an undefined value if
read.
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA5 to PA0).
Bits 7 and 6 are reserved; they return an undeterm ined value if read, and cannot be modified.
When pins are not address outputs in acco rdan ce with the setting of bits AE3 to AE0 in PFCR,
setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Section 9 I/O Ports
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9.5.3 Pin Functions
Port A pins also function as SCI input/outpu t pins (TxD2, RxD2, SCK2) and address bus output
pins (A19 to A16). Port A pin functions are shown in table 9.7.
Table 9.7 Port A Pin F unctions
Pin Selection Method and Pin Functions
PA5*The pin function is switched as shown below according to bit PA5DDR.
PA5DDR 0 1
Pin function PA5 input PA5 output
Note: *In the H8S/2626 Group, PA5 is OSC2.
PA4*The pin function is switched as shown below according to bit PA4DDR.
PA4DDR 0 1
Pin function PA4 input PA4 output
Note: *In the H8S/2626 Group, PA4 is OSC1.
PA3/A19/SCK2 The pin function is switched as shown below according to the operating mode,
bits AE3 to AE0 in PFCR, bit C/A in SMR and bits CKE0 and CKE1 in SCR of
SCI2, and bit PA3DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1011 B'1100 to B'1111
CKE1 0 1 —
C/A01——
CKE0 0 1 —— —
PA3DDR 0 1 ——— —
Pin function PA3
input PA3
output SCK2
output SCK2
output SCK2
input A19 output
Operating mode Mode 7
CKE1 0 1
C/A01—
CKE0 0 1 ——
PA3DDR 0 1 ———
Pin function PA3
input PA3
output SCK2
output SCK2
output SCK2
input
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Pin Selection Method and Pin Functions
PA2/A18/RxD2 The pin function is switched as shown below according to the operating mode,
bits AE3 to AE0 in PFCR, bit RE in SCR of SCI2, and bit PA2DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1011 B'1011 to B'1111
RE 0 1 —
PA2DDR 0 1 ——
Pin function PA2 input PA2 output RxD2 input A18 output
Operating mode Mode 7
RE 0 1
PA2DDR 0 1 —
Pin function PA2 input PA2 output RxD2 input
PA1/A17/TxD2 The pin function is switched as shown below according to the operating mode,
bits AE3 to AE0 in PFCR, bit TE in SCR of SCI2, and bit PA1DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1001 B'1010 to B'1111
TE 0 1 —
PA1DDR 0 1 ——
Pin function PA1 input PA1 output TxD2 output A17 output
Operating mode Mode 7
TE 0 1
PA1DDR 0 1 —
Pin function PA1 input PA1 output TxD2 output
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Pin Selection Method and Pin Functions
PA0/A16 The pin function is switched as shown below according to the operating mode,
bits AE3 to AE0 in PFCR, and bit PA0DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'1000 B'1001 to B'1111
PA0DDR 0 1 —
Pin function PA0 input PA0 output A16 output
Operating mode Mode 7
PA0DDR 0 1
Pin function PA0 input PA0 output
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9.5.4 MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be sp ecified as on or off on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
The prior state is retained in software stan dby mode.
Table 9.8 summarizes the MOS input pull-up states.
Table 9.8 MOS Input Pull-Up States ( Port A)
Pin States Power-On
Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
Address output or
SCI output OFF OFF OFF OFF
Other than above ON/OFF ON/OFF
Legend:
OFF : MOS input pull-up is always off.
ON/OFF : On when PADDR = 0 and PAPCR = 1; otherwise off.
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9.6 Port B
9.6.1 Overview
Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5) and as address outputs; the pin
functions change according to the operating mode.
Port B has a built-in MOS input pull-up function that can be controlled by software.
Figure 9.5 shows the port B pin configuration.
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9 /TIODB3
PB0/A8 /TIOCA3
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
A15
A14
A13
A12
A11
A10
A9
A8
(output) / TIOCB5 (I/O)
(output) / TIOCA5 (I/O)
(output) / TIOCB4 (I/O)
(output) / TIOCA4 (I/O)
(output) / TIOCD3 (I/O)
(output) / TIOCC3 (I/O)
(output) / TIOCB3 (I/O)
(output) / TIOCA3 (I/O)
Port B pins
Pin functions in mode 7
Pin functions in modes 4 to 6
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
(I/O) / TIOCB5 (I/O)
(I/O) / TIOCA5 (I/O)
(I/O) / TIOCB4 (I/O)
(I/O) / TIOCA4 (I/O)
(I/O) / TIOCD3 (I/O)
(I/O) / TIOCC3 (I/O)
(I/O) / TIOCB3 (I/O)
(I/O) / TIOCA3 (I/O)
Port B
Figure 9.5 Port B Pin Functions
Section 9 I/O Ports
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9.6.2 Register Configuration
Table 9.9 shows the port B register configuration.
Table 9.9 Port B Registers
Name Abbreviation R/W Initial Value Address*
Port B data direction register PBDDR W H'00 H'FE3A
Port B data register PBDR R/W H'00 H'FF0A
Port B register PORTB R Undefined H'FFBA
Port B MOS pull-up control register PBPCR R/W H'00 H'FE41
Port B open-drain control register PBODR R/W H'00 H'FE48
Note: *Lower 16 bits of the address .
Port B Data Direction Register (PBDDR)
Bit:76543210
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value:00000000
R/W:WWWWWWWW
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 4 to 6
The corresponding port B pins become addr ess outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as
address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port,
while clearing th e bit to 0 makes the pin an input p ort.
• Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
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Port B Data Register (PBDR)
Bit:76543210
PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBDR is initialized to H'00 by a reset, and in hardware stan dby mode. It retains its prior
state in software standby mode.
Port B Register (PORTB)
Bit:76543210
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Initial value : —*—*—*—*—*—*—*—*
R/W:RRRRRRRR
Note: *Determined by state of pins PB7 to PB0.
PORTB is an 8 -bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB7 to PB0) must always be performed on PBDR.
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B
read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as
PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode.
Port B MOS Pull-Up Control Register (PBPCR)
Bit:76543210
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port B on an individual bit basis.
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In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s
TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for
that pin.
In mode 7, if a pin is in the input state in accord ance with the settings in the TPU’s TIOR and in
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
PBPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its pr ior state in
software standby mode.
Port B Open Drain Control Register (PBODR)
Bit:76543210
PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B
pin (PB7 to PB0).
When pins are not address outputs in acco rdan ce with the setting of bits AE3 to AE0 in PFCR,
setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PBODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
9.6.3 Pin Functions
Port B pins also function as TPU input/output pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3,
TIOCA4, TIOCB4, TIOCA5, TIOCB5) and address bus output pins (A15 to A8). Port B pin
functions are shown in table 9.10.
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Table 9.10 Po rt B Pin Functions
Pin Selection Method and Pin Functions
PB7/A15/
TIOCB5 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR5, bits
IOB3 to IOB0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5, and bit PB7DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'0111 B'1000 to B'1111
TPU channel 5
settings (1) in table
below (2) in table
below —
PB7DDR —01 —
Pin function TIOCB5 output PB7 input PB7 output A15 output
TIOCB5 input*
Operating mode Mode 7
TPU channel 5
settings (1) in table below (2) in table below
PB7DDR —01
Pin function TIOCB5 output PB7 input PB7 output
TIOCB5 input*
TPU channel 5
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
—B'xx00 Not B'xx00
CCLR1, CCLR0 ————Not B'10 B'10
Output function —Output
compare
output
——PWM
mode 2
output
—
x: Don’t care
Note: *TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1.
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Pin Selection Method and Pin Functions
PB6/A14/
TIOCA5 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR5, bits
IOA3 to IOA0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5, and bit PB6DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'0110 B'0111 to B'1111
TPU channel 5
settings (1) in table
below (2) in table
below —
PB6DDR —01 —
Pin function TIOCA5 output PB6 input PB6 output A14 output
TIOCA5 input*1
Operating mode Mode 7
TPU channel 5
settings (1) in table below (2) in table below
PB6DDR —01
Pin function TIOCA5 output PB6 input PB6 output
TIOCA5 input*1
TPU channel 5
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Not
B'xx00 Not B'xx00
CCLR1, CCLR0 ————Not B'01 B'01
Output function —Output
compare
output
—PWM
mode 1
output*2
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1.
2. TIOCB5 is disabled for output.
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Pin Selection Method and Pin Functions
PB5/A13/
TIOCB4 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 4 settings by bits MD3 to MD0 in TMDR4, bits
IOB3 to IOB0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4, and bit PB5DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'0101 B'0110 to B'1111
TPU channel 4
settings (1) in table
below (2) in table
below —
PB5DDR —01 —
Pin function TIOCB4 output PB5 input PB5 output A13 output
TIOCB4 input*
Operating mode Mode 7
TPU channel 4
settings (1) in table below (2) in table below
PB5DDR —01
Pin function TIOCB4 output PB5 input PB5 output
TIOCB4 input*
TPU channel 5
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
—B'xx00 Not B'xx00
CCLR1, CCLR0 ————Not B'10 B'10
Output function 1 Output
compare
output
11PWM
mode 2
output
1
x: Don’t care
Note: *TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 =
B'10xx.
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Pin Selection Method and Pin Functions
PB4/A12/
TIOCA4 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR4, bits
IOA3 to IOA0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4, and bit PB4DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'0100 B'0101 to B'1111
TPU channel 4
settings (1) in table
below (2) in table
below —
PB4DDR —01 —
Pin function TIOCA4 output PB4 input PB4 output A12 output
TIOCA4 input*1
Operating mode Mode 7
TPU channel 4
settings (1) in table below (2) in table below
PB4DDR —01
Pin function TIOCA4 output PB4 input PB4 output
TIOCA4 input*1
TPU channel 4
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Not
B'xx00 Not B'xx00
CCLR1, CCLR0 ————Not B'01 B'01
Output function —Output
compare
output
—PWM
mode 1
output*2
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 =
B'10xx.
2. TIOCB4 is disabled for output.
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Pin Selection Method and Pin Functions
PB3/A11/
TIOCD3 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits
IOD3 to IOD0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3, and bit PB3DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'0011 B'0100 to B'1111
TPU channel 3
settings (1) in table
below (2) in table
below —
PB3DDR —01 —
Pin function TIOCD3 output PB3 input PB3 output A11 output
TIOCD3 input*
Operating mode Mode 7
TPU channel 3
settings (1) in table below (2) in table below
PB3DDR —01
Pin function TIOCD3 output PB3 input PB3 output
TIOCD3 input*
TPU channel 3
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOD3 to IOD0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
—B'xx00 Not B'xx00
CCLR2 to
CCLR0 ————Not B'110 B'110
Output function —Output
compare
output
——PWM
mode 2
output
—
x: Don’t care
Note: *TIOCD3 input when MD3 to MD0 = B'0000 or B'01xx, and IOD3 to IOD0 =
B'10xx.
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Pin Selection Method and Pin Functions
PB2/A10/
TIOCC3 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits
IOC3 to IOC0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3, and bit PB2DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'0010 B'0011 to B'1111
TPU channel 3
settings (1) in table
below (2) in table
below —
PB2DDR —01 —
Pin function TIOCC3 output PB2 input PB2 output A10 output
TIOCC3 input*1
Operating mode Mode 7
TPU channel 3
settings (1) in table below (2) in table below
PB2DDR —01
Pin function TIOCC3 output PB2 input PB2 output
TIOCC3 input*1
TPU channel 3
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Not
B'xx00 Not B'xx00
CCLR2 to
CCLR0 ————Not B'101 B'101
Output function —Output
compare
output
—PWM
mode 1
output*2
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCC3 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx.
2. TIOCD3 is disabled for output.
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Pin Selection Method and Pin Functions
PB1/A9/
TIOCB3 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits
IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3, and bit PB1DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 to B'0001 B'0010 to B'1111
TPU channel 3
settings (1) in table
below (2) in table
below —
PB1DDR —01 —
Pin function TIOCB3 output PB1 input PB1 output A9 output
TIOCB3 input*
Operating mode Mode 7
TPU channel 3
settings (1) in table below (2) in table below
PB1DDR —01
Pin function TIOCB3 output PB1 input PB1 output
TIOCB3 input*
TPU channel 3
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
—B'xx00 Not B'xx00
CCLR2 to
CCLR0 ————Not B'010 B'010
Output function —Output
compare
output
——PWM
mode 2
output
—
x: Don’t care
Note: *TIOCB3 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx.
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Pin Selection Method and Pin Functions
PB0/A8/
TIOCA3 The pin function is switched as shown below according to the operating mode, bits
AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits
IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3, and bit PB0DDR.
Operating mode Modes 4 to 6
AE3 to AE0 B'0000 B'0001 to B'1111
TPU channel 3
settings (1) in table
below (2) in table
below —
PB0DDR —01 —
Pin function TIOCA3 output PB0 input PB0 output A8 output
TIOCA3 input*1
Operating mode Mode 7
TPU channel 3
settings (1) in table below (2) in table below
PB0DDR —01
Pin function TIOCA3 output PB0 input PB0 output
TIOCA3 input*1
TPU channel 3
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Not
B'xx00 Not B'xx00
CCLR2 to
CCLR0 ————Not B'001 B'001
Output function —Output
compare
output
—PWM
mode 1
output*2
PWM
mode 2
output
—
x: Don’t care
Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx.
2. TIOCB3 is disabled for output.
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9.6.4 MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be sp ecified as on or off on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s
TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for
that pin.
In mode 7, if a pin is in the input state in accord ance with the settings in the TPU’s TIOR and in
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
The prior state is retained in software stan dby mode.
Table 9.11 summarizes the MOS input pull-up states.
Table 9.1 1 MOS Input Pull-Up States (Port B)
Pin States Power-On
Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
Address output or
TPU output OFF OFF OFF OFF
Other than above ON/OFF ON/OFF
Legend:
OFF : MOS input pull-up is always off.
ON/OFF : On when PBDDR = 0 and PBPCR = 1; otherwise off.
Section 9 I/O Ports
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9.7 Port C
9.7.1 Overview
Port C is an 8-bit I/O port. Port C has an address bus output function, SCI I/O pins (TxD0, RxD0,
SCK0, TxD1, RxD1 and SCK1), and external interrupt input pins (IRQ4 and IRQ5), and the pin
functions change according to the operating mode.
Port C has a built-in MOS input pull-up function that can be controlled by software.
Figure 9.6 shows the port C pin configuration.
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ4
PC1/A1/RxD0
PC0/A0/TxD0
Port C
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
(input) /
A7
A6
A5
A4
A3
A2
A1
A0
(output)
(output)
(output) / SCK1 (I/O) / IRQ5 (input)
(output) / RxD1 (input)
(output) / TxD1 (output)
(output) / SCK0 (I/O) / IRQ4 (input)
(output) / RxD0 (input)
(output) / TxD0 (output)
Port C pins
Pin functions in mode 6 Pin functions in mode 7
A7
A6
A5
A4
A3
A2
A1
A0
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(output)
Pin functions in modes 4 and 5
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
(I/O)
(I/O)
(I/O) / SCK1 (I/O) / IRQ5 (input)
(I/O) / RxD1 (input)
(I/O) / TxD1 (output)
(I/O) / SCK0 (I/O) / IRQ4 (input)
(I/O) / RxD0 (input)
(I/O) / TxD0 (output)
Figure 9.6 Port C Pin Functions
Section 9 I/O Ports
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9.7.2 Register Configuration
Table 9.12 shows the port C register configuration.
Table 9.12 Port C Registers
Name Abbreviation R/W Initial Value Address*
Port C data direction register PCDDR W H'00 H'FE3B
Port C data register PCDR R/W H'00 H'FF0B
Port C register PORTC R Undefined H'FFBB
Port C MOS pull-up control register PCPCR R/W H'00 H'FE42
Port C open-drain control register PCODR R/W H'00 H'FE49
Note: *Lower 16 bits of the address .
Port C Data Direction Register (PCDDR)
Bit:76543210
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value:00000000
R/W:WWWWWWWW
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. As the SCI is initialized, pin states are determined by the PCDDR and
PCDR specifications. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 4 and 5
The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
• Mode 6
Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while
clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing
the bit to 0 makes the pin an input port.
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Port C Data Register (PCDR)
Bit:76543210
PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to
PC0).
PCDR is initialized to H'00 by a reset, and in hardware standby mod e. It retains its prior state in
software standby mode.
Port C Register (PORTC)
Bit:76543210
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Initial value : —*—*—*—*—*—*—*—*
R/W : RRRRRRRR
Note: *Determined by state of pins PC7 to PC0.
PORTC is an 8 -bit read-only r egister that shows the p in states. It cannot be written to. Writing of
output data for the port C pins (PC7 to PC0) must always be performed on PCDR.
If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C
read is performed while PCDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTC contents are determined by the pin states, as
PCDDR and PCDR are initialized. PORTC retains its prior state in software standby mode.
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Port C MOS Pull-Up Control Register (PCPCR)
Bit:76543210
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port C on an individual bit basis.
In modes 6 and 7, if a pin is in the input state in accordance with the settings in the SCI’s SMR
and SCR, and in PCDDR, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-
up for that pin.
PCPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its pr ior state in
software standby mode.
Port C Open Drain Control Register (PCODR)
Bit:76543210
PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PCODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port C
pin (PC7 to PC0).
If the setting of bits AE3 to AE0 in PFCR is othe r than address output, setting a PCODR bit to 1
makes the corresponding port C pin an NMOS open-drain ou tput, while clearing the bit to 0 makes
the pin a CMOS output.
PCODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state
after a manual reset, and in software standby mode.
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9.7.3 Pin Functions
Port C pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1),
interrupt input pins (IRQ4 and IRQ5), and address bus outputs. The pin functions differ between
modes 4 and 5, mode 6, and mode 7. Port C pin functions are shown in table 9.13.
Table 9.13 Port C P in F unctions
Pin Selection Method and Pin Functions
PC7/A7 The pin function is switched as shown below according to the operating mode
and bit PC7DDR.
Operating
Mode Modes 4
and 5 Mode 6 Mode 7
PC7DDR —0101
Pin function A7
output PC7
input A7
output PC7
input PC7
output
PC6/A6 The pin function is switched as shown below according to the operating mode
and bit PC6DDR.
Operating
Mode Modes 4
and 5 Mode 6 Mode 7
PC6DDR —0101
Pin function A6
output PC6
input A6
output PC6
input PC6
output
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Pin Selection Method and Pin Functions
PC5/A5/SCK1/
IRQ5 The pin function is switched as shown below according to the operating mode,
bit C/A in the SCI1’s SMR, bits CKE0 and CKE1 in SCR, and bit PC5DDR.
Operating
Mode Modes 4
and 5 Mode 6
PC5DDR —01
CKE1 —01—
C/A—01——
CKE0 —01———
Pin function A5
output PC5
input SCK1
output SCK1
output SCK1
input A5
output
IRQ5 input
Operating
Mode Mode 7
CKE1 0 1
C/A01—
CKE0 0 1 ——
PC5DDR 0 1 ———
Pin function PC5
input PC5
output SCK1
output SCK1
output SCK1
input
IRQ5 input
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Pin Selection Method and Pin Functions
PC4/A4/RxD1 The pin function is switched as shown below according to the operating mode,
bit RE in the SCI1’s SCR, and bit PC4DDR.
Operating
Mode Modes 4
and 5 Mode 6
PC4DDR —01
RE —01—
Pin function A4 output PC4 input RxD1 input A4 output
Operating
Mode Mode 7
RE 0 1
PC4DDR 0 1 —
Pin function PC4 input PC4 output RxD1 input
PC3/A3/TxD1 The pin function is switched as shown below according to the operating mode,
bit TE in the SCI1’s SCR, and bit PC3DDR.
Operating
Mode Modes 4
and 5 Mode 6
PC3DDR —01
TE —01—
Pin function A3 output PC3 input TxD1 output A3 output
Operating
Mode Mode 7
TE 0 1
PC3DDR 0 1 —
Pin function PC3 input PC3 output TxD1 output
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Pin Selection Method and Pin Functions
PC2/A2/SCK0/
IRQ4 The pin function is switched as shown below according to the operating mode,
bit C/A in the SCI0’s SMR, bits CKE0 and CKE1 in SCR, and bit PC2DDR.
Operating
Mode Modes 4
and 5 Mode 6
PC2DDR —01
CKE1 —01—
C/A—01——
CKE0 —01———
Pin function A2
output PC2
input SCK0
output SCK0
output SCK0
input A2
output
IRQ4 input
Operating
Mode Mode 7
CKE1 0 1
C/A01—
CKE0 0 1 ——
PC2DDR 0 1 ———
Pin function PC2
input PC2
output SCK0
output SCK0
output SCK0
input
IRQ4 input
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Pin Selection Method and Pin Functions
PC1/A1/RxD0 The pin function is switched as shown below according to the operating mode,
bit RE in the SCI0’s SCR, and bit PC1DDR.
Operating
Mode Modes 4
and 5 Mode 6
PC1DDR —01
RE —01—
Pin function A1 output PC1 input RxD0 input A1 output
Operating
Mode Mode 7
RE 0 1
PC1DDR 0 1 —
Pin function PC1 input PC1 output RxD0 input
PC0/A0/TxD0 The pin function is switched as shown below according to the operating mode,
bit TE in the SCI0’s SCR, and bit PC0DDR.
Operating
Mode Modes 4
and 5 Mode 6
PC0DDR —01
TE —01—
Pin function A0 output PC0 input TxD0 output A0 output
Operating
Mode Mode 7
TE 0 1
PC0DDR 0 1 —
Pin function PC0 input PC0 output TxD0 output
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9.7.4 MOS Input Pull-Up Function
Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an
individual bit basis.
In modes 6 and 7, if a pin is in the input state in accordance with the settings in the SCI’s SMR
and SCR, of pins IRQ4 and IRQ5, and in PCDDR, setting the corresponding PCPCR bit to 1 turns
on the MOS input pull-up for that p in.
The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
The prior state is retained in software stan dby mode.
Table 9.14 summarizes the MOS input pull-up states.
Table 9.1 4 MOS Input Pull-Up States (P ort C)
Pin States Power-On
Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
Address output OFF OFF OFF OFF
Other than above ON/OFF ON/OFF
Legend:
OFF : MOS input pull-up is always off.
ON/OFF : On when PCDDR = 0 and PCPCR = 1; otherwise off.
Section 9 I/O Ports
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9.8 Port D
9.8.1 Overview
Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change
according to the operating mode.
Port D has a built-in MOS input pull-up function that can be controlled by software.
Figure 9.7 shows the port D pin configuration.
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Port D
D15
D14
D13
D12
D11
D10
D9
D8
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
Port D pins Pin functions in modes 4 to 6
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
Pin functions in mode 7
Figure 9.7 Port D Pin Functions
Section 9 I/O Ports
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9.8.2 Register Configuration
Table 9.15 shows the port D register configuration.
Table 9.15 Port D Registers
Name Abbreviation R/W Initial Value Address*
Port D data direction register PDDDR W H'00 H'FE3C
Port D data register PDDR R/W H'00 H'FF0C
Port D register PORTD R Undefined H'FFBC
Port D MOS pull-up control register PDPCR R/W H'00 H'FE43
Note: *Lower 16 bits of the address .
Port D Data Direction Register (PDDDR)
Bit:76543210
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value:00000000
R/W:WWWWWWWW
PDDDR is an 8-bit write-o nly register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'0 0 by a reset, and in hardware standby mod e . It retains its prior state in
software standby mode.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Mode 7
Setting a PDDDR bit to 1 mak es the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
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Port D Data Register (PDDR)
Bit:76543210
PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PDDR is an 8-b it r eadable/writable register that sto res output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port D Register (PORTD)
Bit:76543210
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Initial value : —*—*—*—*—*—*—*—*
R/W : RRRRRRRR
Note: *Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D
read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as
PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode.
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Port D MOS Pull-Up Control Register (PDPCR)
Bit:76543210
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port D on an individual bit basis.
When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding
PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
PDPCR is initialized to H'00 b y a reset, and in hardware stand by m ode . I t retains its prior state in
software standby mode.
9.8.3 Pin Functions
In modes 4 to 6, port D pins automatically function as data bus input/output pins (D15 to D8). In
mode 7, each pin in port D functions as an input/output port, and input or output can be specified
individually for each pin. Port D pin functions are shown in table 9.16.
Table 9.16 Port D P in F unctions
Pin Selection Method and Pin Functions
The pin function is switched as shown below according to the operating mode and
PDDDR.
Operating mode Modes 4 to 6 Mode 7
PDnDDR —01
Pin function Data bus input/
output
(D15 to D8)
PDn input PDn output
PD7/D15,
PD6/D14,
PD5/D13,
PD4/D12,
PD3/D11,
PD2/D10,
PD1/D9,
PD0/D8
n = 7 to 0
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9.8.4 MOS Input Pull-Up Function
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in mode 7, and can be sp ecified as on or off on an individual bit
basis.
When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR b it to 1 turns on
the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
The prior state is retained in software stan dby mode.
Table 9.17 summarizes the MOS input pull-up states.
Table 9.1 7 MOS Input Pull-Up States (P ort D)
Modes Power-On
Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
4 to 6 OFF OFF OFF OFF
7 ON/OFF ON/OFF
Legend:
OFF : MOS input pull-up is always off.
ON/OFF : On when PDDDR = 0 and PDPCR = 1; otherwise off.
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9.9 Port E
9.9.1 Overview
Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change
according to the operating mode and whether 8-bit or 16-bit bus mode is selected.
Port E has a bu ilt-in MOS input pull-up fun ction that can be controlled by sof twar e.
Figure 9.8 shows the port E pin configuration.
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
(I/O) /
Port E pins Pin functions in modes 4 to 6
Pin functions in mode 7
D7
D6
D5
D4
D3
D2
D1
D0
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
(I/O)
Port E
Figure 9.8 Port E Pin Functions
Section 9 I/O Ports
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9.9.2 Register Configuration
Table 9.18 shows the port E register configuration.
Table 9.18 Port E Registers
Name Abbreviation R/W Initial Value Address*
Port E data direction register PEDDR W H'00 H'FE3D
Port E data register PEDR R/W H'00 H'FF0D
Port E register PORTE R Undefined H'FFBD
Port E MOS pull-up control register PEPCR R/W H'00 H'FE44
Note: *Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
Bit:76543210
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value:00000000
R/W:WWWWWWWW
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 4 to 6
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 7, Bus Controller.
• Mode 7
Setting a PEDDR bit to 1 makes the corresponding port E pin an outpu t port, while clearing the
bit to 0 m a kes the pin an input port.
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Port E Data Register (PEDR)
Bit:76543210
PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to
PE0).
PEDR is initialized to H'00 by a reset, and in hardware standby mode. I t r etains its prior state in
software standby mode.
Port E Register (PORTE)
Bit:76543210
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Initial value : —*—*—*—*—*—*—*—*
R/W : RRRRRRRR
Note: *Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a port E read is perfor med while PEDDR bits are set to 1, the PEDR values are read. If a port E
read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as
PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.
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Port E MOS Pull-Up Control Register (PEPCR)
Bit:76543210
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PEPCR is an 8-bit readable/writab le r e gister that controls the MOS input pull-up function
incorporated into port E on an individual bit basis.
When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in modes 4 to
6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the
correspondi ng pin.
PEPCR is initia lized to H'00 b y a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
9.9.3 Pin Functions
Port E pins also function as data bus input/output pins (D7 to D0). If at least one of areas 0 to 7 is
designated as 16-bit bus space in modes 4 to 6, port E pins automatically function as data bus
input/output pins. If all areas are designated as 8-bit bu s space in modes 4 to 6, or in mode 7, each
pin in port E functions as an input/output port, and input or output can be specified individually
for each pin. Port E pin functions are shown in table 9.19.
Table 9.19 Po rt E Pin Functions
Pin Selection Method and Pin Functions
The pin function is switched as shown below according to the operating mode,
ABWCR in the bus controller, and PEDDR.
Operating mode Modes 4 to 6 Mode 7
ABWCR H'FF Not H'FF ——
PEnDDR 0 1 —01
Pin function PEn input PEn output Data bus
input/output
(D7 to D0)
PEn input PEn output
PE7/D7,
PE6/D6,
PE5/D5,
PE4/D4,
PE3/D3,
PE2/D2,
PE1/D1,
PE0/D0
n = 7 to 0
Section 9 I/O Ports
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9.9.4 MOS Input Pull-Up Function
Port E has a bu ilt- in MOS input pull-up func tio n that can be controlled by software. This MOS
input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7,
and can be specified as on or off on an individual bit basis.
When a PEDDR bit is cleared to 0 in modes 4 to 6 when 8-bit bus mode is selected , o r in m ode 7,
setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
The prior state is retained in software stan dby mode.
Table 9.20 summarizes the MOS input pull-up states.
Table 9.2 0 MOS Input Pull-Up States (Port E)
Modes Power-On
Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
7 OFF OFF ON/OFF ON/OFF
4 to 6 8-bit bus
16-bit bus OFF OFF
Legend:
OFF : MOS input pull-up is always off.
ON/OFF : On when PEDDR = 0 and PEPCR = 1; otherwise off.
Section 9 I/O Ports
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9.10 Port F
9.10.1 Overview
Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and
IRQ3), BUZZ output pin*, A/D trigger input pin (ADTRG), bus control signal input/output pins
(AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin.
Note: * BUZZ output pin in the H8S/2626 Group only.
Figure 9.9 shows the port F pin configuration.
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/WAIT/BREQO
PF1/BACK/BUZZ*
PF0/BREQ/IRQ2
Port F
Port F pins
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
(input) / ø (output)
(I/O)
(I/O)
(I/O)
(I/O) / ADTRG (input) / IRQ3 (input)
(I/O)
(I/O) / BUZZ (output)*
(I/O) / IRQ2 (input)
Pin functions in mode 7
PF7 (input) / φ (output)
AS (output)
RD (output)
HWR (output)
PF3 (I/O) / LWR (output) / ADTRG (input) / IRQ3 (input)
PF2 (I/O) /WAIT (input) / BREQO (output)
PF1 (I/O) / BACK (output) / BUZZ (output)*
PF0 (I/O) / BREQ (input) / IRQ2 (input)
Pin functions in modes 4 to 6
Note: * BUZZ output pin in the H8S/2626 Group only.
Figure 9.9 Port F Pin Functions
Section 9 I/O Ports
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9.10.2 Register Configuration
Table 9.21 shows the port F register configuration.
Table 9.21 Port F Registers
Name Abbreviation R/W Initial Value Address*1
Port F data direction register PFDDR W H'80/H'00*2H'FE3E
Port F data register PFDR R/W H'00 H'FF0E
Port F register PORTF R Undefined H'FFBE
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit:76543210
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6
Initial value:10000000
R/W:WWWWWWWW
Mode 7
Initial value:00000000
R/W:WWWWWWWW
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware stan dby mod e , to H'80 in modes 4 to 6, and to
H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used
to select whether the bus control output pins retain their output state or become high-impedance
when a transition is made to software standby mode.
• Modes 4 to 6
Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BREQO, BACK,
Section 9 I/O Ports
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BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes
the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input
port.
• Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the φ output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit:76543210
—PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'0 0 by a reset, and in hard ware standby mode. It retains its prior state in
software standby mode.
Bit 7 in PFDR is re ser ved, and only 0 may be written to it.
Port F Register (PORTF)
Bit:76543210
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
Initial value : —*—*—*—*—*—*—*—*
R/W:RRRRRRRR
Note: *Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as
PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.
Section 9 I/O Ports
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9.10.3 Pin Functions
Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin*,
A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR,
WAIT, BREQO, BREQ, and BACK) and the system clock (φ) out put pi n. The pin functi o ns differ
between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9.22.
Note: * BUZZ output pin in the H8S/2626 Group only.
Table 9.22 Port F Pin Functions
Pin Selection Method and Pin Functions
PF7/φThe pin function is switched as shown below according to bit PF7DDR.
PF7DDR 0 1
Pin function PF7 input φ output
PF6/AS The pin function is switched as shown below according to the operating mode
and bit PF6DDR.
Operating
Mode Modes 4 to 6 Mode 7
PF6DDR —01
Pin function AS output PF6 input PF6 output
PF5/RD The pin function is switched as shown below according to the operating mode
and bit PF5DDR.
Operating
Mode Modes 4 to 6 Mode 7
PF5DDR —01
Pin function RD output PF5 input PF5 output
PF4/HWR The pin function is switched as shown below according to the operating mode
and bit PF4DDR.
Operating
Mode Modes 4 to 6 Mode 7
PF4DDR —01
Pin function HWR output PF4 input PF4 output
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Pin Selection Method and Pin Functions
PF3/LWR/
ADTRG/IRQ3 The pin function is switched as shown below according to the operating mode,
the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR.
Operating
Mode Modes 4 to 6 Mode 7
Bus mode 16-bit bus
mode 8-bit bus mode —
PF3DDR —0101
Pin function LWR PF3 input PF3 output PF3 input PF3 output
output ADTRG input∗1
IRQ3 input∗2
Notes: 1. ADTRG input when TRGS0 = TRGS1 = 1.
2. When used as an external interrupt input pin, do not use as an I/O
pin for another function.
PF2/WAIT/
BREQO The pin function is switched as shown below according to the combination of
the operating mode, and bi ts BREQOE, WAITE, ABW5 to ABW2, and
PF2DDR.
Operating
Mode Modes 4 to 6 Mode 7
BREQOE 0 1 —
WAITE 0 1 ——
PF2DDR 0 1 —— 01
Pin function PF2
input PF2
output WAIT
input BREQO
output PF2
input PF2
output
PF1/BACK/
BUZZ*The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE, BUZZE, and PF1DDR.
Operating
Mode Modes 4 to 6 Mode 7
BRLE 0 1 —
BUZZE 0 1 —01
PF1DDR 0 1 —— 01—
Pin function PF1
input PF1
output BUZZ*
output BACK
output PF1
input PF1
output BUZZ*
output
Note: *BUZZ output pin in the H8S/2626 Group only.
Section 9 I/O Ports
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Pin Selection Method and Pin Functions
PF0/BREQ/IRQ2 The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF0DDR.
Operating
Mode Modes 4 to 6 Mode 7
BRLE 0 1 —
PF0DDR 0 1 —01
Pin function PF0
input PF0
output BREQ
input PF0
input PF0
output
IRQ2 input
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 285 of 1042
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.1 Overview
The H8S/2626 Group and H8S/2623 Group have an on-chip 16-bit timer pulse unit (TPU) that
comprises six 16-bit timer channels.
10.1.1 Features
• Maximum 16-pulse input/output
A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
Waveform output at compare match: Selection of 0, 1, or toggle output
Input capture function: Selection of rising edge, falling edge, or both edge detection
Counter clear operation: Counter clearing possible by compare match or input capture
Synchronous operation:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
PWM mode: Any PWM output duty can be set
Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
Input capture register double-buffering possible
Automatic rewriting of output compare register possible
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
Two-phase encoder pulse up/down-count possible
• Cascaded operation
Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel
4) overflow/underflow
• Fast access via internal 16-bit bus
Fast access is possible via a 16-bit bus interface
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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• 26 interrupt sources
For channels 0 and 3, four compare match/input capture dual-function interrupts and one
overflow interrupt can be requested independently
For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one
overflow interrupt, and one underflow interrupt can be requested independently
• Automatic tran sf er of r egister data
Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer
controller (DTC)
• Programmable pulse generator (PPG) output trigger can be generated
Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger
• A/D converter conversion start trigger can be generated
Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter
conversion start trigger
• Module stop mode can be set
As the initial setting, TPU operation is halted. Register access is enabled by exiting module
stop mode.
Table 10.1 lists the functions of the TPU.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 287 of 1042
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Table 10.1 TPU Functions
Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKC
TCLKD
General registers TGR0A
TGR0B TGR1A
TGR1B TGR2A
TGR2B TGR3A
TGR3B TGR4A
TGR4B TGR5A
TGR5B
General registers/
buffer registers TGR0C
TGR0D ——TGR3C
TGR3D ——
I/O pins TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1 TIOCA2
TIOCB2 TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4 TIOCA5
TIOCB5
Counter clear
function TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
0 output
1 output
Compare
match
output Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode — —
Buffer operation —— ——
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 288 of 1042
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Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
DTC
activation TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
A/D
converter
trigger
TGR0A
compare
match or
input capture
TGR1A
compare
match or
input capture
TGR2A
compare
match or
input capture
TGR3A
compare
match or
input capture
TGR4A
compare
match or
input capture
TGR5A
compare
match or
input capture
PPG
trigger TGR0A/
TGR0B
compare
match or
input capture
TGR1A/
TGR1B
compare
match or
input capture
TGR2A/
TGR2B
compare
match or
input capture
TGR3A/
TGR3B
compare
match or
input capture
——
Interrupt
sources 5 sources
• Compare
match or
input
capture 0A
• Compare
match or
input
capture 0B
• Compare
match or
input
capture 0C
• Compare
match or
input
capture 0D
•Overflow
4 sources
• Compare
match or
input
capture 1A
• Compare
match or
input
capture 1B
•Overflow
• Underflow
4 sources
• Compare
match or
input
capture 2A
• Compare
match or
input
capture 2B
•Overflow
• Underflow
5 sources
• Compare
match or
input
capture 3A
• Compare
match or
input
capture 3B
• Compare
match or
input
capture 3C
• Compare
match or
input
capture 3D
•Overflow
4 sources
• Compare
match or
input
capture 4A
• Compare
match or
input
capture 4B
•Overflow
• Underflow
4 sources
• Compare
match or
input
capture 5A
• Compare
match or
input
capture 5B
•Overflow
• Underflow
Legend:
: Possible
— : Not possible
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 289 of 1042
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10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the TPU.
Channel 3
TMDR
TIORL
TSR
TCR
TIORH
TIER
TGRA
TCNT
TGRB
TGRC
TGRD
Channel 4
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Control logic TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Control logic for channels 3 to 5
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TGRC
Channel 1
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Channel 0
TMDR
TSR
TCR
TIORH
TIER
Control logic for channels 0 to 2
TGRA
TCNT
TGRB
TGRD
TSYRTSTR
Input/output pins
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Clock input
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Interrupt request signals
Channel 3:
Channel 4:
Channel 5:
Interrupt request signals
Channel 0:
Channel 1:
Channel 2:
Internal data bus
PPG output trigger signal
A/D converter convertion start signal
TIORL
Module data bus
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TCI4V
TCI4U
TGI5A
TGI5B
TCI5V
TCI5U
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
Channel 3:
Channel 4:
Channel 5:
Internal clock:
External clock:
Channel 0:
Channel 1:
Channel 2:
Legend:
TSTR: Timer start register
TSYR: Timer synchro register
TCR: Timer control register
TMDR: Timer mode register
TIOR (H, L): Timer I/O control registers (H, L)
TIER: Timer interrupt enable register
TSR: Timer status register
TGR (A, B, C, D): Timer general registers (A, B, C, D)
Channel 2 Common Channel 5
Bus interface
Figure 10.1 Block Diagram of TPU
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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10.1.3 Pin Configuration
Table 10.2 summarizes the TPU pins.
Table 10.2 TPU Pins
Channel Name Symbol I/O Function
All Clock input A TCLKA Input External clock A input pin
(Channels 1 and 5 phase counting mode A
phase input)
Clock input B TCLKB Input External clock B input pin
(Channels 1 and 5 phase counting mode B
phase input)
Clock input C TCLKC Input External clock C input pin
(Channels 2 and 4 phase counting mode A
phase input)
Clock input D TCLKD Input External clock D input pin
(Channels 2 and 4 phase counting mode B
phase input)
0 Input capture/ out
compare match A0 TIOCA0 I/O TGR0A input capture input/output compare
output/PWM output pin
Input capture/ out
compare match B0 TIOCB0 I/O TGR0B input capture input/output compare
output/PWM output pin
Input capture/ out
compare match C0 TIOCC0 I/O TGR0C input capture input/output compare
output/PWM output pin
Input capture/ out
compare match D0 TIOCD0 I/O TGR0D input capture input/output compare
output/PWM output pin
1 Input capture/ out
compare match A1 TIOCA1 I/O TGR1A input capture input/output compare
output/PWM output pin
Input capture/ out
compare match B1 TIOCB1 I/O TGR1B input capture input/output compare
output/PWM output pin
2 Input capture/ out
compare match A2 TIOCA2 I/O TGR2A input capture input/output compare
output/PWM output pin
Input capture/ out
compare match B2 TIOCB2 I/O TGR2B input capture input/output compare
output/PWM output pin
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Name Symbol I/O Function
3 Input capture/ out
compare match A3 TIOCA3 I/O TGR3A input capture input/output compare
output/PWM output pin
Input capture/ out
compare match B3 TIOCB3 I/O TGR3B input capture input/output compare
output/PWM output pin
Input capture/ out
compare match C3 TIOCC3 I/O TGR3C input capture input/output compare
output/PWM output pin
Input capture/ out
compare match D3 TIOCD3 I/O TGR3D input capture input/output compare
output/PWM output pin
4 Input capture/ out
compare match A4 TIOCA4 I/O TGR4A input capture input/output compare
output/PWM output pin
Input capture/ out
compare match B4 TIOCB4 I/O TGR4B input capture input/output compare
output/PWM output pin
5 Input capture/ out
compare match A5 TIOCA5 I/O TGR5A input capture input/output compare
output/PWM output pin
Input capture/ out
compare match B5 TIOCB5 I/O TGR5B input capture input/output compare
output/PWM output pin
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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10.1.4 Register Configuration
Table 10.3 summarizes the TPU registers.
Table 10.3 TPU Registers
Channel Name Abbreviation R/W Initial Value Address*1
0 Timer control register 0 TCR0 R/W H'00 H'FF10
Timer mode register 0 TMDR0 R/W H'C0 H'FF11
Timer I/O control register 0H TIOR0H R/W H'00 H'FF12
Timer I/O control register 0L TIOR0L R/W H'00 H'FF13
Timer interrupt enable register 0 TIER0 R/W H'40 H'FF14
Timer status register 0 TSR0 R/(W)*2H'C0 H'FF15
Timer counter 0 TCNT0 R/W H'0000 H'FF16
Timer general register 0A TGR0A R/W H'FFFF H'FF18
Timer general register 0B TGR0B R/W H'FFFF H'FF1A
Timer general register 0C TGR0C R/W H'FFFF H'FF1C
Timer general register 0D TGR0D R/W H'FFFF H'FF1E
1 Timer control register 1 TCR1 R/W H'00 H'FF20
Timer mode register 1 TMDR1 R/W H'C0 H'FF21
Timer I/O control register 1 TIOR1 R/W H'00 H'FF22
Timer interrupt enable register 1 TIER1 R/W H'40 H'FF24
Timer status register 1 TSR1 R/(W)*2H'C0 H'FF25
Timer counter 1 TCNT1 R/W H'0000 H'FF26
Timer general register 1A TGR1A R/W H'FFFF H'FF28
Timer general register 1B TGR1B R/W H'FFFF H'FF2A
2 Timer control register 2 TCR2 R/W H'00 H'FF30
Timer mode register 2 TMDR2 R/W H'C0 H'FF31
Timer I/O control register 2 TIOR2 R/W H'00 H'FF32
Timer interrupt enable register 2 TIER2 R/W H'40 H'FF34
Timer status register 2 TSR2 R/(W)*2H'C0 H'FF35
Timer counter 2 TCNT2 R/W H'0000 H'FF36
Timer general register 2A TGR2A R/W H'FFFF H'FF38
Timer general register 2B TGR2B R/W H'FFFF H'FF3A
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 293 of 1042
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Channel Name Abbreviation R/W Initial Value Address*1
3 Timer control register 3 TCR3 R/W H'00 H'FE80
Timer mode register 3 TMDR3 R/W H'C0 H'FE81
Timer I/O control register 3H TIOR3H R/W H'00 H'FE82
Timer I/O control register 3L TIOR3L R/W H'00 H'FE83
Timer interrupt enable register 3 TIER3 R/W H'40 H'FE84
Timer status register 3 TSR3 R/(W)*2H'C0 H'FE85
Timer counter 3 TCNT3 R/W H'0000 H'FE86
Timer general register 3A TGR3A R/W H'FFFF H'FE88
Timer general register 3B TGR3B R/W H'FFFF H'FE8A
Timer general register 3C TGR3C R/W H'FFFF H'FE8C
Timer general register 3D TGR3D R/W H'FFFF H'FE8E
4 Timer control register 4 TCR4 R/W H'00 H'FE90
Timer mode register 4 TMDR4 R/W H'C0 H'FE91
Timer I/O control register 4 TIOR4 R/W H'00 H'FE92
Timer interrupt enable register 4 TIER4 R/W H'40 H'FE94
Timer status register 4 TSR4 R/(W)*2H'C0 H'FE95
Timer counter 4 TCNT4 R/W H'0000 H'FE96
Timer general register 4A TGR4A R/W H'FFFF H'FE98
Timer general register 4B TGR4B R/W H'FFFF H'FE9A
5 Timer control register 5 TCR5 R/W H'00 H'FEA0
Timer mode register 5 TMDR5 R/W H'C0 H'FEA1
Timer I/O control register 5 TIOR5 R/W H'00 H'FEA2
Timer interrupt enable register 5 TIER5 R/W H'40 H'FEA4
Timer status register 5 TSR5 R/(W)*2H'C0 H'FEA5
Timer counter 5 TCNT5 R/W H'0000 H'FEA6
Timer general register 5A TGR5A R/W H'FFFF H'FEA8
Timer general register 5B TGR5B R/W H'FFFF H'FEAA
All Timer start register TSTR R/W H'00 H'FEB0
Timer synchro register TSYR R/W H'00 H'FEB1
Module stop control register A MSTPCRA R/W H'3F H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 294 of 1042
REJ09B0275-0500
10.2 Register Descriptions
10.2.1 Timer Control Register (TCR)
Channel 0: TCR0
Channel 3: TCR3
Bit:76543210
CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Channel 1: TCR1
Channel 2: TCR2
Channel 4: TCR4
Channel 5: TCR5
Bit:76543210
—CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value:00000000
R/W : — R/W R/W R/W R/W R/W R/W R/W
The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR
registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and
in hardware standby mode.
TCR register settings should be made only when TCNT operation is stopped.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter
clearing source.
Channel Bit 7
CCLR2 Bit 6
CCLR1 Bit 5
CCLR0 Description
0, 3 0 0 0 TCNT clearing disabled (Initial value)
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by cou nter cle arin g for another
channel perf orm ing syn chr onous clearing/
synchronous operation*1
1 0 0 TCNT c learing disabled
1 TCNT cleared by TGRC compare match/input
capture*2
1 0 TCNT cleared by TGRD compare match/input
capture*2
1 TCNT cleared by cou nter cle arin g for another
channel perf orm ing syn chr onous clearing/
synchronous operation*1
Channel Bit 7
Reserved*3Bit 6
CCLR1 Bit 5
CCLR0 Description
1, 2, 4, 5 0 0 0 TCNT clearing disabled (Initial value)
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by cou nter cle arin g for another
channel perf orm ing syn chr onous clearing/
synchronous operation*1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
CKEG1 Bit 3
CKEG0 Description
0 0 Count at rising edge (Initial value)
1 Count at falling edge
1 — Count at both edges
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 10.4 shows the
clock sources that can be set for each channel.
Table 10.4 TPU Clock Sources
Internal Clock E xternal Clock
Channel φ
φφ
φ/1 φ
φφ
φ/4 φ
φφ
φ/16 φ
φφ
φ/64 φ
φφ
φ/256 φ
φφ
φ/1024 φ
φφ
φ/4096 TCLKA TCLKB TCLKC TCLKD
Overflow/
Underflow
on Another
Channel
0
1
2
3
4
5
Legend:
: Setting
Blank : No setting
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
0 0 0 0 Internal clock: co unts on φ/1 (Initial value)
1 Internal clo ck: co unts on φ/4
1 0 Interna l clo ck: co unts on φ/16
1 Internal clo ck: co unts on φ/64
1 0 0 External clock: count s on TCLKA pin input
1 External clo ck: co unts on TCLKB pin input
1 0 Extern al clo ck: co unts on TCLKC pin input
1 External clo ck: counts on TCLKD pin input
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
1 0 0 0 Internal clock: co unts on φ/1 (Initial value)
1 Internal clo ck: co unts on φ/4
1 0 Interna l clo ck: co unts on φ/16
1 Internal clo ck: co unts on φ/64
1 0 0 External clock: count s on TCLKA pin input
1 External clo ck: co unts on TCLKB pin input
1 0 Interna l clo ck: co unts on φ/256
1 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
2 0 0 0 Internal clock: co unts on φ/1 (Initial value)
1 Internal clo ck: co unts on φ/4
1 0 Interna l clo ck: co unts on φ/16
1 Internal clo ck: co unts on φ/64
1 0 0 External clock: count s on TCLKA pin input
1 External clo ck: co unts on TCLKB pin input
1 0 Extern al clo ck: co unts on TCLKC pin input
1 Internal clo ck: co unts on φ/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
3 0 0 0 Internal clock: co unts on φ/1 (Initial value)
1 Internal clo ck: co unts on φ/4
1 0 Interna l clo ck: co unts on φ/16
1 Internal clo ck: co unts on φ/64
1 0 0 External clock: count s on TCLKA pin input
1 Internal clo ck: co unts on φ/1024
1 0 Interna l clo ck: co unts on φ/256
1 Internal clo ck: co unts on φ/4096
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
4 0 0 0 Internal clock: co unts on φ/1 (Initial value)
1 Internal clo ck: co unts on φ/4
1 0 Interna l clo ck: co unts on φ/16
1 Internal clo ck: co unts on φ/64
1 0 0 External clock: count s on TCLKA pin input
1 External clo ck: counts on TCLKC pin input
1 0 Interna l clo ck: co unts on φ/1024
1 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
5 0 0 0 Internal clock: co unts on φ/1 (Initial value)
1 Internal clo ck: co unts on φ/4
1 0 Interna l clo ck: co unts on φ/16
1 Internal clo ck: co unts on φ/64
1 0 0 External clock: count s on TCLKA pin input
1 External clo ck: counts on TCLKC pin input
1 0 Interna l clo ck: co unts on φ/256
1 External clo ck: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 299 of 1042
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10.2.2 Timer Mode Register (TMDR)
Channel 0: TMDR0
Channel 3: TMDR3
Bit:76543210
——BFB BFA MD3 MD2 MD1 MD0
Initial value:11000000
R/W : ——R/W R/W R/W R/W R/W R/W
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit:76543210
————MD3 MD2 MD1 MD0
Initial value:11000000
R/W : ————R/W R/W R/W R/W
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode.
TMDR register settings should be made only when TCNT operation is stopped.
Bits 7 and 6—Reserved: These bits are always read as 1 and cannot be modified.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and
cannot be modified.
Bit 5
BFB Description
0 TGRB operates normally (Initial value)
1 TGRB and TGRD used together for buffer operation
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the nor mal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot
be modified.
Bit 4
BFA Description
0 TGRA operates normally (Initial value)
1 TGRA and TGRC used together for buffer operation
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3
MD3*1Bit 2
MD2*2Bit 1
MD1 Bit 0
MD0 Description
0 0 0 0 Normal operation (Initial value)
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
1***—
*: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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10.2.3 Timer I/O Control Register (TIOR)
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Channel 3: TIOR3H
Channel 4: TIOR4
Channel 5: TIOR5
Bit:76543210
IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Channel 0: TIOR0L
Channel 3: TIOR3L
Bit:76543210
IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR
registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR
registers are initialized to H'00 by a reset, and in h ardwar e standby mode.
Care is required since TIOR is affected by th e TMDR setting. The initial outpu t specified by
TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in
PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Bits 7 to 4— I/O C ontrol B3 to B0 (IOB3 to IOB0 )
I/O Control D3 to D0 (IOD3 to IOD0):
Bits IOB3 to IOB0 specif y the function of TGRB.
Bits IOD3 to IOD0 specify the functio n of TGRD.
Channel Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Description
0 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR0B
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCB0 pin Input capture at both edges
1**
TGR0B
is input
capture
register Capture inp ut
source is channel
1/count clock
Input capture at TCNT1
count-up/count-down*1
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 7
IOD3 Bit 6
IOD2 Bit 5
IOD1 Bit 4
IOD0 Description
0 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR0D
is output
compare
register*2
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCD0 pin Input capture at both edges
1**
TGR0D
is input
capture
register*2
Capture input
source is channel
1/count clock
Input capture at TCNT1
count-up/count-down*1
*: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invali d and input cap ture/output compare is not generate d.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Description
1 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR1B
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCB1 pin Input capture at both edges
1**
TGR1B
is input
capture
register Capture inp ut
source is TGR0C
compare match/
input capture
Input capture at generation
of TGR0C compare match/
input capture
*: Don’t care
Channel Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Description
2 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR2B
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1*0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
TGR2B
is input
capture
register
Capture input
source is
TIOCB2 pin Input capture at both edges
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Description
3 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR3B
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCB3 pin Input capture at both edges
1**
TGR3B
is input
capture
register Capture inp ut
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down*1
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 306 of 1042
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Channel Bit 7
IOD3 Bit 6
IOD2 Bit 5
IOD1 Bit 4
IOD0 Description
3 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR3D
is output
compare
register*2
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCD3 pin Input capture at both edges
1**
TGR3D
is input
capture
register*2
Capture input
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down*1
*: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this
setting is invali d and input cap ture/output compare is not generate d.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Description
4 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR4B
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCB4 pin Input capture at both edges
1**
TGR4B
is input
capture
register Capture inp ut
source is TGR3C
compare match/
input capture
Input capture at generation
of TGR3C compare match/
input capture
*: Don’t care
Channel Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Description
5 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR5B
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1*0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
TGR5B
is input
capture
register
Capture input
source is
TIOCB5 pin Input capture at both edges
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0)
I/O Control C3 to C0 (IOC3 to IOC0):
IOA3 to IOA0 specify the function of TGRA.
IOC3 to IO C0 specify th e function of TGRC.
Channel Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Description
0 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR0A
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCA0 pin Input capture at both edges
1**
TGR0A
is input
capture
register Capture inp ut
source is channel
1/count clock
Input capture at TCNT1
count-up/count-down
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 3
IOC3 Bit 2
IOC2 Bit 1
IOC1 Bit 0
IOC0 Description
0 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR0C
is output
compare
register*1
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCC0 pin Input capture at both edges
1**
TGR0C
is input
capture
register*1
Capture input
source is channel
1/count clock
Input capture at TCNT1
count-up/count-down
*: Don’t care
Note: 1 . When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invali d and input cap ture/output compare is not generate d.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Description
1 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR1A
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCA1 pin Input capture at both edges
1**
TGR1A
is input
capture
register Capture inp ut
source is TGR0A
compare match/
input capture
Input capture at generation
of channel 0/TGR0A
compare match/input
capture
*: Don’t care
Channel Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Description
2 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR2A
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1*0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
TGR2A
is input
capture
register
Capture input
source is
TIOCA2 pin Input capture at both edges
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Description
3 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR3A
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCA3 pin Input capture at both edges
1**
TGR3A
is input
capture
register Capture inp ut
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 3
IOC3 Bit 2
IOC2 Bit 1
IOC1 Bit 0
IOC0 Description
3 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR3C
is output
compare
register*1
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCC3 pin Input capture at both edges
1**
TGR3C
is input
capture
register*1
Capture input
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down
*: Don’t care
Note: 1 . When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this
setting is invali d and input cap ture/output compare is not generate d.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Channel Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Description
4 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR4A
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
Capture input
source is
TIOCA4 pin Input capture at both edges
1**
TGR4A
is input
capture
register Capture inp ut
source is TGR3A
compare match/
input capture
Input capture at generation
of TGR3A compare match/
input capture
*: Don’t care
Channel Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Description
5 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR5A
is output
compare
register
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1*0 0 Input capture at rising edge
1 Input capture at falli ng edge
1*
TGR5A
is input
capture
register
Capture input
source is
TIOCA5 pin Input capture at both edges
*: Don’t care
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 314 of 1042
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10.2.4 Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit:76543210
TTGE ——TCIEV TGIED TGIEC TGIEB TGIEA
Initial value:01000000
R/W : R/W ——R/W R/W R/W R/W R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit:76543210
TTGE —TCIEU TCIEV ——TGIEB TGIEA
Initial value:01000000
R/W : R/W — R/W R/W ——R/W R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
Bit 7—A/D Conv ersion Start Request Enable ( TTGE): Enables or disables generation of A/D
conversion start requests by TGRA input capture/compare match.
Bit 7
TTGE Description
0 A/D conversion start request generation disabled (Initial value)
1 A/D conversion start request generation enabled
Bit 6—Reserved: This bit is always read as 1 and canno t be modified.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by
the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5
TCIEU Description
0 Interrupt requests (TCIU) by TCFU disabled (Initial value)
1 Interrupt requests (TCIU) by TCFU enabled
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by
the TCFV flag when the TCFV flag in TSR is set to 1 .
Bit 4
TCIEV Description
0 Interrupt requests (TCIV) by TCFV disabled (Initial value)
1 Interrupt requests (TCIV) by TCFV enabled
Bit 3—TG R Interrupt Enable D (TGIED) : Enables or disables interrupt requests ( T GI D) by the
TGFD bit when the TGFD bit in TSR is set to 1 in ch annels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3
TGIED Description
0 Interrupt requests (TGID) by TGFD bit disabled (Initial value)
1 Interrupt requests (TGID) by TGFD bit enabled
Bit 2—TG R Interrupt Enable C (TGIEC) : Enables or disables interrupt re quests ( TGIC) by th e
TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 an d 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2
TGIEC Description
0 Interrupt requests (TGIC) by TGFC bit disabled (Initial value)
1 Interrupt requests (TGIC) by TGFC bit enabled
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 316 of 1042
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Bit 1—TG R Interrupt Enable B (TG IEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1
TGIEB Description
0 Interrupt requests (TGIB) by TGFB bit disabled (Initial value)
1 Interrupt requests (TGIB) by TGFB bit enabled
Bit 0—TG R Interrupt Enable A (TGIEA) : Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0
TGIEA Description
0 Interrupt requests (TGIA) by TGFA bit disabled (Initial value)
1 Interrupt requests (TGIA) by TGFA bit enabled
10.2.5 Timer Status Register (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit:76543210
———TCFV TGFD TGFC TGFB TGFA
Initial value:11000000
R/W : ———R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: *Only 0 can be written, for flag clearing.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit:76543210
TCFD —TCFU TCFV ——TGFB TGFA
Initial value:11000000
R/W : R — R/(W)*R/(W)*——R/(W)*R/(W)*
Note: *Only 0 can be written, for flag clearing.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 317 of 1042
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The TSR registers are 8-bit registers that indicate the status of each channel. Th e TPU has six TSR
registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
Bit 7
TCFD Description
0 TCNT counts down
1 TCNT counts up (Initial value)
Bit 6—Reserved: This bit is always read as 1 and cannot be modified.
Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred
when channels 1, 2, 4, and 5 are set to phase counting mode.
In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5
TCFU Description
0 [Clearing cond iti on] (Initial val ue)
When 0 is written to TCFU after reading TCFU = 1
1 [Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurr ed.
Bit 4
TCFV Description
0 [Clearing cond iti on] (Initial val ue)
When 0 is written to TCFV after reading TCFV = 1
1 [Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the
occurrence of TGRD input capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3
TGFD Description
0 [Clearing cond iti ons ] (Initial value)
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1
1 [Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while TGRD is
functioning as input capture regis ter
Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the
occurrence of TGRC input captu re or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2
TGFC Description
0 [Clearing cond iti ons ] (Initial value)
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
1 [Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while TGRC is
functioning as input capture regis ter
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 319 of 1042
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Bit 1—Input Capture/Output Compare Flag B (TGF B) : Status flag that indicates the
occurrence of TGRB input captu re or compare match.
Bit 1
TGFB Description
0 [Clearing cond iti ons ] (Initial value)
• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
1 [Setting conditions]
• When TCNT = TGRB while TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal while TGRB is
functioning as input capture regis ter
Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the
occurrence of TGRA inpu t capture or compare match.
Bit 0
TGFA Description
0 [Clearing cond iti ons ] (Initial value)
• When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFA after reading TGFA = 1
1 [Setting conditions]
• When TCNT = TGRA while TGRA is functioning as output compare register
• When TCNT value is transferred to TGRA by input capture signal while TGRA is
functioning as input capture regis ter
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 320 of 1042
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10.2.6 Timer Counter (TCNT)
Channel 0: TCNT0 (up-counter)
Channel 1: TCNT1 (up/down-counter*)
Channel 2: TCNT2 (up/down-counter*)
Channel 3: TCNT3 (up-counter)
Channel 4: TCNT4 (up/down-counter*)
Channel 5: TCNT5 (up/down-counter*)
Bit :1514131211109876543210
Initial value:000000000000000 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: *These counters can be used as up/down-counters only in phase counting mode or
when counting overflow/underflow on another channel. In other cases they function as
up-counters.
The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
10.2.7 Timer General Register (TGR)
Bit :1514131211109876543210
Initial value:111111111111111 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TGR registers are 16-bit registers with a dual function as ou tput compare and input capture
registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels
1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as
buffer registers*. The TGR registers are initialized to H'FFFF b y a reset, and in hardware standby
mode.
The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 321 of 1042
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10.2.8 Timer Start Register (TSTR)
Bit:76543210
——CST5 CST4 CST3 CST2 CST1 CST0
Initial value:00000000
R/W : ——R/W R/W R/W R/W R/W R/W
TSTR is an 8-bit readable/writable register that selects operation/stoppage fo r channels 0 to 5.
TSTR is initialized to H'00 by a reset, and in hardware standby mode. Wh en setting the operating
mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn Description
0 TCNTn count operation is stopped (Initial value)
1 TCNTn performs count operation n = 5 to 0
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
10.2.9 Timer Synchro Register (TSYR)
Bit:76543210
——SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
Initial value:00000000
R/W : ——R/W R/W R/W R/W R/W R/W
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Should always be written with 0.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 322 of 1042
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Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*1, and
synchronous clearing through counter clearing on another channel*2 are possible.
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also b e set by means of bits CCLR2 to CCLR0 in TCR.
Bit n
SYNCn Description
0 TCNTn operates independently (TCNT presetting/clearing is unrelated to
other channels) (Initial value)
1 TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0
10.2.10 Module Stop Control Register A (MSTPCRA)
Bit:76543210
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value:00111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle
and a transition is made to module stop mode. Registers cannot be read or written to in module
stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset an d in hardware standby mode. It is not initialized in
software standby mode.
Bit 5—Module Stop (MSTPA5): Specifies the TPU module stop mode.
Bit 5
MSTPA5 Description
0 TPU module stop mode cleared
1 TPU module stop mode set (Initial value)
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 323 of 1042
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10.3 Interface to Bus Master
10.3.1 16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these
registers can b e r ead and written to in 16-bit units.
These registers cannot be read or written to in 8-bit units; 16-bit access must always be used.
An example of 16-bit register access operation is shown in figure 10.2.
Bus interface
H
Internal data bus
L
Bus
master Module
data bus
TCNTH TCNTL
Figure 10.2 16-Bit Register Access Operation [Bus Master ↔
↔↔
↔ TCNT (16 Bits)]
10.3.2 8-Bit Registers
Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these
registers can be r ead and written to in 16-bit units. They can also b e read and written to in 8-bit
units.
Examples of 8-bit register access operation are shown in figures 10.3 to 10.5.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 324 of 1042
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Bus interface
H
Internal data bus
LModule
data bus
TCR
Bus
master
Figure 10.3 8-Bit Register Access Operation [Bus Master ↔
↔↔
↔ TCR (Upper 8 Bits)]
Bus interface
H
Internal data bus
LModule
data bus
TMDR
Bus
master
Figure 10.4 8-Bit Register Access Operation [Bus Master ↔
↔↔
↔ TMDR (Lower 8 Bits)]
Bus interface
H
Internal data bus
LModule
data bus
TCR TMDR
Bus
master
Figure 10.5 8-Bit Register Access Operation [Bus Master ↔
↔↔
↔ TCR and TMDR (16 Bits)]
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 325 of 1042
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10.4 Operation
10.4.1 Overview
Operation in each mode is o utlined below.
Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting,
and is also capable of free-running operation, synchronous counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Synchronous Opera tion: When synchronous operation is designated for a channel, TCNT for
that channel performs synchronous presetting. That is, when TCNT for a channel designated for
synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at
the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer
synchronization bits in TSYR for channels designated for synchronous operation.
Buffer Operation
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the relevant channel is
transferr ed to TGR.
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transfer to TGR and the value previously
held in TGR is transferred to the buffer register.
Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4
counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32-
bit counter.
PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of
TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the
setting of each TGR register.
Phase Counting Mode: In this m o de, TCNT is incremented or de cremented by detecting the
phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When
phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT
performs up- or down-counting.
This can be used for two-phase encoder pulse input.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 326 of 1042
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10.4.2 Basic Functions
Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for
the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic
counter, and so on.
• Example of count operation setting procedure
Figure 10.6 shows an example of the count operation setting procedure.
Select counter clock
Operation selection
Select counter clearing source
Periodic counter
Set period
Start count operation
<Periodic counter>
[1]
[2]
[4]
[3]
[5]
Free-running counter
Start count operation
<Free-running counter>
[5]
[1]
[2]
[3]
[4]
[5]
Select output compare register
Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
Set the periodic
counter cycle in the
TGR selected in [2].
Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 10.6 Example of Counter Operation Setting Procedure
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 327 of 1042
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• Free-running count operation and periodic count operation
Immediately after a reset, the TPU’s TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-
count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),
the TCFV bit in TSR is set to 1. If the value of the corresponding TCIE V bit in TIER is 1 at
this point, the TPU r equests an interrupt. After overflo w, TCNT starts cou nting up again from
H'0000.
Figure 10.7 illustrates free-r unning counter operatio n.
TCNT value
H'FFFF
H'0000
CST bit
TCFV
Time
Figure 10.7 Free-Running Counter Operatio n
When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of b its CCLR2 to CCLR0 in TCR. After the settin gs have been made, TCNT starts
up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 328 of 1042
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Figure 10.8 illustrates periodic counter operation.
TCNT value
TGR
H'0000
CST bit
TGF
Time
Counter cleared by TGR
compare match
Flag cleared by software or
DTC activation
Figure 10.8 Periodic Counter Operation
Wavefo rm Output by Compa re Match: The TPU can perform 0, 1, or toggle output from the
corresponding output pin using compare match.
• Example of setting procedure for waveform output by compare match
Figure 10.9 shows an example of the setting procedure for waveform output by compare match
Select waveform output mode
Output selection
Set output timing
Start count operation
<Waveform output>
[1]
[2]
[3]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 10.9 Example of Setting Procedure for Waveform Output by Compare Match
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 329 of 1042
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• Examples of waveform output operation
Figure 10.10 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been
made so that 1 is output by comp are match A, and 0 is output by compare match B. When the
set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
H'0000
TIOCA
TIOCB
Time
TGRA
TGRB
No change No change
No change No change
1 output
0 output
Figure 10.10 Example of 0 Output/1 Output Operation
Figure 10.11 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing
performed by compare match B), and settings have been made so that output is toggled by both
compare match A and compare match B.
TCNT value
H'FFFF
H'0000
TIOCB
TIOCA
Time
TGRB
TGRA
Toggle output
Toggle output
Counter cleared by TGRB compare match
Figure 10.11 Example of Toggle Output Operation
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC
pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3,
and 4, it is also possible to specify another channel’s counter input clock or compare match signal
as the input capture source.
Note: When another channel’s counter input clock is used as the input capture input for channels
0 and 3, φ/1 should not be selected as the counter input clock used for inpu t capture input.
Input capture will not be generated if φ/1 is selected.
• Example of input capture operation setting procedure
Figure 10.12 shows an example of the input capture operation setting procedure.
Select input capture input
Input selection
Start count
<Input capture operation>
[1]
[2]
[1] Designate TGR as an input capture register by
means of TIOR, and select rising edge, falling
edge, or both edges as the input capture source
and input signal edge.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 10.12 Example of Input Ca pt ure Operation Setting Procedure
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 331 of 1042
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• Example of input capture operation
Figure 10.13 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input
capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,
and counter clearing by TGRB input capture has been design ated for TCNT.
TCNT value
H'0180
H'0000
TIOCA
TGRA
Time
H'0010
H'0005
Counter cleared by TIOCB
input (falling edge)
H'0160
H'0005 H'0160 H'0010
TGRB H'0180
TIOCB
Figure 10.13 Example of Input Ca pt ure Operation
10.4.3 Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous op eration enables TGR to be incremented with respect to a single time base.
Channels 0 to 5 can all be designated for synchronous operation.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Example of Synchronous Operation Setting Procedure: Figure 10.14 shows an example of the
synchronous operation setting procedure.
Set synchronous
operation
Synchronous operation
selection
Set TCNT
Synchronous presetting
<Synchronous presetting>
[1]
[2]
Synchronous clearing
Select counter
clearing source
<Counter clearing>
[3]
Start count [5]
Set synchronous
counter clearing
<Synchronous clearing>
[4]
Start count [5]
Clearing
sourcegeneration
channel?
No
Yes
[1]
[2]
[3]
[4]
[5]
Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
When the TCNT counter of any of the channels designated for synchronous operation is
written to, the same value is simultaneously written to the other TCNT counters.
Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,
etc.
Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing
source.
Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 10.14 Example of Synchronous Operation Setting Procedure
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Example of Synchronous Operation: Figure 10.15 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous
clearing has been set for the channel 1 and 2 counter clearing sources.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle.
For details of PWM modes, see section 10.4.6, PWM Modes.
TCNT0 to TCNT2 values
H'0000
TIOC0A
TIOC1A
Time
TGR0B
Synchronous clearing by TGR0B compare match
TGR2A
TGR1A
TGR2B
TGR0A
TGR1B
TIOC2A
Figure 10.15 Example of Synchronous Operation
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10.4.4 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 10.5 shows the register combinations used in buffer operation.
Table 10.5 Register Combinations in Buffer Operation
Channel Timer General Register Buffer Register
0TGR0A TGR0C
TGR0B TGR0D
3TGR3A TGR3C
TGR3B TGR3D
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general r egister.
This opera tion is illustrated in figure 10.16.
Buffer register Timer general
register TCNTComparator
Compare match signal
Figure 10.16 Compare Match Buffer Operation
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• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is tran sf er red to the buffer register.
This opera tion is illustrated in figure 10.17.
Buffer register Timer general
register TCNT
Input capture
signal
Figure 10.17 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure: Figure 10.18 shows an example of the buffer
operation setting procedure.
Select TGR function
Buffer operation
Set buffer operation
Start count
<Buffer operation>
[1]
[2]
[3]
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 10.18 Example of Buffer Operation Setting Procedure
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Examples of Buffer Operation
• When TGR is an output compare register
Figure 10.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultan eously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 10.4.6, PWM Modes.
TCNT value
TGR0B
H'0000
TGR0C
Time
TGR0A
H'0200 H'0520
TIOCA
H'0200
H'0450 H'0520
H'0450
TGR0A H'0450H'0200
Transfer
Figure 10.19 Example of Buffer Operation (1)
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• When TGR is an input capture register
Figure 10.20 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'09FB
H'0000
TGRC
Time
H'0532
TIOCA
TGRA H'0F07H'0532
H'0F07
H'0532
H'0F07
H'09FB
Figure 10.20 Example of Buffer Operation (2)
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10.4.5 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10.6 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase coun ting mode.
Table 10.6 Casca ded Combinations
Combination Upper 16 Bits Lower 16 Bits
Channels 1 and 2 TCNT1 TCNT2
Channels 4 and 5 TCNT4 TCNT5
Example of Cascaded Operation Setting Procedure: Figure 10.21 shows an example of the
setting procedure for cascaded operation.
Set cascading
Cascaded operation
Start count
<Cascaded operation>
[1]
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B’111 to select TCNT2
(TCNT5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Figure 10.21 Cascaded Operation Setting Procedure
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Examples of Cascaded Operation: Figure 10.22 illustrates the operation when counting upon
TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated
as input capture registers, and TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data ar e tr ansferred to TGR1A, and th e lower 16 bits to TGR2A.
TCNT2
clock
TCNT2 H'FFFF H'0000 H'0001
TIOCA1,
TIOCA2
TGR1A H'03A2
TGR2A H'0000
TCNT1
clock
TCNT1 H'03A1 H'03A2
Figure 10.22 Example of Cascaded Operation (1)
Figure 10.23 illustrates the operation when counting upon TCNT2 overflow/underflow has been
set for TCNT1, and phase counting mode has been designated for channel 2.
TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
TCLKA
TCNT2 FFFD
TCNT1 0001
TCLKB
FFFE FFFF 0000 0001 0002 0001 0000 FFFF
0000 0000
Figure 10.23 Example of Cascaded Operation (2)
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10.4.6 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B
and D. The initial outp ut value is the value set in TGRA or TGRC. I f the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronizatio n register compare match , the outpu t v alue of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is po ssible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 10.7.
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Table 10.7 PWM O ut put Register s and Output Pins
Output Pins
Channel Registers PWM Mode 1 PWM Mode 2
0 TGR0A TIOCA0 TIOCA0
TGR0B TIOCB0
TGR0C TIOCC0 TIOCC0
TGR0D TIOCD0
1 TGR1A TIOCA1 TIOCA1
TGR1B TIOCB1
2 TGR2A TIOCA2 TIOCA2
TGR2B TIOCB2
3 TGR3A TIOCA3 TIOCA3
TGR3B TIOCB3
TGR3C TIOCC3 TIOCC3
TGR3D TIOCD3
4 TGR4A TIOCA4 TIOCA4
TGR4B TIOCB4
5 TGR5A TIOCA5 TIOCA5
TGR5B TIOCB5
Note: In PWM mode 2, PWM output is no t possible for the TGR register in which the period is set.
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Example of P WM Mode Setting Procedure: Figure 10.24 shows an example of the PWM mode
setting procedure.
Select counter clock
PWM mode
Select counter clearing source
Select waveform output level
<PWM mode>
[1]
[2]
[3]
Set TGR [4]
Set PWM mode [5]
Start count [6]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
[6] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 10.24 Example of PWM Mode Setting Procedure
Examples of PWM Mode Operation: Figure 10.25 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and outpu t value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as
the duty.
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TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
Counter cleared by
TGRA compare match
Figure 10.25 Example of PWM Mode Operation (1)
Figure 10.26 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match
is set as the TCNT clearing so urce, and 0 is set for the initial output valu e and 1 for th e outp ut
value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM
waveform.
In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as
the duty.
TCNT value
TGR1B
H'0000
TIOCA0
Counter cleared by TGR1B
compare match
TGR1A
TGR0D
TGR0C
TGR0B
TGR0A
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Time
Figure 10.26 Example of PWM Mode Operation (2)
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Figure 10.27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
0% duty
TGRB rewritten
TGRB
rewritten
TGRB rewritten
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty
register compare matches occur simultaneously
0% duty
Figure 10.27 Example of PWM Mode Operation (3)
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10.4.7 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, th e TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 10.8 shows the correspondence between external clock pins and channels.
Table 10. 8 Phase Counting Mode Clock Inp ut Pins
External Clock Pins
Channels A-Phase B-Phase
When channel 1 or 5 is set to phase counting mode TCLKA TCLKB
When channel 2 or 4 is set to phase counting mode TCLKC TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 10.28 shows an example of the
phase counting mode setting procedure.
Select phase counting mode
Phase counting mode
Start count
<Phase counting mode>
[1]
[2]
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 10.28 Example of Phase Counting Mode Setting Procedure
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
• Phase counting mode 1
Figure 10.29 shows an example of phase counting mode 1 operation, and table 10.9
summarizes th e TCNT up/down-count co nditions.
TCNT value
Time
Down-countUp-count
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
Figure 10.29 Example of Phase Counting Mode 1 Operation
Table 10.9 Up/Down- Count Condit ions in Phase Cou nt ing Mode 1
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4) Operation
High level Up-count
Low level Up-count
Low level Up-count
High level Up-count
High level Down-count
Low level Down-count
High level Down-count
Low level Down-count
Legend:
: Rising edge
: Falling edge
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• Phase counting mode 2
Figure 10.30 shows an example of phase counting mode 2 operation, and table 10.10
summarizes th e TCNT up/down-count co nditions.
TCNT value
Time
Down-countUp-count
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Figure 10.30 Example of Phase Counting Mode 2 Operation
Table 10.10 Up/Down-Count Conditions in P hase Counting Mode 2
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4) Operation
High level Don’t care
Low level Don’t care
Low level Don’t care
High level Up-count
High level Don’t care
Low level Don’t care
High level Don’t care
Low level Down-count
Legend:
: Rising edge
: Falling edge
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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• Phase counting mode 3
Figure 10.31 shows an example of phase counting mode 3 operation, and table 10.11
summarizes th e TCNT up/down-count co nditions.
TCNT value
Time
Up-count
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
Down-count
Figure 10.31 Example of Phase Counting Mode 3 Operation
Table 10.11 Up/Down-Co unt Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4) Operation
High level Don’t care
Low level Don’t care
Low level Don’t care
High level Up-count
High level Down-count
Low level Don’t care
High level Don’t care
Low level Don’t care
Legend:
: Rising edge
: Falling edge
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• Phase counting mode 4
Figure 10.32 shows an example of phase counting mode 4 operation, and table 10.12
summarizes th e TCNT up/down-count co nditions.
Time
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
Up-count Down-count
TCNT value
Figure 10.32 Example of Phase Counting Mode 4 Operation
Table 10.12 Up/Down-Count Conditions in P hase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4) Operation
High level Up-count
Low level Up-count
Low level Don’t care
High level Don’t care
High level Down-count
Low level Down-count
High level Don’t care
Low level Don’t care
Legend:
: Rising edge
: Falling edge
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Phase Counting Mode Application Example: Figure 10.33 shows an example in which phase
counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo
motor 2-phase encoder pulses in order to detect the position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C
are used for the compare match f unc tio n, and are set with the speed contro l period and position
control period. TGR0B is used fo r input capture , with TGR0 B and TGR0D op e r a ting in buffer
mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and
detection o f the pulse width of 2-phase encod er 4-multiplication pulses is performed.
TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and
TGR0C compare matches are selected as the input capture source, and store the up/down-counter
values for the control periods.
This procedure en ables accurate p osition/speed detection to be achiev ed.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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TCNT1
TCNT0
Channel 1
TGR1A
(speed period capture)
TGR0A (speed control period)
TGR1B
(position period capture)
TGR0C
(position control period)
TGR0B (pulse width capture)
TGR0D (buffer operation)
Channel 0
TCLKA
TCLKB
Edge
detection
circuit
+
–
+
–
Figure 10.33 Phase Counting Mode Application Example
10.5 Interrupts
10.5.1 Interrupt Source s and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
correspo ndin g enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by th e interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
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Table 10.13 lists th e TPU interrupt sources.
Table 10.13 TPU Interrupts
Channel Interrupt
Source Description DTC Activation Priority
0 TGI0A TGR0A input capture/compare match Possible High
TGI0B TGR0B input capture/compare match Possible
TGI0C TGR0C input capture/compare match Possible
TGI0D TGR0D input capture/compare match Possible
TCI0V TCNT0 overflow Not possible
1 TGI1A TGR1A input capture/compare match Possible
TGI1B TGR1B input capture/compare match Possible
TCI1V TCNT1 overflow Not possible
TCI1U TCNT1 underflow Not possible
2 TGI2A TGR2A input capture/compare match Possible
TGI2B TGR2B input capture/compare match Possible
TCI2V TCNT2 overflow Not possible
TCI2U TCNT2 underflow Not possible
3 TGI3A TGR3A input capture/compare match Possible
TGI3B TGR3B input capture/compare match Possible
TGI3C TGR3C input capture/compare match Possible
TGI3D TGR3D input capture/compare match Possible
TCI3V TCNT3 overflow Not possible
4 TGI4A TGR4A input capture/compare match Possible
TGI4B TGR4B input capture/compare match Possible
TCI4V TCNT4 overflow Not possible
TCI4U TCNT4 underflow Not possible
5 TGI5A TGR5A input capture/compare match Possible
TGI5B TGR5B input capture/compare match Possible
TCI5V TCNT5 overflow Not possible
TCI5U TCNT5 underflow Not possible Low
Note: This table shows the initia l state im m ediate ly after a reset. The rela tiv e chann el prior itie s
can be changed by the interrupt controller.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Input Capture/Compa re Match Interrupt: An inter r upt is requested if the TGI E bit in TI ER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each
for channels 1, 2, 4, and 5.
Overflow Interrupt: An interrupt is requ ested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is r equested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one
each for channels 1, 2, 4, and 5.
10.5.2 DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 8, Data Tr ansfer Controller (DTC).
A total of 16 TPU input capture/compare match interrup ts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
10.5.3 A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is started.
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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10.6 Operation Timing
10.6 .1 Input/O utput Timing
TCNT Count Timing: Figure 10.34 shows TCNT count timing in internal clock operation, and
figure 10.35 shows TCNT count timing in external clock operation.
TCNT
TCNT
input clock
Internal clock
φ
N–1 N N+1 N+2
Falling edge Rising edge
Figure 10.34 Count Timing in Internal Clock Operation
TCNT
TCNT
input clock
External clock
φ
N–1 N N+1 N+2
Rising edge Falling edge
Falling edge
Figure 10.35 Count Timing in External Clock Operation
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Output Compa re Output Timing : A co mpare match sig nal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a comp are match signal is generated, the output value set in TI OR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the TCNT input clock is generated.
Figure 10.36 shows ou tput compare output timing.
TGR
TCNT
TCNT
input clock
φ
N
N N+1
Compare
match signal
TIOC pin
Figure 10.36 Output Compa re Output Timing
Input Capture S ignal Timing: Figure 10.37 shows input capture signal timing.
TCNT
Input capture
input
φ
N N+1 N+2
NN+2
TGR
Input capture
signal
Figure 10. 37 Input Capture Input Signal Timing
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 356 of 1042
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Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.38 shows the
timing when counter clearing by compare match occurrence is specified, and figure 10.39 shows
the timing when counter clearing by input capture occurrence is specified.
TCNT
Counter
clear signal
Compare
match signal
φ
TGR N
N H'0000
Figure 10.38 Counter Clear Timing (Compare Match)
TCNT
Counter clear
signal
Input capture
signal
φ
TGR
N H'0000
N
Figure 10.39 Counter Clear Timing (Input Capture)
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 357 of 1042
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Buffer Operation Timing: Figures 10.40 and 10.41 show the timing in buffer operation.
TGRA,
TGRB
Compare
match signal
TCNT
φ
TGRC,
TGRD
nN
N
n n+1
Figure 10.40 Buffer Operation Timing (Compare Match)
TGRA,
TGRB
TCNT
Input capture
signal
φ
TGRC,
TGRD
N
n
n N+1
N
N N+1
Figure 10.41 Buffer Operation Timing (Input Capture)
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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10.6.2 Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 10.42 shows the timing for
setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal
timing.
TGR
TCNT
TCNT input
clock
φ
N
N N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 10.42 TGI Interrupt Timing (Compare Match)
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 359 of 1042
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TGF Flag Setting Timing in Case of Input Capture: Figure 10.43 sh ows the timing for settin g
of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.
TGR
TCNT
Input capture
signal
φ
N
N
TGF flag
TGI interrupt
Figure 10. 43 TGI Interrupt Timing (Input Capture)
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 360 of 1042
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TCFV Flag/TCFU Flag Setting Timing: Figure 10.44 shows the timing for setting of the TCFV
flag in TSR by ov erflow occurrence, and TCIV interrupt request signal timing.
Figure 10.45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
TCIU interrupt request sign a l timing.
Overflow
signal
TCNT
(overflow)
TCNT input
clock
φ
H'FFFF H'0000
TCFV flag
TCIV interrupt
Figure 10.44 TCIV Interrupt Setting Timing
Underflow signal
TCNT
(underflow)
TCNT
input clock
φ
H'0000 H'FFFF
TCFU flag
TCIU interrupt
Figure 10.45 TCIU Interrupt Setting Timing
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Status Fla g Clearing Timing: After a status flag is read as 1 b y the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.46 shows the
timing for status flag clearing by the CPU, and figure 10.47 shows the timing for status flag
clearing by the DTC.
Status flag
Write signal
Address
φ
TSR address
Interrupt
request
signal
TSR write cycle
T1 T2
Figure 10.46 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
Address
φ
Source address
DTC
read cycle
T1 T2
Destination
address
T1 T2
DTC
write cycle
Figure 10.47 Timing for Status Flag Clearing by DTC Activation
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 362 of 1042
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10.7 Usage Notes
Note that the kinds of operation and contention described below occur during TPU operation.
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in th e case o f both-edge detection. The TPU will n ot
operate properly with a narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.48 shows the input clock
conditions in phase counting mode.
Overlap
Phase
differ-
ence
Phase
differ-
ence
Overlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width Pulse width
Pulse width Pulse width
Notes: Phase difference and overlap
Pulse width : 1.5 states or more
: 2.5 states or more
Figure 10.48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in
the final state in which it matches th e TGR value (the point at which the count value matched by
TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
f = φ
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set valu e
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 363 of 1042
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Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 10.49 shows the timing in this case.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
N H'0000
Figure 10.49 Contention between TCNT Write and Clear Operations
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 364 of 1042
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Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10.50 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
N M
TCNT write data
Figure 10.50 Contention between TCNT Write and Increment Operations
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 365 of 1042
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Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A co mpar e m a tch does not occur even if the same value as before is wr itten.
Figure 10.51 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T1 T2
N M
TGR write data
TGR
N N+1
Inhibited
Figure 10.51 Contention between TGR Write and Compare Match
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a TGR write cycle, the data transferred to TGR b y the buf f e r ope r a tion will b e th e
data prior to the wr ite.
Figure 10.52 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T1 T2
N
TGR
N M
Buffer register write data
Figure 10.52 Contention between Buffer Register Write and Compare Match
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 367 of 1042
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Contention between TGR Read and Inp ut Capture: If the inpu t cap ture signal is genera ted in
the T1 state of a TGR read cycle, the data that is r ead will be the data after input capture tran sf er.
Figure 10.53 shows the timing in this case.
Input capture
signal
Read signal
Address
φ
TGR address
TGR
TGR read cycle
T1 T2
M
Internal
data bus
X M
Figure 10.53 Contention betw een TG R Read and Input Capture
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 368 of 1042
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Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 10.54 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T1 T2
M
TGR
M
TGR address
Figure 10.54 Contention between TGR Write and Input Capture
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 369 of 1042
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Contention between Buf fer Register Write and Input Capture: If the input capture signal is
generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 10.55 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T1 T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 10.55 Contention between Buff er Register Write and Input Ca pt ure
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence.
Figure 10.56 shows the operation timing when a TGR compare match is specified as the clearing
source, an d H'FFFF is set in TGR.
Counter
clear signal
TCNT input
clock
φ
TCNT
TGF
Disabled
TCFV
H'FFFF H'0000
Figure 10.56 Contention between Overflow and Counter Clearing
Section 10 16-Bit Ti mer Pulse Unit (TPU)
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Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write
takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 10.57 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
H'FFFF M
TCNT write data
TCFV flag
Figure 10.57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins: In the H8S/2626 Group and H8S/2623 Group, the TCLKA input pin is
multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the
TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
When an external clock is input, compare match output should not be performed from a
multiplexe d pin.
Interrupts and Module St op Mode: If module stop mode is entered when an interrupt has been
requested , it will not be possible to clear the CPU interrupt sou r ce or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Section 10 16-Bit Ti mer Pulse Unit (TPU)
Rev. 5.00 Jan 10, 2006 page 372 of 1042
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Section 11 Programmable Pu lse Generator (PPG)
Rev. 5.00 Jan 10, 2006 page 373 of 1042
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Section 11 Programmable Pulse Generator (PPG)
11.1 Overview
The H8S/2626 Group and H8S/2623 Group have an on-chip programmable pulse generator (PPG)
that provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG
pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both
simultaneously and independently.
11.1.1 Features
PPG features are listed below.
• 8-bit output data
Maximum 8-bit data can be output, and output can be enabled on a bit-by-bit basis
• Two output groups
Output trigger signals can be selected in 4-bit groups to provide up to two different 4-bit
outputs
• Selectable output trigger signals
Output trigger signals can be selected for each group from the compare match signals of
four TPU channels
• Non-overlap mode
A non-overlap margin can be provided between pulse outputs
• Can operate to gether with the data transfer contr oller (DTC)
The compare match signals selected as output trigger signals can activate the DTC for
sequential o utput of data withou t CPU intervention
• Settable inverted output
Inverted data can be output for each group
• Module stop mode can be set
As the initial setting, PPG operation is halted. Register access is enabled by exiting module
stop mode
Section 11 Programmable Pu lse Generator (PPG)
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11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the PPG.
Compare match signals
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Legend: : PPG output mode register
: PPG output control register
: Next data enable register H
: Next data enable register L
: Next data register H
: Next data register L
: Output data register H
: Output data register L
Internal
data bus
PMR
PCR
NDERH
NDERL
NDRH
NDRL
PODRH
PODRL
Pulse output
pins, group 3
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
PODRH
PODRL
NDRH
NDRL
Control logic
NDERH
PMR
NDERL
PCR
Figure 11.1 Block Diagram of PPG
Section 11 Programmable Pu lse Generator (PPG)
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11.1.3 Pin Configuration
Table 11.1 summarizes the PPG pins.
Table 11.1 PPG Pins
Name Symbol I/O Function
Pulse output 8 PO8 Output Group 2 pulse output
Pulse output 9 PO9 Output
Pulse output 10 PO10 Output
Pulse output 11 PO11 Output
Pulse output 12 PO12 Output Group 3 pulse output
Pulse output 13 PO13 Output
Pulse output 14 PO14 Output
Pulse output 15 PO15 Output
Section 11 Programmable Pu lse Generator (PPG)
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11.1.4 Registers
Table 11.2 summarizes the PPG registers.
Table 11.2 PPG Registers
Name Abbreviation R/W Initial Value Address*1
PPG output control register PCR R/W H'FF H'FE26
PPG output mode register PMR R/W H'F0 H'FE27
Next data enable register H NDERH R/W H'00 H'FE28
Next data enable register L*4NDERL R/W H'00 H'FE29
Output data register H PODRH R/(W)*2H'00 H'FE2A
Output data register L*4PODRL R/(W)*2H'00 H'FE2B
Next data register H NDRH R/W H'00 H'FE2C*3
H'FE2E
Next data register L*4NDRL R/W H'00 H'FE2D*3
H'FE2F
Port 1 data direction register P1DDR W H'00 H'FE30
Module stop control register A MSTPCRA R/W H'3F H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Bits used for pulse output cannot be written to.
3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FE2C. When the output triggers are different, the
NDRH address is H'FE2E for group 2 and H'FE2C for group 3
Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by
the PCR setting, the NDRL address is H'FE2D. When the output triggers are different,
the NDRL address is H'FE2F for group 0 and H'FE2D for group 1.
4. The H8S/2626 Group and H8S/2623 Group have no pins corresponding to PODRL
(pulse output groups 0 and 1).
Section 11 Programmable Pu lse Generator (PPG)
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11.2 Register Descriptions
11.2.1 Next Da ta Enable Registers H and L (NDERH, NDERL)
NDERH
Bit:76543210
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
NDERL
Bit:76543210
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a
bit-by-bit basi s .
If a bit is enabled fo r pu lse o utput by NDERH or NDERL, the NDR value is automatically
transferred to the corresponding PODR bit when the TPU compare match event specified by PCR
occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from
NDR to PODR and the output value does not change.
NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They
are not initialized in software standby mode.
NDERH Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or
disable pulse output on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8 Description
0 Pulse outputs PO15 to PO8 a re disabled (NDR15 to NDR8 are not
transferred to POD15 to POD8) (Initial value)
1 Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred
to POD15 to POD8)
Section 11 Programmable Pu lse Generator (PPG)
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NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or
disable pulse output on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0 Description
0 Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not
transferred to POD7 to POD0) (Initial value)
1 Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to
POD7 to POD0)
11.2.2 Output Da ta Reg isters H a nd L (PODRH, PODRL)
PODRH
Bit:76543210
POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8
Initial value:00000000
R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
PODRL
Bit:76543210
POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0
Initial value:00000000
R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: *A bit that has been set for pulse output by NDER is read-only.
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse
output. However, the H8S/2626 Group and H8S/2623 Group have no pins corresponding to
PODRL.
Section 11 Programmable Pu lse Generator (PPG)
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11.2.3 Next Da ta Registers H and L (NDRH, NDRL)
NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output.
During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in
PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH
and NDRL addresses differ depending on whether pulse output groups have the same output
trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access.
NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are
not initialized in software standby m ode.
11.2.4 Notes on NDR Access
The NDRH and NDRL addresses differ depending on whether pulse output groups have the same
output trigger or different output triggers.
Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the
same compare match event, the NDRH address is H'FE2C. The upper 4 bits belong to group 3
and the lower 4 bits to group 2. Address H'FE2E consists entirely of reserved bits that cannot be
modified and are always read as 1.
• Address H'FE2C
Bit:76543210
NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
• Address H'FE2E
Bit:76543210
————————
Initial value:11111111
R/W:————————
If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address
is H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F
consists entirely of reserved bits that cannot be modified and are always read as 1. However, the
H8S/2626 Group and H8S/2623 Group have no output pins corresponding to pulse output groups
0 and 1.
Section 11 Programmable Pu lse Generator (PPG)
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• Address H'FE2D
Bit:76543210
NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
• Address H'FE2F
Bit:76543210
————————
Initial value:11111111
R/W:————————
Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by
different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and
the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4
of address H'FE2E are reserved bits that cannot be modified and are always read as 1.
• Address H'FE2C
Bit:76543210
NDR15 NDR14 NDR13 NDR12 ————
Initial value:00001111
R/W:R/WR/WR/WR/W————
• Address H'FE2E
Bit:76543210
— — — — NDR11 NDR10 NDR9 NDR8
Initial value:11110000
R/W : — — — — R/W R/W R/W R/W
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the
upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is
H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that
cannot be modified and are always read as 1. However, the H8S/2626 Group and H8S/2623 Group
have no output pins corresponding to pulse output groups 0 and 1.
Section 11 Programmable Pu lse Generator (PPG)
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• Address H'FE2D
Bit:76543210
NDR7 NDR6 NDR5 NDR4 ————
Initial value:00001111
R/W:R/WR/WR/WR/W————
• Address H'FE2F
Bit:76543210
— — — — NDR3 NDR2 NDR1 NDR0
Initial value:11110000
R/W : — — — — R/W R/W R/W R/W
11.2.5 PPG Output Control Register (PCR)
Bit:76543210
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value:11111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a
group-by-group basis.
PCR is initialized to H'FF by a reset and in hardware standby m ode . I t is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match that triggers pulse output group 3 (pins PO15 to PO12).
Description
Bit 7
G3CMS1 Bit 6
G3CMS0 Output Trigger for Pulse Output Group 3
0 0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
1 0 Compare match in TPU channel 2
1 Compare match in TPU channel 3 (Initial value)
Section 11 Programmable Pu lse Generator (PPG)
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Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match that triggers pulse output group 2 (pins PO11 to PO8).
Description
Bit 5
G2CMS1 Bit 4
G2CMS0 Output Trigger for Pulse Output Group 2
0 0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
1 0 Compare match in TPU channel 2
1 Compare match in TPU channel 3 (Initial value)
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the
H8S/2626 Group and H8S/2623 Group have no output pins corresponding to pulse output group 1.
Description
Bit 3
G1CMS1 Bit 2
G1CMS0 Output Trigger for Pulse Output Group 1
0 0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
1 0 Compare match in TPU channel 2
1 Compare match in TPU channel 3 (Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match that triggers pulse output group 0 (pins PO3 to PO0). However, the
H8S/2626 Group and H8S/2623 Group have no output pins corresponding to pulse output group 0.
Description
Bit 1
G0CMS1 Bit 0
G0CMS0 Output Trigger for Pulse Output Group 0
0 0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
1 0 Compare match in TPU channel 2
1 Compare match in TPU channel 3 (Initial value)
Section 11 Programmable Pu lse Generator (PPG)
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11.2.6 PPG Output Mode Register (PMR)
Bit:76543210
G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV
Initial value:11110000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping
operation for each group.
The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB
and the non-overlap margin is set in TGRA. The output values change at compare match A and B.
For details, see section 11.3.4, Non-Overlapping Pulse Output.
PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output
group 3 (pins PO15 to PO12).
Bit 7
G3INV Description
0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
(Initial value
)
Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output
group 2 (pins PO11 to PO8).
Bit 6
G2INV Description
0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)
1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)
(Initial value
)
Section 11 Programmable Pu lse Generator (PPG)
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Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output
group 1 (pins PO7 to PO4). However, the H8S/2626 Group and H8S/2623 Group have no pins
corresponding to pulse output group 1.
Bit 5
G1INV Description
0 Inverted output for pulse outpu t group 1 (low-level output at pin for a 1 in PODRL)
1 Direct outpu t for pulse output group 1 (high-level output at pin for a 1 in PODRL)
(Initial value)
Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output
group 0 (pins PO3 to PO0). However, the H8S/2626 Group and H8S/2623 Group have no pins
corresponding to pulse output group 0.
Bit 4
G0INV Description
0 Inverted output for pulse outpu t group 0 (low-level output at pin for a 1 in PODRL)
1 Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)
(Initial value)
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse
output group 3 (pins PO15 to PO12).
Bit 3
G3NOV Description
0 Normal operation in pulse output group 3 (output values updated at compare matc h A
in the selected TPU channel) (Initial value)
1 Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse
output group 2 (pins PO11 to PO8).
Bit 2
G2NOV Description
0 Normal operation in pulse output group 2 (output values updated at compare matc h A
in the selected TPU channel) (Initial value)
1 Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Section 11 Programmable Pu lse Generator (PPG)
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Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse
output group 1 (pins PO7 to PO4). However, the H8S/2626 Group and H8S/2623 Group have no
pins corresponding to pulse output group 1.
Bit 1
G1NOV Description
0 Normal operation in pulse output group 1 (output values updated at compare matc h A
in the selected TPU channel) (Initial value)
1 Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse
output group 0 (pins PO3 to PO0). However, the H8S/2626 Group and H8S/2623 Group have no
pins corresponding to pulse output group 0.
Bit 0
G0NOV Description
0 Normal operation in pulse output group 0 (output values updated at compare matc h A
in the selected TPU channel) (Initial value)
1 Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
11.2.7 Port 1 Data Direction Register (P1DDR)
Bit:76543210
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value:00000000
R/W:WWWWWWWW
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1.
Port 1 is mu ltiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG ou tput must
be set to 1. For further information about P1DDR, see section 9.2, Port 1.
Section 11 Programmable Pu lse Generator (PPG)
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11.2.8 Module Sto p Co ntro l Register A (MSTPCRA)
Bit:76543210
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value:00111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRA is a 16-bit readable/writable register that performs module stop mode control.
When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cy cle
and a transition is made to module stop mode. Registers cannot be read or written to in module
stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset an d in hardware standby mode. It is not initialized in
software standby mode.
Bit 3—Module Stop (MSTPA3): Specifies the PPG module stop mode.
Bit 3
MSTPA3 Description
0 PPG module stop mode cleared
1 PPG module stop mode set (Initial value)
Section 11 Programmable Pu lse Generator (PPG)
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11.3 Operation
11.3.1 Overview
PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In
this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 11 .2 illu strates the PPG output operation and table 11.3 summarizes the PPG op e r ating
conditions.
Output trigger signal
Pulse output pin Internal data bus
Normal output/inverted output
C
PODRQD
NDER
Q
NDRQD
DDR
Figure 11.2 PPG Output Operation
Table 11.3 PPG O perating Conditio ns
NDER DDR Pin Function
0 0 Generic input port
1 Generic output port
1 0 Generic input port (but the PODR bit is a read-onl y bit, and when
compare ma tch occurs, the NDR bi t value is transferred to the PODR bit)
1 PPG pulse output
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before
the next compare match. For details of non-overlapping operation, see section 11.3.4, Non-
Overlapping Pulse Output.
Section 11 Programmable Pu lse Generator (PPG)
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11.3 .2 Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 11.3 shows the timing of these operations for th e case of
normal output in groups 2 and 3, triggered by compare match A.
TCNT N N+1
φ
TGRA N
Compare match
A signal
NDRH
mn
PODRH
PO8 to PO15
n
mn
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)
Section 11 Programmable Pu lse Generator (PPG)
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11.3.3 Normal Pulse Output
Sample Setup Procedure for Normal Pulse Output: Figure 11.4 shows a sample procedure for
setting up normal pulse output.
Select TGR functions [1]
Set TGRA value
Set counting operation
Select interrupt request
Set initial output data
Enable pulse output
Select output trigger
Set next pulse
output data
Start counter
Set next pulse
output data
Normal PPG output
No
Yes
TPU setup
Port and
PPG setup
TPU setup
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Compare match?
[1] Set TIOR to make TGRA an output
compare register (with output
disabled)
[2] Set the PPG output trigger period
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR1 and CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC can also be set up to
transfer data to NDR.
[5] Set the initial output values in
PODR.
[6]
Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[7] Select the TPU compare match
event to be used as the output
trigger in PCR.
[8] Set the next pulse output values in
NDR.
[9] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[10]
At each TGIA interrupt, set the next
Figure 11.4 Setup Procedure for Normal Pulse Output (Example)
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Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11.5 shows
an example in which pulse output is used for cyclic five-phase pulse ou tput.
TCNT value TCNT
TGRA
H'0000
NDRH
00 80 C0 40 60 20 30 10 18 08 88
PODRH
PO15
PO14
PO13
PO12
PO11
Time
Compare match
C0
80
C080 40 60 20 30 10 18 08 88 80 C0 40
Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output)
[1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output
compare register and the counter will be cleared by compare match A. Set th e trigger period in
TGRA and set the TGIEA b it in TIER to 1 to enable the compare match A (TGI A) interrupt.
[2] Write H'F8 in P1DDR and NDERH, and set the G3 CMS1 , G3 CMS0 , G2CMS1, and G2CMS0
bits in PCR to select compare m a tch in the TPU channel set up in the previous step to be the
output trigger. Write output data H'80 in NDRH.
[3] T he timer counter in the TPU channel starts. When compare match A occurs, the NDRH
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
[4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained
subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88, ... at successive TGIA
interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained
without imposing a load on the CPU.
Section 11 Programmable Pu lse Generator (PPG)
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11.3.4 Non-Overlapping Pulse Output
Sample Setup Pr ocedure for Non-O verlapping Pulse Output: Figure 11.6 shows a sample
procedure for setting up non-overlapping pulse output.
Select TGR functions [1]
Set TGR values
Set counting operation
Select interrupt request
Set initial output data
Enable pulse output
Select output trigger
Set next pulse
output data
Start counter
Set next pulse
output data
Compare match? No
Yes
TPU setup
PPG setup
TPU setup
Non-overlapping
PPG output
Set non-overlapping groups
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[1] Set TIOR to make TGRA and
TGRB an output compare registers
(with output disabled)
[2] Set the pulse output trigger period
in TGRB and the non-overlap
margin in TGRA.
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR1 and CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC can also be set up to
transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[7] Select the TPU compare match
event to be used as the pulse
output trigger in PCR.
[8] In PMR, select the groups that will
operate in non-overlap mode.
[9] Set the next pulse output values in
NDR.
[10] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[11] At each TGIA interrupt, set the next
output values in NDR.
Figure 11.6 Setup Pro cedure f or Non-Overla pping Pulse Output (Example)
Section 11 Programmable Pu lse Generator (PPG)
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Example of Non-Overlapping Pulse Output (Exa mple of Four-Phase Complement ary Non-
Overlapping Output): Figure 11.7 shows an example in which pulse output is used for four-
phase complementary non-overlapping pulse output.
TCNT value
TCNT
TGRB
TGRA
H'0000
NDRH 95 65 59 56 95 65
00 95 05 65 41 59 50 56 14 95 05 65
PODRH
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Time
Non-overlap margin
Figure 11.7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
Section 11 Programmable Pu lse Generator (PPG)
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[1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are
output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
[2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare m a tch in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
[3] T he timer counter in the TPU channel starts. When a compare match with TGRB occurs,
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
[4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by
writing H'59 , H'56, H'95, ... at successive TGIA interrupts. I f the DTC is set for activation by
this interrupt, pulse output can be obtained without imposing a load on the CPU.
Section 11 Programmable Pu lse Generator (PPG)
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11.3.5 Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 11.8 shows the outputs when G3 INV and G2INV are cleared to 0, in addition to the
settings of figure 11.7.
TCNT value
TCNT
TGRB
TGRA
H'0000
NDRH 95 65 59 56 95 65
00 95 05 65 41 59 50 56 14 95 05 65
PODRL
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Time
Figure 11.8 Inverted Pulse Output (Example)
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11.3.6 Pulse Output Trigg ered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
function s as an input capture register in the TPU channel selected b y PCR, pulse outp u t will be
triggered by the input capture signal.
Figure 11.9 shows the timing of this output.
φ
N
MN
TIOC pin
Input capture
signal
NDR
PODR
MN
PO
Figure 11.9 Pulse Output Triggered by Input Capture (Example)
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11.4 Usage Notes
Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions
such as the TPU. When output by another peripheral function is enabled, the corresponding pins
cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits
takes place, regardless of the usage of the pins.
Pin functions should be changed only under conditio ns in which the output trigger even t will not
occur.
Note on Non- Overlapping Out put : During non-overlapping operation, the transfer of NDR bit
values to PODR bits takes place as follows.
• NDR bits are always transferred to PODR bits at compare match A.
• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their valu e is 1.
Figure 11.10 illustrates the non-overlapp ing pu lse output oper a tion.
Compare match A
Compare match B
Pulse
output
pin Normal output/inverted output
C
PODRQD
NDER
Q
NDRQD
Internal data bus
DDR
Figure 11.10 Non-Overlapping P ulse Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. The NDR contents should not be altered during the interval from compare
match B to compare match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must
be written before th e next co mpare match B occurs.
Section 11 Programmable Pu lse Generator (PPG)
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Figure 11.11 shows the timing of this operation.
0/1 output0 output 0/1 output0 output
Do not write
to NDR here
Write to NDR
here
Compare match A
Compare match B
NDR
PODR
Do not write
to NDR here
Write to NDR
here
Write to NDR Write to NDR
Figure 11.11 Non-Overlapping Operation and NDR Write Timing
Section 11 Programmable Pu lse Generator (PPG)
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Section 12 Watchdog Timer
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Section 12 Watchdog Timer
12.1 Overview
A single on-chip watchdog timer channel (WDT0) is provided in the H8S/2623 Group, and two
watchdog timer channels (WDT0 and WDT1) in the H8S/2626 Group. The WDT outputs an
overflow signal (WDTOVF) if a system crash preven ts the CPU from writing to the timer counter,
allowing it to overflow. At the same time, the WDT can also generate an inter nal reset signal for
the H8S/2626 Group or H8S/2623 Group.
When this watchdog function is not needed, the WDT can be used as an in terval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
12.1.1 Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
• WDTOVF output when in watchdog timer mode
If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether the LSI
is internally re set or an NMI interrupt is gen e r a ted at the same time.
• Interrupt gener a tion wh en in in terval tim er m ode
If the counter overf lows, the WDT g enerates an interval timer interrupt.
• WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be
selected
The maximum interval of the WDT is given as a system clock cycle × 131072 × 256.
A subclock may be selected for the input counter of WDT1.
Where a subclock is selected, the maximum interval is given as a subclock cycle × 256 × 256.
• Selected clock can be output from the BUZZ output pin (WDT1)
Section 12 Watchdog Timer
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12.1.2 Block Diagram
Figures 12.1 (a) and 12.1 (b) show block diagrams of the WDT.
Overflow
Interrupt
control
WOVI 0
(interrupt request
signal)
WDTOVF
Internal reset signal*Reset
control
RSTCSR TCNT TSCR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock Clock
select
Internal clock
sources
Bus
interface
Module bus
Legend:
TCSR
TCNT
RSTCSR
Note: * The type of internal reset signal depends on a register setting.
: Timer control/status register
: Timer counter
: Reset control/status register
Internal bus
WDT
Figure 12.1 (a) Block Diagram of WDT0
Section 12 Watchdog Timer
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Overflow
Interrupt
control
Reset
control
WOVI1
(Interrupt request signal)
BUZZ
Internal reset signal*
TCNT TCSR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock Clock
select
Internal clock
Bus
interface
Internal bus
Module bus
TCSR :
TCNT : Timer control/status register
Timer counter
WDT
Legend:
Note: * An internal reset signal can be generated by setting the register.
Internal NMI
Interrupt request signal
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Figure 12.1 (b) Block Diagram of WDT1
Section 12 Watchdog Timer
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12.1.3 Pin Configuration
Table 12.1 describes the WDT output pin.
Table 12.1 WDT Pin
Name Symbol I/O Function
Watchdog timer overf low WDTOVF Output Outputs counter ov erflow si gnal in watchdog
time r mode
Buzzer output*BUZZ Output Outputs clock selected by watchdog timer
(WDT1)
Note: *Cannot be used in the H8S/2623 Group.
12.1.4 Register Configuration
Table 12.2 summarizes the WDT register configuration. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 12.2 WDT Registers
Address*1
Channel Name Abbreviation R/W Initial Value Write*2Read
0 Timer control/status register 0 TCSR0 R/(W)*3H'18 H'FF74 H'FF74
Timer counter 0 TCNT0 R/W H'00 H'FF74 H'FF75
Reset control/ stat us r egi ster RSTCSR R/(W)*3H'1F H'FF76 H'FF77
1*4Timer control/status register 1 TCSR1 R/(W)*3H'00 H'FFA2 H'FFA2
Timer counter 1 TCNT1 R/W H'00 H'FFA2 H'FFA3
All Pin function control register PFCR R/W H'0D/H'00 H'FDEB
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 12.2.5, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.
4. Cannot be used in the H8S/2623 Group.
Section 12 Watchdog Timer
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12.2 Register Descriptions
12.2.1 Timer Counter (TCNT)
Bit:76543210
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts cou nting pulses generated from the in ter nal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), eith er the watchdog timer overflow sig nal (WDTOVF) or an interval timer in terrupt
(WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mod e, or wh en the TME bit is cleared
to 0. It is no t initialized in software standby mode.
Note: * TCNT is write-protected by a password to prev en t accidental overwriting. For details
see section 12.2.5, Notes on Register Access.
Section 12 Watchdog Timer
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12.2.2 Timer Control/Status Register (TCSR)
• TCSR0
Bit:76543210
OVF WT/IT TME — — CKS2 CKS1 CKS0
Initial value:00011000
R/W : R/(W)*R/W R/W — — R/W R/W R/W
Note: *Only a 0 can be written, for flag clearing.
• TCSR1*1
Bit:76543210
OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0
Initial value:00000000
R/W : R/(W)*2R/W R/W R/W R/W R/W R/W R/W
Notes: 1. Cannot be used in the H8S/2623 Group.
2. Only a 0 can be written, for flag clearing.
TCSR is an 8-b it r eadable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in h ardwar e standby mode. It is not
initialized in software standby mode.
Note: * TCSR is write-protected by a passwor d to prevent accidental overwriting. For details
see section 12.2.5, Notes on Register Access.
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.
Bit 7
OVF Description
0[Clearing cond iti ons ] (Initial val ue)
• Cleared when 0 is written to the TME bit (Only applies to WDT1)
• Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
1[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
Section 12 Watchdog Timer
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In interval timer mode, to clear OVF flag in WOVI handling routine, read TCSR when OVF = 1,
then write with 0 to OVF, as stated above.
When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR
read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0 to OVF.
In this case, reading TCSR when OVF = 1 two times meet the requirements of OVF clear
condition. Please read TCSR when OVF = 1 two times before writing with 0 to OVF.
Bit 6—Timer Mode Select (WT/IT
ITIT
IT): Selects whether the WDT is used as a watchdog timer or
interval timer. Wh en TCNT overflows, WDT0 generates the WDTOVF signal when in watchdog
timer mode, or a WOVI in terrupt request to the CPU when in interval timer mode. WDT1
generates a reset or NMI interrupt request when in watchdog timer mode, or a WOVI interrupt
request to the CPU when in interval timer mode.
• WDT0 Mode Select
WDT0
WT/IT
ITIT
IT Description
0 Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows. (Initial value)
1 Watchdog timer mode: WDT0 outputs a WDTOVF signal when the TCNT overflows.*
Note: *For details on a TCNT overflow in watchdog timer mode, see section 12.2.3, Reset
Control/Status Register (RSTCSR).
• WDT1 Mode Select*
WDT1
WT/IT
ITIT
IT Description
0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows. (Initial value)
1 Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from
the CPU when the TCNT overflows.
Note: *Cannot be us ed in the H8S/2623 Group.
Bit 5—Timer Enable (TME) : Selects whether TCNT runs or is halted.
Bit 5
TME Description
0 TCNT is initialized to H'00 and halted (Initial value)
1 TCNT counts
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 406 of 1042
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WDT0 TCSR Bit 4—Reserved Bit: This bit is always read as 1 and cannot be modified.
WDT1 TCSR Bit 4—Prescaler Select (PSS): This bit is used to select an input clock source for
the TCNT of WDT1.
See the descriptions of Clock Select 2 to 0 for details.
This bit cannot be used in the H8S/2623 Group.
WDT1 TCSR
Bit 4
PSS Description
0 The TCNT counts frequency-division clock pulses of the φ based
prescaler (PSM). (Initial value)
1 The TCNT counts frequency-division clock pulses of the φ SUB-based prescaler
(PSS).
WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified.
WDT1 TCSR Bit 3—R eset or NMI (RST/NMI
NMINMI
NMI): This bit is used to choose between an internal
reset request and an NMI request when the TCNT overflows during the watchdog timer mode.
This bit cannot be used in the H8S/2623 Group.
Bit 3
RTS/NMI
NMINMI
NMI Description
0 NMI request. (Initial value)
1 Internal reset request.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 407 of 1042
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Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (φ) or subclock (φ SUB), for input to TCNT.
• WDT0 Input Clock Select
Bit 2 Bit 1 Bit 0 Description
CKS2 CKS1 CKS0 Clock Overflow Period* (where φ
φφ
φ = 20 MHz)
000 φ/2 (Initial value) 25.6 µs
1φ/64 819.2 µs
10 φ/128 1.6 ms
1φ/512 6.6 ms
100 φ/2048 26.2 ms
1φ/8192 104.9 ms
10 φ/32768 419.4 ms
1φ/131072 1.68 s
Note: *An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the oc currence of a TCNT overflow.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 408 of 1042
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• WDT1 Input Clock Select*2
Description
Bit 4 Bit 2 Bit 1 Bit 0
PSS CKS2 CKS1 CKS0 Clock Overflow Period*1 (where φ
φφ
φ = 20 MHz)
(where φ
φφ
φ SUB = 32.768 kHz)
0000 φ/2 (Initial value) 25.6 µs
1φ/64 819.2 µs
10 φ/128 1.6 ms
1φ/512 6.6 ms
100 φ/2048 26.2 ms
1φ/8192 104.9 ms
10 φ/32768 419.4 ms
1φ/131072 1.68 s
1000 φSUB/2 15.6 ms
1φSUB/4 31.3 ms
10 φSUB/8 62.5 ms
1φSUB/16 125 ms
100 φSUB/32 250 ms
1φSUB/64 500 ms
10 φSUB/128 1 s
1φSUB/256 2 s
Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the oc currence of a TCNT overflow.
2. Cannot be used in the H8S/2623 Group.
12.2.3 Reset Control/Status Register (RSTCSR)
Bit:76543210
WOVFRSTERSTS—————
Initial value:00011111
R/W : R/(W)*R/WR/W—————
Note: *Only 0 can be written, for flag clearing.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 409 of 1042
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RSTCSR is initialized to H'1F by a reset sig nal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For
details see section 12.2.5, Notes on Register Access.
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) d uring watchdog timer oper ation. Th is bit is not set in interval timer mode.
Bit 7
WOVF Description
0 [Clearing cond iti on] (Initial val ue)
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
1 [Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Bit 6—Re se t Enable (RSTE) : Specifies whether or not a reset signa l is generated in the chip if
TCNT overflows during watchdog timer operation.
Bit 6
RSTE Description
0 Reset signal is not gen erate d if TCNT overfl ow s* (Initial value)
1 Reset signal is gen erate d if TCNT overflow s
Note: *The modules within the chip are not reset, but TCNT and TCSR within the WDT are
reset.
Bit 5—Reset Select (R STS): Selects the typ e of internal reset generated if TCNT overflo ws
during watchdog timer operation.
For details of the types of reset, see section 4, Exception Handling.
Bit 5
RSTS Description
0 Power-on reset (Initial value)
1 Setting prohibited
Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 410 of 1042
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12.2.4 Pin Function Control Register (PFCR)
Bit:76543210
— — BUZZE — AE3 AE2 AE1 AE0
Initial value : 0 0 0 0 1/0 1/0 0 1/0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control
Register (PF CR).
Bit 5—BUZZ Output Enab le (BUZZE)*: Enables or disables BUZZ output from the PF1 pin.
The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal.
Note: * In the H8S/2623 Group this bit is reserved, and must be written with 0.
Bit 5
BUZZE Description
0 Functions as PF1 I/O pin (Initial value)
1 Functions as BUZZ output pin
12.2.5 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be wr itten to by a word transfer instruction.
They cannot be written to with byte instructions.
Figure 12 .2 sh ows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 411 of 1042
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TCNT write
TCSR write
Address: H'FF74
Address: H'FF74
H'5A Write data
15 8 7 0
H'A5 Write data
15 8 7 0
Figure 12.2 Format of Data Written to TCNT and TCSR
Writing to RSTCSR: RSTCSR must be written to by word transfer instr uction to address
H'FF76. It cannot be written to with byte instructions.
Figure 12.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF
bit differs from that for writing to the RSTE and RSTS bits.
To write 0 to the WOVF bit, the wr ite data must have H'A5 in the upper byte and H'00 in the
lower byte. This clears th e WOVF b it to 0, but h as no ef f ect on the RSTE and RSTS bits. To write
to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the
write data. This writes th e values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits,
but has no effect on the WOVF bit.
H'A5 H'00
15 8 7 0
H'5A Write data
15 8 7 0
Writing 0 to WOVF bit
Writing to RSTE and RSTS bits
Address: H'FF76
Address: H'FF76
Figure 12.3 Format of Data Written to RSTCSR
Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as
other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for
RSTCSR.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 412 of 1042
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12.3 Operation
12.3.1 Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and TME bit to 1. Software
must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflows occurs. This ensur e s that TCNT does not ov erflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system crash or other error, in
the WDT0 the WDTOVF signal is output. This is shown in figure 12.4 (a). This WDTOVF signal
can be used to reset the system. The WDTOVF signal is output for 132 states when RSTE = 1, and
for 130 states when RSTE = 0.
If TCNT over f lows when 1 is set in the RSTE bit in RSTCSR, a signal that re sets the chip
internally is g e n e r a ted at the sam e tim e as the WDTOVF signal. This reset can be selected as a
power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The
internal reset signal is output for 518 states.
If a reset caused by a signal input to th e RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
In the case of WDT1, the chip is reset, or an NMI interrupt request is g enerated, for 516 sy stem
clock periods (516φ) (515 or 516 states when the clock source is φSUB (PSS = 1)). T his is
illustrated in figure 12.4 (b ).
An NMI request from the watchdog timer and an interrupt request from the NMI pin are both
treated as having the same vector. So, avoid handling an NMI request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 413 of 1042
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TCNT count
H'00 Time
H'FF
WT/IT=1
TME=1 H'00 written
to TCNT WT/IT=1
TME=1 H'00 written
to TCNT
132 states*
2
518 states
WDTOVF signal
Internal reset signal*
1
WT/IT
TME
Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1.
2. 130 states when the RSTE bit is cleared to 0.
Overflow
WDTOVF and
internal reset are
generated
WOVF=1
: Timer mode select bit
: Timer enable bit
Legend:
Figure 12.4 (a) WDT0 Watchdog Timer Operation
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 414 of 1042
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TCNT value
H'00 Time
H'FF
WT/IT= 1
TME= 1 Write H'00'
to TCNT WT/IT= 1
TME= 1 Write H'00'
to TCNT
515/516 states
Internal
reset signal
WT/IT
TME
Overflow
Occurrence
of internal reset
WOVF= 1*
: Timer Mode Select bit
: Timer Enable bit
Note: * The WOVF bit is set to 1 and then cleared to 0 by an internal reset.
Figure 12.4 (b) WDT1 Operation in Watchdog Timer Mode
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 415 of 1042
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12.3.2 Interval Timer Operation
To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1.
An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the
WDT is operating as an interval timer, as shown in figure 12.5. This function can be used to
generate interrupt requests at regular intervals.
TCNT count
H'00 Time
H'FF
WT/IT=0
TME=1 WOVI
Overflow Overflow Overflow Overflow
Legend:
WOVI: Interval timer interrupt request generation
WOVI WOVI WOVI
Figure 12.5 Interval Timer Operation
12.3.3 Timing of Setting Overflow Flag (OVF)
The OVF flag is set to 1 if TCNT overflows during in ter val timer operation. At the sam e time, an
interval timer in terrupt (WOVI) is requested. This timing is sh own in figure 12.6.
With WDT1, the OVF bit of the TCSR is set to 1 and a simultaneous NMI interrupt is requested
when the TCNT overflows if the NMI request has been chosen in the watchdog timer mode.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 416 of 1042
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φ
TCNT H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 12.6 Timing of Setting of OVF
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
In the WDT0, th e WOVF f lag is set to 1 if TCNT overflows during watchdog timer oper a tion. At
the same time, the WDTOVF signal g oes low. If TCNT overflows while the RSTE bit in RSTCSR
is set to 1, an in ternal reset signa l is generated for the entire chip. Figure 12.7 shows the timing in
this case.
φ
TCNT H'FF H'00
Overflow signal
(internal signal)
WOVF
WDTOVF signal
Internal reset
signal
132 states
518 states (WDT0)
515/516 states (WDT1)
Figure 12.7 Timing of Setting of WOVF
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 417 of 1042
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12.4 Interrupts
During interval timer mode operation, an overflow gener ates an interval timer interrupt (WOVI) .
The interval timer interrupt is requested wh enever the OVF flag is set to 1 in TCSR. OVF mu st be
cleared to 0 in the interrupt handling routine.
If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated
when a TCNT overflow occurs.
12.5 Usage Notes
12.5.1 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 12.8 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT NM
T
1
T
2
TCNT write cycle
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 418 of 1042
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12.5.2 Changing Va lue of PSS and CKS2 to CKS0
If bits PSS and CKS2 to CKS0 in TCS R are wr itten to while the WDT is operating, errors could
occur in the increm entation. Software must stop the watchdog timer (by clearing the TME bit to 0)
befor e chan ging the value of bits PSS and CKS2 to CKS0.
12.5.3 Switching between Watchdo g Timer Mode a nd Int erval Timer Mo de
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
12.5.4 System Reset by WDTOVF
WDTOVFWDTOVF
WDTOVF Signal
If the WDTOVF output signal is input to the RES pin of the H8S/2626 Group or H8S/2623 Group,
the chip will no t b e initialized correctly. Make sure th at the WDTOVF signal is not input logically
to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown
in figure 12.9.
Reset input
Reset signal to entire system
H8S/2626 Group or
H8S/2623 Group
RES
WDTOVF
Figure 12.9 Circuit for System Reset by WDTOVF
WDTOVFWDTOVF
WDTOVF Signal (Example)
12.5.5 Internal Reset in Watchdog Timer Mode
The H8S/2626 Group or H8S/2623 Group is not reset internally if TCNT overflows while the
RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TCSR of the WDT are
reset.
TCNT, TCSR, and RSTCSR cannot be written to while the WDTOVF signal is low. Also note
that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg,
therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 419 of 1042
REJ09B0275-0500
12.5.6 OVF Flag Clearing in Interval Timer Mode
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there
is a possibility th at the OVF flag setting an d reading will conflict, su ch as wh en the OVF flag is
polled with th e interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before
writing 0 to the OVF bit to clear the flag.
Section 12 Watchdog Timer
Rev. 5.00 Jan 10, 2006 page 420 of 1042
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Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 421 of 1042
REJ09B0275-0500
Section 13 Serial Communication Interface (SCI)
13.1 Overview
The H8S/2626 Group and H8S/2623 Group have three independent serial communication
interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial
communication. A function is also provided for serial communication between processors
(multipr ocessor communication function) .
13.1.1 Features
SCI features are listed below.
• Choice of asynchronous or clocked synchronous serial communication mode
Asynchronous mode
Serial data communication executed using asynchronous system in which synchronization
is achieved character by character
Serial data communication can be carried out with standard asynchronous communication
chips such as a Un iversal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
A multipro cessor communicatio n function is provided that enables serial data
communication with a number of processors
Choice of 12 serial data transfer formats
Data length : 7 or 8 bits
Stop bit length : 1 or 2 bits
Parity : Even, odd, or none
Multiprocessor bit : 1 or 0
Receive error detection : Parity, overrun, and framing errors
Break detection : Break can be detected by reading the RxD pin level directly in
case of a framing error
Clocked Synchronous mode
Serial data communication synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
commun ication function
One serial data transfer format
Data length : 8 bits
Receive error detection : Overrun errors detected
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 422 of 1042
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• Full-duplex communication capab ility
The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• Choice of LSB-first or MSB- first transfer
Can be selected regardless of the communication mode* (except in the case of
asynchronous mode 7-bit data)
Note: * Descriptions in this section refer to LSB-first transf er .
• On-chip baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Four interrupt sources
Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive
error — that can issue requests independently
The transmit-data-empty interrupt and receive data full interrupts can activate the data
transfer controller (DTC) to execute data transfer
• Module stop mode can be set
As the initial setting, SCI operation is halted. Register access is enabled by exiting module
stop mode.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 423 of 1042
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13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the SCI.
Bus interface
TDR
RSR
RDR
Module data bus
TSR
SCMR
SSR
SCR
Transmission/
reception control
BRR
Baud rate
generator
Internal
data bus
RxD
TxD
SCK
Parity generation
Parity check
Clock
External clock
φ
φ/4
φ/16
φ/64
TXI
TEI
RXI
ERI
SMR
Legend:
RSR
RDR
TSR
TDR
SMR
SCR
SSR
SCMR
BRR
: Receive shift register
: Receive data register
: Transmit shift register
: Transmit data register
: Serial mode register
: Serial control register
: Serial status register
: Smart card mode register
: Bit rate register
Figure 13.1 Block Diagram of SCI
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 424 of 1042
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13.1.3 Pin Configuration
Table 13.1 shows the serial pins for each SCI channel.
Table 13.1 SCI Pins
Channel Pin Name Symbol*I/O Function
0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output
Receive data pin 0 RxD0 Input SCI0 receive data input
Transmit data pin 0 TxD0 Output SCI0 transmit data output
1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output
Receive data pin 1 RxD1 Input SCI1 receive data input
Transmit data pin 1 TxD1 Output SCI1 transmit data output
2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output
Receive data pin 2 RxD2 Input SCI2 receive data input
Transmit data pin 2 TxD2 Output SCI2 transmit data output
Note: *Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 425 of 1042
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13.1.4 Register Configuration
The SCI has the internal registers shown in table 13.2. These registers are used to specify
asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control
transmitter/receiver.
Table 13.2 SCI Registers
Channel Name Abbreviation R/W Initial Value Address*1
0 Serial mode register 0 SMR0 R/W H'00 H'FF78
Bit rate register 0 BRR0 R/W H'FF H'FF79
Serial control register 0 SCR0 R/W H'00 H'FF7A
Transmit data register 0 TDR0 R/W H'FF H'FF7B
Serial status register 0 SSR0 R/(W)*2H'84 H'FF7C
Receive data regist er 0 RDR0 R H'00 H'FF7 D
Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E
1 Serial mode register 1 SMR1 R/W H'00 H'FF80
Bit rate register 1 BRR1 R/W H'FF H'FF81
Serial control register 1 SCR1 R/W H'00 H'FF82
Transmit data register 1 TDR1 R/W H'FF H'FF83
Serial status register 1 SSR1 R/(W)*2H'84 H'FF84
Receive data regist er 1 RDR1 R H'00 H'FF8 5
Smart card mode register 1 SCMR1 R/W H'F2 H'FF86
2 Serial mode register 2 SMR2 R/W H'00 H'FF88
Bit rate register 2 BRR2 R/W H'FF H'FF89
Serial control register 2 SCR2 R/W H'00 H'FF8A
Transmit data register 2 TDR2 R/W H'FF H'FF8B
Serial status register 2 SSR2 R/(W)*2H'84 H'FF8C
Receive data regist er 2 RDR2 R H'00 H'FF8 D
Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E
All Module stop control register B MSTPCRB R/W H'FF H'FDE9
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 426 of 1042
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13.2 Register Descriptions
13.2.1 Receive Shift Register (RSR)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit
R/W
:
:
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferr ed to RDR automatically.
RSR cannot be directly read or written to by the CPU.
13.2.2 Receive Data Register (RDR)
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit
Initial value
R/W
:
:
:
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to
RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, enables continuous receive
operations to be performed.
RDR is a read-o nly register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep
mode, or module stop mode.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 427 of 1042
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13.2.3 Transmit Shift Register (TSR)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit
R/W
:
:
TSR is a register used to transmit serial d ata.
To perform serial data transmission , the SCI first transfers transmit data from TDR to TSR, then
sends the data to the TxD pin starting with the LSB (bit 0).
When transm ission of one byte is completed, the nex t tr ansmit data is transf erred from TDR to
TSR, and transm ission started, au tomatically. Howev er, d ata transfer from TDR to TSR is not
performed if the TDRE bit in SSR is set to 1.
TSR cannot be directly read or written to by the CPU.
13.2.4 Transmit Data Register (TDR)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
R/W
:
:
:
TDR is an 8-bit register that stores data for serial transmission.
When the SCI detects that TSR is empty , it transfers the tr ansmit data written in TDR to TSR and
starts serial transmission. Continuous serial transmission can be carried out by writing the next
transmit data to TDR during serial transmission of the data in TSR.
TDR can be read or written to by the CPU at all times.
TDR is initialized to H'FF by a reset, in stand by mode, watch mode, subactiv e mode, subsleep
mode, or module stop mode.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 428 of 1042
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13.2.5 Serial Mode Register (SMR)
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Bit
Initial value
R/W
:
:
:
SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SMR can be read o r written to by the CPU at all times.
SMR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bit 7—Communication Mode (C/A
AA
A): Selects asynchronous mode or clocked synchronous mode
as the SCI operating mode.
Bit 7
C/A
AA
ADescription
0 Asynchronous mode (Initial value)
1 Clocked sy nchronous mode
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR Description
0 8-bit data (Initial value)
1 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not
possible to choose between LSB-first or MSB-first transfer.
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In clocked synchronous mode
with a multipr ocessor format, parity bit addition and checking is not performed, regardless o f the
PE bit setting.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 429 of 1042
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Bit 5
PE Description
0 Parity bit addition and checking disabled (Initial value)
1 Parity bit addition and checking enabled*
Note: *When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
Bit 4—Parity Mode (O/E
EE
E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is on ly valid when the PE bit is set to 1 , enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode,
when parity addition and checking is disabled in asynchronous mode, and when a multip r ocessor
format is used.
Bit 4
O/E
EE
EDescription
0 Even parity*1 (Initial value)
1 Odd parity*2
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1 bi ts in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bi ts in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Bit 3—St op Bit Le ngth (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the
STOP bit setting is invalid since stop bits are not added.
Bit 3
STOP Description
0 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end
of a transmit character before it is sent. (Initial value)
1 2 stop bits:In transmission, two 1 bits (stop bits) are added to the end of a transmit
character before it is sent.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 430 of 1042
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In reception, only the first stop bit is checked, regardless of the STOP bit settin g. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as th e star t bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit p a r ity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in clocked synchronous mode.
For details of the multiprocesso r communication fun c tion, see section 13.3.3, Multipr ocessor
Communication Function.
Bit 2
MP Description
0 Multiprocessor function disabled (Initial value)
1 Multiprocessor format selected
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source fo r the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 13.2.8, Bit Rate Register (BRR).
Bit 1 Bit 0
CKS1 CKS0 Description
00φ clock (Initial value)
1φ/4 clock
10φ/16 clock
1φ/64 clock
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 431 of 1042
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13.2.6 Serial Control Register (SCR)
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit
Initial value
R/W
:
:
:
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt
(TXI) request generation when serial transmit d a ta is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1 .
Bit 7
TIE Description
0 Transmit data empty interrupt (TXI) requests disabled (Initial value)
1 Transmit data empty interrupt (TXI) requests enabled
Note: TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then
clearing it to 0, or cl earing the TIE bit to 0.
Section 13 Serial Communication Interface (SCI)
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Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)
request and receive erro r interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE Description
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
disabled* (Initial value)
1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
enabled
Note: *RXI and ERI interrupt request cancellation can be performed by reading 1 from the
RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the
RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE Description
0 Transmi ss ion dis abl ed*1 (Initial value)
1 Transmi ss ion enab led *2
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting mu st be performed to decide the transfer format before setting the TE bit
to 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE Description
0 Recept ion di sab led *1 (Initial value)
1 Recept ion ena ble d*2
Notes: 1. Cle aring the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bi t
to 1.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 433 of 1042
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Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or d isables multiprocessor interrup ts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1.
The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0 Multiprocessor interrupts disabled (normal reception performed) (Initial value)
[Clearing cond iti ons ]
• When the MPIE bit is cleared to 0
• When MPB= 1 data is received
1 Multiprocessor interrupts enabled*
Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: *When receive data including MPB = 0 is received, receive data transfer from RSR to
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,
is not performed. When rece ive data including MPB = 1 is received, the MPB bit in SSR
is set to 1, the MPIE bit is cleared to 0 automa tically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt
(TEI) request g e neration when there is no valid transmit data in TDR in MSB data transmission.
Bit 2
TEIE Description
0 Transmit end interrupt (TEI) request disabled* (Initial value)
1 Transmit end interrupt (TEI) request enabled*
Note: *TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 434 of 1042
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Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case
of external clock operation (CKE1 = 1). Note that the SCI’s operating mode must be decided using
SMR before setting the CKE1 and CKE0 bits.
For details of clock source selection, see table 13.9.
Bit 1 Bit 0
CKE1 CKE0 Description
0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port*1
Clocked sy nchr ono us
mode Intern al clo ck/SC K pin f un ctio ns as serial clock
output*1
1 Asynchronous mode Internal clock/SC K pin fun ctio ns as clo ck output*2
Clocked sy nchr ono us
mode Intern al clo ck/SC K pin f un ctio ns as serial clock
output
1 0 Asynchronou s mode External clo ck/SCK pin fun ction s as clo ck input*3
Clocked sy nchr ono us
mode External clo ck/SC K pin fun ction s as seri al clo ck
input
1 Asynchronous mode External clock/SC K pin fun ction s as clo ck input*3
Clocked sy nchr ono us
mode External clo ck/SC K pin fun ction s as seri al clo ck
input
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 435 of 1042
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13.2.7 Serial Status Register (SSR)
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Bit
Initial value
R/W
:
:
:
Note: *Only 0 can be written, for flag clearing.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multipr ocessor bits.
SSR can be read o r wr itten to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, in standby mode, watch mode, subactive mode, subsleep
mode, or module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE Description
0 [Clearing cond iti ons ]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions] (Initial value)
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Section 13 Serial Communication Interface (SCI)
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Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF Description
0 [Clearing cond iti ons ] (Initial value)
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
1 [Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER Description
0 [Clearing cond iti on] (Initial value) *1
When 0 is written to ORER after reading ORER = 1
1 [Setting condition]
When the next serial reception is completed while RDRF = 1*2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
Section 13 Serial Communication Interface (SCI)
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Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER Description
0 [Clearing cond iti on] (Initial value) *1
When 0 is written to FER after reading FER = 1
1 [Setting condition]
When the SCI checks whether the stop bit at the end of the receive data when
reception ends, and the stop bit is 0 *2
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception c annot be continued while the
FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 3
PER Description
0 [Clearing cond iti on] (Initial value) *1
When 0 is written to PER after reading PER = 1
1 [Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does not
match the parity setting (even or odd) specified by the O/E bit in SMR*2
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In clocked synchronous mode, serial transmission cannot be continued, either.
Section 13 Serial Communication Interface (SCI)
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Bit 2—Transmit End (T EN D ): Indicates that there is no valid d a ta in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND Description
0[Clearing cond iti ons ]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
1 [Setting conditions] (Initial value)
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
Bit 1—Multiprocessor Bit (MPB): When reception is performed using multipro cesso r format in
asynchro nou s mode, MPB stores the multiprocesso r b it in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB Description
0 [Clearing cond iti on] (Initial value)*
When data with a 0 multiprocessor bit is received
1 [Setting condition]
When data with a 1 multiprocessor bit is received
Note: *Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor
format.
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when multiprocessor format is not used, when not tran sm itting,
and in clocked synchronous mode.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 439 of 1042
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Bit 0
MPBT Description
0 Data with a 0 multiprocessor bit is transmitted (Initial value)
1 Data with a 1 multiprocessor bit is transmitted
13.2.8 Bit Rate Register (BRR)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
R/W
:
:
:
BRR is an 8-bit register that sets th e serial transfer bit r a te in accordance with the baud ra te
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all tim es.
BRR is initialized to H'FF by a reset and in hardware standby mode. It retains its previous state in
module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 1 3.3 shows sam ple BRR settin gs in async hronou s mode, and table 13.4 shows sample BRR
settings in clocked synchronous mode.
Section 13 Serial Communication Interface (SCI)
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Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
φ
φφ
φ = 4 MHz φ
φφ
φ = 4.9152 MHz φ
φφ
φ = 5 MHz
Bit Rate
(bit/s) nN Error
(%) nN Error
(%) nN Error
(%)
110 2 70 0.03 2 86 0.31 2 88 –0.25
150 1 207 0.16 1 255 0.00 2 64 0.16
300 1 103 0.16 1 127 0.00 1 129 0.16
600 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 25 0.16 0 31 0.00 0 32 –1.36
9600 0 12 0.16 0 15 0.00 0 15 1.73
19200 —— — 0 7 0.00 0 7 1.73
31250 0 3 0.00 0 4 –1.70 0 4 0.00
38400 —— — 0 3 0.00 0 3 1.73
φ
φφ
φ = 6 MHz φ
φφ
φ = 6.144 MHz φ
φφ
φ = 7.3728 MHz φ
φφ
φ = 8 MHz
Bit Rate
(bit/s) n N Error
(%) nN Error
(%) nN Error
(%) nN Error
(%)
110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03
150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16
300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16
600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16
1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16
2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16
4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16
9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16
19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16
31250 0 5 0.00 0 5 2.40 —— — 0 7 0.00
38400 0 4 –2.34 0 4 0.00 0 5 0.00 —— —
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 441 of 1042
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φ
φφ
φ = 9.8304 MHz φ
φφ
φ = 10 MHz φ
φφ
φ = 12 MHz φ
φφ
φ = 12.288 MHz
Bit Rate
(bit/s) nN Error
(%) nN Error
(%) nN Error
(%) nN Error
(%)
110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08
150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00
300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00
600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00
1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00
2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00
4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00
9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00
19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00
31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40
38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00
φ
φφ
φ = 14 MHz φ
φφ
φ = 14.7456 MHz φ
φφ
φ = 16 MHz φ
φφ
φ = 17.2032 MHz
Bit Rate
(bit/s) n N Error
(%) nN Error
(%) nN Error
(%) nN Error
(%)
110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48
150 2 181 0.13 2 191 0.00 2 207 0.13 2 223 0.00
300 2 90 0.13 2 95 0.00 2 103 0.13 2 111 0.00
600 1 181 0.13 1 191 0.00 1 207 0.13 1 223 0.00
1200 1 90 0.13 1 95 0.00 1 103 0.13 1 111 0.00
2400 0 181 0.13 0 191 0.00 0 207 0.13 0 223 0.00
4800 0 90 0.13 0 95 0.00 0 103 0.13 0 111 0.00
9600 0 45 –0.93 0 47 0.00 0 51 0.13 0 55 0.00
19200 0 22 –0.93 0 23 0.00 0 25 0.13 0 27 0.00
31250 0 13 0.00 0 14 –1.70 0 15 0.00 0 13 1.20
38400 —— — 0 11 0.00 0 12 0.13 0 13 0.00
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 442 of 1042
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φ
φφ
φ = 18 MHz φ
φφ
φ = 19.6608 MHz φ
φφ
φ = 20 MHz
Bit Rate
(bit/s) nN Error
(%) nN Error
(%) nN Error
(%)
110 3 79 –0.12 3 86 0.31 3 88 –0.25
150 2 233 0.16 2 255 0.00 3 64 0.16
300 2 116 0.16 2 127 0.00 2 129 0.16
600 1 233 0.16 1 255 0.00 2 64 0.16
1200 1 116 0.16 1 127 0.00 1 129 0.16
2400 0 233 0.16 0 255 0.00 1 64 0.16
4800 0 116 0.16 0 127 0.00 0 129 0.16
9600 0 58 –0.69 0 63 0.00 0 64 0.16
19200 0 28 1.02 0 31 0.00 0 32 –1.36
31250 0 17 0.00 0 19 –1.70 0 19 0.00
38400 0 14 –2.34 0 15 0.00 0 15 1.73
Section 13 Serial Communication Interface (SCI)
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Table 13.4 BRR Setting s f or Various Bit Ra tes (Clocked Synchronous Mode)
φ
φφ
φ = 4 MHz φ
φφ
φ = 8 MHz φ
φφ
φ = 10 MHz φ
φφ
φ = 16 MHz φ
φφ
φ = 20 MHz
Bit Rate
(bit/s) n N n N n N n N n N
110 ——
250 2 249 3 124 —— 3 249
500 2 124 2 249 —— 3 124 ——
1 k 1 249 2 124 —— 2 249 ——
2.5 k 1 99 1 199 1 249 2 99 2 124
5 k 0 199 1 99 1 124 1 199 1 249
10 k 0 99 0 199 0 249 1 99 1 124
25 k 0 39 0 79 0 99 0 159 0 199
50 k 0 19 0 39 0 49 0 79 0 99
100 k 0 9 0 19 0 24 0 39 0 49
250 k 0 3 0 7 0 9 0 15 0 19
500 k 0 1 0 3 0 4 0 7 0 9
1 M 0 0*01 03 04
2.5 M 0 0*01
5 M 00
*
Legend:
Blank: Cannot be set.
—: Can be set, but there will be a degree of error.
*: Continuous transfer is not possible.
Note: As far as possible, the setting should be made so that the error is no more than 1%.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 444 of 1042
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The BRR setting is found from the following formulas.
Asynchronous mode:
N = φ
64 × 22n–1 × B × 106 – 1
Clocked synchronous mode:
N = φ
8 × 22n–1 × B × 106 – 1
Where B: Bit r a te ( bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 25 5)
φ: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR Setting
n Clock CKS1 CKS0
0φ00
1φ/4 0 1
2φ/16 1 0
3φ/64 1 1
The bit rate error in asynchronous mode is found from the following formula:
Error (%) = { φ × 106
(N + 1) × B × 64 × 22n–1 – 1} × 100
Section 13 Serial Communication Interface (SCI)
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Table 13.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13.6
and 13.7 show the maximum bit rates with external clock input.
Table 13.5 Maximum Bit Rat e for Each Frequency (Asynchronous Mode)
φ
φφ
φ (MHz) Maximum Bit Rate (bit/s) n N
4 125000 0 0
4.9152 153600 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
12 375000 0 0
12.288 384000 0 0
14 437500 0 0
14.7456 460800 0 0
16 500000 0 0
17.2032 537600 0 0
18 562500 0 0
19.6608 614400 0 0
20 625000 0 0
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 446 of 1042
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Table 13.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ
φφ
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)
4 1.0000 62500
4.9152 1.2288 76800
5 1.2500 78125
6 1.5000 93750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
12 3.0000 187500
12.288 3.0720 192000
14 3.5000 218750
14.7456 3.6864 230400
16 4.0000 250000
17.2032 4.3008 268800
18 4.5000 281250
19.6608 4.9152 307200
20 5.0000 312500
Table 13.7 Maximum Bit Rat e with External Clo c k Input (Clocked Synchronou s Mode)
φ
φφ
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
12 2.0000 2000000.0
14 2.3333 2333333.3
16 2.6667 2666666.7
18 3.0000 3000000.0
20 3.3333 3333333.3
Section 13 Serial Communication Interface (SCI)
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13.2.9 Smart Card Mode Register (SCMR)
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Bit
Initial value
R/W
:
:
:
SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous
mode 7-bit d a ta, LSB- first or MSB-first can b e selected regardless of th e serial com munication
mode. The descr iptions in this chapter refer to LSB-first transfer.
For details of the other bits in SCMR, see 14.2.1, Smart Card Mode Register (SCMR).
SCMR is initial ized to H'F2 by a reset and in hardware standby mode. It retains its prev ious state
in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.
Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
This bit is valid wh en 8-bit data is used as the transmit/receive format.
Bit 3
SDIR Description
0 TDR contents are transmitted LSB-first (Initial value)
Receive data is stored in RDR LSB-first
1 TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 448 of 1042
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Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the
O/E bit in SMR.
Bit 2
SINV Description
0 TDR contents are transmitted without modification (Initial value)
Receive data is stored in RDR without modification
1 TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Bit 1—Reserved: This bit is always read as 1 and cannot be modified.
Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a
norma l SCI , 0 should be written in this bit.
Bit 0
SMIF Description
0 Operates as normal SCI (smart card interface function disabled) (Initial value)
1 Smart card interface function enabled
13.2.10 Module Stop Control Register B (MSTPCRB)
7
MSTPB7
1
R/W
6
MSTPB6
1
R/W
5
MSTPB5
1
R/W
4
MSTPB4
1
R/W
3
MSTPB3
1
R/W
0
MSTPB0
1
R/W
2
MSTPB2
1
R/W
1
MSTPB1
1
R/W
Bit
Initial value
R/W
:
:
:
MSTPCRB
MSTPCRB is 8-bit readable/writable registers that perform modu le stop mode control.
When one of bits MSTPB7 to MSTPB5 is set to 1, SCI0, SCI1, or SCI2, respectively, stops
operation at the end of the bus cycle, and enters module stop mode. For details, see sections
21A.5, 21B.5, Module Stop Mode.
MSTPCRB is initialized to H'FF b y a reset and in hardware standby mode. They are not
initialized in software standby mode.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 449 of 1042
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Bit 7—Module Stop (MSTPB7): Specifies the SCI0 module stop mode.
Bit 7
MSTPB7 Description
0 SCI0 module stop mode is cleared
1 SCI0 module stop mode is set (Initial value)
Bit 6—Module Stop (MSTPB6): Specifies the SCI1 module stop mode.
Bit 6
MSTPB6 Description
0 SCI1 module stop mode is cleared
1 SCI1 module stop mode is set (Initial value)
Bit 5—Module Stop (MSTPB5): Specifies the SCI2 module stop mode.
Bit 5
MSTPB5 Description
0 SCI2 module stop mode is cleared
1 SCI2 module stop mode is set (Initial value)
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 450 of 1042
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13.3 Operation
13.3.1 Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and clocked synchr onous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or clocked synchronous mode and the transmission format is made
using SMR as shown in table 13.8. The SCI clock is determined by a combination of the C/A bit
in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9.
Asynchronous Mo de
• Data length: Choice of 7 or 8 bits
• Choice of p a r ity addition, multiprocesso r bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
• Detection of framing, parity, and overrun errors, and breaks, during reception
• Choice of internal or external clock as SCI clock source
When internal clock is selected:
The SCI operates on the baud rate generator clock and a clock with the same frequency as
the bit rate can be output
When external clock is selected:
A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate
generator is not used)
Clocked Synchro nous Mode
• Transfer format: Fixed 8-bit data
• Detection of overrun errors during reception
• Choice of internal or external clock as SCI clock source
When internal clock is selected:
The SCI operates on the baud rate generator clock and a serial clock is output off-chip
When external clock is selected:
The on-chip baud rate generator is not used, and the SCI operates on the input serial clock
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 451 of 1042
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Table 13.8 SMR Settings and Serial Transfer Format Selection
SMR Settings SCI Transfer Format
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3
C/A
AA
ACHR MP PE STOP Mode Data
Length
Multi
Processor
Bit Parity
Bit Stop Bit
Length
00000 8-bit dataNo No1 bit
1
Asynchronous
mode 2 bits
10 Yes1 bit
12 bits
1 0 0 7-bit data No 1 bit
12 bits
10 Yes1 bit
12 bits
01—0 8-bit data Yes No 1 bit
—12 bits
1 — 0
Asynchronous
mode (multi-
processor f ormat) 7-bit data 1 bi t
—12 bits
1————Clocked
synchronous mode 8-bit data No None
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Setting SCI Transmit/Receive Clock
Bit 7 Bit 1 Bit 0
C/A
AA
ACKE1 CKE0 Mode Clock
Source SCK Pin Function
0 0 0 Internal SCI does not use SCK pin
1 Outputs clock with same frequency as bit
rate
10 External
1
Asynchronous
mode
Inputs clock with frequency of 16 times
the bit rate
1 0 0 Internal Outputs serial clock
1
1 0 External Inputs serial clock
1
Clocked
synchronous
mode
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 452 of 1042
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13.3.2 Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and stop bits indicating the end of communication. Serial communication
is thus carried out with synchronization established on a character-by-character basis.
Inside the SCI, the tran smitter and receive r are independ ent un its, en abling full-d uplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written du ring transmission or reception, en abling continuous data
transfer.
Figure 13.2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order ) , a par ity bit (high or low level), and finally stop bits (high level).
In asynchro nous mode, the SCI perfor m s sy nchronization at the fallin g edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
LSB
Start
bit
MSB
Idle state
(mark state)
Stop bit
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 1
Serial
data Parity
bit
1 bit 1 or
2 bits
7 or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 453 of 1042
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Data Transfer Format
Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected accordin g to the SMR settin g .
Table 13.10 Serial Transfer Formats (Asynchronous Mode)
PE
0
0
1
1
0
0
1
1
—
—
—
—
S8-bit data
STOP
S7-bit data
STOP
S8-bit data
STOP STOP
S8-bit data P
STOP
S7-bit data
STOP
P
S8-bit data
MPB STOP
S8-bit data
MPB STOP STOP
S7-bit data
STOPMPB
S7-bit data
STOPMPB STOP
S7-bit data
STOPSTOP
CHR
0
0
0
0
1
1
1
1
0
0
1
1
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Settings
123456789101112
Serial Transfer Format and Frame Length
STOP
S8-bit data P
STOP
S7-bit data
STOP
P
STOP
Legend:
S : Start bit
STOP : Stop bit
P: Parity bit
MPB : Multiproc essor bit
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 454 of 1042
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Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting o f the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table
13.9.
When an external clock is input at the SCK pin, the clock frequ ency should be 16 times the bit rate
used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequen cy of the clock output in this case is equ al to the bit rate, and the phase is such th at the
rising edge of th e clo ck is in th e middle of the transmit data, as sh o w n in f igure 13.3.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
Figure 13.3 Relation between Output Clock and Transfer Data Phase
(Asynchrono us Mo de)
Data Transfer Operations
SCI initializat ion (asynchronous mode): Before transmitting and receiving data, you should first
clear the TE and RE bits in SCR to 0, then initialize th e SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clear ing the RE bit to 0 does no t ch ange the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When an external clock is used the clock should not be stopped during operation, including
initialization, sin ce operation is uncer tain.
Figure 13.4 shows a sample SCI initialization flowchart.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 455 of 1042
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Wait
<Transfer completion>
Start initialization
Set data transfer format in
SMR and SCMR
[1]
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits [4]
1-bit interval elapsed?
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Figure 13.4 Sample SCI Initialization Flowchart
Serial data transmission (asy nchronous mode): Figure 13.5 shows a sample flowchart for serial
transmission.
The following procedure should be used for serial data transmission.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 456 of 1042
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No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request, and date is
written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Figure 13.5 Sample Serial Transmission Flowchart
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 457 of 1042
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In serial transmission, the SCI operates as described below.
[1] T he SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transf ers the data from TDR to TSR.
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit da ta empty interrupt (TXI) is generated.
The serial transmit d a ta is sent from the TxD pin in th e follo wing order.
[a] Start bit:
One 0-bit is output.
[b] Transmit d a ta:
8-bit or 7-bit data is output in LSB-first order.
[c] Parity bit or mu ltiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is o utput can also be
selected.
[d] Stop bit(s):
One or two 1-bits (stop bits) are output.
[e] Mark state:
1 is output continuously u ntil the start bit that starts the next transmission is sent.
[3] T he SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is clear ed to 0, the data is transferred from TDR to TSR, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
“mark state” is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at
this time, a TEI interr upt r e quest is generated.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 458 of 1042
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Figure 13.6 shows an ex ample of the operation for transmission in asynchronous mode.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
DataStart
bit Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
TXI interrupt
request generated Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Serial data reception (asynchronous mode): Figure 13.7 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 459 of 1042
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Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Read ORER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
PER ∨ FER ∨ ORER = 1
RDRF = 1
All data received?
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
Receive error processing and
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
processing, ensure that the
ORER, PER, and FER flags are
all cleared to 0. Reception cannot
be resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
the input port corresponding to
the RxD pin.
SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when DTC is activated by an RXI
interrupt and the RDR value is
read.
[1]
[2] [3]
[4]
[5]
Figure 13.7 Sample Serial Reception Data Flowchart
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 460 of 1042
REJ09B0275-0500
<End>
[3]
Error processing
Parity error processing
Yes
No
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
No
Yes
Overrun error processing
ORER = 1
FER = 1
Break?
PER = 1
Clear RE bit in SCR to 0
Figure 13.7 Sample Serial Reception Data Flowchart (cont)
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 461 of 1042
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In serial reception, the SCI operates as described below.
[1] The SCI mo nitors the transmissio n line, and if a 0 stop bit is detected, perform s in ternal
synchronization and starts reception.
[2] The received data is stored in RSR in LSB-to-MSB order.
[3] The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
[a] Parity check:
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
[b] Stop bit check:
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
[c] Status check:
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred fro m RSR to RDR.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error* is detected in the error check, the operation is as shown in table 13.11.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
[4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt
(RXI) request is generated.
Also, if the RIE b it in SCR is set to 1 when the ORER, PER, or FER flag ch anges to 1, a
receive error interrupt (ERI) request is generated.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 462 of 1042
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Table 13.11 Receive Errors and Conditions for Occurrence
Receive Error Abbreviation Occurrence Condition Data Transfer
Overrun error ORER When the next data reception
is completed while the RDRF
flag in SSR is set to 1
Receive data is not
transferred from RSR to
RDR.
Framing error FER When the stop bit is 0 Receive data is transferre d
from RSR to RDR.
Parity error PER When the received data di ffers
from the parity (even or odd)
set in SMR
Receive data is transferre d
from RSR to RDR.
Figure 13.8 shows an example of the operation for reception in asynchronous mode.
RDRF
FER
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0
1 1
DataStart
bit Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
RXI interrupt
request
generated ERI interrupt request
generated by framing
error
Idle state
(mark state)
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 463 of 1042
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13.3.3 Multiprocessor Communication Function
The multipr ocessor communication fun ction performs serial communication using the
multipro cessor format, in wh ich a multiprocessor bit is ad ded to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharin g transm ission lines.
When multipro cessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiv in g station , and a data transmission cy cle. The multip rocesso r bit is used
to differentiate b e tween the ID transmission cycle and the data tran sm ission cycle.
The transmitting statio n first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multipr ocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station sk ips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multip rocessor bit is received, the receiving statio n compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multip rocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 13.9 shows an example of inter-processor communication using the multiprocesso r for mat.
Data Transfer Format
There are four data transfer formats.
When the multiprocessor format is specified , the parity bit specification is invalid.
For details, see table 1 3.10.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 464 of 1042
REJ09B0275-0500
Clock
See the section on asynchronous mode.
Transmitting
station
Receiving
station A
(ID= 01)
Receiving
station B
(ID= 02)
Receiving
station C
(ID= 03)
Receiving
station D
(ID= 04)
Serial transmission line
Serial
data
ID transmission cycle =
receiving station
specification
Data transmission cycle =
Data transmission to
receiving station specified by ID
(MPB= 1) (MPB= 0)
H'01 H'AA
Legend:
MPB: Multiprocessor bit
Figure 13.9 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Statio n A)
Data Transfer Operations
Multiprocessor serial data transmission: Figure 13.10 shows a sample flowchart for
multiprocessor serial da ta transmission .
The following procedure should be used for multiprocessor serial data transmission.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 465 of 1042
REJ09B0275-0500
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
set MPBT bit in SSR
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
Clear TDRE flag to 0
SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmit
data empty interrupt (TXI)
request, and data is written to
TDR.
Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
[1]
[2]
[3]
[4]
Figure 13.10 Sample Multiprocessor Serial Transmission Flowchart
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 466 of 1042
REJ09B0275-0500
In serial transmission, the SCI operates as described below.
[1] T he SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transf ers the data from TDR to TSR.
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit in SCR is set to 1 at this time, a transm it data empty interrupt (TXI) is generated.
The serial transmit d a ta is sent from the TxD pin in th e follo wing order.
[a] Start bit:
One 0-bit is output.
[b] Transmit d a ta:
8-bit or 7-bit data is output in LSB-first order.
[c] Multiprocessor bit
One multipr ocessor bit (MPBT valu e) is output.
[d] Stop bit(s):
One or two 1-bits (stop bits) are output.
[e] Mark state:
1 is output continuously u ntil the start bit that starts the next transmission is sent.
[3] T he SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is clear ed to 0, data is transferred from TDR to TSR, the stop bit is sent, and
then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a transmissio n end interr upt (TEI) request is gener a ted.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 467 of 1042
REJ09B0275-0500
Figure 13.11 shows an exam ple of SCI operation for transmission using the multiprocessor
format.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
DataStart
bit
Multi-
proce-
ssor
bit Stop
bit Start
bit Data Multi-
proces-
sor bit Stop
bit
TXI interrupt
request generated Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt service
routine
TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 13.11 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Multiprocessor serial data reception: Figure 13.12 shows a sample flowchart for
multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 468 of 1042
REJ09B0275-0500
Yes
<End>
[1]
No
Initialization
Start reception
No
Yes
[4]
Clear RE bit in SCR to 0
Error processing
(Continued on
next page)
[5]
No
Yes
FER ∨ ORER = 1
RDRF = 1
All data received?
Read MPIE bit in SCR [2]
Read ORER and FER flags in SSR
Read RDRF flag in SSR [3]
Read receive data in RDR
No
Yes
This station’s ID?
Read ORER and FER flags in SSR
Yes
No
Read RDRF flag in SSR
No
Yes
FER ∨ ORER = 1
Read receive data in RDR
RDRF = 1
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
ID reception cycle:
Set the MPIE bit in SCR to 1.
SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Receive error processing and
break detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
processing, ensure that the
ORER and FER flags are all
cleared to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
[1]
[2]
[3]
[4]
[5]
Figure 13.12 Sample Multiprocessor Serial Reception Flowchart
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 469 of 1042
REJ09B0275-0500
<End>
Error processing
Yes
No
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
Overrun error processing
ORER = 1
FER = 1
Break?
Clear RE bit in SCR to 0
[5]
Figure 13.12 Sample Multiprocessor Serial Reception Flowchart (cont)
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 470 of 1042
REJ09B0275-0500
Figure 13.13 sh o ws an examp le of SCI op eration for multiprocessor format reception.
MPIE
RDR
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
1 1
Data (ID1)Start
bit MPB Stop
bit Start
bit Data (Data1) MPB Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
Idle state
(mark state)
RDRF
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
If not this station’s ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
ID1
(a) Data does not match station’s ID
MPIE
RDR
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
1 1
Data (ID2)Start
bit
MPB Stop
bit Start
bit Data (Data2) MPB Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
Idle state
(mark state)
RDRF
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
MPIE bit set to 1
again
ID2
(b) Data matches station’s ID
Data2ID1
Figure 13.13 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 471 of 1042
REJ09B0275-0500
13.3.4 Operation in Clocked Synchronous Mode
In clocked synchronous mode, data is transmitted or received in synchronization with clo ck
pulses, making it suitable for high-speed serial communication.
Inside the SCI, the tran smitter and receive r are independ ent un its, en abling full-d uplex
communication by use of a common clock. Both the transmitter and th e receiver also h ave a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 13.14 shows the general format for clocked synchronous serial communication.
Don’t
care
Don’t
care
One unit of transfer data (character or frame)
Bit 0
Serial
data
Serial
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
*
Note: * High except in continuous transfer
*
Figure 13.14 Data Format in Synchronous Communication
In clocked synchronous serial communication, data on the transmission line is output from one
falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of
the serial clock.
In clocked serial communication, one character consists of data output starting with the LSB and
ending with the MSB. After the MSB is ou tput, the transm ission line holds th e MSB state.
In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the
serial clock.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 472 of 1042
REJ09B0275-0500
Data Transfer Format
A fixed 8-bit data format is used.
No parity or m ultiprocessor bits are added.
Clock
Either an internal clock generated by the on-chip baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1
and CKE0 bits in SCR. For details of SCI clock source selection, see table 13.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is outp ut until an overrun error occurs or the RE bit is cleared to 0. If you want to
perform receive operations in units of one character, you should select an external clock as the
clock source.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 473 of 1042
REJ09B0275-0500
Data Transfer Operations
SCI initialization (clocked sy nchronous mo de): Before transmittin g and receiving data, you
should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clear ing the RE bit to 0 does no t ch ange the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 13.15 shows a sample SCI initialization f lowchart.
Wait
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Start initialization
Set data transfer format in
SMR and SCMR
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits [4]
1-bit interval elapsed?
[1]
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
Figure 13.15 Sa mple SCI Initialization Flowchart
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 474 of 1042
REJ09B0275-0500
Serial data transmission (clocked synchronous mode): Figure 13.16 shows a sample flowchart
for se rial transmission.
The following procedure should be used for serial data transmission.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR.
Figure 13.16 Sample Serial Transmission Flowchart
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 475 of 1042
REJ09B0275-0500
In serial transmission, the SCI operates as described below.
[1] T he SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transf ers the data from TDR to TSR.
[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt
(TXI) is generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7 ) .
[3] T he SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sen t, an d the
TxD pin maintains its state.
If the TEIE bit in SCR is set to 1 at this time, a TEI inter r upt r e quest is generated.
[4] After completion of serial transmission, the SCK pin is fixed high.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 476 of 1042
REJ09B0275-0500
Figure 13.17 shows an example of SCI operation in transmission.
Transfer direction
Bit 0
Serial data
Serial clock
1 frame
TDRE
TEND
Bit 1 Bit 7 Bit 0 Bit 1 Bit 7Bit 6
Data written to TDR
and TDRE flag
cleared to 0 in TXI
interrupt service routine
TEI interrupt
request generated
TXI interrupt
request generated
TXI interrupt
request generated
Figure 13.17 Example of SCI Operation in Transmission
Serial data reception (clocked synchronous mode): Figure 13.18 shows a sample flowchart for
serial reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to clocked synchronous, be sure to check
that the ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not b e set if the FER or PER flag is set to 1 , and neither transmit nor receive
operatio ns will be possible.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 477 of 1042
REJ09B0275-0500
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Error processing
(Continued below)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
RDRF = 1
All data received?
Read ORER flag in SSR
[1]
[2] [3]
[4]
[5]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
Receive error processing:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag
to 0. Transfer cannot be resumed
if the ORER flag is set to 1.
SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DTC is
activated by a receive data full
interrupt (RXI) request and the
RDR value is read.
<End>
Error processing
Overrun error processing
[3]
Clear ORER flag in SSR to 0
Figure 13.18 Sample Serial Reception Flowchart
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 478 of 1042
REJ09B0275-0500
In serial reception, the SCI operates as described below.
[1] The SCI per f orms internal initialization in synchronization with serial clock input or output.
[2] The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred fro m RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a
receive error is detected in the error check, the operation is as shown in table 13.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
[3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error
interrupt (ERI) request is generated.
Figure 13.19 shows an example of SCI operation in reception.
Bit 7
Serial
data
Serial
clock
1 frame
RDRF
ORER
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RXI interrupt request
generated RDR data read and
RDRF flag cleared to 0
in RXI interrupt service
routine
RXI interrupt request
generated ERI interrupt request
generated by overrun
error
Figure 13.19 Example of SCI Operation in Reception
Simultaneous serial data transmission and reception (clocked synchronous mode): Figure
13.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 479 of 1042
REJ09B0275-0500
Yes
<End>
[1]
No
Initialization
Start transmission/reception
[5]
Error processing
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
All data received?
[2]
Read TDRE flag in SSR
No
Yes
TDRE = 1
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
RDRF = 1
Read ORER flag in SSR
[4]
Read RDRF flag in SSR
Clear TE and RE bits in SCR to 0
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to
0, then set both these bits to 1 simultaneously.
[1]
[2]
[3]
[4]
[5]
SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
Receive error processing:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag to
0. Transmission/reception cannot be
resumed if the ORER flag is set to
1.
SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit data empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC is activated by a receive data
full interrupt (RXI) request and the
RDR value is read.
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 480 of 1042
REJ09B0275-0500
13.4 SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 13.12 shows the interrup t so urces and their relative pr iorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of
interrup t r eque st is sen t to the interrupt contro ller independently.
When the TDRE flag in SSR is set to 1, a TXI interr upt request is generated . Wh en the TEND flag
in SSR is set to 1, a TEI interrupt reque st is g e nerated. A TXI interrupt can activate th e DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC. The DTC cannot be activated by a TEI interrupt request.
When the RDRF flag in SSR is set to 1, an RXI interru pt request is gener a ted. Wh en the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is ge nerated. An RXI interrupt can
activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data
transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 481 of 1042
REJ09B0275-0500
Table 13.12 SCI Interrupt Sources
Channel Interrupt
Source Description DTC
Activation Priority*
0 ERI Interrupt due to receive error (ORER, FER,
or PER) Not possible High
RXI Interrupt due to receive data full state (RDRF) Possible
TXI Interrupt due to transmit data empty state
(TDRE) Possible
TEI Interrupt due to transmission end (TEND) Not possible
1 ERI Interrupt due to receive error (ORER, FER,
or PER) Not possible
RXI Interrupt due to receive data full state (RDRF) Possible
TXI Interrupt due to transmit data empty state
(TDRE) Possible
TEI Interrupt due to transmission end (TEND) Not possible
2 ERI Interrupt due to receive error (ORER, FER,
or PER) Not possible
RXI Interrupt due to receive data full state (RDRF) Possible
TXI Interrupt due to transmit data empty state
(TDRE) Possible
TEI Interrupt due to transmission end (TEND) Not possible Low
Note: *This table shows the initia l state im m ediate ly after a reset. R elat iv e priorit ies am ong
channels can be changed by means of the interrupt controller.
A TEI interrupt is requ e sted when the TEND flag is set to 1 while the TEIE bit is set to 1 . The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance,
with the result th at the TDRE and TEND flags are cleared. Note that the TEI inter rupt will not be
accepted in this case.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 482 of 1042
REJ09B0275-0500
13.5 Usage Notes
The following points should be noted when using the SCI.
Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data f r om TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR r e g ardless of the state of the TDRE flag. Ho wev e r, if n ew data is
written to TDR when the TDRE flag is cleared to 0, the data sto r ed in TDR will be lost since it has
not yet been tran sf erred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before wr iting transmit data to TDR.
Operation when Multiple Receive Errors Occur Simultaneously
If a number of receive errors occur at the same time, the state of the status flags in SSR is as
shown in table 13.13. If there is an overrun error, data is not transferred from RSR to RDR, and
the receive data is lost.
Table 13.13 State of SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF ORER FER PER Receive Data Transfer
RSR to RDR Receive Error Status
1 1 0 0 X Overrun error
0010 Framing error
0001 Parity error
1 1 1 0 X Overrun error + framing error
1 1 0 1 X Overrun error + parity error
0011 Framing error + parity error
1 1 1 1 X Overrun error + framing error +
parity error
Notes: : Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 483 of 1042
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Break Detection and Processing ( A synchronous Mode Only): When framing error (FER)
detection is performed, a break can be detected by reading the RxD pin value directly. In a break,
the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag
(PER) may also be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the FER
flag is cleared to 0, it will be set to 1 again.
Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port
whose direction (input or output) is determined by DR and DDR. This can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced
by the value of DR (the pin does not functio n as the TxD pin until the TE bit is set to 1).
Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1.
To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.
When the TE bit is clear ed to 0, the transmitter is initialized regardless of the current transmission
state, the TxD pin becomes an I/O port, and 0 is output from th e TxD pin.
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only):
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode:
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate.
In reception, the SCI samples the falling edge of the start bit using the basic clo ck, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
basic clock. This is illustrated in figure 13.21.
Section 13 Serial Communication Interface (SCI)
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Internal basic
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
Thus the reception margin in asynchronous mode is given by formula (1) below.
M = | (0.5 –1
2N ) – (L – 0.5) F –| D – 0.5 |
N (1 + F) | × 100% ... Formula (1)
Where M: Reception margin (%)
N: Ratio of b it r ate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by
formula (2) below.
When D = 0.5 and F = 0,
M = (0.5 –1
2 × 16 ) × 100%
= 46.875% ... Formula (2)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
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Restrictions on Use of DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transm it clock is input within 4 φ clocks after TDR is updated. (Figure 13.22)
• When RDR is read by the DTC, be sure to set the activation source to the r elevant SCI
reception end interrupt (RXI).
t
D0
LSB
Serial data
SCK
D1 D3 D4 D5D2 D6 D7
Note: When operating on an external clock, set t >4 clocks.
TDRE
Figure 13.22 Example of Clocked Synchronous Transmission by DTC
Operation in Case of Mode Transition
• Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition.
TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby
mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and
becomes high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined. When transmitting without
changing the transmit mode after the relevant mode is cleared, transmission can be started by
setting TE to 1 again, and performing the following sequence: SSR read -> TDR write ->
TDRE clearance. To transmit with a different tran smit mode after clearing the relevant mode,
the procedur e must be started again from initialization. Figure 13.23 shows a sample flo wchart
for mode transition during transmission. Port pin states are shown in figu res 13.24 and 13.25.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC transfer to module stop mode, software standby mode,
watch mode, subactive mode, or subsleep mode transition. To perform transmission with the
DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI f lag and star t
DTC transmission.
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• Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode,
software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR,
RDR, and SSR are reset. If a transition is made without stopping operation, the data being
received will be in v a lid.
To continue receiving without changing the reception mode after the relevant mode is cleared,
set RE to 1 before starting reception. To receive with a different receive mode, the procedure
must be started again from initialization.
Figure 13.26 shows a sample flowchart for mode transition during reception.
Read TEND flag in SSR
TE = 0
Transition to software
standby mode, etc.
Exit from software
standby mode, etc.
Change
operating mode? No
All data
transmitted?
TEND = 1
Yes
Yes
Yes
<Transmission>
No
No
[1]
[3]
[2]
TE = 1Initialization
<Start of transmission>
[1] Data being transmitted is interrupted.
After exiting software standby mode,
etc., normal CPU transmission is
possible by setting TE to 1, reading
SSR, writing TDR, and clearing
TDRE to 0, but note that if the DTC
has been activated, the remaining
data in DTCRAM will be transmitted
when TE and TIE are set to 1.
[2] If TIE and TEIE are set to 1, clear
them to 0 in the same way.
[3] Includes module stop mode, watch
mode, subactive mode, and subsleep
mode.
Figure 13.23 Sample Flowchart for Mode Transition during Transmission
Section 13 Serial Communication Interface (SCI)
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SCK output pin
TE bit
TxD output pin Port input/output High outputPort input/output High output Start Stop
Start of transmission End of
transmission
Port input/output
SCI TxD output Port SCI TxD
output
Port
Transition
to software
standby
Exit from
software
standby
Figure 13.24 Asynchronous Transmission Using Internal Clock
Port input/output
Last TxD bit held
High output*
Port input/output Marking output
Port input/output
SCI TxD output PortPort
Note: * Initialized by software standby.
SCK output pin
TE bit
TxD output pin
SCI TxD
output
Start of transmission End of
transmission
Transition
to software
standby
Exit from
software
standby
Figure 13.25 Synchronous Transmission Using Internal Clock
Section 13 Serial Communication Interface (SCI)
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RE = 0
Transition to software
standby mode, etc.
Read receive data in RDR
Read RDRF flag in SSR
Exit from software
standby mode, etc.
Change
operating mode? No
RDRF = 1
Yes
Yes
<Reception>
No [1]
[2]
RE = 1Initialization
<Start of reception>
[1] Receive data being received
becomes invalid.
[2] Includes module stop mode,
watch mode, subactive mode,
and subsleep mode.
Figure 13.26 Sample Flowchart for Mode Transition during Reception
Section 13 Serial Communication Interface (SCI)
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Switching from SCK P in F unction to Port Pin Function:
• Problem in Operation: When switching the SCK pin function to the output port function (high-
level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0,
CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
1. End of serial data transmission
2. TE bit = 0
3. C/A bit = 0 ... switchover to port output
4. Occurrence of low-level output (see figure 13.27)
SCK/port
Data
TE
C/A
CKE1
CKE0
Bit 7Bit 6
1. End of transmission 4. Low-level output
3. C/A = 0
2. TE = 0
Half-cycle low-level output
Figure 13.27 Operation when Switching from SCK Pin Function to Port Pin Function
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• Sample Procedu r e for Avoid ing Low-Level Output: As this samp le procedure temporarily
places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an
external circuit.
With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following
settings in the order shown.
1. End of serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 ... switchover to port output
5. CKE1 bit = 0
SCK/port
Data
TE
C/A
CKE1
CKE0
Bit 7Bit 6
1. End of transmission
3. CKE1 = 1 5. CKE1 = 0
4. C/A = 0
2. TE = 0
High-level output
Figure 13.28 Operation when Switching from SCK Pin Function to Port Pin Function
(Example of Preventing Low-Level Output)
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Section 14 Smart Card Interface
14.1 Overview
The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification
Card) as a serial communication interface extension function.
Switching between the normal serial communication interface and the Smart Card interface is
carried out by means of a register setting.
14.1.1 Features
Features of the Smart Card interface supported by the H8S/2626 Group and H8S/2623 Group are
as follows.
• Asynchronous mode
Data length: 8 bits
Parity bit generation and checking
Transmission of erro r signal (parity error) in receive mode
Error sig nal detection and automatic da ta retransmission in transmit mode
Direct convention and inverse convention both supported
• On-chip baud rate generator allows any bit rate to be selected
• Three interrupt sources
Three interrupt sources (transmit data empty, receive data full, and transmit/receive error)
that can issue requests independ ently
The transmit data empty interrupt and receive data full interrupt can activate the data
transfer controller (DTC) to execute data transfer
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14.1.2 Block Diagram
Figure 14.1 shows a block diagram of the Smart Card interface.
Bus interface
TDR
RSR
RDR
Module data bus
TSR
SCMR
SSR
SCR
Transmission/
reception control
BRR
Baud rate
generator
Internal
data bus
RxD
TxD
SCK
Parity generation
Parity check
Clock
φ
φ/4
φ/16
φ/64
TXI
RXI
ERI
SMR
Legend:
SCMR
RSR
RDR
TSR
TDR
SMR
SCR
SSR
BRR
: Smart Card mode register
: Receive shift register
: Receive data register
: Transmit shift register
: Transmit data register
: Serial mode register
: Serial control register
: Serial status register
: Bit rate register
Figure 14.1 Block Diagram of Smart Card Interface
Section 14 Smart Card Interface
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14.1.3 Pin Configuration
Table 14.1 shows the Smart Card interface pin configuration.
Table 14.1 Smart Card Interface Pins
Channel Pin Name Symbol I/O Function
0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output
Receive data pin 0 RxD0 Input SCI0 receive data input
Transmit data pin 0 TxD0 Output SCI0 transmit data output
1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output
Receive data pin 1 RxD1 Input SCI1 receive data input
Transmit data pin 1 TxD1 Output SCI1 transmit data output
2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output
Receive data pin 2 RxD2 Input SCI2 receive data input
Transmit data pin 2 TxD2 Output SCI2 transmit data output
Section 14 Smart Card Interface
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14.1.4 Register Configuration
Table 14.2 sho ws the registers used by the Smart Card interf ace. Details of SMR, BRR, SCR,
TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register
descriptions in section 13, Serial Co mmunication Interface (SCI).
Table 14.2 Smart Card Interface Registers
Channel Name Abbreviation R/W Initial Value Address*1
0 Serial mode register 0 SMR0 R/W H'00 H'FF78
Bit rate register 0 BRR0 R/W H'FF H'FF79
Serial control register 0 SCR0 R/W H'00 H'FF7A
Transmit data register 0 TDR0 R/W H'FF H'FF7B
Serial status register 0 SSR0 R/(W)*2H'84 H'FF7C
Receive data regist er 0 RDR0 R H'0 0 H'FF7D
Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E
1 Serial mode register 1 SMR1 R/W H'00 H'FF80
Bit rate register 1 BRR1 R/W H'FF H'FF81
Serial control register 1 SCR1 R/W H'00 H'FF82
Transmit data register 1 TDR1 R/W H'FF H'FF83
Serial status register 1 SSR1 R/(W)*2H'84 H'FF84
Receive data regist er 1 RDR1 R H'0 0 H'FF85
Smart card mode register 1 SCMR1 R/W H'F2 H'FF86
2 Serial mode register 2 SMR2 R/W H'00 H'FF88
Bit rate register 2 BRR2 R/W H'FF H'FF89
Serial control register 2 SCR2 R/W H'00 H'FF8A
Transmit data register 2 TDR2 R/W H'FF H'FF8B
Serial status register 2 SSR2 R/(W)*2H'84 H'FF8C
Receive data regist er 2 RDR2 R H'0 0 H'FF8D
Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E
All Module stop contro l
register B MSTPCRB R/W H'FF H'FDE9
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
Section 14 Smart Card Interface
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14.2 Register Descriptions
Registers added with the Smart Card interface and bits for which the function changes are
described here.
14.2.1 Smart Card Mode Register (SCMR)
Bit:76543210
————SDIRSINV—SMIF
Initial value:11110010
R/W:————R/WR/W—R/W
SCMR is an 8-bit readable/writable register that selects the Smart Card interface function.
SCMR is initial ized to H'F2 by a reset and in standby mode.
Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3
SDIR Description
0 TDR contents are transmitted LSB-first (Initial value)
Receive data is stored in RDR LSB-first
1 TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used together with the SDIR bit for communication with an inverse convention card.
The SINV bit do e s not af f ect the logic level of the parity bit. For par ity-related setting procedures,
see section 14.3.4, Register Settings.
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Bit 2
SINV Description
0 TDR contents are transmitted as they are (Initial value)
Receive data is stored as it is in RDR
1 TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
Bit 1—Reserved: This bit is always read as 1 and cannot be modified.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface
function.
Bit 0
SMIF Description
0 Smart Card interface function is disabled (Initial value)
1 Smart Card interface function is enabled
14.2.2 Serial Status Register (SSR)
Bit:76543210
TDRE RDRF ORER ERS PER TEND MPB MPBT
Initial value:10000100
R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*RRR/W
Note: *Only 0 can be written, for flag clearing.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial
Status Register ( SSR) .
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
Smart Card interface mode.
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Bit 4
ERS Description
0 Normal reception, with no error signal
[Clearing cond iti ons ] (Initial value)
• Upon reset, and in standb y mode or modu le stop mo de
• When 0 is written to ERS after reading ERS = 1
1 Error signal sent from receiver indicating detection of parity error
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
state.
Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial
Status Register ( SSR) .
However, the setting conditions for the TEND bit, are as shown below.
Bit 2
TEND Description
0 Transmi ss ion is in progre ss
[Clearing cond iti ons ]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and write data to TDR
1Transmiss ion has end ed (Initial value)
[Setting conditions]
• Upon reset, and in standb y mode or modu le stop mo de
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a
1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a
1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a
1-byte serial character when GM = 1 and BLK = 1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Section 14 Smart Card Interface
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14.2.3 Serial Mode Register (SMR)
Bit:76543210
GM BLK PE O/EBCP1 BCP0 CKS1 CKS0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5.
The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode.
Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.
This bit is cleared to 0 when the normal smart card interf ace is used. In GSM mo de, this bit is set
to 1, the timing of setting of the TEND flag that indicates tr ansmission completion is adv anced
and clock output con trol mode ad dition is performed. The contents of the clock outp ut control
mode addition are sp ecified by bits 1 and 0 of the serial control register (SCR).
Bit 7
GM Description
0 Normal smart card inte rfac e mode oper atio n (Initial value)
• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of
start bit
• Clock output ON/OFF control only
1 GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output ON/OFF control (set by
SCR)
Note: etu: Elementary time unit (time for transfer of 1 bit)
Section 14 Smart Card Interface
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Bit 6—Block Transfer Mo de (BLK): Selects block transfer mode.
Bit 6
BLK Description
0 Normal Smart Card interface mode operation
• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
1 Block transfer mode operation
• Error signal transmission/detection and automatic data retransmission not
performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Bits 3 and 2—Basic Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of basic
clock periods in a 1-bit transfer interval on the Smart Card interface.
Bit 3 Bit 2
BCP1 BCP0 Description
0 1 32 clock periods (Initial value)
0 64 clock periods
1 1 372 clock periods
0 256 clo ck peri ods
Bits 5, 4, 1, and 0: Operate in the same way as for the normal SCI. For details, see section 13.2.5,
Serial Mode Register (SMR).
Section 14 Smart Card Interface
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14.2.4 Serial Control Register (SCR)
Bit:76543210
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial
mode register (SMR) is set to 1.
Bits 7 to 2—Operate in the same way as for the normal SCI.
For details, see section 13.2.6, Serial Control Register (SCR).
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin.
In smart card interface mode, in addition to the normal switching between clock output enabling
and disabling, the clock output can be specified as to be fixed high or low.
SCMR SMR SCR Setting
SMIF C/A
AA
A, GM CKE1 CKE0 SCK Pin Function
0 See the SCI
1 0 0 0 Operates as port I/O pin
1 0 0 1 Outputs clock as SCK output pin
1 1 0 0 Operates as SCK output pin, with output fixed
low
1 1 0 1 Outputs clock as SCK output pin
1 1 1 0 Operates as SCK output pin, with output fixed
high
1 1 1 1 Outputs clock as SCK output pin
Section 14 Smart Card Interface
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14.3 Operation
14.3.1 Overview
The main functions of the Smart Card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmissio n, a guard time of at least 2 etu (Eleme ntary Time Unit: the time for transfer of 1
bit) is left between th e end of the parity bit and the start of th e next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If the error sig nal is sampled dur ing tr ansmission, the same data is tran smitted automatically
after the elapse of 2 etu or longer. (except in block transfer mode)
• Only asynchronous communication is supported; there is no clocked synchronous
communication function.
14.3.2 Pin Connections
Figure 14.2 shows a schematic diagram of Smart Card interface related pin connections.
In communication with an IC card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The
data transmission line should be pulled up to the VCC power supply with a resistor.
When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is
input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock.
LSI port output is used as the reset signal.
Other pins must normally be connected to the power supply or ground.
Section 14 Smart Card Interface
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TxD
RxD
SCK
Rx (port)
H8S/2626 Group or
H8S/2623 Group
I/O
CLK
RST
V
CC
Connected equipment
IC card
Data line
Clock line
Reset line
Figure 14.2 Schematic Diagram of Smart Card Interface Pin Connections
Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed
transmission/reception is possible, enabling self-diagnosis to be carried out.
Section 14 Smart Card Interface
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14.3.3 Data Format
(1) Normal Transfer Mode
Figure 14.3 shows the no rmal Smart Card interface data format. In reception in this mode, a parity
check is carried out on each frame, and if an error is detected an error signal is sent back to the
transmitting end, and retransmission of the data is requested. If an error signal is sampled during
transmission, the same da ta is r e tr ansmitted.
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When there is no parity error
Transmitting station output
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When a parity error occurs
Transmitting station output
DE
Receiving station
output
: Start bit
: Data bits
: Parity bit
: Error signal
Legend:
Ds
D0 to D7
Dp
DE
Figure 14.3 Normal Smart Card Interface Data Format
Section 14 Smart Card Interface
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The operation sequence is as follows.
[1] When the data line is not in use it is in the high-imp edance state, and is fixed high with a pull-
up resistor.
[2] The transmitting station starts tr ansfer of one frame of data. The d a ta frame star ts with a start
bit (Ds, low-lev el), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data
line is pulled high with a pull-up r e sistor.
[4] The receiving station carries out a parity check.
If there is no parity error and the data is received normally, the receiving station waits for
reception of the next data.
If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)
to reque st r e transmission of the data. After outputting the error signal for the prescribed length
of time, the receiving station places the signal line in the high-impedance state again. The
signal line is pulled high again by a pull-up resistor.
[5] If the transmitting station does not receive an error signal, it proceeds to transmit th e next data
frame.
If it does receive an error signal, however , it returns to step [2] and retransmits the erroneous
data.
(2) Block Transfer Mode
The operation sequence in block transfer mode is as follows.
[1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pull-
up resistor.
[2] The transmitting station starts tr ansfer of one frame of data. The d a ta frame star ts with a start
bit (Ds, low-lev el), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
[3] With the Smart Card interface, the data line then returns to th e high-impedance state. The data
line is pulled high with a pull-up r e sistor.
[4] After reception, a parity error check is carried ou t, but an error signal is not output even if an
error has occurred. When an error occurs reception cannot be continued, so the error flag
should be cleared to 0 before the parity bit of the next frame is received.
[5] The transmitting station proceeds to transmit the next d a ta frame.
Section 14 Smart Card Interface
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14.3.4 Register Settings
Table 14.3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 14.3 Smart Card Interface Register Settings
Bit
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SMR GM BLK 1 O/EBCP1 BCP0 CKS1 CKS0
BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR TIE RIE TE RE 0 0 CKE1*CKE0
TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0
SSR TDRE RDRF ORER ERS PER TEND 0 0
RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
SCMR ————SDIR SINV —SMIF
Notes: — : Unused bit.
*: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in
GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct conv ention type, and set to 1
if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and
BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section
14.3.5, Clock.
The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer
mode.
BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of
calculating the v a lue to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 13, Serial Communication Interface (SCI).
Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these
bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in
SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.
Section 14 Smart Card Interface
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Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the
direct convention type, and set to 1 if of the inverse convention type.
The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the
inverse convention type.
The SMIF bit is set to 1 in the case of the Smart Card interface.
Examples of register settings and the waveform of the start char acter are shown below for the two
types of IC card (direct convention and inverse convention).
• Direct convention (SDIR = SINV = O/E = 0)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
AZZAZZZAAZ(Z) (Z) State
With the direct convention type, the logic 1 level co rresponds to state Z and the logic 0 level to
state A, and transf er is performed in LSB-first order. The start character data above is H'3B.
The parity bit is 1 sin ce even parity is stipulated for the Smart Card.
• Inverse convention (SDIR = SINV = O/E = 1)
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
AZZAAAAAAZ(Z) (Z) State
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F.
The parity bit is 0, corresponding to state Z, since even parity is stipulated for th e Smart Card.
With the H8S/2626 Group and H8S/2623 Group, inversion specified by the SINV bit applies
only to th e data b its, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity
mode (the same applies to both transmission and reception).
Section 14 Smart Card Interface
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14.3.5 Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with BRR an d the CKS1,
CKS0, BCP1 and BCP0 bits in SM R. The formula for calculatin g the bit rate is as shown below.
Table 14.5 shows some sample bit rates.
If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock
frequency is determined by the bit rate and the setting of bits BCP1 and BCP0.
B = φ
S × 22n+1 × (N + 1) × 106
Where: N = Value set in BRR (0 ≤ N ≤ 255)
B = Bit rate (bit/s)
φ = Operating frequency (MHz)
n = See table 14.4
S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0
Table 14.4 Correspondence between n and CKS1, CKS0
n CKS1 CKS0
000
11
210
31
Table 14.5 Examples of Bit Rate B (bit/s) for Various BRR Settings
(When n = 0 and S = 372)
φ
φφ
φ (MHz)
N 10.00 10.714 13.00 14.285 16.00 18.00 20.00
0 13441 14400 17473 19200 21505 24194 26882
1 6720 7200 8737 9600 10753 12097 13441
2 4480 4800 5824 6400 7168 8065 8961
Note: Bit rates are rounded to the nearest whole number.
Section 14 Smart Card Interface
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The method of calculating the value to be set in the b it r a te register (BRR) from th e oper ating
frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the
smaller error is specified.
N = φ
S × 22n+1 × B × 106 – 1
Table 14.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372)
φ
φφ
φ (MHz)
7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00bit/s
N Error N Error N Error N Error N Error N Error N Error N Error
9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60
Table 14.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)
φ
φφ
φ (MHz) Maximum Bit Rate (bit/s) N n
7.1424 9600 0 0
10.00 13441 0 0
10.7136 14400 0 0
13.00 17473 0 0
14.2848 19200 0 0
16.00 21505 0 0
18.00 24194 0 0
20.00 26882 0 0
The bit rate error is given by the following fo rmula:
Error (%) = ( φ
S × 22n+1 × B × (N + 1) × 106 – 1) × 100
Section 14 Smart Card Interface
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14.3.6 Data Transfer Operations
Initialization: Before transmitting and receiving data, initialize the SCI as describ ed below.
Initialization is also necessary when switching from transmit mode to receive mode, or vice versa.
[1] Clear the TE and RE bits in SCR to 0.
[2] Clear the error flags ERS, PER, and ORER in SSR to 0.
[3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 bits in SMR. Set th e PE bit to 1.
[4] Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,
and are placed in the high-impedance state.
[5] Set the value corresponding to the bit rate in BRR.
[6] Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.
If the CKE0 b it is set to 1, the clock is ou tput from the SCK pin.
[7] Wait at least one bit inter val, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
Section 14 Smart Card Interface
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Serial Data Transmission: As data transmission in smart card mode involves error signal
sampling and retransmission processing, the processing procedure is different from that for the
normal SCI. Figure 14.4 shows a flowchart for transmitting, and fig ure 14.5 shows the relation
between a transmit operation and the internal registers.
[1] Perform Smart Card interface mode initialization as described above in Initialization.
[2] Check that the ERS error flag in SSR is cleared to 0.
[3] Repeat steps [2] an d [3] until it can be confirm ed th at th e TEND flag in SSR is set to 1.
[4] Write the transmit da ta to TDR, clear the TDRE flag to 0, and pe r form the transmit oper ation.
The TEND flag is cleared to 0.
[5] When transm itting data con tinuously, go back to step [2] .
[6] To end transmission, clear the TE bit to 0.
With the above processing, interrupt servicing or data transfer by the DTC is possible.
If transmissio n ends and the TEND flag is set to 1 wh ile the TIE bit is set to 1 and interrupt
requests are en abled, a transmit data empty in ter rup t ( T XI) re quest will b e generated. If an error
occurs in transmission and the ERS f lag is set to 1 while the RIE bit is set to 1 and in ter rup t
requests are enabled, a transfer error interrupt (ERI) reque st will be generated.
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND
flag set timing is shown in figure 14.6.
If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transm itted
automatically, including automatic re tr ansmission.
For details, see Interrupt Operation (Except Block Transfer Mode) and Data Transfer Operation by
DTC below.
Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.
Section 14 Smart Card Interface
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Initialization
No
Yes
Clear TE bit to 0
Start transmission
Start
No
No
No
Yes
Yes
Yes
Yes
No
End
Write data to TDR,
and clear TDRE flag
in SSR to 0
Error processing
Error processing
TEND = 1?
All data transmitted?
TEND = 1?
ERS = 0?
ERS = 0?
Figure 14.4 Example of Transmission Processing Flow
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(1) Data write
TDR TSR
(shift register)
Data 1
(2) Transfer from
TDR to TSR Data 1 Data 1 ; Data remains in TDR
(3) Serial data output
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
In case of normal transmission: TEND flag is set
In case of transmit error: ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
I/O signal line output
Data 1 Data 1
Figure 14.5 Relation between Transmit Operation and Internal Registers
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
I/O data
12.5etu
TXI
(TEND interrupt)
11.0etu
DE
Guard
time
When GM = 1
Legend:
Ds : Start bit
D0 to D7 : Data bits
Dp : Parity bit
DE : Error signal
When GM = 0
etu: Elementary Time Unit (time for transfer of 1 bit)
Figure 14.6 TEND Flag Generation Timing in Transmission Operation
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Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses
the same processing procedure as for the normal SCI. Figure 14.7 shows an example of the
transmission processing flow.
[1] Perform Smart Card interface mode initialization as described above in Initialization.
[2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the
appropriate receive error processing, then clear both the ORER and the PER flag to 0.
[3] Repeat steps [2] and [3] until it can be conf ir med that the RDRF flag is set to 1.
[4] Read the receive data from RDR.
[5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2].
[6] To end reception, clear the RE bit to 0.
Initialization
Read RDR and clear
RDRF flag in SSR to 0
Clear RE bit to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0 and
PER = 0
RDRF = 1?
All data received?
Yes
Figure 14.7 Example of Reception Processing Flow
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With the above processing, interrupt servicing or data transfer by the DTC is possible.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in
reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI)
request will b e generated.
If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped,
and only the number of bytes of receive data set in the DTC are transferred.
For details, see Interrupt Operation (Except Block Transfer Mode) and Data Transfer Operation by
DTC below.
If a parity error occurs during reception and the PER is set to 1, th e receiv e d data is still
transferred to RDR, and therefore this data can be read.
Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.
Mode Switching Operation: When switching from receive mode to transmit mode, first confirm
that the receive operation has been completed, then start from initialization, clearing RE bit to 0
and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the
receive operation has been completed.
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, th en start from initialization, clearing TE bit to 0 and setting RE bit to 1. The
TEND flag can be used to check that the transmit operation has been completed.
Fixing Cloc k Output Level: When the GM bit in SMR is set to 1, the clock output level can be
fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be
made the specified width.
Figure 14.8 shows the timing for fixing the clock output level. In this example, GSM is set to 1,
CKE1 is cleared to 0, and th e CKE0 bit is controlled.
SCK
Specified pulse width
SCR write
(CKE0 = 0) SCR write
(CKE0 = 1)
Specified pulse width
Figure 14.8 Timing for Fixing Clock Output Level
Section 14 Smart Card Interface
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Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart
card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI)
requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is
not used in this mode.
When the TEND flag in SSR is set to 1, a TXI interrupt request is gener ated.
When the RDRF flag in SSR is set to 1, an RXI interru pt request is gener a ted.
When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.
The relationship between the operating states and interrupt sources is shown in table 14.8.
Note: For block transfer mode, see section 13.4, SCI Interrupts.
Table 14.8 Smart Ca rd Mode Operating States and Interrupt So urces
Operating State Flag Enable Bit Interrupt Source DTC Activation
Transmit
Mode Normal
operation TEND TIE TXI Possible
Error ERS RIE ERI Not possible
Receive
Mode Normal
operation RDRF RIE RXI Possible
Error PER, ORER RIE ERI Not possible
Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be
carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time
as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is de signated
beforeh and as a DTC activation source, the DTC will b e activated by the TXI request, and tr ansfer
of the transm it data will be carried out. The TDRE and TEND flags are automatically cleared to 0
when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same
data automatically. During this period, TEND r emains cleared to 0 and the DTC is not activated.
Therefore, the SCI and DTC will automatically transmit the sp ecif ied number of bytes, including
retransmission in the event of an error. However, the ERS flag is not cleared automatically when
an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be
generated in the ev ent of an error, and the ERS flag will be cleared.
When perf orm ing transfer using the DTC, it is essential to set and enable the DTC before carrying
out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller
(DTC).
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI re quest is designated beforehand as a DTC activation source, the DTC will be
Section 14 Smart Card Interface
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activated by the RXI request, an d transfer of the receive data will b e carried out. The RDRF flag is
cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error
flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but in stead, an ERI
interrupt request is sent to the CPU. Therefore, the error flag should be cleared.
Note: For block transfer mode, see section 13.4, SCI Interrupts.
14.3.7 Operation in GSM Mode
Switching the Mode: When switching between smart card interface mode and software standby
mode, the following switching procedure should be followed in order to maintain the clock duty.
• When changing from smart card interface mode to software standby mode
[1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to
the value for the fixed output state in software standby mode.
[2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to h a lt tran smit/receive
operation. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
[3] Write 0 to the CKE0 bit in SCR to halt th e clock.
[4] Wait for one serial clock period.
During th is interval, clock output is fixed at the specified level, with the duty preserved.
[5] Make the transition to the software standby state.
• When returning to smart card interface mode from software standby mode
[6] E xit the software standby state.
[7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
norma l du ty.
[1] [2] [3] [4] [5] [6] [7]
Software
standby
Normal operation Normal operation
Figure 14.9 Clock Halt and Restart Procedure
Section 14 Smart Card Interface
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Powering On: To secure the clock duty from power-on, the following switching procedure should
be followed.
[1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
to fix the potential.
[2] Fix the SCK pin to the specified output level with the CKE1 b it in SCR.
[3] Set SMR and SCMR, and switch to smart card mode operation.
[4] Set the CKE0 bit in SCR to 1 to start cloc k output.
14.3.8 Operation in Block Transfer Mode
Operation in block transfer mode is the same as in SCI asynchronous mode, except for the
following points. For details, see section 13.3.2, Operation in Asynchronous Mode.
(1) Data Format
The data format is 8 bits with parity. There is no sto p bit, but there is a 2-bit (1-bit or m ore in
reception) error guard time.
Also, except during transmission (with start bit, da ta bits, and parity b it) , the tr ansmission pins go
to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor.
(2) Transmit/Receive Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock. The number of basic clo c k periods in a 1-bit transfer interval can be set to
32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 14.3.5, Clock.
(3) ERS (FER) Flag
As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since
error signal transmission and reception is not performed, this flag is always cleared to 0.
Section 14 Smart Card Interface
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14.4 Usage Notes
The following points should be noted when using the SCI as a Smart Card interface.
Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In
Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or
256 times the transfer rate (as determined by bits BCP1 and BCP0).
In reception, the SCI samples the falling edge of the start bit using the basic clo ck, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd,
186th, or 128th pulse of the basic clock. Figure 14.10 shows the receive data sampling timing
when using a clock of 372 times the transfer rate.
Internal
basic
clock
372 clocks
186 clocks
Receive
data (RxD)
Synchro-
nization
sampling
timing
D0 D1
Data
sampling
timing
185 371 0
371
185 0
0
Start bit
Figure 14.10 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Transfer Rate)
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Thus the reception margin in asynchronous mode is given by the following formula.
Formula for reception margin in smart card interface mode
M = (0.5 – 1
2N ) – (L – 0.5) F – D – 0.5
N (1 + F) × 100%
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32 , 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
When D = 0.5 and F = 0,
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Section 14 Smart Card Interface
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Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by
the SCI in receive mode and transmit mode as described below.
• Retransfer operation when SCI is in receive mode
Figure 14.11 illustrates the retransfer operation when the SCI is in receiv e mode.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this tim e, an ERI interrupt reque st is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
[2] The RDRF bit in SSR is not set fo r a frame in which an error h as occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
If DTC data transfer by an RXI source is enabled, the contents of RDR can be read
automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared
to 0.
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
error signal tr ansmission.
D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp(DE)DsD0D1D2D3D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
RDRF
[1]
PER
[2]
[3]
[4]
Figure 14.11 Retransfer Operation in SCI Receive Mode
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• Retransfer operation when SCI is in transmit m ode
Figure 14.12 illustrates the retransfer operation when the SCI is in transmit mod e.
[6] If an error signal is sent back from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enab led at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 un til the next
parity b it is sam pled.
[7] The TEND bit in SSR is n ot set for a frame for which an error signal indicating an abnormality
is received.
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
a retransfer, is ju dged to have been completed, and the TEND bit in SSR is set to 1. If th e TI E
bit in SCR is enabled at this time, a TXI inter r upt request is gen erated.
If data transf er by the DTC by m e ans of the TXI source is enabled, the next data can be wr itten
to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is
automatically cleared to 0.
D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp (DE) DsD0D1D2D3D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
TDRE
TEND
[6]
FER/ERS
Transfer to TSR from TDR
[7] [9]
[8]
Transfer to TSR from TDR Transfer to TSR
from TDR
Figure 14.12 Retransfer Operation in SCI Transmit Mode
Section 14 Smart Card Interface
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Section 15 Controller Area Network (HCAN)
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Section 15 Controller Area Network (HCAN)
15.1 Overview
The HCAN is a module for contro lling a controller area network (CAN) for realtime
communication in vehicular and industrial equipment systems, etc. The H8S/2626 Group and
H8S/2623 Group have a single-channel on-chip HCAN module.
Reference: BOSCH CAN Specification Version 2.0 1991, Robert Bosch GmbH
15.1.1 Features
• CAN version: Bosch 2.0B active compatible
Communication sy stems:
NRZ (Non-Return to Zero) sy stem (with bit-stu ffin g function)
Broadcast communication system
Transmission path: Bidirectional 2-wire serial communication
Communication sp eed: Max. 1 Mbps
Data length: 0 to 8 bytes
• Number of channels: 1
• Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception)
• Data transmission: Choice of two methods:
Mailbox (buffer) number order (low-to-high)
Message priority (identifier) high-to-low order
• Data reception: Two methods:
Message identifier match (tran smit/receive-settin g buffers)
Reception with message identifier masked (receive-only)
• CPU interrupts: Five interrupt vectors:
Error interrupt
Reset processing interrupt
Message reception interrupt (mailboxes 1 to 15)
Message reception interrupt (mailbox 0)
Message transmission inter rupt
• HCAN operating modes: Support for various modes:
Hardware reset
Software reset
Section 15 Controller Area Network (HCAN)
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Normal status (error-active, error-passive)
Bus of f status
HCAN configuration mode
HCAN sleep mode
HCAN halt mode
• Other features: DTC can be activated by message reception mailbox (HCAN mailbox 0 only)
15.1.2 Block Diagram
Figure 15.1 shows a block diagram of the HCAN.
Peripheral address bus
Peripheral data bus
HTxD
MBI
Message buffer
HRxD
MPI
Microprocessor interface
(CDLC)
CAN
Data Link Controller
Bosch CAN 2.0B active
CPU interface
Control register
Status register
HCAN
Tx buffer
Rx buffer
Message control
Message data
MC0–MC15, MD0–MD15
LAFM
Mailboxes
Figure 15.1 HCAN Block Diagram
Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter
mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messag e s
are written by the CPU. For receive messag es, the data received by the CDLC is stored
automatically.
Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status
register, etc., controls HCAN internal data, statuses, and so forth.
CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of
messages conforming to the Bosch CAN Ver. 2.0B active standard (d ata frames, remote frames,
error fram es, overload fra mes, inte r-frame spacing), as we ll as CRC checking, bus arbitration, and
other functions.
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15.1.3 Pin Configuration
Table 15.1 shows the HCAN’s pins.
When using HCAN pins, settings must be made in the HCAN configuration mode (during
initialization: MCR0 = 1 and GSR3 = 1).
Table 15.1 HCAN Pins
Name Abbreviation Input/Output Function
HCAN transmit data pin HTxD Output CAN bus transmission pin
HCAN receive data pin HRxD Input CAN bus reception pin
A bus driver is necessary between the pins and the CAN bus. A Philips PCA82C250 compatible
model is recommended.
Section 15 Controller Area Network (HCAN)
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15.1.4 Register Configuration
Table 15.2 lists the HCAN’s registers.
Table 15.2 HCAN Registers
Name Abbreviation R/W Initial Value Address*Access Size
Master control register MCR R/W H'01 H'F800 8 bits 16 bits
General status register GSR R/W H'0C H'F801 8 bits
Bit configuration register BCR R/W H'0000 H'F802 8/16 bits
Mailbox configuration register MBCR R/W H'0100 H'F804 8/16 bits
Transmit wait register TXPR R/W H'0000 H'F806 8/16 bits
Transmit wait cancel register TXCR R/W H'0000 H'F808 8/16 bits
Transmit acknowledge register TXACK R/W H'0000 H'F80A 8/16 bits
Abort acknowledge register ABACK R/W H'0000 H'F80C 8/16 bits
Receive complete register RXPR R/W H'0000 H'F80E 8/16 bits
Remote request register RFPR R/W H'0000 H'F810 8/16 bits
Interrupt register IRR R/W H'0100 H'F812 8/16 bits
Mailbox interrupt mask register MBIMR R/W H'FFFF H'F814 8/16 bits
Interrupt mask register IMR R/W H'FEFF H'F816 8/16 bits
Receive error counter REC R H'00 H'F818 8 bits 16 bits
Transmit error counter TEC R H'00 H'F819 8 bits
Unread message status register UMSR R/W H'0000 H'F81A 8/16 bits
Local acceptance filter mask L LAFML R/W H'0000 H'F81C 8/16 bits
Local acceptance filter mask H LAFMH R/W H'0000 H'F81E 8/16 bits
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Name Abbreviation R/W Initial Value Address*Access Size
Message control 0 [1:8] MC0 [1:8] R/W Undefined H'F820 8/16 bits
Message control 1 [1:8] MC1 [1:8] R/W Undefined H'F828 8/16 bits
Message control 2 [1:8] MC2 [1:8] R/W Undefined H'F830 8/16 bits
Message control 3 [1:8] MC3 [1:8] R/W Undefined H'F838 8/16 bits
Message control 4 [1:8] MC4 [1:8] R/W Undefined H'F840 8/16 bits
Message control 5 [1:8] MC5 [1:8] R/W Undefined H'F848 8/16 bits
Message control 6 [1:8] MC6 [1:8] R/W Undefined H'F850 8/16 bits
Message control 7 [1:8] MC7 [1:8] R/W Undefined H'F858 8/16 bits
Message control 8 [1:8] MC8 [1:8] R/W Undefined H'F860 8/16 bits
Message control 9 [1:8] MC9 [1:8] R/W Undefined H'F868 8/16 bits
Message control 10 [1:8] MC10 [1:8] R/W Undefined H'F870 8/16 bits
Message control 11 [1:8] MC11 [1:8] R/W Undefined H'F878 8/16 bits
Message control 12 [1:8] MC12 [1:8] R/W Undefined H'F880 8/16 bits
Message control 13 [1:8] MC13 [1:8] R/W Undefined H'F888 8/16 bits
Message control 14 [1:8] MC14 [1:8] R/W Undefined H'F890 8/16 bits
Message control 15 [1:8] MC15 [1:8] R/W Undefined H'F898 8/16 bits
Message data 0 [1:8] MD0 [1:8] R/W Undefined H'F8B0 8/16 bits
Message data 1 [1:8] MD1 [1:8] R/W Undefined H'F8B8 8/16 bits
Message data 2 [1:8] MD2 [1:8] R/W Undefined H'F8C0 8/16 bits
Message data 3 [1:8] MD3 [1:8] R/W Undefined H'F8C8 8/16 bits
Message data 4 [1:8] MD4 [1:8] R/W Undefined H'F8D0 8/16 bits
Message data 5 [1:8] MD5 [1:8] R/W Undefined H'F8D8 8/16 bits
Message data 6 [1:8] MD6 [1:8] R/W Undefined H'F8E0 8/16 bits
Message data 7 [1:8] MD7 [1:8] R/W Undefined H'F8E8 8/16 bits
Message data 8 [1:8] MD8 [1:8] R/W Undefined H'F8F0 8/16 bits
Message data 9 [1:8] MD9 [1:8] R/W Undefined H'F8F8 8/16 bits
Message data 10 [1:8] MD10 [1:8] R/W Undefined H'F900 8/16 bits
Message data 11 [1:8] MD11 [1:8] R/W Undefined H'F908 8/16 bits
Message data 12 [1:8] MD12 [1:8] R/W Undefined H'F910 8/16 bits
Message data 13 [1:8] MD13 [1:8] R/W Undefined H'F918 8/16 bits
Message data 14 [1:8] MD14 [1:8] R/W Undefined H'F920 8/16 bits
Message data 15 [1:8] MD15 [1:8] R/W Undefined H'F928 8/16 bits
Module stop contro l
register C MSTPCRC R/W H'FF H'FDEA 8/16 bits
Note: *Lower 16 bits of the address.
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15.2 Register Descriptions
15.2.1 Master Control Register (MCR)
The master control register (MCR) is an 8-bit readable/writable register that controls the CAN
interface.
MCR
Bit:76543210
MCR7 — MCR5 — — MCR2 MCR1 MCR0
Initial value:00000001
R/W: R/W R R/W R R R/W R/W R/W
Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by
bus operation.
Bit 7
MCR7 Description
0 HCAN sleep mode release by CAN bus operation disabled (Initial value)
1 HCAN sleep mode release by CAN bus operation enabled
Bit 6—Reserved: This bit always reads 0. The write value should always be 0.
Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition.
Bit 5
MCR5 Description
0 HCAN sleep mode released (Initial value)
1 Transition to HCAN sleep mode enabled
Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0.
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Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit
messages.
Bit 2
MCR2 Description
0 Transmi ss ion order determined by messa ge iden tifi er priority (Initial val ue)
1 Transmiss ion order determ i ned by mai lbo x (buffer) num ber prior ity
(TXPR1 > TXPR15)
Bit 1—Halt Request (MCR1): Controls halting of the HCAN module.
Bit 1
MCR1 Description
0 HCAN normal operating mode (Initial value)
1 HCAN halt mode transition request
Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module.
Bit 0
MCR0 Description
0 Normal operating mode (MCR0 = 0 and GSR3 = 0)
[Setting condition]
When 0 is written after an HCAN reset
1 HCAN reset mode transition request (Initial value)
In order for GSR3 to change from 1 to 0 after 0 is wr itten to MCR0, time is required before the
HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0
is cleared to 0.
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15.2.2 General Status Register (GSR)
The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN
bus.
GSR
Bit:76543210
————GSR3GSR2GSR1GSR0
Initial value:00001100
R/W:RRRRRRRR
Bits 7 to 4—Reserved: These bits always read 0.
Bit 3—Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating
state or the reset state. Writes are invalid.
Bit 3
GSR3 Description
0 Normal operating state
[Setting condition]
After an HCAN internal reset
1 Configuration mode
[Reset condit ion]
MCR0 reset mode and sl eep mode (Initial value)
Bit 2—Message Transmission Status Flag (GSR2): Flag that indicates whether the module is
currently in the message transmission period. The “message transmission period” is the period
from th e start of message transmission (SOF) u ntil the end of a 3-bit interm ission interval af ter
EOF (End of Frame). Writes are invalid.
Bit 2
GSR2 Description
0 Message t ransmission period
1 [Reset Condition]
Idle period ( Initi al val ue)
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Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. Writes
are invalid.
Bit 1
GSR1 Description
0 [Reset con dit ion]
When TEC < 96 and REC < 96 or TEC ≥ 256 (Initial value)
1 When TEC ≥ 96 or REC ≥ 96
Bit 0—Bus Off Flag (GSR0): Flag that indicates the bus off state. Writes are invalid.
Bit 0
GSR0 Description
0 [Reset con dit ion]
Recovery from bus off state (Initial value)
1 When TEC ≥ 256 (bus off state)
15.2.3 Bit Configuration Register (BCR)
The bit configu r ation register (BCR) is a 16 - bit readable/writable reg ister that is used to set CAN
bit timing p a r ameters and the baud rate prescaler.
BCR
Bit: 15 14 13 12 11 10 9 8
BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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Bits 15 and 14—Resy nchronization Jump Width (SJW): These bits set the bit synch r onization
range.
Bit 15 Bit 14
BCR7 BCR6 Description
0 0 Bit synchronization width = 1 time quantum (Initial value)
1 Bit synchronization width = 2 time quanta
1 0 Bit synchronization width = 3 time quanta
1 Bit synchronization width = 4 time quanta
Bits 13 to 8—Baud Rate Prescaler (BRP): These bits are used to set the CAN bus baud rate.
Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 Description
0000002 × system clo ck (Initial value)
0000014 × system clock
0000106 × system clock
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1 1 1 1 1 1 128 × system clock
Bit 7—Bit Sample Point (BSP): Sets the point at which data is sampled.
Bit 7
BCR15 Description
0 Bit sampling at one point (end of time segment 1 (TSEG1)) (Initial value)
1 Bit sampling at three points (end of TSEG1 and preceding and following time
quantum)
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Bits 6 to 4—Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1-
bit time error . A valu e fro m 2 to 8 can be set.
Bit 6 Bit 5 Bit 4
BCR14 BCR13 BCR12 Description
0 0 0 Setting prohibited (Initial value)
1 TSEG2 = 2 time quanta
1 0 TSEG2 = 3 time quanta
1 TSEG2 = 4 time quanta
1 0 0 TSEG2 = 5 time quanta
1 TSEG2 = 6 time quanta
1 0 TSEG2 = 7 time quanta
1 TSEG2 = 8 time quanta
Bits 3 to 0—Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing
output buffer, CAN bus, and input buffer delay. A value from 1 to 16 can be set.
Bit 3 Bit 2 Bit 1 Bit 0
BCR11 BCR10 BCR9 BCR8 Description
0 0 0 0 Setting prohibited (Initial value)
0001Setting prohibited
0010Setting prohibited
0 0 1 1 TSEG1 = 4 time quanta
0 1 0 0 TSEG1 = 5 time quanta
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1 1 1 1 TSEG1 = 16 time quanta
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15.2.4 Mailbox Configuration Register (MBCR)
The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to
set mailbox (buffer) transmission/reception.
MBCR
Bit: 15 14 13 12 11 10 9 8
MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 —
Initial value:00000001
R/W: R/W R/W R/W R/W R/W R/W R/W R
Bit:76543210
MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 9 and 7 to 0—Mailbox Setting Register (MBCR7 to MBCR1, MBCR15 to
MBCR8): These bits set the polarity of the corresponding mailboxes.
Bit x
MBCRx Description
0 Corresponding mailbox is set for transmission (Initial value)
1 Corresponding mailbox is set for reception
Bit 8—Reserved: This bit always reads 1. The write value should always be 1.
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15.2.5 Transmit Wait Register (TXPR)
The transmit wait re gister (TXPR) is a 16 - bit readable/writable reg ister that is used to set a
transmit wait after a tr ansmit message is sto r ed in a mailbo x (buf f e r) (CAN bus arbitration wait).
TXPR
Bit: 15 14 13 12 11 10 9 8
TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R
Bit:76543210
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 9 and 7 to 0—Transmit Wait Register (TXPR7 to TXPR1, TXPR15 to TXPR8):
These bits set a transmit wait for the corresponding mailboxes.
Bit x
TXPRx Description
0 Transmit mess age idle state in correspo ndi ng mai lbo x (Initial value)
[Clearing cond iti on]
Message transmission completion and cancellation completion
1 Transmit message transmit wait in corresponding mailbox (CAN bus arbitration)
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
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15.2.6 Transmit Wait Cancel Register (TXCR)
The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls
cancellation of transmit wait messages in mailboxes (buffers).
TXCR
Bit: 15 14 13 12 11 10 9 8
TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R
Bit:76543210
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register (TXCR7 to TXCR1, TXCR15 to
TXCR8): These bits control cancellation of transmit wait messages in the corresponding HCAN
mailboxes.
Bit x
TXCRx Description
0 Transmit mess age cancellation idle state in correspo nding mailbo x (Initial value)
[Clearing cond iti on]
Completion of TXPR clearing (when transmit message is canceled normally)
1 TXPR cleared fo r corresponding mailbox (transmit message cancellation)
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
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15.2.7 Transmit Acknowledge Register (TXACK)
The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing
status flags that indicate normal transmission of mailbox (buffer) transmit messages.
TXACK
Bit: 15 14 13 12 11 10 9 8
TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 —
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R
Bit:76543210
TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: *Can only be written with 1 for flag clearing .
Bits 15 to 9 and 7 to 0—Transmit Acknowledge Register (TXACK7 to TXACK1, TXACK15
to TXACK8): These bits indicate that a transmit message in the corresponding HCAN mailbox
has been tr ansmitted normally.
Bit x
TXACKx Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Completion of message transmission for corresponding mailbox
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
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15.2.8 Abort Acknowledge Register (ABACK)
The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status
flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages.
ABACK
Bit: 15 14 13 12 11 10 9 8
ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 —
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R
Bit:76543210
ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: *Can only be written with 1 for flag clearing .
Bits 15 to 9 and 7 to 0—Abort Acknowledge Register (ABACK7 to ABACK1, ABACK15 to
ABACK8): These bits indicate that a transmit message in the corresponding mailbox has been
canceled (aborted) normally.
Bit x
ABACKx Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Completion of transmit message cancellation for corresponding mailbox
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
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15.2.9 Receive Complete Register (RXPR)
The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags
that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers).
In the case of remote frame reception, the corresponding remote request register (RFPR) is also set
simultaneously.
RXPR
Bit: 15 14 13 12 11 10 9 8
RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Bit:76543210
RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: *Can only be written with 1 for flag clearing .
Bits 15 to 0—Receive Complete Register (RXPR7 to RXPR0, RXPR15 to RXPR8): These bits
indicate that a receive message has been received normally in the corresponding mailbox.
Bit x
RXPRx Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Completion of message (data frame or remote frame) reception in corresponding
mailbox
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15.2.10 Remote Request Register (RFPR)
The remote request register (RFPR) is a 16-bit readable/writable register containing status flags
that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register
is set, the corresponding reception complete bit is set simultaneously.
RFPR
Bit: 15 14 13 12 11 10 9 8
RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Bit:76543210
RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: * Can only be written with 1 for flag clea ring.
Bits 15 to 0—Remote Request Register (RFPR7 to PFPR0, RFPR15 to PFDR8): These bits
indicate that a remote frame has been received normally in the corresponding mailbox.
Bit x
RFPRx Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Completion of remote frame reception in corresponding mailbox
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15.2.11 Interrupt Register (IRR)
The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the
various interrupt sources.
IRR
Bit: 15 14 13 12 11 10 9 8
IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
Initial value:00000001
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*RRR/(W)
*
Bit:76543210
— — — IRR12 — — IRR9 IRR8
Initial value:00000000
R/W: ———R/(W)
*——RR/(W)
*
Note: * Can only be written with 1 for flag clea ring.
Bit 15—Overload Frame/Bus Off Recovery Interrupt Flag (IRR7): Status flag indicating that
the HCAN has transm itted an overload frame or recovered from th e bus o ff state.
Bit 15
IRR7 Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Overload frame transmission or recovery from bus off state
[Setting conditions]
Error active/passive state
• When overloa d frame is transm it t ed
Bus off state
• When 11 recessive bits is received 128 times (REC ≥ 128)
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Bit 14—Bus Off Interrupt Flag (IRR6): Status flag indicating the bus off state caused by the
transmit error counter.
Bit 14
IRR6 Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Bus off state caused by transmit error
[Setting condition]
When TEC ≥ 256
Bit 13—Error Passive Interrupt Flag (IRR5): Status flag indicating the error passive state
caused by the transmit/receive error counter.
Bit 13
IRR5 Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Error passive state caused by transmit/receiv e error
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
Bit 12—Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error
warning state caused by the receive error counter.
Bit 12
IRR4 Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Error warning state caused by receive error
[Setting condition]
When REC ≥ 96
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Bit 11—Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error
warning state caused by the transmit error counter.
Bit 11
IRR3 Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Error warning state caused by transmit error
[Setting condition]
When TEC ≥ 96
Bit 10—Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote
frame has been received in a mailbox (buffer).
Bit 10
IRR2 Description
0 [Clearing cond iti on]
Clearing of all bits in RFPR (remote request register) of mailbox for which receive
interrupt requests are enabled by MBIMR (Initial value)
1 Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed, when corresponding
MBIMR = 0
Bit 9—Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer)
receive message has been received normally.
Bit 9
IRR1 Description
0 [Clearing cond iti on]
Clearing of all bits in RXPR (receive complete register) of mailbox for which receive
interrupt requests are enabled by MBIMR (Initial value)
1 Data frame or remote frame received and stored in mail box
[Setting conditions]
When data frame or remote frame reception is completed, when corresponding
MBIMR = 0
Section 15 Controller Area Network (HCAN)
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Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been
reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after
reset input or recovery from software standby mode, interrupt handling will be performed as soon
as interrupts ar e enabled by the interrupt controller .
Bit 8
IRR0 Description
0 [Clearing cond iti on]
Writing 1
1 Hardware reset (HCAN module stop*, software stan dby) (Initial value)
[Setting condition]
When reset processing is completed after a hardware reset (HCAN module stop*,
software standby)
Note: *After reset or hardware standby release, the module stop bit is initialized to 1, and so
the HCAN enters the module stop state.
Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0.
Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit
due to bus operation when the HCAN module is in HCAN sleep mode.
Bit 4
IRR12 Description
0 CAN bus idle state (Initial value)
[Clearing cond iti on]
Writing 1
1 CAN bus operation in HCAN sleep mode
[Setting condition]
Bus operation (dominant bit detection) in HCAN sleep mode
Bit 1—Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been
overwritten while still unread .
Section 15 Controller Area Network (HCAN)
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Bit 1
IRR9 Description
0 [Clearing cond iti on]
Clearing of all bits in UMSR (unread message status register) (Initial value)
1 Unread message overwrite
[Setting condition]
When UMSR (unread message status register) is set
Bit 0—Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit
message can be stored in the mailbox.
Bit 0
IRR8 Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Transmit message has been transmitted or aborted, and new message can be stored
[Setting condition]
When TXPR (transmit wait register) is cleared by completion of transmission or
completion of transmission abort
15.2.12 Mailbox Interrupt Mask Register (MBIMR)
The mailbox inter r upt mask register ( MBIMR) is a 16-bit readab le/writable register containing
flags that enable or disable individual mailbox (buffer) interrupt requests.
MBIMR
Bit: 15 14 13 12 11 10 9 8
MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8
Initial value:11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Section 15 Controller Area Network (HCAN)
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Bits 15 to 0—Mailbox Interrupt Mask (MBIMRx) (MBIMR7 to MBIMR0, MBIMR15 to
MBIMR8): Flags that enable or disable individual mailbox interrupt requests.
Bit x
MBIMRx Description
0 [Transmitting]
Interrupt request to CPU due to TXPR clearing
[Receiving]
Interrupt request to CPU due to RXPR setting
1 Interrupt requests to CPU disabled (Initial value)
15.2.13 Interrupt Mask Register (IMR)
The interrupt mask register (IMR) is a 16-bit read able/writable register containing flags that
enable or disable requests by individual interrupt sources.
IMR
Bit: 15 14 13 12 11 10 9 8
IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 —
Initial value:11111110
R/W: R/W R/W R/W R/W R/W R/W R/W R
Bit:76543210
— — — IMR12 — — IMR9 IMR8
Initial value:11111111
R/W: R R R R/W R R R/W R/W
Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables
overload frame/bus off recovery interrupt requests.
Bit 15
IMR7 Description
0 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 enabled
1 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 disabled
(Initial value)
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Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused
by the transmit error counter.
Bit 14
IMR6 Description
0 Bus off inte rrupt request (ERS0) to CPU by IRR6 enabled
1 Bus off interrupt request (ERS0) to CPU by IRR6 disabled (Initial value)
Bit 13—Error Passive Interrupt Mask (IMR5): Enables or disables erro r passive interrupt
requests caused b y the transmit/receive error counter.
Bit 13
IMR5 Description
0 Error passive interrupt request (ERS0) to CPU by IRR5 enabled
1 Error passive interrupt request (ERS0) to CPU by IRR5 disabled (Initial value)
Bit 12—Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning
interrupt requests caused by the receive error coun ter.
Bit 12
IMR4 Description
0 REC error warning interrupt request (OVR0) to CPU by IRR4 enabled
1 REC error warning interrupt request (OVR0) to CPU by IRR4 disabled (Initial value)
Bit 11—Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error
warning interrupt requests caused by the transmit error counter.
Bit 11
IMR3 Description
0 TEC error warning interrupt request (OVR0) to by IRR3 CPU enabled
1 TEC error warning interrupt request (OVR0) to by IRR3 CPU disabled (Initial value)
Section 15 Controller Area Network (HCAN)
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Bit 10—Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame
reception interrupt requests.
Bit 10
IMR2 Description
0 Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled
1 Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled
(Initial value)
Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception
interrupt requests.
Bit 9
IMR1 Description
0 Message reception interrupt request (RM1) to CPU by IRR1 enabled
1 Message reception interrupt request (RM1) to CPU by IRR1 disabled (Initial value)
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.
Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to
bus operation in sleep mode.
Bit 4
IMR12 Description
0 Bus operation interrupt request (OVR0) to CPU by IRR12 enabled
1 Bus operation interrupt request (OVR0) to CPU by IRR12 disabled (Initial value)
Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite
interrupt requests.
Bit 1
IMR9 Description
0 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 enabled
1 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 disabled
(Initial value)
Section 15 Controller Area Network (HCAN)
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Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt
requests.
Bit 0
IMR8 Description
0 Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled
1 Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled (Initial value)
15.2.14 Receive Error Counter (REC)
The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol.
REC
Bit:76543210
Initial value:00000000
R/W:RRRRRRRR
15.2.15 Transmit Error Counter (TEC)
The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter
indicating th e num ber of transmit message err ors on the CAN bus. The count value is stipulated in
the CAN protocol.
TEC
Bit:76543210
Initial value:00000000
R/W:RRRRRRRR
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15.2.16 Unread Message Status Register (UMSR)
The unread message status register (UMSR) is a 16-bit readable/writable register containing status
flags that indicate, for individual mailboxes (buffers), that a received message has been
overwritten by a new receive message before being read. When a messag e is overwritten by a new
receive message, the old data is lost.
UMSR
Bit: 15 14 13 12 11 10 9 8
UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Bit:76543210
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8
Initial value:00000000
R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: *Can only be written with 1 for flag clearing .
Bits 15 to 0—Unread Message Status Flags (UMSR7 to UMSR0, UMSR15 to UMSR8):
Status flags indicating th at an unread receive message has been overwritten.
Bit x
UMSRx Description
0 [Clearing cond iti on]
Writing 1 (Initial value)
1 Unread receive message is overwritten by a new message
[Setting condition]
When a new message is received before RXPR is cleared x = 0 to 15
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15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)
The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that
filter receive messages to be sto r ed in the receive-only mailbox (MC0, MD0) according to the
identifier. I n these r egisters, consist of LAFMH1 5 (MSB) to LAFMH5 (L SB) are 11
standard/extended identifier bits, and LAFMH1 (MSB) to LAFML0 (LSB) are 18 extended
identifier bits.
LAFML
Bit: 15 14 13 12 11 10 9 8
LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:76543210
LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
LAFMH
Bit: 15 14 13 12 11 10 9 8
LAFMH7 LAFMH6 LAFMH5 ———LAFMH1 LAFMH0
Initial value:00000000
R/W: R/W R/W R/W R R R R/W R/W
Bit:76543210
LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Section 15 Controller Area Network (HCAN)
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LAFMH Bits 7 to 0 and 15 to 13—11-Bit Identifier Filter (LAFMH7 to LAFMH5,
LAFMH15 to LAFMH8): Filter mask bits for the first 11 bits of the receive message identifier
(for both standard and extended identifiers).
Bit x
LAFMHx Description
0 Stored in MC0, MD0 (receive-only mailbox) depending on bit match between MC0
message identifier and receive message identifier (Initial value)
1 Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between MC0
message identifier and receive message identifier
LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be 0.
LAFMH Bits 9 and 8, LAFML Bits 15 to 0—18-Bit Identifier Filter (LAFMH1, LAFMH0,
LAFML7 to LA FML0 , LAFM L15 to LAFML8 ): Filter mask bits fo r the 18 bits of the receive
message identifier (extended).
Bit x
LAFMHx
LAFMLx Description
0 Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message
identifier and receive message identifier (Initial value)
1 Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message
identifier and receive message identifier
Section 15 Controller Area Network (HCAN)
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15.2.18 Message Control (MC0 to MC15)
The message co ntrol register sets (MC0 to MC15) con sist o f eight 8-bit readable/writable r e g ister s
(MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15).
The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).
MCx [1]
Bit:76543210
————DLC3DLC2DLC1DLC0
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MCx [2]
Bit:76543210
————————
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MCx [3]
Bit:76543210
————————
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MCx [4]
Bit:76543210
————————
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Section 15 Controller Area Network (HCAN)
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MCx [5]
Bit:76543210
STD_ID2 STD_ID1 STD_ID0 RTR IDE —EXD_ID17EXD_ID16
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MCx [6]
Bit:76543210
STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MCx [7]
Bit:76543210
EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MCx [8]
Bit:76543210
EXD_ID15EXD_ID14EXD_ID13EXD_ID12EXD_ID11EXD_ID10 EXD_ID9 EXD_ID8
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
x = 0 to 15
MCx[1] Bits 7 to 4—Reserved: The initial value of these bits is undefined; they must be
initialized (by wr iting 0 or 1).
Section 15 Controller Area Network (HCAN)
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MCx[1] Bits 3 to 0—Data Length Code (DLC): These bits indicate the required length of d a ta
frames and remote frames.
Bit 3 Bit 2 Bit 1 Bit 0
DLC3 DLC2 DLC1 DLC0 Description
0000Data length = 0 bytes
1 Data length = 1 byte
1 0 Data length = 2 bytes
1 Data length = 3 bytes
100Data length = 4 bytes
1 Data length = 5 bytes
1 0 Data length = 6 bytes
1 Data length = 7 bytes
1 0/1 0/1 0 /1 Data length = 8 bytes
MCx[2] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be
initialized (by wr iting 0 or 1).
MCx[3] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be
initialized (by wr iting 0 or 1).
MCx[4] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be
initialized (by wr iting 0 or 1).
MCx[6] Bits 7 to 0—Standard Identifier (STD_ID10 to STD_ID3):
MCx[5] Bits 7 to 5—Standard Identifier (STD_ID2 to STD_ID0):
These bits set the identifier (standar d identifier) of data frames and re mote frames.
Standard identifier
SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
STD_IDxx
IDE
SRR
Figure 15.2 Standard Identifier
Section 15 Controller Area Network (HCAN)
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MCx[5] Bit 4—Remote Transmission Request (RTR): Used to distinguish between data frames
and remote frames.
Bit 4
RTR Description
0 Data frame
1 Remote frame
MCx[5] Bit 3—Identifier Extension (IDE): Used to distinguish between the standard format and
extended format of data frames and remote frames.
Bit 3
IDE Description
0 Standard format
1 Extended format
MCx[5] Bit 2—Reserved: The initial value of this bit is undefined; it must be initialized (by
writing 0 or 1).
MCx[5] Bits 1 and 0—Extended Identifier (EXD_ID17, EXD_ID16):
MCx[8] Bits 7 to 0—Extended Identifier (EXD_ID15 to EXD_ID8):
MCx[7] Bits 7 to 0—Extended Identifier (EXD_ID7 to EXD_ID0):
These bits set the identifier (extended identifier) of data frames and r emote frames.
Extended Identifier
IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5
EXD_IDxx
ID4 ID3 ID2 ID1 ID0 RTR R1
EXD_IDxx
Figure 15.3 Extended Identifier
Section 15 Controller Area Network (HCAN)
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15.2.19 Message Data (MD0 to MD15)
The message data register sets (MD0 to MD15) consist of eight 8-b it readab le/wr itable registers
(MDx[1] to MDx[8]). Th e HCAN has 16 sets of these registers (MD0 to MD15).
The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).
MDx [1]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [2]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [3]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [4]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Section 15 Controller Area Network (HCAN)
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MDx [5]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [6]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [7]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [8]
Bit:76543210
Initial value: ********
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
x = 0 to 15
Section 15 Controller Area Network (HCAN)
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15.2.20 Module Stop Control Register C (MSTPCRC)
Bit:76543210
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value: 11111111
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC3 bit is set to 1, HCAN operation is stopped at the end of the bus cycle, and
module stop mode is entered. Register read/write accesses are not possible in module stop mode.
For details, see sections 21A.5, 21B.5, Module Stop Mode.
MSTPCRC is initialized to H'FF by a reset, and in hardware standby m ode . It is not initialized in
software standby mode.
Bit 3—Module Stop (MSTPC3): Specifies the HCAN module stop mode.
Bit 3
MSTPC3 Description
0 HCAN module stop mode is cleared
1 HCAN module stop mode is set (Initial value)
Section 15 Controller Area Network (HCAN)
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15.3 Operation
15.3.1 Hardware and Software Resets
The HCAN can be reset by a hardware reset or software reset.
Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization
is performed by automatic setting of the MCR reset r e quest bit (MCR0) in MCR and the reset state
bit (GSR3) in GSR within the HCAN (har dware reset). At the sam e tim e, all internal registers are
initialized. However mailbox contents are retained. A flowchart of this reset is sh o w n in figure
15.4.
Note: * In a reset and in hardware stan dby mode, the module stop b it is in itialized to 1 and the
HCAN enters the module stop state.
Software Reset (Write to MCR0): In normal operation initialization is performed by setting the
MCR reset requ est bit (MCR0) in MCR (Software reset). With this kind of reset, if the CAN
controller is performing a commun ication o peration (transmission or reception), the initialization
state is not entered until the message has been completed. During initialization, the reset state bit
(GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are
initialized but other registers and RAM (mailboxes) are not. A flowchart of this reset is shown in
figure 15.5.
Section 15 Controller Area Network (HCAN)
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IRR0 = 1 (automatic)*
1
GSR3 = 1 (automatic)
Initialization of HCAN module
Clear IRR0
BCR setting
MBCR setting
Mailbox (RAM) initialization
Message transmission method initialization
Hardware reset
MCR0 = 1 (automatic)
GSR3 = 0?
GSR3 = 0 & 11
recessive bits received?
CAN bus communication enabled
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MC[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
MCR0 = 0
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
: Settings by user
: Processing by hardware
Yes
Yes
No
No
Notes: 1. When IRR0 is set to 1 (automatically) due to a hardware reset
*
2, a "hardware reset
initiated reset processing" interrupt is generated.
2. In a reset and in hardware standby mode, the module stop bit is initialized to 1 and
the HCAN enters the module stop state.
Figure 15.4 Hardware Reset Flowchart
Section 15 Controller Area Network (HCAN)
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Initialization of REC and TEC only
MCR0 = 1
GSR3 = 1 (automatic)
Bus idle?
CAN bus communication enabled
: Settings by user
: Processing by hardware
Yes
Yes
No
No
MCR0 = 0
GSR3 = 0? No
IMR setting
MBIMR setting
MC[x] setting
LAFM setting
OK?
No
Yes
Yes
Yes
Correction
Correction
No
BCR setting
MBCR setting
Mailbox (RAM) initialization
Message transmission method
initialization
OK?
GSR3 = 0 & 11
recessive bits received?
Figure 15.5 Software Reset Flowchart
Section 15 Controller Area Network (HCAN)
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15.3.2 Initialization after Hardware Reset
After a hardware reset, the following initialization processing should be carried out:
• Clearing of IRR0 bit in interrupt register (IRR)
• Bit rate setting
• Mailbox transmit/receive settings
• Mailbox (RAM) initialization
• Message transmission method setting
These initial settings must be made while the HCAN is in bit configuration mod e. Configuration
mode is a state in which the reset requ est bit (MCR0) in the master control r egister ( M CR) is 1 and
the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is
exited by clear ing the reset request bit in MCR to 0; when MCR0 is clear ed to 0, the HCAN
automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up
sequence then begins, and communication with the CAN bus is possible as soon as the sequence
ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a reset or reco very from
software standby mode. As an HCAN interrupt is initiated immediately when interrupts are
enabled, IRR0 should be cleared.
Bit Rate and Bit Timing Settings: As bit rate settings, a b a ud rate setting and bit timing setting
must be made each time a CAN node begins communication. The baud rate and bit timing settings
are made in the bit configuration register (BCR).
a. Note
BCR can be written to at all times, but should only be modified in configuration mode.
Settings should be made so that all CAN controllers connected to the CAN bus have the same
baud rate and bit width.
Refer to table 15.3 for the range of values that can be used as settings (TSEG1, TSEG2, BRP,
sample point, and SJW) for BCR.
Section 15 Controller Area Network (HCAN)
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Table 15.3 BCR Register Value Setting Ranges
Name Abbreviation Min. Value Max. Value
Time segment 1 TSEG1 B'0000 B'1111
Time segment 2 TSEG2 B'000 B'111
Baud rate prescaler BRP B'000000 B'111111
Sample point SAM B'0 B'1
Re-synchr oni zation jump width SJW B'00 B'11
b. Value Setting Ranges
• The bit width consists of th e total of the settable Time Quanta (TQ). TQ (number of system
clocks) is determined by the baud rate prescaler (BRP).
2 × (BRP + 1)
fCLK
TQ =
• The value of SJW is stipulated in the CAN specifications.
3 ≥ SJW ≥ 0
• The minimum value of TSEG1 is stipulated in the CAN specifications.
TSEG1 > TSEG2
• The minimum value of TSEG2 is stipulated in the CAN specifications.
TSEG2 ≥ SJW
The following fo rmula is u sed to calculate the baud rate.
f
CLK
2 × (BRP + 1) × (3 + TSEG1 + TSEG2)
Bit rate [b/s] =
Note: fCLK = φ (system clock)
The BCR values are used for BRP, TSEG1, and TSEG2.
Example: With a 1 Mb/s baud rate and a 20 MHz input clock:
20 MHz
2 × (0 + 1) × (3 + 4 + 3)
1 Mb/s =
Section 15 Controller Area Network (HCAN)
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Item Set Values Actual Values
fCLK 20 MHz —
BRP 0 (B'000000) System clock × 2
TSEG1 4 (B'0100) 5TQ
TSEG2 3 (B'011) 4TQ
SYNC_SEG PRSEG PHSEG1 PHSEG2
1-bit time
Legend:
Note: * The Time Quanta value for TSEG1 and TSEG2 is the TSEG value + 1.
1-bit time (8–25 time quanta)
Quantum
1 TSEG1 (time segment 1)*
2 to 16
TSEG2 (time segment 2)
*
2 to 8
SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal
bit edge transitions occur in this segment.)
PRSEG: Segment for compensating for physical delay between networks.
PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronization (resynchronization) is established.)
PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is
shortened when synchronization (resynchronization) is established.)
Figure 15.6 Detailed Description of One Bit
HCAN bit rate calculation:
fCLK
2 × (BRP + 1) × (3 + TSEG1 + TSEG2)
Bit rate =
Note: fCLK = φ (system clock)
The BCR values are used for BRP, TSEG1, and TSEG2.
BCR Setting Constraints
TSEG1 > TSEG2 ≥ SJW (SJW = 0 to 3)
TSEG2 > B'001 (BRP = B'000000)
TSEG2 > B'000 (BRP > B'000000)
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These constraints allow the setting range shown in table 15.4 for TSEG1 and TSEG2 in BCR.
Table 15.4 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR [14:12])
001 010 011 100 101 110 111
0011 NoYesNoNoNoNoNoTSEG1
(BCR [11:8]) 0100 Yes*Yes Yes No No No No
0101 Yes*Yes Yes Yes No No No
0110 Yes*Yes Yes Yes Yes No No
0111 Yes*Yes Yes Yes Yes Yes No
1000 Yes*Yes Yes Yes Yes Yes Yes
1001 Yes*Yes Yes Yes Yes Yes Yes
1010 Yes*Yes Yes Yes Yes Yes Yes
1011 Yes*Yes Yes Yes Yes Yes Yes
1100 Yes*Yes Yes Yes Yes Yes Yes
1101 Yes*Yes Yes Yes Yes Yes Yes
1110 Yes*Yes Yes Yes Yes Yes Yes
1111 Yes*Yes Yes Yes Yes Yes Yes
Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.
*Setting is enabled except when BRP [13:8] = B'000000.
Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receive-
only, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set
for transmission or reception must be designated either for transmission use or fo r reception use
before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while
mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software
reset.
• Setting for transmissio n
Transmit mailbox setting (mailboxes 1 to 15)
Clearing a bit to 0 in the ma ilbox conf iguration register ( M BCR) designates the c orresponding
mailbox for transmission use. After a reset, mailboxes are initialized for tran smission use, so
this setting is n ot necessary.
• Setting for reception
Transmit/receive mailbox setting (mailboxes 1 to 15)
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Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresp on ding
mailbox for reception use. When setting mailboxes for reception, to improve message
transmission efficiency, high-priority messages should be set in low-to-high mailbox order
(priority order: mailbox 1 (MCx[1]) > mailbox 15 (MCx[15]).
• Receive-only mailbox (mailbox 0)
No setting is necessary, as this mailbox is always used for reception.
Mailbox (Message Contro l/Data (MCx[ x], MDx[x]) Initial Settings: After power is supplied,
all registers and RAM ( message contro l/data, control registers, status register s, etc.) ar e initialized.
Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined.
Initial values must therefore be set in all the mailboxes (by writing 0s or 1s).
Setting the Message Transmission Method: Either of the follo wing message transm ission
methods can be selected with the message transmission method bit (MCR2) in the master control
register (MCR):
a. Transmission order determined by message identifier priority
b. Transmiss i on order determined by mailbox num ber pri orit y
When a is selected, if a number of messages are designated as waiting for transmission (TXPR =
1), the message with the highest priority set in the me ssage identifier (MCx[5]–MCx[8]) is stored
in the transm it buffer. CAN bus arbitration is then carried out for the messag e in the transmit
buffer, and message transmission is performed when the transmission right is acquired. When the
TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found
and stored in the transmit buffer.
When b is selected, if a number of messages are designated as waiting for transmission (TXPR =
1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:
mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit
buffer, and message transmission is performed when the bus is acquired.
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15.3.3 Transmit Mode
Message transmission is performed using mailboxes 1 to 15. The transmission procedure is
described below, and a transmission flowchart is shown in figure 15.7.
Initialization (after hardware reset only)
a. Clearing of IRR0 bit in interrupt register (IRR)
b. Bit rate settin gs
c. Mailbox transmit/receive settings
d. Mailbox initialization
e. Message transmission method setting
Interrupt and transmit data settings
a. CPU interrupt sou r ce setting
b. Arbitr ation field setting
c. Control field setting
d. Data field setting
Message transmission and interrupts
a. Message tra nsmission wa it
b. Message transmission completion and interrupt
c. Message tr ansmission abo rt
d. Message retransmission
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Initializatio n (After Hardwa re Reset Only): These settings should be made while the HCAN is
in bit configuration mode.
• IRR0 clearing
The reset interrupt f lag (IRR0) is always set after a reset o r r ecovery from software standby
mode. As an HCAN interrupt is initiated immediately when in terru pts are enabled, IRR0
should be cleared .
• Bit rate settings
Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit
Rate and Bit Timing Settings in 15.3.2, Initialization after Hard war e Reset, f or details.
• Mailbox transmit/receive settings
Mailbox transmit/receive settings should be made in advance. A total of 15 mailboxes can be
set for transmission or reception (mailboxes 1 to 15). To set a mailbox for tran smission, clear
the corresponding bit to 0 in the mailbox configuration register (MBCR). Refer to Mailbox
Transmit/Receive Settings in 1 5 . 3.2, Initialization after Hardware Reset, for details.
• Mailbox initialization
As message con tr ol/data registers (M Cx[x], MDx[x]) are configured in RAM, their initial
values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to
the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings in
15.3.2, Initialization af ter Hardware Reset, for details.
• Message transmission method setting
Set the transmission method for mailbox es designated for transmission. The following two
transmission methods can be used. Refer to Setting the Message Transmission Method in
15.3.2, Initialization af ter Hardware Reset, for details.
a. Transmission order determined by message identifier priority
b. Transmiss i on order determined by mailbox num ber pri orit y
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Initialization (after hardware reset only)
IRR0 clearing
BCR setting
MBCR setting
Mailbox initialization
Message transmission method setting
Interrupt settings
Transmit data setting
Arbitration field setting
Control field setting
Data field setting
Message transmission wait
TXPR setting
Bus idle? No
Message transmission
GSR2 = 0 (during transmission only)
Transmission completed? No
TXACK = 1
IRR8 = 1
IMR8 = 1? Yes
Interrupt to CPU
Clear TXACK
Clear IRR8
End of transmission
: Settings by user
: Processing by hardware
Yes
Yes
No
Figure 15.7 Transmission Flowchart
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Interrupt and Transmit Da ta Settings: When mailbox initializatio n is finished, CPU interrupt
source settings and data settings must be made. Interrupt source settings are made in the mailbox
interrup t r egister (MBIMR) and interrupt mask r egister ( IMR), while transmit data settings are
made by writing the necessary data from the arbitration field, control field, and data field,
described below, in the corresponding message control (MCx[1]–MCx[8]) and message data
(MDx[1]–MDx[8]).
• CPU interrupt source settings
Transmission acknowledge and transmission abort acknowledge interrupts can be masked for
individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR)
interrup ts can be masked in the interrupt mask register (IMR).
• Arbitration f ield setting
In the arbitration field, the 11-bit identifier ( STD_ ID0–STD_ID10) and RTR bit (standard
format) or 29-bit identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) and IDE.RTR bit
(extended format) are set. The registers to be set are MCx[5]–MCx[8].
• Control field setting
In the control field, the byte length of the data to be transmitted is set in DLC0–DLC3. The
register to be set is MCx[1].
• Data field setting
In the data field, th e data to be transmitted is set in byte u nits in the range of 0 to 8 bytes. The
registe rs to be set are MDx[1]–MDx[8].
The number of bytes in th e data actually transmitted d e pends on the data length code (DLC) in the
control field. If a value exceeding the value set in DLC is set in the data field, only the number of
bytes set in DLC will actua lly be transmitted.
Message Transmission a nd Interr upts:
• Message tr ansmission wait
If message transmission is to be performed after completion of the message control (MCx[1]–
MCx[8]) and message data (MDx[1]–MDx[8]) settings, transmission is started by setting the
corresponding mailbox transmit wait bit (TXPR1–TXPR15) to 1 in the transmit wait reg ister
(TXPR). The following two transmission methods can be used:
a. Transmission order determined by message identifier priority
b. Transmiss i on order determined by mailbox num ber pri orit y
When a is selected, if a number of messages are designated as waiting for transmission (TXPR
= 1), messages are stored in the transmit buffer in low-to-hig h mailbox order (priority order:
Section 15 Controller Area Network (HCAN)
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mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the
transmit buffer, and message transmission is performed when the bus is acquired.
When b is selected, if a number of messages are designated as waiting for transmission (TXPR
= 1), the message with the highest priority set in the message identifier (MCx [5]–MCx[8]) is
stored in th e transmit buffer. CAN bus arbitration is then carried out for the message in the
transmit buffer, and message transmission is performed when the transmission right is
acquired. When the TXPR bit is set, internal ar bitration is per for med again, the highest-prio r ity
message is found and stored in the transmit buffer, CAN bus arbitration is carried ou t in the
same way, and message transmission is performed when the transmission right is acquired.
• Message transmission completion and interrupt
When a message is tr ansmitted error -free using the above procedure, the correspond ing
acknowledge bit (TXAC K1–TXACK15) in the transmit acknowledge register (TXACK) and
transmit wait b it ( TXPR1–TXPR15) in the transmit wait r e gister (TXPR) are au tomatically
initialized. Also, if the correspond ing b it (MBIMR1–MBIMR15) in the mailbox interrupt mask
register (MBIMR) and the mailbox empty interrupt bit (IRR8) in th e interrupt mask register
(IMR) are set to the interrupt enab le state at the same time, an interrupt can be sent to the CPU.
• Message transmission cancellation
Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait
message. A tran sm it wait message is canceled by setting the bit for the corresponding mailbox
(TXCR1–TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is
executed, th e transm it wait r e gister (TXPR) is auto matically reset, and the corresponding bit is
set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested.
Also, if the mailbox empty interrupt (IRR8) is enabled fo r the bits (MBIMR1–MBIMR15)
corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register
(IMR), inter r upts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
a. During internal arbitratio n or CAN bus arbitration
b. During data frame or remote frame transmission
Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure
15.8 shows a flowchart of transmit message cancellation.
• Message retran smission
If transm ission of a transmit message is abor ted in the following cases, th e message is
retransmitted automatically :
a. CAN bus arbitration f ailure (failure to acquire the bus)
b. Error during transmission (bit error, stuff error, CRC error, frame erro r, ACK error)
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Message transmit wait TXPR setting
Set TXCR bit corresponding to message
to be canceled
Cancellation possible? No
Message not sent
Clear TXCR, TXPR
ABACK = 1
IRR8 = 1
IMR8 = 1? Yes
Interrupt to CPU
Clear TXACK
Clear ABACK
Clear IRR8
End of transmission/transmission
cancellation
Completion of message transmission
TXACK = 1
Clear TXCR, TXPR
IRR8 = 1
Yes
No
: Settings by user
: Processing by hardware
Figure 15.8 Transmit Message Cancellation Flowchart
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15.3.4 Receive Mode
Message reception is performed using mailbox es 0 and 1 to 15. The reception procedure is
described below, and a reception flowchart is shown in figure 15.9.
Initialization (after hardware reset only)
a. Clearing of IRR0 bit in interrupt register (IRR)
b. Bit rate settin gs
c. Mailbox transmit/receive settings
d. Mailbox (RAM) initialization
Interrupt and receive message settings
a. CPU interrupt sou r ce setting
b. Arbitr ation field setting
c. Local acceptance filter mask (LAFM) settings
Message reception and interrupts
a. Message reception CRC check
b. Data frame reception
c. Remote frame reception
d. Unread message reception
Initializatio n (After Hardwa re Reset Only): These settings should be made while the HCAN is
in bit configuration mode.
• IRR0 clearing
The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby
mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0
should be cleared .
• Bit rate settings
Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit
Rate and Bit Timing Setting in 15.3.2, Initialization after Hardware Reset, for details.
• Mailbox transmit/receive settings
Each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for
reception. Thus a total of 16 mailboxes can be used for reception. To set a mailbox for
reception, set the correspond ing bit to 1 in the m a ilbox configuration register (M BCR). The
Section 15 Controller Area Network (HCAN)
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initial setting for mailboxes is 0, designating transmission use. Refer to Mailbox
transmit/receive settings in 1 5.3.2, Initialization after Hardware Reset, for details.
• Mailbox (RAM) initialization
As message con tr ol/data registers (M Cx[x], MDx[x]) are configured in RAM, their initial
values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to
the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings in
15.3.2, Initialization af ter a Hardware Reset, for details.
Section 15 Controller Area Network (HCAN)
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Initialization IRR0 clearing
BCR setting
MBCR setting
Mailbox (RAM) initialization
Interrupt settings
Arbitration field setting
Local acceptance filter settings
Receive data setting
Message reception
(Match of identifier
in mailbox?)
No
Same RXPR = 1? Yes
Data frame? No
RXPR
IRR1 = 1
Yes
IMR1 = 1?
Interrupt to CPU
Message control read
Message data read
Clear all RXPRn bits of mailbox for which
receive interrupt requests are enabled
by MBIMR
End of reception
Yes
No
Yes
No
Unread message
RXPR, RFPR = 1
IRR2 = 1, IRR1 = 1
Yes
IMR2 = 1?
Interrupt to CPU
Message control read
Message data read
Clear all RXPRn bits of mailbox for which
receive interrupt requests are enabled
by MBIMR
Transmission of data frame corresponding
to remote frame
IRR1 = 0 IRR2 = 0, IRR1 = 0
No
: Settings by user
: Processing by hardware
Figure 15.9 Reception Flowchart
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Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt
source settings and receive message specifications must be mad e . Interrupt so urce settings are
made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a
message, the id entifier must b e set in advance in the messag e control (MCx[1]–MCx[8]) for the
receiving mailbox. When a message is received, all the bits in the receive message identifier are
compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox
0 (MC0[x], MD0[x]) has a local acceptance filter mask (LAFM) that allows Don ’t care settin gs to
be made.
• CPU interrupt source settings
When transmitting, transmission acknowledge and transmission abort acknowledge interrupts
can be mask ed fo r individual mailboxes in the mailbox interr upt mask register (MBIMR) .
When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt
register (IRR) interrupts can be masked in the interrupt mask register (IMR).
• Arbitration f ield setting
In the arbitration f ield, the identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) of the
message to be received is set. If all the bits in the set identifier do not match, the message is not
stored in a m ailbox.
Example: Mailbox 1 010_1010_1010 (standard identifier)
Only one kind of message identifier can be received by MB1
Identifier 1: 010_1010_1010
• Local acceptance filter mask (LAFM) setting
The local acceptance filter mask is provided for mailbox 0 (MC0[x], MD0[x]) only, enabling a
Don’t care specification to be made for all bits in the received identifier. This allows various
kinds of messages to be received.
Example: Mailbox 0 010_1010_1010 (standard identifier)
LAFM 000_0000_0011 (0: Care, 1: Don’t care)
A total of four kinds of message identifiers can be received by MB0
Identifier 1: 010_1010_1000
Identifier 2: 010_1010_1001
Identifier 3: 010_1010_1010
Identifier 4: 010_1010_1011
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Message Reception and Interrupts:
• Message reception CRC check
When a message is received, a CRC check is performed au to matically (by hardware). If the
result of the CRC check is no r mal, ACK is transmitted in the ACK field irr e spective of
whether or not the message can be received.
• Data frame reception
If the received message is confirmed to be error-free by the CRC check, etc., the identifier in
the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive
message are com pared, and if a complete match is found, the m essage is stored in th e mailbox.
The message identifier comparison is carried out on each mailbox in turn, starting with
mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at
that point, the message is stored in the matching mailbox, and the corresponding receive
complete bit (RXPR0–RXPR15) is set in the receive complete register (RXPR). However,
when a mailbox 0 LAFM comparison is carried out, even if the iden tif ier match es, the mailbox
comparison sequ ence does not end at that point, but continues with mailbox 1 and then the
remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received
by another mailbox (however, the same message cannot be stored in mo re than one of
mailboxes 1 to 15). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox interrupt
mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask
register (IMR) ar e set to the interrupt enable value at this time, an interrupt can be sent to the
CPU.
• Remote frame reception
Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A
remote frame differs from a data frame in that th e remo te reception request bit (RTR) in the
message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned
in a data frame must be stored in the data length code (DLC) in the control field.
When a remote frame (RTR = recessive) is received, the co rresponding bit is set in the remote
request wait register (RFPR). If the corresponding bit (MBIMR0–MBIMR15) in the m a ilbox
interrupt mask register (M BIMR) and the remote frame request interr upt mask (IRR2) in the
interrupt m a sk register (IMR) are set to the interrupt enable value at this time, an interrupt can
be sent to the CPU.
• Unread message reception
When the identifier in a mailbox matches a receive message, the message is stored in the
mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding
bit (UMSR0 –UMSR15) is set in the u nread message r egister (UMSR). In ove r writing of an
unread message, when a new message is received before the corresponding bit in the receive
complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the
Section 15 Controller Area Network (HCAN)
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unread interrupt f lag (IRR9 ) in the interrup t m a sk register (IMR) is set to the interrupt enable
value at this time, an interrupt can be sent to the CPU. Figure 15.10 shows a flowchart of
unread message overwriting.
UMSR = 1
IRR9 = 1
Unread message overwrite
IMR9 = 1?
End
Yes
Interrupt to CPU
Clear IRR9
Message control/message data read
No
: Settings by user
: Processing by hardware
Figure 15.10 Unread Message Overwrite Flowchart
15.3.5 HCAN Sleep Mode
The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep
state to reduce curr ent dissipation. Figure 15.11 shows a flowchart of the HCAN sleep mode.
Section 15 Controller Area Network (HCAN)
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MCR5 = 1
Bus operation?
IRR12 = 1
Initialize TEC and REC
IMR12 = 1?
Sleep mode clearing method
MCR7 = 0?
MCR5 = 0
CAN bus communication possible
CPU interrupt
MCR5=0
Clear sleep mode?
Yes
Yes
No
Yes
No
Yes (manual)
No (automatic)
No
Yes
Yes
No
: Settings by user
: Processing by hardware
11 recessive bits?
No
Bus idle?
Figure 15.11 HCAN Sleep Mode Flowchart
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HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is
delayed until the bus becomes idle.
Either of the following methods of clearing HCAN sleep mode can be selected by making a setting
in the MCR7 b it.
1. Clearing by software
2. Clearing by CAN bus operation
Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus
communication is enabled again.
Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the
CAN bus performs an operation and this change is detected. In this case, the first message is not
received in the mailbox, and normal reception starts from the next message. When a change is
detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in
the interru pt register (IRR). If the bus interrupt mask (IMR12) in the inter rup t mask register (IMR)
is set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
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15.3.6 HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 15.12 shows a flowchart of the HCAN halt mode.
MCR1 = 1
Bus idle?
CAN bus communication possible
No
MBCR setting
MCR1 = 0
Yes
: Settings by user
: Processing by hardware
Figure 15.12 HCAN Halt Mode Flowchart
HCAN halt mod e is entered by setting the halt request bit ( M CR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes id le.
HCAN halt mode is cleared by clearing MCR1 to 0.
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15.3.7 Interrupt Interface
There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned.
Table 15.5 lists the HCAN interrupt sources.
With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is
implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register
(IMR).
Table 15.5 HCAN Interrupt Sources
IPR Bits Vector Vector
Number IRR Bit Description
IPRM (6–4) ERS0 104 IRR5 Error passive interrupt (TEC ≥ 128 or REC ≥
128)
IRR6 Bus off interrupt (TEC ≥ 256)
OVR0 105 IRR0 Hardware reset processing interrupt
IRR2 Remote frame reception interrupt
IRR3 Error warning interrupt (TEC ≥ 96)
IRR4 Error warning interrupt (REC ≥ 96)
IRR7 Overload frame transmission interrupt/bus off
recovery interrupt (11 recessive bits × 128 times)
IRR9 Unread message overwrite interrupt
IRR12 HCAN sleep mode CAN bus operation interrupt
RM0 106 IRR1 Mailbox 0 message reception interrupt
RM1 107 IRR1 Mailbox 1–15 message reception interrupt
IPRM (2–0) SLE0 108 IRR8 Message transmission/cancellation interrupt
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15.3.8 DTC Interface
The DTC can be activated by reception of a message in the HCAN’s mailbox 0. When DTC
transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge
signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent
to the CPU in this case. Figure 15.13 shows a DTC transfer flowchart.
DTC enable register setting
DTC register information setting
End of DTC transfer?
End
No
DTC initialization
Message reception in HCAN’s
mailbox 0
DTC activation
Transfer counter = 0
or DISEL = 1? No
Interrupt to CPU
Yes
Yes
: Settings by user
: Processing by hardware
RXPR and RFPR clearing
Figure 15.13 DTC Transfer Flowchart
Section 15 Controller Area Network (HCAN)
Rev. 5.00 Jan 10, 2006 page 585 of 1042
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15.4 CAN Bus Interface
A bus transceiver IC is necessary to connect the H8S/2626 Group or H8S/2623 Group chip to a
CAN bus. A Philips PCA82C250 transceiver IC, or compatible device, is recommended. Figure
15.14 shows a sample conn ection diagram.
RS
RxD
TxD
Vref
Vcc
CANH
CANL
GND
HRxD
HTxD
H8S/2626 Group or
H8S/2623 Group
CAN bus
124 Ω
124 Ω
Vcc
PCA82C250
No connection
Figure 15.14 High-Speed Interface Using PCA82C250
15.5 Usage Notes
1. Reset
The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All
the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data
(MDx[x]) are not. However, after powering on, mailboxes (message control
(MCx[x]) /m essage data (MDx[x]) are initialized, and th eir values are undefined. Therefore,
mailbox initialization must always be carried out after a reset or a transition to hardware
standby mode or software standby mode. Also, the reset interrupt flag (IRR0) is always set
after reset input or recovery from software standby mode. As this bit cannot be masked in the
interrup t m ask register (IMR), if HCAN interrupts are set as enabled by the interrupt contro ller
without this flag having been cleared, an HCAN interrupt will be initiated immediately. IRR0
must therefore be cleared during initialization.
2. HCAN sleep mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation
in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode
Section 15 Controller Area Network (HCAN)
Rev. 5.00 Jan 10, 2006 page 586 of 1042
REJ09B0275-0500
release. Also note that the reset status bit ( GSR3) in the ge neral status register (GSR) is set in
sleep mode.
3. Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8.2.1) is
not set by reception completion, transmission completion, or transmission cancellation for the
set mailboxes.
4. Error counters
In the case of error active and erro r passive, REC and TEC normally count up and down. In the
bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set.
5. Register access
Byte or word access can be used on all HCAN registers. Longword access cannot be used.
6. HCAN medium-speed mode
HCAN registers cannot be read or written to in medium-speed mode.
7. Register retention during standby
All HCAN register s ar e initialized in hardware standby mode and software standby mode .
8. Using bit operation instructions
Start flags in HCAN are cleared by writing 1 to them; there is no need to use bit operation
instructions to clear th em. To clear a flag, use the MOV instruction to write a 1 to the bit to b e
cleared.
9. HTxD pin output in error passive state
If the HRxD pin becomes fixed at 1 during message transmission or reception when the HCAN
is in the error active state, the HTxD pin will outpu t 0 continuously while in the error passive
state. To stop continuous 0 output to the CAN bus, disable the HCAN by means of an error
warning interrupt or by setting the HCAN module stop mode th rough detection of a fixed 1
state by the HxRD pin monitor.
10.Transition to HCAN sleep mode
The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0 immediately after
an HCAN sleep mod e tr ansition effected by settin g TXPR of the HCAN to 1 and setting
MCR5 to 1. When a transition is made to the HCAN sleep mode by means of the above steps,
a 10-cycle wait should be inserted after the TxPR setting. After an HCAN sleep mode
transition, release the HCAN sleep mode by clearing MCR5 to 0.
Section 15 Controller Area Network (HCAN)
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11.Message transmission cancellation (TxCR)
If all the following conditions are met when cancellation of a transmission message is
performed by m eans of TxCR of the HCAN, th e Tx CR or TxPR bit indicating cancellation is
not cleared even though internal transmission is canceled.
When canceling a message using TxCR, 1 should be written continuously until TxCR or TxPR
becomes 0.
12.TxCR in the bus off state
If TxPR is set before the HCAN goes to the bus off state, and a transition is made to the bus off
state with transmission incom plete, cancellation will be per for m ed ev en if Tx CR is set during
the bus off per iod, and th e m e ssage will be transmitted after a transition to the error active
state.
Section 15 Controller Area Network (HCAN)
Rev. 5.00 Jan 10, 2006 page 588 of 1042
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Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 589 of 1042
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Section 16 A/D Converter
16.1 Overview
The H8S/2626 Group and H8S/2623 Group include a successive approximation type 10-bit A/D
converter that allows up to sixteen analog input channels to be selected.
16.1.1 Features
A/D converter features are listed below.
• 10-b it resolution
• Sixteen input channels
• Settable analog conversion voltage range
Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference
voltage
• High-speed conversion
Minimum conversion time: 13.3 µs per channel (at 20-MHz operation)
• Choice of single mode or scan mode
Single mode: Single-channel A/D conversion
Scan mode: Continuous A/D conversion on 1 to 4 channels
• Four data registers
Conversion results are held in a 16-bit data register for each channel
• Sample and hold fun c tion
• Three kinds of conversion start
Choice of software or timer conversion start trigger (TPU), or ADTRG pin
• A/D conversion end interrupt generation
A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion
• Module stop mode can be set
As the initial setting, A/D converter operation is halted. Register access is enabled by
exiting module stop mode.
Section 16 A/D Converter
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16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the A/D converter.
Module data bus
Control circuit
Internal data bus
10-bit D/A
Comparator
+
–
Sample-and-
hold circuit
φ/2
φ/4
φ/8
ADI
interrupt
φ/16
Bus interface
A
D
C
S
R
A
D
C
R
A
D
D
R
D
A
D
D
R
C
A
D
D
R
B
A
D
D
R
A
AVCC
Vref
AVSS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
ADTRG Conversion start
trigger from TPU
Successive approximations
register
Multiplexer
ADCR
ADCSR
ADDRA
ADDRB
ADDRC
ADDRD
: A/D control register
: A/D control/status register
: A/D data register A
: A/D data register B
: A/D data register C
: A/D data register D
Figure 16.1 Block Diagram of A/D Converter
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 591 of 1042
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16.1.3 Pin Configuration
Table 16.1 summarizes the input pins used by the A/D converter.
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter.
The Vref pin is the A/D conversion reference voltage pin.
The 16 analog input pins are divided into two channel sets and two groups, with analog input pins
0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 15 (AN8 to AN15)
comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11)
comprising group 0, and analog input pins 4 to 7 and 12 to 15 (AN4 to AN7, AN12 to AN15)
comprising group 1.
Table 16.1 A/D Converter Pins
Pin Name Symbol I/O Function
Analog power supply pin AVCC Input Analog block power supply
Analog ground pin AVSS Input Analog block ground and reference voltage
Reference voltage pin Vref Input A/D conversion reference voltage
Analog input pin 0 AN0 Input Channel set 0 (CH3 = 0) group 0 analog inputs
Analog input pin 1 AN1 Input
Analog input pin 2 AN2 Input
Analog input pin 3 AN3 Input
Analog input pin 4 AN4 Input Channel set 0 (CH3 = 0) group 1 analog inputs
Analog input pin 5 AN5 Input
Analog input pin 6 AN6 Input
Analog input pin 7 AN7 Input
Analog input pin 8 AN8 Input Channel set 1 (CH3 = 1) group 0 analog inputs
Analog input pin 9 AN9 Input
Analog input pi n 10 AN10 Input
Analog input pi n 11 AN11 Input
Analog input pin 12 AN12 Input Channel set 1 (CH3 = 1) group 1 analog inputs
Analog input pi n 13 AN13 Input
Analog input pi n 14 AN14 Input
Analog input pi n 15 AN15 Input
A/D external trigger input
pin ADTRG Input External trigger input for starting A/D conversion
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 592 of 1042
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16.1.4 Register Configuration
Table 16.2 summarizes the registers of the A/D conv erter.
Table 16.2 A/D Converter Registers
Name Abbreviation R/W Initial Value Address*1
A/D data register AH ADDRAH R H'00 H'FF90
A/D data register AL ADDRAL R H'00 H'FF91
A/D data register BH ADDRBH R H'00 H'FF92
A/D data register BL ADDRBL R H'00 H'FF93
A/D data register CH ADDRCH R H'00 H'FF94
A/D data register CL ADDRCL R H'00 H'FF95
A/D data register DH ADDRDH R H'00 H'FF96
A/D data register DL ADDRDL R H'00 H'FF97
A/D control/status register ADCSR R/(W)*2H'00 H'FF98
A/D control register ADCR R/W H'33 H'FF99
Module stop control register A MSTPCRA R/W H'3F H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Bit 7 can only be written with 0 for flag clearing.
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 593 of 1042
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16.2 Register Descriptions
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
15
AD9
0
R
Bit
Initial value
R/W
:
:
:
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
—
0
R
4
—
0
R
3
—
0
R
2
—
0
R
1
—
0
R
0
—
0
R
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to sto r e the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are tran sferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in
table 16.3.
ADDR can always be read by the CPU. The upper by te can be read directly, but for the lower
byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3,
Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop
mode.
Table 16.3 Analo g Input Channels a nd Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1)
Group 0 Group 1 Group 0 Group 1 A/D Data Register
AN0 AN4 AN8 AN12 ADDRA
AN1 AN5 AN9 AN13 ADDRB
AN2 AN6 AN10 AN14 ADDRC
AN3 AN7 AN11 AN15 ADDRD
Section 16 A/D Converter
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16.2.2 A/D Control/Status Register (ADCSR)
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CH3
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Bit
Initial value
R/W
:
:
:
Note: * Only 0 can be written to bit 7, to clear this flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.
ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module sto p mode.
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing cond iti ons ] (Initial value)
• When 0 is written to the ADF flag after reading ADF = 1
• When the DTC is activated by an ADI interrupt and ADDR is read
1 [Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE Description
0 A/D conversion end interrupt (ADI) request disabled (Initial value)
1 A/D conversion end interrupt (ADI) request enabled
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 595 of 1042
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Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1
during A/D conversion.
The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external
trigger input pin (ADTRG).
Bit 5
ADST Description
0• A/D conversion stopped (Initial value)
1• Single mode: A/D conversion is started. Cleared to 0 automatically when
conversion on the specified channel ends
• Scan mode: A/D conversion is started. Conversion continues sequentially on the
selected channels until ADST is cleared to 0 by software, a rese t, or
a transition to standby mode or module stop mode.
Bit 4—Scan Mo de (SCAN): Selects single mode or scan mode as the A/D conversion operating
mode. See section 16 .4, Operation, for single mode and scan mode operation. Only set the SCAN
bit while conversion is stopped (ADST = 0).
Bit 4
SCAN Description
0 Single mode (Initial value)
1 Scan mode
Bit 3—Channel Select 3 (CH3): Switches the analog input pins assigned to group 0 or group 1.
Setting CH3 to 1 enables AN8 to AN15 to b e used instead of AN0 to AN7.
Bit 3
CH3 Description
0 AN8 to AN11 are group 0 analog input pins, AN12 to AN15 are group 1 analog input
pins
1 AN0 to AN3 are group 0 analog input pins , AN4 to AN7 are group 1 analog input pins
(Initial value)
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 596 of 1042
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Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, th ese bits select
the analog input channels.
Only set the input channel while conversion is stopped (ADST = 0).
Channel Selection Description
CH3 CH2 CH1 CH0 Single Mode
(SCAN = 0) Scan Mode
(SCAN = 1)
0000 AN0 (Initial value)AN0
1 AN1 AN0, AN1
1 0 AN2 AN0 to AN2
1 AN3 AN0 to AN3
100 AN4 AN4
1 AN5 AN4, AN5
1 0 AN6 AN4 to AN6
1 AN7 AN4 to AN7
1000 AN8 AN8
1 AN9 AN8, AN9
1 0 AN10 AN8 to AN10
1 AN11 AN8 to AN11
1 0 0 AN12 AN12
1 AN13 AN12, AN13
1 0 AN14 AN12 to AN14
1 AN15 AN12 to AN15
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 597 of 1042
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16.2.3 A/D Co ntrol Register (ADCR)
7
TRGS1
0
R/W
6
TRGS0
0
R/W
5
—
1
—
4
—
1
—
3
CKS1
0
R/W
0
—
1
—
2
CKS0
0
R/W
1
—
1
—
Bit
Initial value
R/W
:
:
:
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations and sets the A/D conversion time.
ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of
the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion
is stopped (ADST = 0).
Bit 7 Bit 6
TRGS1 TRGS0 Description
0 0 A/D conversion start by software is enabled (Initial value)
1 A/D conversion start by TPU conversion start trigger is enabled
1 0 Setting prohibited
1 A/D conversion start by external trigger pin (ADTRG) is enabled
Bits 5, 4, 1, and 0—Reserved: These bits are always read as 1 and cannot be modified.
Bits 3 and 2—Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time.
The conversion time should be changed only when ADST = 0. Make a setting that gives a value
not lower than that shown in table 22-8.
Bit 3 Bit 2
CKS1 CKS0 Description
0 0 Conversion time = 530 states (max.) (Initial value)
1 Conversion time = 266 states (max.)
1 0 Conversion time = 134 states (max.)
1 Conversion time = 68 states (max.)
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 598 of 1042
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16.2.4 Module Sto p Co ntro l Register A (MSTPCRA)
7
MSTPA7
0
R/W
6
MSTPA6
0
R/W
5
MSTPA5
1
R/W
4
MSTPA4
1
R/W
3
MSTPA3
1
R/W
0
MSTPA0
1
R/W
2
MSTPA2
1
R/W
1
MSTPA1
1
R/W
Bit
Initial value
R/W
:
:
:
MSTPCR is a 8-bit readable/writable register that performs module stop mode control.
When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. Registers cannot be read or written to in
module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a reset an d in hardware standby mode. It is not initialized in
software standby mode.
Bit 1—Module Stop (MSTPA1): Specifies the A/D converter module stop mode.
Bit 1
MSTPA1 Description
0 A/D converter module stop mode cleared
1 A/D converter module stop mode set (Initial value)
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 599 of 1042
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16.3 Interface to Bus Master
ADDRA to ADDRD are 16-b it registers, and the data bus to the bus master is 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data read from ADDR is performed as follows. When the upper byte is read, the upper byte
value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADDR. always read the upper byte before the lower byte. It is possible to read only
the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 16.2 shows the data flow for ADDR access.
Bus master
(H'AA)
ADDRnH
(H'AA) ADDRnL
(H'40)
Lower byte read
ADDRnH
(H'AA) ADDRnL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
(n = A to D)
(n = A to D)
Module data bus
Module data bus
Bus interface
Upper byte read
Bus master
(H'40) Bus interface
Figure 16.2 ADDR Access Operation (Reading H'AA40)
Section 16 A/D Converter
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16.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode.
16.4.1 Single Mode (SCAN = 0)
Single mode is selected when A/D conversion is to be performed on a single channel only. A/D
conversion is started when the ADST bit is set to 1, according to the software or external trigger
input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0
when conversion ends.
On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an
ADI interrup t r equest is generated. The ADF flag is clear ed by writing 0 after reading ADCSR.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST
bit can be set at the same time as the operating mode or input channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure
16.3 shows a timing diagram for this example.
[1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH3 = 0, CH2 = 0,
CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started
(ADST = 1).
[2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the
ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
[3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
[4] The A/D interr upt handling ro utine star ts.
[5] The rou tine reads ADCSR, then writes 0 to the ADF flag.
[6] The routine reads and processes the connection resu lt (ADDRB).
[7] Execution of th e A/D in terrupt handling routin e ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps [2] to [7] are repeated.
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 601 of 1042
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ADIE
ADST
ADF
State of channel 0 (AN0)
A/D
conversion
starts
2
1
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1 (AN1)
State of channel 2 (AN2)
State of channel 3 (AN3)
Note:
*
Vertical arrows ( ) indicate instructions executed by software.
Set
*
Set
*
Clear
*
Clear
*
A/D conversion result 1
A/D conversion
A/D conversion result 2
Read conversion result
Read conversion result
Idle
Idle
Idle
Idle
Idle Idle
A/D conversion
Set
*
Figure 16.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Section 16 A/D Converter
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16.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the
first channel in the group (AN0). When two or more channels are selected, after conversion of the
first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion
continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversio n
results are transferred for storage into the ADDR registers corresponding to the channels.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first
channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel
is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 16.4 shows a timing diagram for this example.
[1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is
selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and
A/D conversion is started (ADST = 1)
[2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
[3] Conversion proceeds in the same way through the third channel (AN2).
[4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
to 1 and conversion of the first channel (AN0) starts again . I f the ADI E bit is set to 1 at this
time, an ADI interrupt is requested after A/D conversion ends.
[5] Steps [2] to [4] are repeated as long as the ADST bit rem ains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
Section 16 A/D Converter
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ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 0 (AN0)
State of channel 1 (AN1)
State of channel 2 (AN2)
State of channel 3 (AN3)
Set*
1
Clear*
1
Idle
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
Clear*
1
Idle
Idle
A/D conversion time
Idle
Continuous A/D conversion execution
A/D conversion 1
Idle
Idle
Idle
Idle
Idle
Transfer
*
2
A/D conversion 3
A/D conversion 2 A/D conversion 5
A/D conversion 4
A/D conversion result 1
A/D conversion result 2
A/D conversion result 3
A/D conversion result 4
Figure 16.4 Example of A/D Converter Operation
(Scan Mode, 3 Channels AN0 to AN2 Selected)
Section 16 A/D Converter
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16.4.3 Input Sampling and A/D Co nversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16.5 shows the A/D
conversion timing. Table 16.4 indicates the A/D conversion time.
As indicated in figure 16.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 16.4.
In scan mode, the values given in table 16.4 apply to the first conversion time. The values given
in table 16.5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and
CKS0 in ADCR to give a value not lo wer than that shown in table 22-8 .
(1)
(2)
tDtSPL tCONV
φ
Input sampling
timing
ADF
Address
Write signal
Legend:
(1) : ADCSR write cycle
(2) : ADCSR address
tD : A/D conversion start delay
tSPL : Input sampling time
tCONV : A/D conversion time
Figure 16.5 A/D Conversion Timing
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 605 of 1042
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Table 16.4 A/D Conversion Time (Single Mode)
CKS1 = 0 CKS1 = 0
CKS0 = 0 CKS0 = 1 CKS 0 = 0 CKS0 = 1Item Symbol
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
A/D conversion start
delay tD18 —33 10 —17 6 —94— 5
Input sampling time tSPL —127 ——63 ——31 ——15 —
A/D conversion time tCONV 515 —530 259 —266 131 —134 67 —68
Note: Values in the table are the number of states.
Table 16.5 A/D Conversion Time (Scan Mode)
CKS1 CKS0 Conversion Time (State)
0 0 512 (Fixed)
1 256 (Fixed)
1 0 128 (Fixed)
1 64 (Fixed)
16.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit has been set to 1 by software. Figure 16.6 shows the
timing.
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 606 of 1042
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φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 16.6 External Trigger Input Timing
16.5 Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR.
The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in
response to an ADI interrupt enables continuous conversion to be achieved without imposing a
load on software.
The A/D converter interrupt source is shown in table 16.6.
Table 16.6 A/D Converter Interrupt Source
Interrupt Source Description DTC Activation
ADI Interrupt due to end of conversion Possible
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 607 of 1042
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16.6 Usage Notes
The following points should be noted when using the A/D converter.
Setting Rang e of Analog Power Supply and Other P ins:
(1) Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVSS ≤ ANn ≤ Vref.
(2) Relation between AVCC, AVSS and VCC, VSS
As the relationship b etween AVCC, AVSS and VCC, VSS, set AVSS = VS S. If the A/D
converter is not used, the AVCC and AVSS pins must on no account be left open.
(3) Vref input range
The analog reference voltage input at the Vref pin set in the range Vref ≤ AVCC.
If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely
affected.
Notes on Board Design: In board design, digital circuitry and analog circuitry should be as
mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit
signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so
may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D
conversion values.
Also, digital circu itry must be isolated from the analog input sign als ( AN0 to AN15), analog
reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS).
Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS)
on the board.
Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an
abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) and analog
reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure
16.7.
Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to
AN0 to AN15 must be connected to AVSS.
If a filter capacitor is connected as shown in figure 16.7, the input currents at the analog input pins
(AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed
frequently, as in scan mode, if the current charged and discharged by the capacitance of the
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 608 of 1042
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sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance
(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required
when deciding the circuit constants.
AVCC
*1*1
Vref
AN0 to AN15
AVSS
Notes: Values are reference values.
1.
2. Rin: Input impedance
Rin*2100 Ω
0.1 µF
0.01 µF10 µF
Figure 16.7 Example o f Analog Input Pr otection Circuit
Table 16.7 Analog Pin Specificat ions
Item Min Max Unit
Analog input capacitance —20 pF
Permissible signal source impedance —5kΩ
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 609 of 1042
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20 pF
To A/D converterAN0 to AN15 10 kΩ
Note: Values are reference values.
Figure 16.8 Analog Input Pin Equiva lent Circuit
A/D Conversion Precision Definitions: H8S/2626 Group and H8S/2623 Group A/D conversion
precision d e f in itions are given below.
• Resolution
The number of A/D converter digital output codes
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'00) to
B'0000000001 (H'01) (see figure 16.10).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see
figure 16.10).
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.9).
• Nonlinearity er ror
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not includ e the offset error, full-scale error, or quantization error.
• Absolute pr ecision
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
Section 16 A/D Converter
Rev. 5.00 Jan 10, 2006 page 610 of 1042
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111
110
101
100
011
010
001
000 FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
1
1024 2
1024 1022
1024 1023
1024
Figure 16.9 A/D Conversion Precision Definitions (1)
FS
Offset error
Nonlinearity
error
Actual A/D conversion
characteristic
Analog
input voltage
Digital output
Ideal A/D conversion
characteristic
Full-scale error
Figure 16.10 A/D Conversion Precision Definitions (2)
Section 16 A/D Converter
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Permissible Signal Source Impedance: H8S/2626 Group and H8S/2623 Group analog input is
designed so that conversion precision is guaranteed for an input signal for which the signal source
impedance is 10 kΩ or less. This specification is provided to enable the A/D conv e r ter ’s sample-
and-hold circ u it input capacitance to be charged within th e sam pling time; if the sensor outp ut
impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee
the A/D conversion precision.
However, if a large cap acitance is provided externally, the in put load will essentially compr ise
only the in ternal input resistance of 10 kΩ, and the signal source impedance is ignored.
However, sin ce a low-pass filter effect is ob tained in this case, it may not be possible to follow an
analog signal with a large differential coefficient (e.g., 5 mV/µs or greater).
When converting a high-speed analog signal, a low-impedance buffer should be inserted.
Influences on Absolute Precision: Adding capacitance results in coupling with GND, and
therefore noise in GND may adversely affect absolute precision. Be sure to make the connection
to an electrically stable GND su ch as AVSS.
Care is also required to in sure that filter circuits d o not communicate with digital signals on th e
mounting board, so acting as antennas.
A/D converter
equivalent circuit
H8S/2626 Group or
H8S/2623 Group
20 pF
Cin =
15 pF
10 kΩ
to 5 kΩ
Low-pass
filter C
to 0.1 µF
Sensor output
impedance
Sensor input
Figure 16.11 Example of Ana log Input Circuit
Section 16 A/D Converter
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Section 17 D/A Converter [Provided in the H8S/2626 Group only]
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Section 17 D/A Converter
[Provided in th e H8S/2626 Group only]
17.1 Overview
The H8S/2626 Group has an on-chip two-channel D/A converter.
17.1.1 Features
The D/A converter has the following features.
• 8-bit re solution
• Two output channels
• Conversion time: maximum 10 µs (with 20 pF capacitive load)
• Output voltage: 0 V to Vref
• D/A output retention in software standby mode
• Module stop mode setting possible
The initial setting is for D/A converter operation to be halted. Register access is enabled by
clearing module stop mode.
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
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17.1.2 Block Diagram
Figure 17.1 shows a block diagram of the D/A converter.
Module data bus Internal data bus
Vref
AVCC
DA3
DA2
AVSS
8-bit D/A
Control circuit
DADR2
Legend:
DACR23: D/A control register 23
DADR2, DADR3: D/A data registers 2 and 3
Bus interface
DADR3
DACR23
Figure 17.1 Block Diagram of D/A Converter
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
Rev. 5.00 Jan 10, 2006 page 615 of 1042
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17.1.3 Pin Configuration
Table 17.1 summarizes the input and output pins used by the D/A converter.
Table 17.1 D/A Converter Pins
Pin Name Symbol I/O Function
Analog power supply pin AVCC Input Analog power supply
Analog ground pin AVSS Input Analog ground and reference voltage
Analog output pin 2 DA2 Output Channel 2 analog output
Analog output pin 3 DA3 Output Channel 3 analog output
Reference volt age pin Vref Input Analog reference volt age
17.1.4 Register Configuration
Table 17.2 summarizes the registers of the D/A conv erter.
Table 17.2 D/A Converter Registers
Channel Name Abbreviation R/W Initial Value Address*
2, 3 D/A data register 2 DADR2 R/W H'00 H'FDAC
D/A data register 3 DADR3 R/W H'00 H'FDAD
D/A control register 23 DACR23 R/W H'1F H'FDAE
All Module stop control register C MSTPCRC R/W H'FF H'FDEA
Note: *Lower 16 bits of the address
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
Rev. 5.00 Jan 10, 2006 page 616 of 1042
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17.2 Register Descriptions
17.2.1 D/A Da ta Registers 2 and 3 (DADR2, DADR3 )
Bit:76543210
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DADR2 and DADR3 are 8-bit readable/writable registers that store the data to be conv erted.
When analog output is enabled, the values in DADR2 and DADR3 are constantly converted and
output at the analog output pins.
The D/A data registers are initialized to H'00 by a reset and in hardware standby mode.
17.2.2 D/A Co ntrol Register 23 (DACR23)
Bit:76543210
DAOE1DAOE0DAE—————
Initial value:00011111
R/W:R/WR/WR/W—————
DACR23 is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR23 is initialized to H'1F by a re set and in hardware standby mode.
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7
DAOE1 Description
0 DA3 analog output is disabled (Initial value)
1 Channel 3 D/A conversion and DA3 analog output are enabled
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
Rev. 5.00 Jan 10, 2006 page 617 of 1042
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Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6
DAOE0 Description
0 DA2 analog output is disabled (Initial value)
1 Channel 2 D/A conversion and DA2 analog output are enabled
Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.
When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 2 and 3.
When the DAE bit is set to 1, D/A conversion is controlled together in channels 2 and 3.
Output of the conversion result is always controlled independently by bits DAOE0 and DAOE1.
Bit 7 Bit 6 Bit 5
DAOE1 DAOE0 DAE Description
00*D/A conversion is disabled in channels 2 and 3 (Initial value)
1 0 D/A conversion is enabled in channel 2
D/A conversion is disabled in channel 3
1 D/A conversion is enabled in channels 2 and 3
0 0 0 D/A conversion is disabled in channel 2
D/A conversion is enabled in channel 3
1 D/A conversion is enabled in channels 2 and 3
1*D/A conversion is enabled in channels 2 and 3
*: Don’t care
If the chip enters software standby mode while D/A conversion is enabled, the D/A output is
retained and the analog power supply current is the same as the analog power supply current
during D/A conversion. If it is necessary to reduce the analog power supply current in software
standby mode, D/A output should be disabled by clearing both the DAOE0 bit and the DAOE1 bit
to 0.
Bits 4 to 0—Reserved: These bits are always read as 1, and cannot be modified.
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
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17.2.3 Module Sto p Co ntro l Register C (MSTPCRC)
Bit:76543210
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value:11111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC5 bit is set to 1, D/A converter operation is stopped at the end of the bus cycle,
and module stop mode is entered. Register read/write accesses are not possible in module stop
mode. For details, see section 21B.5, Module Stop Mode.
MSTPCRC is initialized to H'FF by a reset and in hardware standby m ode. I t is not initialized in
software standby mode.
Bit 5—Module Stop (MSTPC5): Specifies module stop mode for the D/A converter (channels 2
and 3).
Bit 5
MSTPC5 Description
0 D/A converter (channels 2 and 3) module stop mode is cleared
1 D/A converter (channels 2 and 3) module stop mode is set (Initial value)
17.3 Operation
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR23. If the DADR2 or DADR3
value is modified, conversion of the new data begins immediately. The conversion results are
output when bits DAOE0 and DAOE1 are set to 1.
An example of D/A conversion on channel 2 is given below. The timing is shown in figure 17.2.
1. Data to be co nverted is written in DADR2.
2. Bit DAOE0 is set to 1 in DACR23. D/A conversion starts and DA2 becomes an output pin.
The conversion result is output after the conversion time. The output value is (DADR2
contents/256) × Vref. Output of this conversion result contin ues until the value in DADR2 is
modified or the DAOE0 bit is cleared to 0 .
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
Rev. 5.00 Jan 10, 2006 page 619 of 1042
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3. If the DADR2 value is modified, conversion starts immediately, and the result is ou tp ut after
the conversion time.
4. When the DAOE0 b it is cleared to 0, DA2 becomes an input pin.
Conversion data 1
Conversion
result 1
High-impedance state
tDCONV
DADR2
write cycle
DA2
DAOE0
DADR2
Address
φ
DACR23
write cycle
Conversion data 2
Conversion
result 2
tDCONV
Legend:
tDCONV: D/A conversion time
DADR2
write cycle DACR23
write cycle
Figure 17.2 Example of D/A Converter Operation
Section 17 D/A Converter [Provided in the H8S/2626 Group only]
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Section 18 RAM
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Section 18 RAM
18.1 Overview
The H8S/2626 and H8S/2623 have 12 kbytes of on-chip high-speed static RAM, the H8S/2625
and H8S/2622 have 8 kbytes, and the H8S/2624 and H8S/2621 have 4 kbytes. The RAM is
connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data
and word data. This makes it possible to perform fast word data transfer.
The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the
system control register (SYSCR).
18.1.1 Block Diagram
Figure 18.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFC000
H'FFC002
H'FFC004
H'FFFFC0
H'FFC001
H'FFC003
H'FFC005
H'FFFFC1
H'FFFFFE H'FFFFFF
H'FFEFBE H'FFEFBF
Figure 18.1 Block Diagram of RAM (H8S/2623)
Section 18 RAM
Rev. 5.00 Jan 10, 2006 page 622 of 1042
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18.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 18.1 shows th e address and initial value of
SYSCR.
Table 18.1 RAM Register
Name Abbreviation R/W Initial Value Address*
System control register SYSCR R/W H'01 H'FDE5
Note: *Lower 16 bits of the address.
18.2 Register Descriptions
18.2.1 System Control Register (SYSCR)
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
—
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
The on-chip RAM is en abled or disabled by the RAME b it in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RA M Enable ( R AME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in sof twar e stan dby mode.
Note: Whe n the DTC is used, the RAME bit must be set to 1.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
Section 18 RAM
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18.3 Operation
When the RAME bit is set to 1, accesses to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to
H'FFFFFF in the H8S/2626 and H8S/2623, to addresses H'FFD000 to H'FFEFBF and H'FFFFC0
to H'FFFFFF in the H8S/2625 and H8S/2622, and to addresses H'FFE000 to H'FFEFBF and
H'FFFFC0 to H'FFFFFF in the H8S/2624 and H8S/2621, are directed to the on-chip RAM. When
the RAME bit is cleared to 0, the off-chip address space is accessed.
Since the on- chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to
and read in byte or word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
18.4 Usage Notes
When Using the DTC: DTC register information can be lo cated in addresses H'FFEBC0 to
H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0.
Reserved Areas: Addresses H'FFB000 to H'FFBFFF in the H8S/2626 and H8S/2623, H'FFB000
to H'FFCFFF in the H8S/2625 and H8S/2622, and H'FFB000 to H'FFDFFF in the H8S/2624 and
H8S/2621, are reserved areas that cannot be read or written to. When the RAME bit is cleared to
0, external address space is accessed.
Section 18 RAM
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Section 19 ROM (Preliminary)
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Section 19 ROM (Preliminary)
19.1 Features
The H8S/2626 Group and H8S/2623 Group have 256 kbytes of on-chip flash memory. The
features of the flash memory are summarized below.
• Four flash memo ry operating modes
Program mode
Erase mode
Program-verif y mode
Erase-verify mode
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can
be performed. To erase the entire flash memory, each block must be erased in turn. Block
erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks.
• Programm ing/er a se times
The flash memory programming time is 10 ms (typ.) fo r simultaneous 128-byte programming,
equivalent to 78 µs (typ.) per byte, and the erase time is 100 ms (typ.).
• Reprogram ming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
Boot mode
User program mode
• Automatic bit r ate adjustment
With data transf er in boot mode, the LSI’s bit rate can be automatically adjusted to m atch the
transfer bit rate of the host.
• Flash memory emulation in RAM
Flash memory programming can be emulated in real time by overlapping a part of RAM onto
flash memory.
• Protect modes
There are three protect modes, hardware, software, and error protection which allow protected
status to be designated for flash memory program/erase/verify operations.
Section 19 ROM (Preliminary)
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• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
19.2 Overview
19.2.1 Block Diagram
Module bus
Bus interface/controller
Flash memory
(256 kbytes)
Operating
mode
FLMCR2
Internal address bus
Internal data bus (16 bits)
FWE pin
Mode pin
EBR1
EBR2
RAMER
FLPWCR
FLMCR1
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register
Legend:
FLMCR1:
FLMCR2:
EBR1:
EBR2:
RAMER:
FLPWCR:
Figure 19.1 Block Diagram of Flash Memory
Section 19 ROM (Preliminary)
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19.2.2 Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the
microcomputer enters an operating mode as shown in figure 19.2. In user mode, flash memory can
be read but not programmed or erased.
The boot, user program and programmer modes are provided as modes to write and erase the flash
memory.
Boot mode
On-board programming mode
User
program mode
User mode
(on-chip ROM
enabled)
Reset state
Programmer
mode
RES = 0
FWE = 1 FWE = 0
*1
*1
*2
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. RAM emulation possible
2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1
RES = 0
MD1 = 1,
MD2 = 0,
FWE = 1
RES = 0
RES = 0
MD1 = 1,
MD2 = 1,
FWE = 0
MD1 = 1,
MD2 = 1,
FWE = 1
Figure 19.2 Flash Memory State Transitions
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 628 of 1042
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19.2.3 On-Board Programming Modes
Boot Mode
Flash memory
LSI
RAM
Host
Programming control
program
SCI
Application program
(old version)
New application
program
Flash memory
LSI
RAM
Host
SCI
Application program
(old version)
Boot program area
New application
program
Flash memory
LSI
RAM
Host
SCI
Flash memory
preprogramming
erase
Boot program
New application
program
Flash memory
LSI
Program execution state
RAM
Host
SCI
New application
program
Boot program
Programming control
program
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program
in the H8S/2626 or H8S/2623 (originally
incorporated in the chip) is started and the
programming control program in the host is
transferred to RAM via SCI communication. The
boot program required for flash memory erasing
is automatically transferred to the RAM boot
program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Programming control
program
Boot programBoot program
Boot program area Boot program area
Programming control
program
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 629 of 1042
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User Program Mode
Flash memory
LSI
RAM
Host
Programming/
erase control program
SCI
Boot program
New application
program
Flash memory
LSI
RAM
Host
SCI
New application
program
Flash memory
LSI
RAM
Host
SCI
Flash memory
erase
Boot program
New application
program
Flash memory
LSI
Program execution state
RAM
Host
SCI
Boot program
Boot program
FWE assessment
program
Application program
(old version)
New application
program
1. Initial state
The FWE assessment program that confirms that
user program mode has been entered, and the
program that will transfer the programming/erase
control program from flash memory to on-chip
RAM should be written into the flash memory by
the user beforehand. The programming/erase
control program should be prepared in the host or
in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software confirms this fact, executes transfer
program in the flash memory, and transfers the
programming/erase control program to RAM.
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Programming/
erase control program
Programming/
erase control program
Programming/
erase control program
Transfer program
Application program
(old version)
Transfer program
FWE assessment
program
FWE assessment
program
Transfer program
FWE assessment
program
Transfer program
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 630 of 1042
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19.2.4 Flash Memory Emulation in RAM
Emulation should be performed in user mode or user program mode. When the emulation block
set in RAMER is accessed wh ile the emulation function is being executed, data written in the
overlap RAM is read.
Application program
Execution state
Flash memory
Emulation block
RAM
SCI
Overlap RAM
(emulation is performed
on data written in RAM)
Figure 19.3 Reading Overlap RAM Data in User Mode or User Program Mode
When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and
writes should actually be performed to the flash memory.
When the programming control program is transferr e d to RAM, ensure that the transfer destination
and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Section 19 ROM (Preliminary)
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Application program
Flash memory RAM
SCI
Programming control
program execution state
Overlap RAM
(programming data)
Programming data
Figure 19.4 Writing Overlap RAM Data in User Program Mode
19.2.5 Differences between Boot Mode and User Program Mode
Table 19.1 Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode
Total erase Yes Yes
Block erase No Yes
Programming contr ol program *Program/program-verify Erase/erase-verify
Program/program-verify
Emulation
Note: *To be provided by the user, in accordance with the recommended algorithm.
Section 19 ROM (Preliminary)
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19.2.6 Block Configuration
The flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte
blocks.
Address H'00000
Address H'3FFFF
64 kbytes
32 kbytes
64 kbytes
64 kbytes
256 kbytes
4 kbytes × 8
Figure 19.5 Flash Memory Block Configuration
19.3 Pin Configuration
The flash memory is controlled by means of the pins shown in table 19.2.
Table 19.2 Pin Configuratio n
Pin Name Abbreviation I/O Function
Reset RES Input Reset
Flash write enable FWE Input Flash memory program/erase protection by hardware
Mode 2 MD2 Input Sets MCU operating mode
Mode 1 MD1 Input Sets MCU operating mode
Mode 0 MD0 Input Sets MCU operating mode
Port F0 PF0 Input Sets MCU operating mode in programmer mode
Port 16 P16 Input Sets MCU operating mode in programmer mode
Port 14 P14 Input Sets MCU operating mode in programmer mode
Transmit data TxD2 Output Serial transm it data outpu t
Receive data RxD2 Input Serial receive data input
Section 19 ROM (Preliminary)
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19.4 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 19.3.
In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER,
SCRX).
Table 19.3 Register Configuration
Register Name Abbreviation R/W Initial Value Address*1
Flash memory control register 1 FLMCR1*5R/W*2H'00*3H'FFA8
Flash memory control register 2 FLMCR2*5R*2H'00 H'FFA9
Erase block regi ster 1 EBR1*5R/W*2H'00*4H'FFAA
Erase block regi ster 2 EBR2*5R/W*2H'00*4H'FFAB
RAM emulation register RAMER*5R/W H'00 H'FEDB
Flash memory power control register*6FLPWCR*5R/W*2H'00*4H'FFAC
Serial control register X SCRX R/W H'00 H'FDB4
Notes: 1. Lower 16 bits of the address.
2. To access these registers, set the FLSHE bit to 1 in serial control register X. Even if
FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is
disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the
FWE bit in FLMCR1 is not set to 1.
3. When a high level is input to the FWE pin, the initial value is H'80.
4. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in
FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers.
Use byte access on thes e registers.
6. An invalid register in the H8S/2623.
19.5 Register Descriptions
19.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode fo r addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the PV1 or E V1 bit. Program mode for addresses H'00000 to H'3FFFF is
entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting th e
P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the ESU1 bit, and finally settin g the E1 bit. FLMCR1 is initialized by a
reset, and in h ardwar e standby mode and software stan dby mode. Its initial value is H'80 when a
Section 19 ROM (Preliminary)
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high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash
memory is d isabled, a read will return H'00, and writes are invalid.
Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled wh en
FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when
FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 wh en FWE = 1, SWE1 = 1, and PSU1 = 1.
Bit:76543210
FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1
Initial value: —*0000000
R/W: R R/W R/W R/W R/W R/W R/W R/W
Note: *Determined by the state of the FWE pin.
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE Description
0 When a low level is input to the FWE pin (hardware-protected state)
1 When a high level is input to the FWE pin
Bit 6—Software Write Enable Bit 1 (SWE1): This bit selects write and er ase valid/invalid of the
flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2.
Bit 6
SWE1 Description
0 Writes disabled (Initial value)
1 Writes enabled
[Setting condition]
When FWE = 1
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Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Set this bit to 1 before
setting the E1 b it in FLMCR1 to 1. Do not set th e SWE1, PSU1, EV1, PV1, E1, or P1 bit at the
same time.
Bit 5
ESU1 Description
0 Erase setup clear ed (Initial value)
1 Erase setu p
[Setting condition]
When FWE = 1 and SWE1 = 1
Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to prog r am mode . Set this bit to 1
before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit
at the same time.
Bit 4
PSU1 Description
0 Program setup cle ared (Initial val ue)
1 Program setup
[Setting condition]
When FWE = 1 and SWE1 = 1
Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the
SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time.
Bit 3
EV1 Description
0 Erase-verify mode cleared (Initial value)
1 Transition to erase-verify mode
[Setting condition]
When FWE = 1 and SWE1 = 1
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Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set
the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time.
Bit 2
PV1 Description
0 Program-verify mode cleared (Initial value
)
1 Transition to program-verify mode
[Setting condition]
When FWE = 1 and SWE1 = 1
Bit 1—Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1,
PSU1, EV1, PV1, or P1 bit at the same time.
Bit 1
E1 Description
0 Erase mode cleared (Initial value
)
1 Transition to eras e mode
[Setting condition]
When FWE = 1, SWE1 = 1, and ESU1 = 1
Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1,
PSU1, ESU1, EV1, PV1, or E1 bit at the same time.
Bit 0
P1 Description
0 Program mode cle ared (Initial value
)
1 Transition to program mode
[Setting condition]
When FWE = 1, SWE1 = 1, and PSU1 = 1
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19.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is
initialized to H'00 by a reset, and in hardware standby m ode and software standby mode. When
on-chip flash me m ory is disabled, a read will return H'00.
Bit:76543210
FLER———————
Initial value:00000000
R/W:R———————
Note: FLMCR2 is a read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7
FLER Description
0 Flash memory is operating normally (Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing cond iti on]
Reset or hardware stan db y mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 19.8.3, Error Protection
Bits 6 to 0—Reserved: These bits always read 0.
Section 19 ROM (Preliminary)
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19.5.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 comb ined can be set. Do not
set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically
cleared to 0. When o n-ch ip flash m em ory is disabled, a read will return H'00, and writes are
invalid.
The flash memory block configuration is shown in table 19.4.
Bit:76543210
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
19.5.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is not set, even
though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block
can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2
combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and
EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must o nly be written with 0.
When on- chip flash memory is disabled , a read will r eturn H'00, and writes are invalid.
The flash memory block configuration is shown in table 19.4.
Bit:76543210
————EB11EB10EB9EB8
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 639 of 1042
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Table 19.4 Flash Memory Erase Blocks
Block (Size) Addresses
EB0 (4 kbytes) H'000000–H'000FFF
EB1 (4 kbytes) H'001000–H'001FFF
EB2 (4 kbytes) H'002000–H'002FFF
EB3 (4 kbytes) H'003000–H'003FFF
EB4 (4 kbytes) H'004000–H'004FFF
EB5 (4 kbytes) H'005000–H'005FFF
EB6 (4 kbytes) H'006000–H'006FFF
EB7 (4 kbytes) H'007000–H'007FFF
EB8 (32 kbytes) H'008000–H'00FFFF
EB9 (64 kbytes) H'010000–H'01FFFF
EB10 (64 kbytes) H'020000–H'02FFFF
EB11 (64 kbytes) H'030000–H'03FFFF
19.5.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash m emory programming. RAMER initialized to H'00 by a r e set and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 19.5. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bit:76543210
————RAMSRAM2RAM1RAM0
Initial value:00000000
R/W: R R R/W R/W R/W R/W R/W R/W
Bits 7 and 6—Reserved: These bits always read 0.
Bits 5 and 4—Reserved: Only 0 may be written to these bits.
Section 19 ROM (Preliminary)
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Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3
RAMS Description
0 Emulation not selected (Initial value)
Program/erase-protection of all flash memory blocks is disabled
1 Emulation selected
Program/erase-protection of all flash memory blocks is enabled
Bits 2 to 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the
flash memory area to be overlapped with RAM. (See table 19.5.)
Table 19.5 Flash Memory Area Divisions
Addresses Block Name RAMS RAM2 RAM1 RAM0
H'FFD000–H'FFDFFF RAM area 4 kbytes 0 ***
H'000000–H'000FFF EB0 (4 kbytes) 1 0 0 0
H'001000–H'001FFF EB1 (4 kbytes) 1 0 0 1
H'002000–H'002FFF EB2 (4 kbytes) 1 0 1 0
H'003000–H'003FFF EB3 (4 kbytes) 1 0 1 1
H'004000–H'004FFF EB4 (4 kbytes) 1 1 0 0
H'005000–H'005FFF EB5 (4 kbytes) 1 1 0 1
H'006000–H'006FFF EB6 (4 kbytes) 1 1 1 0
H'007000–H'007FFF EB7 (4 kbytes) 1 1 1 1
*: Don't care
Section 19 ROM (Preliminary)
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19.5.6 Flash Memory Power Control Register (FLPWCR)*
Bit:76543210
PDWND———————
Initial value:00000000
R/W:R/WRRRRRRR
FLPWCR enables or disables a transition to the flash memory po wer-down mode when the LSI
switches to sub active mode.
Note: * An invalid register in the H8S/2 623.
Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory
power-down mode when the LSI switches to subactive mode.
Bit 7
PDWND Description
0 Transition to flash memory power-down mode enabled (Initial value)
1 Transition to flash memory power-down mode disabled
Bits 6 to 0—Reserved: These bits always read 0.
19.5.7 Serial Co ntrol Register X (SCRX)
Bit 76543210
————FLSHE———
Initial value00000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W
SCRX is an 8-bit readable/writable r egister th at controls on-ch ip flash memory.
SCRX is initialized to H'00 by a reset an d in hardware standby mode.
Bits 7 to 4—Reserved: Only 0 may be wr itten to these bits.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 642 of 1042
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Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1
enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, th e flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
Bit 3
FLSHE Description
0 Flash control registers deselected in area H'FFFFA8 to H'FFFFAC (Initial value)
1 Flash control registers selected in area H'FFFFA8 to H'FFFFAC
Bits 2 to 0—Reserved: Only 0 may be wr itten to these bits.
19.6 On-Board Programming Modes
When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
19.6. For a diagram of the transitions to the various flash memory modes, see figure 19.2.
Table 19.6 Setting On-Board Programming Modes
Mode FWE MD2 MD1 MD0
Boot mode Expanded mode 1 0 1 0
Single-chip mo de 0 1 1
User program mode Expanded mode 1 1 1 0
Single-chip mo de 1 1 1
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19.6.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI channel to be used is set to asynchronous mode.
When a reset-start is executed after the H8S/2626 or H8S/2623 pins have been set to boot mode,
the boot program built into the LSI is started and the programming control program prepared in
the host is serially transmitted to the LSI via the SCI. In the H8S/2626 and H8S/2623, the
programming control program received via the SCI is written into th e p rog r amming control
program area in on-chip RAM. After the transfer is completed, control branches to th e star t
address of the programming control program area and the programming control program execution
state is entered (flash memory programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 19.6, and the boot mode execution
procedure in figure 19.7.
RxD2
TxD2 SCI2
H8S/2626 or H8S/2623
Flash memory
Write data reception
Verify data transmission
Host
On-chip RAM
Figure 19.6 System Configuration in Boot Mode
Section 19 ROM (Preliminary)
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Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Start
Set pins to boot mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
LSI measures low period
of H'00 data transmitted by host
LSI calculates bit rate and
sets value in bit rate register
After bit rate adjustment, LSI
transmits one H'00 data byte to
host to indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
LSI transmits one H'AA
data byte to host
Host transmits number
of programming control program
bytes (N), upper byte followed
by lower byte
LSI transmits received
number of bytes to host as verify
data (echo-back)
n = 1
Host transmits programming control
program sequentially in byte units
LSI transmits received
programming control program to
host as verify data (echo-back)
Transfer received programming
control program to on-chip RAM
n = N? No
Yes
End of transmission
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
LSI transmits one H'AA data
byte to host
Execute programming control
program transferred to on-chip RAM
n + 1 → n
Figure 19.7 Boot Mode Execution Procedure
Section 19 ROM (Preliminary)
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Automatic SCI Bit Rate Adjustment
Start
bit
Stop
bit
D0 D1 D2 D3 D4 D5 D6 D7
Low period (9 bits) measured (H'00 data) High period
(1 or more bits)
When boot mode is initiated, the LSI measures the low period of the asynchronous SCI
communication data (H'00) transmitted contin uously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no par ity. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the LSI’s system clock frequenc y, there will be
a discrepancy between the bit rates of the host an d the LSI. Set the host transfer bit rate at 2,400,
4,800, 9,600 or 19,200 bps to operate the SCI properly.
Table 19.7 shows host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI bit rate is possible. The boot program should be executed within this system
clock range.
Table 19.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate System Clock Frequency for Which Automatic Adjustment
of LSI Bit Rate is Possible
2,400 bps 2 to 8 MHz
4,800 bps 4 to 16 MHz
9,600 bps 8 to 20 MHz
19,200 bps 16 to 20 MHz
Section 19 ROM (Preliminary)
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On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an
area used by the boot program and an area to which the programming control program is
transferred via the SCI, as shown in figure 19.8. The boot program area cannot be used until the
execution state in boot mode switches to the programming control program transferred from the
host.
H'FFC000
H'FFDFFF
H'FFE000
H'FFEFBF
Boot program area
(4 kbytes)
Programming
control program area
(8 kbytes)
Note: The boot program area cannot be used until a transition is made to the execution state for
the programming control program transferred to RAM. Note also that the boot program
remains in this area of the on-chip RAM even after control branches to the programming
control program.
Figure 19.8 RAM Areas in Boot Mode
Notes on Use of Boot Mode:
• When the chip comes out of reset in boot mode, it m easures the low-level per iod of the input at
the SCI’s RxD2 p in. The reset should end with RxD2 high. After the reset ends, it takes
approximately 100 states before the chip is ready to measure the low-level period of the RxD2
pin.
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD2 and TxD2 pins should be pulled up on the board.
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• Before branching to the programming control program (RAM area H'FFC000), the chip
terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE
and T E bits in SCR to 0 ), but the a djusted bit r a te value remains set in BRR. The transmit data
output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1).
The contents of the CPU’s internal general register s ar e undefined at this time, so these
registers must be initialized immediately after branching to the prog r ammin g control program.
In particular, since th e stack pointer (SP) is used imp licitly in subroutin e calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip register s ar e not changed.
• Boot mode can be entered by making the pin settings shown in table 19.6 and executing a
reset-start.
Boot mod e can be cleared by driving the reset pin low, waitin g at least 20 states, then setting
the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a
WDT overflow reset.
Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low
while the boot program is being executed or while flash memory is being programmed or
erased*2.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of por ts with multiplexed address functions and bu s control output pins (AS, RD, HWR)
will change according to the ch ange in the microcomputer’s operating mode*3.
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins d uring a reset, or to prevent collisio n with signals outside the micro com puter.
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4
states) with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 19.13,
Flash Memory Programming and Erasing Precautions.
3. See appendix D, Pin States.
19.6.2 User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means of FWE control and supply of
programming data, and storing a program/erase control program in part of the program area as
necessary.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 648 of 1042
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To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7),
and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash
memory operate as they normally would in modes 6 and 7.
The flash memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external m e m ory . If the program is to be located in external memory, the instruction for
writing to flash memory, and the following instruction, should be placed in on-chip RAM.
Figure 19.9 shows the procedure for executing the program/erase control program when
transferred to on-chip RAM.
Clear FWE
*
FWE = high
*
Branch to flash memory application
program
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Transfer program/erase control
program to RAM
MD2, MD1, MD0 = 110, 111
Reset-start
Write the FWE assessment program and
transfer program (and the program/erase
control program if necessary) beforehand
Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin
only when the flash memory is programmed or erased. Also, while a high level is
applied to the FWE pin, the watchdog timer should be activated to prevent
overprogramming or overerasing due to program runaway, etc.
* For further information on FWE application and disconnection, see section 19.13,
Flash Memory Programming and Erasing Precautions.
Figure 19.9 User Program Mode Execution Procedure
Section 19 ROM (Preliminary)
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19.7 Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the on -
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses
H'000000 to H'03FFFF are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in
FLMCR1.
The flash memory cannot be read while being programmed or erased. Ther efore, the program
(user program) that controls flash memory programming/erasing should be located and executed in
on-chip RAM or exter nal memory. If the program is to be located in external mem ory, the
instruction for writing to flash memory, and the following instruction, should be placed in on-chip
RAM. Also ensure that the DTC is not activated before or after execution of the flash memory
write instructio n.
In the followin g operation descriptio ns, wait times after setting o r clearing individual bits in
FLMCR1 are given as parameters; for details of the wait times, see section 22.6, Flash Memory
Characteristics.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1,
E1, and P1 bits in FLMCR1 is executed by a program in flash memory.
2. When programmin g or erasing, set FWE to 1 (p rog r amming/erasing will not b e
executed if FWE = 0).
3. Programming must be executed in the erased state. Do not perf orm additional
programming on addresses that have already been programmed.
Section 19 ROM (Preliminary)
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Normal mode
On-board
programming mode
Software programming
disable state
Erase setup
state Erase mode
Program mode
Erase-verify
mode
Program
setup state
Program-verify
mode
SWE1 = 1
SWE1 = 0
FWE = 1 FWE = 0
E1 = 1
E1 = 0
P1 = 1
P1 = 0
Software
programming
enable
state
*1
*2
*3
*4
Notes: In order to perform a normal read of flash memory, SWE1 must be cleared to 0. Also note that verify-reads
can be performed during the programming/erasing process.
1. : Normal mode : On-board programming mode
2. Do not make a state transition by setting or clearing multiple bits simultaneously.
3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing
through the software programming enable state.
4. After a transition from program mode to the program setup state, do not enter program mode without
passing through the software programming enable state.
ESU1 = 0
ESU1 = 1
PSU1 = 1
PSU1 = 0
PV1 = 1
PV1 = 0
EV1 = 0
EV1 = 1
Figure 19.10 FLMCR1 Bit Settings and State Transitions
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 651 of 1042
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19.7.1 Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 19.11 should be followed. Performing programming operations according to this flowchart
will enable data or pro grams to b e written to f lash memory without subjecting the device to
voltage stre ss or sacrificing pro gram data reliability . Prog r amming should be carried out 128 bytes
at a time.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of programming operations (N) are shown in table 22.10.
Following the elapse of (×0) µs or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte
program data is stored in the program data area and reprogram data area, and the 128-byte data in
the program data area in RAM is written consecutively to the program address ( the lower 8 bits of
the first address written to must b e H'00 or H'8 0). 128 consecu tive byte data transfers ar e
performed. The program address and program data are latched in the flash memory. A 128-byte
data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must
be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by settin g the PSU1 bit in FLMCR1, and after the elapse of (y) µs or mo r e , the
operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during
which the P1 b it is set is the flash memo ry p rog r ammin g time. Refer to the table in figure 19.11
for the programming time.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 652 of 1042
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19.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of the given programming time, clear the P1 bit in FLMCR1, then wait for at least
(α) µs before clearing the PSU1 bit to exit program mode. After the elapse of at least (β) µs , the
watchdog timer is cleared and the operating mode is switched to program-verify mode by setting
the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data
should be made to the addresses to be read. The dummy write should be executed after the elapse
of (γ) µs or more. When the flash m e m ory is read in this state (verify data is read in 16-bit units),
the data at the latche d address is read. Wait at least (ε) µs after the dummy write before performing
this read ope r ation. Next, the originally written data is compared with the verify data, and
reprogram data is computed (see figure 19.11) and transferred to RAM. After verification of 128
bytes of data has been completed, exit program-verify mode, wait for at least (η) µs, then clear the
SWE1 bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the
program/program -verif y sequ e n ce as before. The maximum number of repetitions of the
program/program-verify sequence is indicated by the maximum programming count (N).
However, ensure that the program/program-verify sequence is not repeated more than (N) times on
the same bits.
Notes on Program/Program-Verify Procedure
1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must
be H'00 or H'80.
2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer
should be used.
128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write
H'FF data to the extra addresses.
3. Verify da ta is r ead in wor d un its.
4. The write pulse is applied and a flash m emor y write executed while the P1 bit in FLMCR1 is
set. In the H8S/2626 and H8S/2623, write pulses should be applied as follows in the
program/program-verify procedure to prevent voltage stress on the device and loss of write
data reliability .
a. After write pulse application, perform a verify-read in program-verify mode and apply a
write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write
bits in the 12 8-b yte write data are read as 0 in the verify-read oper a tion, the
program/program-verify procedure is completed. In the H8S/2626 and H8S/2623, the
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 653 of 1042
REJ09B0275-0500
number of loops in reprogramming processing is guaranteed not to exceed the maximum
value of the maximum programming count (N).
b. After write pulse application, a verify-read is performed in program-verify mode, and
programming is judged to have been completed for bits read as 0.
c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing
should be executed. If a bit for which programming has been judged to be completed is
read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.
5. The period for which the P1 bit in FLMCR1 is set (the write pulse width) should be changed
according to the degree of progress through the program/program-verify procedure. For
detailed wait time specifications, see section 22.6, Flash Memory Characteristics.
6. The program/program-verify flowchart for the H8S/2626 and H8S/2623 is shown in figu re
19.11.
To cover the points noted above, bits on which reprogramming processing is to be executed,
and bits on which additional programming is to be executed, must be determined as shown
below.
Since reprogram data and additional-programming data vary according to the progress of the
programming procedure, it is recommended that the following data storage areas (128 bytes
each) be provided in RAM.
Reprogram Data Computation Table
(D)
Result of Verify-Read
after Write Pulse
Application (V) (X)
Result of Operation Comments
0 0 1 Programming completed: reprogram m ing
processing not to be executed
1 0 Programming incomplete: reprogramming
processing to be executed
10 1
1 Still in erased state: no action
Legend:
(D): Source data of bits on which programming is exec uted
(X): Source data of bits on which reprogramming is executed
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 654 of 1042
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Additional-Programming Data Computation Table
(X')
Result of Verify-Read
after Write Pulse
Application (V) (Y)
Result of Operation Comments
0 0 0 Programming by write pulse application
judged to be completed: additional
programming proc es sin g to be execut ed
1 1 Programming by write pulse application
incomplete: additional programming
processing not to be executed
1 0 Programming already completed: additional
programming processing not to be executed
1 Still in erased state: no action
Legend:
(Y): Data of bits on which additional programming is executed
(X'): Data of bits on which reprogramming is executed in a certain reprogramming loop
7. It is necessary to execute additional programming processing during the course of the
H8S/2626 or H8S/2623 program/program-verify procedure. However, once 128-byte-unit
programming is finished, additional programming should not be carried out on the same
address area. When executing reprogramming, an erase must be executed first. Note that
normal operation of reads, etc., is not guaranteed if additional programming is performed on
addresses for which a prog ram/program-verify operation has finished.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 655 of 1042
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START
End of programming
Set SWE1 bit in FLMCR1
Wait (× 0) µs
tsswe:
tcpv:
tcswe:
n = 1
m = 0
Sub-Routine-Call
Set PV1 bit in FLMCR1
Wait (γ) µs
Wait (ε) µs
Read verify data
NG
NG
NG
NG
NG
OK
OK
OK
OK
*
4
*
2
*
4
*
3
Wait (η) µs
Additional-programming data computation
Reprogram data computation
Transfer additional-programming data to
additional-programming data area
*
4
Transfer reprogram data to reprogram data area
Program data =
verify data?
Clear PV1 bit in FLMCR1
Clear SWE1 bit in FLMCR1
m = 1
128-byte data
verification completed?
Wait (×1) µs
m = 0 ?
N1 ≥ n ?
NG
N1 ≥ n ?
Increment address
Programming failure
OK
Clear SWE1 bit in FLMCR1
Wait (×1) µs
n ≥ (N1 + N2) ?
n ← n + 1
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first
address written to must be H'00 or H'80. A 128-byte data transfer
must be performed even if writing fewer than 128 bytes; in this case,
H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed in the 128-byte programming
loop will be subject to programming again if they fail the subsequent verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data,
and a 128-byte area for storing additional-programming data must be provided in RAM.
The reprogram and additional-programming data contents are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See note *6 for details of the pulse widths.
When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Original Data
(D) Verify Data
(V) Reprogram Data
(X) Comments
Programming complete
Programming is incomplete:
reprogramming should be performed
Left in the erased state
Write pulse application subroutine
Programming must be executed in the erased state.
Do not perform additional programming on addresses
that have already been programmed.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area (128 bytes)
Store 128 bytes of program data in program
data area and reprogram data area
*
1
*
5
Successively write 128-byte reprogram
data to flash memory
Enable WDT
Disable WDT
Set PSU1 bit in FLMCR1
Set P1 bit in FLMCR1
Clear PSU1 bit in FLMCR1
Wait (y) µs
tspsu:
tspv:
tspur:
tcswe:
Wait (α) µs
Wait (β) µs
tcp:
tsp10 or tsp30 or tsp200:
Wait (z0) µs or (z1) µs or (z2) µs
Sub-Routine-Call
Additional programming subroutine
*
1
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
H'FF dummy write to verify address
tcswe:
Sub-Routine Write Pulse
End Sub
Clear P1 bit in FLMCR1
Start of programming
Write pulse application subroutine
*
5
Number of Writes
1
2
·
·
·
N1–1
N1
N1+1
N1+2
N1+3
·
·
·
N1+N2–2
N1+N2–1
N1+N2
Programming
z0
z0
·
·
·
z0
z0
z2
z2
z2
·
·
·
z2
z2
z2
z1
z1
·
·
·
z1
z1
—
—
—
·
·
·
—
—
—
Additional
Programming
Note: 6. Programming Time
Reprogram Data Computation Table Reprogram Data
(X') Verify Data
(V) Additional-Programming
Data (X) Comments
Additional programming should be performed
Additional programming should not be performed
Additional programming should not be performed
Additional programming should not be performed
Additional-Programming Data Computation Table
P1 Bit Set Time (µs)
0
0
1
1
0
1
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
Figure 19.11 Program/Program-Verify Flowchart
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 656 of 1042
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19.7.3 Erase Mode
When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 19.12
should be followed.
To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in
erase block register 1 and 2 (EBR1, EBR2) at least (x) µs after setting the SWE1 bit to 1 in
FLMCR1. Next, the watch dog timer (WDT) is set to prevent overerasing due to program
runaway, etc. Set 6.6 ms as the WDT overflow period. Preparation for entering erase mode (erase
setup) is performed next by setting the ESU1 bit in FLMCR1. The operating mode is then
switched to erase m ode by setting the E1 b it in FLMCR1 after the elapse of at least (y ) µs. The
time durin g which the E1 bit is set is the flash mem ory erase time. Ensure that the er ase time does
not exceed (z) ms.
Note: With f lash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all 0) is not necessary before starting the erase procedure.
19.7.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E1 bit in FLMCR1, then wait for at least (α) µs
before clearing the ESU1 bit to exit erase mode. After exiting erase mode, the watchdog timer is
cleared after the elapse of (β) µs or more. The operating mode is then switched to erase-verify
mode by setting the EV1 bit in FLMCR1. Before reading in erase-verify mode, a dummy write of
H'FF data should be made to the addresses to be read. The dummy write should be executed after
the elapse of (γ) µs or mo re. When the flash memory is read in this state (verify data is read in 16-
bit units), the data at the latched address is r ead. Wait at least (ε) µs after the dummy write before
performing this read operation. If the read data has been erased (all 1), a dummy write is
performed to the next address, and erase-verify is performed. If the read data is unerased, set erase
mode again and repeat the erase/erase-verify sequence in the same way. The maximum number of
reoperations of the erase/erase-verify sequence is indicated by the maximum erase count (N).
However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When
verification is completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been
completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If ther e are any unerased
blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-
verify sequence as before.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 657 of 1042
REJ09B0275-0500
End of erasing
Start
Set SWE1 bit in FLMCR1
Set ESU1 bit in FLMCR1
Set E1 bit in FLMCR1
tsswe: Wait (x) µs
tsesu: Wait (y) µs
n = 1
Set EBR1 and 2
Enable WDT
*3
tse: Wait (z) ms
tce: Wait (α) µs
tcesu: Wait (β) µs
tsev: Wait (γ) µs
Set block start address to verify address
tsevr: Wait (ε) µs
tcev: Wait (η) µs
*2
*4
Start erase
Clear E1 bit in FLMCR1
Clear ESU1 bit in FLMCR1
Set EV1 bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV1 bit in FLMCR1
tcev: Wait (η) µs
Clear EV1 bit in FLMCR1
Clear SWE1 bit in FLMCR1
Disable WDT
Halt erase
*1
Verify data = all "1"?
Last address of block?
End of
erasing of all erase
blocks?
Erase failure
Clear SWE1 bit in FLMCR1
n ≥ (N)?
NG
NG
NG NG
OK
OK
OK OK
n ← n + 1
Increment
address
tcswe: Wait (× 1) µs tcswe: Wait (× 1) µs
Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.
2. Verify data is read in 16-bit (W) units.
3. Set only one bit in EBR1 and 2. More than 2 bits cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 19.12 Erase/Erase-Verify Flowchart
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 658 of 1042
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19.8 Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
19.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase
block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the
error-protected state. (See table 19.8.)
Table 19.8 Hardware Protection
Functions
Item Description Program Erase
FWE pin protection • When a low level is input to the FWE pin,
FLMCR1, FLMCR2, (exc ept bit FLER)
EBR1, and EBR2 are initialized, and the
program/erase-protected state is entered.
Yes Yes
Reset/standby
protection • In a reset (including a WDT reset) and in
standby mode, FLMCR1, FLMCR2, EBR1,
and EBR2 are initialized, and the
program/erase-protected state is entered.
• In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscil lati on stab ilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width sp ecified in the AC
Charact eri stics section.
Yes Yes
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 659 of 1042
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19.8.2 Software Protection
Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register
1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register
(RAMER). When sof twar e protection is in ef f ect, setting the P1 or E1 bit in flash memory control
register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table
19.9.)
Table 19.9 Software Protection
Functions
Item Description Program Erase
SWE bit protection • Setting bit SWE1 in FLMCR1 to 0 will
place area H'000000 to H'03FFFFF in the
program/erase-protected state. (Execute
the program in the on-chip RAM, external
memory)
Yes Yes
Block specification
protection • Erase protection can be set for individual
blocks by settings in erase block register 1
(EBR1) and erase block register 2
(EBR2).
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-prot ect ed state.
—Yes
Emulation protection • Setting the RAMS bit to 1 in the RAM
emulation register (RAMER) places all
blocks in the program /eras e-prot ected
state.
Yes Yes
Section 19 ROM (Preliminary)
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19.8.3 Error Protection
In error protection, an error is detected when H8S/2626 or H8S/2623 runaway occurs during flash
memory programming/erasing, or operation is not performed in accordance with the
program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase
operation prevents damage to the flash memo ry due to overprogramming or overerasing.
If the H8S/2626 or H8S/2623 malfunctions during flash memory programming/erasing, the FLER
bit is set to 1 in FLMCR2 and the err or p rotectio n state is entered. The FLMCR1, FLMCR2,
EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at
which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1
or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify
mode.
FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
2. When a SLEEP instruction (including software standby) is executed during
programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 661 of 1042
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Figure 19.13 shows the flash memory state transition diagram.
RD VF PR ER FLER = 0
Error
occurrence
RES = 0 or HSTBY = 0
RES = 0 or
HSTBY = 0
RD VF PR ER FLER = 0
Program mode
Erase mode Reset or standby
(hardware protection)
RD VF PR ER FLER = 1 RD VF PR ER FLER = 1
Error protection mode Error protection mode
(software standby)
Software
standby mode
FLMCR1, FLMCR2, EBR1, EBR2
initialization state
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Software standby
mode release
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Legend:
RES = 0 or
HSTBY = 0
Error occurrence
(software standby)
Figure 19.13 Flash Memory State Transitions
Section 19 ROM (Preliminary)
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19.9 Flash Memory Emulation in RAM
Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped
onto the flash memory area so that data to be written to flash m emor y can b e emulated in RAM in
real time. After the RAMER setting has been made, accesses cannot be made from the flash
memory area or the RAM area overlapping flash memory. Emulation can be performed in user
mode and user program mode. Figure 19.14 shows an example of emulation of real-time flash
memory programmin g.
Start of emulation program
End of emulation program
Tuning OK?
Yes
No
Set RAMER
Write tuning data to overlap
RAM
Execute application program
Clear RAMER
Write to flash memory emulation
block
Figure 19.14 Flowchart for Flash Memory Emulation in RAM
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 663 of 1042
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H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
H'3FFFF
Flash memory
EB8 to EB11
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
H'FFD000
H'FFDFFF
H'FFEFBF
On-chip RAM
This area can be accessed
from both the RAM area
and flash memory area
Figure 19.15 Example of RAM Overlap Operation
Example in which F lash Memory Blo c k Area EB0 is Overla pped
1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the
area (EB0) for which real-time programming is required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory sp ace (EB0).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM2 to RAM0 (emulation pro tection) . In th is state, setting
the P1 or E1 bit in flash memory control register 1 (FLMCR1), will not cau se a
transition to program mode or erase mode. When actually programming or erasing a
flash memory area, the RAMS bit should be cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
3. Block area EB0 contains the vector table. When performing RAM emulation, the
vector table is needed in the overlap RAM.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 664 of 1042
REJ09B0275-0500
19.10 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI interrupt is disabled when flash memory is being programmed or
erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot
mode*1, to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
not be read correctly*2, possibly resulting in MCU runaway.
3. If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All requests, including NMI interrupt, must
therefore be restricted inside and outside the MCU when programming or erasing flash memory.
NMI interrupt is also disabled in the error - protection state while the P1 or E1 bit r emains set in
FLMCR1.
Notes: 1. Interrupt requests m ust be disabled insid e and outside the MCU u ntil the programming
control program has completed programming.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P1 or E1 bit
is set in FLMCR1), correct read data will no t b e obtained (undetermined values will
be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt
exception h andling will not be executed correctly.
19.11 Flash Memory Programmer Mode
Programs an d data can be written and erased in programmer mode as well as in the on-b oard
programming modes. In programmer mode, flash memory read mode, auto-program mode, au to-
erase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and
status read mode , a statu s p o lling procedure is used, and in status read mode, detailed in ter nal
signals are output after execution of an auto-program or auto-erase operation.
In programmer mode, set the mode pins to programmer mode (see table 19.10) and input a 12
MHz input clock.
Table 19.10 shows the pin settings for programmer mode.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 665 of 1042
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Table 19.10 Programmer Mode Pin Settings
Pin Names Settings
Mode pins: MD2, MD1, MD0 Low level input to MD2, MD1, and MD0.
Mode setting pins: PF0, P16, P14 High level input to PF0, low level input to P16 and P14
FWE pin High level input (in auto-program and auto-erase
modes)
RES pin Reset circuit
XTAL, EXTAL, PLLVCC, PLLCAP,
PLLVSS pins Oscillator circuit
19.11.1 Socket Adapter Pin Correspondence Diagram
Connect the so cket adapter to the chip as shown in figure 19.17. This will enable conversion to a
40-pin arrangement. The on-chip ROM memory map is shown in figure 19.16, and the socket
adapter pin correspondence diagram in figure 19.17.
H'000000
Addresses in
MCU mode Addresses in
programmer mode
H'03FFFF
H'00000
H'3FFFF
On-chip ROM space
256 kbytes
Figur e 19.16 On-Chip R OM Memory Map
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 666 of 1042
REJ09B0275-0500
Socket Adapter
(Conversion to 40-Pin
Arrangement)
H8S/2626 or H8S/2623
Pin No. Pin Name
28
29
30
31
32
33
34
35
36
38
40
41
42
43
44
45
46
47
20
21
22
23
24
25
26
27
19
16
18
67
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
D8
D9
D10
D11
D12
D13
D14
D15
CE
OE
WE
FWE
HN27C4096HG (40 Pins)
Pin No. Pin Name
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
19
18
17
16
15
14
13
12
2
20
3
4
1, 40
11, 30
5, 6, 7
8
9
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CE
OE
WE
FWE
VCC
VSS
NC
A20
A19
A18
60
64
66
59
58
57
Other than the above
RES
XTAL
EXTAL
PLL VCC
PLLCAP
PLL VSS
NC (OPEN)
VCC
VSS
Power-on
reset circuit
6, 9, 13, 17, 39, 52, 61, 62,
63, 75, 76, 77, 97
2, 4, 8, 14, 15, 37, 48, 49,
53, 54, 55, 56, 65, 94, 95, 98
Oscillator circuit
PLL circuit
Legend:
FWE: Flash write enable
I/O7–I/O0: Data input/output
A18–A0: Address input
CE: Chip enable
OE: Output enable
WE: Write enable
Figure 19.17 Socket Adapter Pin Correspondence Diagram
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 667 of 1042
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19.11.2 Programmer Mode Operation
Table 19.11 shows how the different operating modes are set when using programmer mode, and
table 19.12 lists the commands used in programmer mode. Details of each mode are given below.
• Memory Read Mode
Memory read mode supports byte reads.
• Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
• Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used
to confirm the end of auto -programming.
• Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the I/O6 signal. In status read mode, error information is output if an
error occurs.
Table 19.11 Settings for Various Operating Modes in Programmer Mode
Pin Names
Mode FWE CE
CECE
CE OE
OEOE
OE WE
WEWE
WE I/O7– I/O0 A18–A0
Read H or L L L H Data output Ain
Output disable H or L L H H Hi-Z X
Command write H or L*3L H L Data input Ain*2
Chip disable*1H or L H X X Hi-Z X
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. Ain indicates that there is also address input in auto-program mode.
3. For command writes in auto-program and auto-erase modes, input a high level to the
FWE pin.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 668 of 1042
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Table 19.12 Programmer Mode Commands
1st Cycle 2nd Cycle
Command Name Number
of Cycles Mode Address Data Mode Address Data
Memory read mode 1 + n Write X H'00 Read RA Dout
Auto-program mode 129 Write X H'40 Write WA Din
Auto-erase mode 2 Write X H'20 Write X H'20
Status read mode 2 Write X H'71 Write X H'71
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
19.11.3 Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the
command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command wr ite, af ter which the memory contents are read.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. Once memory read mode has been entered, consecutive reads can be performed.
4. After powering on, memory read mode is entered.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 669 of 1042
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Table 19.13 AC Characteristics in Transition to Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
OE
CE
A18–A0
OE
WE
I/O7–I/O0
Note: Data is latched on the rising edge of WE.
t
ceh
t
wep
t
f
t
r
t
ces
t
nxtc
Address stable
t
ds
t
dh
Command write Memory read mode
Figure 19.18 Timing Waveforms for Memory Read after Memory Write
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 670 of 1042
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Table 19.14 AC Characteristics in Transition from Memory Read Mode to Another Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
A18–A0
OE
WE
I/O7–I/O0
Note: Do not enable WE and OE at the same time.
t
ceh
t
wep
t
f
t
r
t
ces
t
nxtc
Address stable
t
ds
t
dh
Other mode command writeMemory read mode
Figure 19.19 Timing Waveforms in Transition from Memory Read Mode to Another Mo de
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 671 of 1042
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Table 19.15 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Access tim e tacc —20 µs
CE output delay time tce —150 ns
OE output delay ti me toe —150 ns
Output disable delay time tdf —100 ns
Data output hold time toh 5 — ns
CE
A18–A0
OE
WE
I/O7–I/O0
VIL
VIL
VIH tacc tacc
toh toh
Address stableAddress stable
Figure 19.20 CE
CECE
CE and OE
OEOE
OE Enable State Read Timing Waveforms
CE
A18–A0
OE
WE
I/O7–I/O0
V
IH
t
acc
t
ce
t
oe
t
oe
t
ce
t
acc
t
oh
t
df
t
df
t
oh
Address stableAddress stable
Figure 19.21 CE
CECE
CE and OE
OEOE
OE Clock System Read Timing Waveforms
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 672 of 1042
REJ09B0275-0500
19.11.4 Auto-Program Mode
1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
2. A 128-byte data transfer is necessary even when programming fewer than 128 by tes. In this
case, H'FF data must be wr itten to the extra addr esses.
3. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
4. Memory address transfer is performed in the second cycle (figure 19.22). Do not perform
transfer after the third cycle.
5. Do not perform a command write during a programming operation.
6. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
8. Status pollin g I/O6 and I/O7 pin information is retained until th e next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 673 of 1042
REJ09B0275-0500
Table 19.16 AC Characteristics in Auto-Program Mo de
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time twsts 1 — ms
Status polling access time tspa —150 ns
Address setup time tas 0 — ns
Address hold time tah 60 —ns
Memory write time twrite 1 3000 ms
Write setup time tpns 100 —ns
Write end setup time tpnh 100 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 674 of 1042
REJ09B0275-0500
CE
A18–A0
FWE
OE
WE
I/O7
I/O6
I/O5–I/O0
t
pns
t
wep
t
ds
t
dh
t
f
t
r
t
as
t
ah
t
wsts
t
write
t
spa
t
ces
t
ceh
t
nxtc
t
nxtc
t
pnh
Address
stable
H'40 H'00
Data transfer
1 to 128 bytes
Write operation end decision signal
Write normal end decision signal
Figure 19.22 Auto-Program Mode Timing Waveforms
19.11.5 Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.
2. Do not perform a command write during auto-erasing.
3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also
be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).
4. Status pollin g I/O6 and I/O7 pin information is retained until th e next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 675 of 1042
REJ09B0275-0500
Table 19.17 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ± 5°C
Item Symbol Min Max Unit
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time tests 1 — ms
Status polling access time tspa —150 ns
Memory erase time terase 100 40000 ms
Erase setup time tens 100 —ns
Erase end setup time t enh 100 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
A18–A0
FWE
OE
WE
I/O7
I/O6
I/O5–I/O0
t
ens
t
wep
t
ds
t
dh
t
f
t
r
t
ests
t
erase
t
spa
t
ces
t
ceh
t
nxtc
t
nxtc
t
pnh
H'20 H'20 H'00
Erase end
decision signal
Erase normal
end
decision signal
Figure 19.23 Auto-Erase Mode Timing Waveforms
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 676 of 1042
REJ09B0275-0500
19.11.6 Status Read Mode
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a statu s read mo d e comm and
write is executed.
Table 19.18 AC Characteristics in Status Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit
Read time after command wr ite tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
OE output delay ti me toe —150 ns
Disable delay time tdf —100 ns
CE output delay time tce —150 ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
A18–A0
OE
WE
I/O7–I/O0
t
wep
t
f
t
r
t
oe
t
df
t
ds
t
ds
t
dh
t
dh
t
ces
t
ceh
t
ce
t
ceh
t
nxtc
t
nxtc
t
nxtc
t
ces
H'71
t
wep
t
f
t
r
H'71
Note: I/O2 and I/O3 are undefined.
Figure 19.24 Status Read Mode Timing Waveforms
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 677 of 1042
REJ09B0275-0500
Table 19.19 Status Read Mo de Return Commands
Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Attribute Normal
end
decision
Command
error Program-
ming error Erase
error ——Programming
or erase
count
exceeded
Effective
address
error
Initial va lu e 0 0 0 0 0 0 0 0
Indications Normal
end: 0
Abnormal
end: 1
Command
error: 1
Otherwise: 0
Program-
ming
error: 1
Otherwise: 0
Erasing
error: 1
Otherwise: 0
——Count
exceeded: 1
Otherwise: 0
Effective
address
error: 1
Otherwise: 0
Note: I/O2 and I/O3 are undefined.
19.11.7 Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 19. 20 Status Po lling Output Truth Table
Pin Name During Inte rnal
Operation Abnormal End — Normal End
I/O7 0 1 0 1
I/O6 0 0 1 1
I/O0–I/O5 0 0 0 0
19.11.8 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 19.21 Stipulated Transition Times to Command Wait State
Item Symbol Min Max Unit
Standby release (oscillation
stabilization time) tosc1 30 —ms
Programmer mode setup time tbmv 10 —ms
VCC hold time tdwn 0 — ms
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 678 of 1042
REJ09B0275-0500
tosc1 tbmv tdwn
VCC
RES
FWE
Memory read
mode
Command
wait state Auto-program mode
Auto-erase mode
Command wait state
Normal/abnormal
end decision
Note: When using other than the automatic write mode and automatic erase mode, drive the FWE
input pin low.
Figure 19.25 Oscillat ion Stabilization Time, Bo ot Program Transfer Time, and
Power-Down Sequence
19.11.9 Notes on Memory Programming
1. When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming.
2. When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-pr ogramming.
Notes: 1 . The flash memory is in itially in the erased state when th e device is shipped by Ren e sas.
For other chips for which the erasure history is unknown, it is recommended that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Additional programming cannot be performed on previously programmed address
blocks.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 679 of 1042
REJ09B0275-0500
19.12 Flash Memory and Power-Down States
In addition to its normal operating state, the flash memor y has power-down states in which power
consumption is reduced by halting part or all of the internal power supply circuitry.
There are three flash memory operating states:
(1) Normal operating mode: The flash memory can be read and written to .
(2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be
read when the LSI is operating on the subclock.
(3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or
written to.
States (2) and (3) are flash memory power-down states. Table 19.22 shows the correspondence
between the operating states of the LSI and the flash memory.
Table 19.22 Flash Memory Operating States
LSI Operating State Flash Memory Operating State
High-speed mode
Medium-speed mode
Sleep mode
Normal mode (read/write)
Subactive mode
Subsleep mode When PDWND = 0: Power-down mode (read-only)
When PDWND = 1: Normal mode (read-only)
Watch mode
Software standb y mode
Hardware standby mode
Standby mode
19.12.1 Note on Power-Down States
When the flash memory is in a power-down state, part or all of the internal power supply circuitry
is halted. Therefore, a power supply circuit stabilization period must be provided when returning
to normal operation. When the flash memory return s to its normal op erating state from a po wer-
down state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 µs
(power supply stabilization time), even if an oscillation stabilization period is not necessary.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 680 of 1042
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19.13 Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
programmer mode are summarized below.
1. Use the specified voltages and timing for programming and erasing.
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip
flash memory (FZTAT256V3A).
Do not select the HN27C4096 setting for the PROM programmer, and only use the specified
socket adapter. Failure to observe these points may result in damage to the device.
2. Powering on and off (see figures 19.26 to 19.28)
Do not apply a high lev el to the FWE pin until VCC has stabilized. Also, drive the FWE pin low
before turning off VCC.
When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory
in the hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a
power failure and subsequent recovery.
3. FWE application/disconnection (see figures 19.26 to 19.28)
FWE application should be carried out when MCU operation is in a stable condition. If MCU
operation is no t stable, fix the FWE pin low and set the protection state.
The following points must be observed concerning FWE application and disconnection to
prevent unintentional programming or erasing of flash memory:
•Apply FWE when the VCC voltage has stabilized within its rated voltage range.
Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling
time).
•In boot mode, apply and disconnect FWE during a reset.
•In user program mode, FWE can be switched between high and low level regardless of
RES input.
FWE input can also be switched during execution of a program in flash memory.
•Do not apply FWE if program runaway has occurred.
•Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in
FLMCR1 are cleared.
Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits are not set by mistake
when applying or disconnecting FWE.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 681 of 1042
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4. Do not apply a constant high level to the FWE pin.
Apply a high level to the FWE pin only when programming or erasing flash memory. A
system configuration in which a high level is constantly applied to the FWE pin should be
avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be
activated to prevent overprogramming or overerasing due to program runaway, etc.
5. Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress o r sacrificing prog r am data reliability. When setting the
P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against
program runaway, etc.
6. Do not set or clear the SWE1 bit during execution of a program in flash memory.
Do not set or clear the SWE1 bit during execution of a program in flash memory. Wait for at
least 100 µs after clearing the SWE1 bit before executing a program or reading data in flash
memory. When the SWE1 bit is set, data in f lash memory can be rewritten, but when SWE1 =
1, flash memory can only be read in program-verify or erase-verify mode. Access flash
memory only for verify operations (verification during programming/erasing). Do not clear the
SWE1 bit during programming, erasing, or verifying.
Similarly, when using the RAM emulation function while a high level is being input to the
FWE pin, the SWE1 bit must be cleared before executing a program or reading data in flash
memory. However, the RAM area overlapping flash memory space can be read and written to
regardless of whether the SWE1 b it is set or cleared.
7. Do not use interrupts while fla sh memo ry is being pro grammed or erased.
All interrupt requests, including NMI, should be disabled during FWE application to give
priority to program/erase op erations.
8. Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 128-byte
programming unit block. In programmer mode, also, perform only one programming operation
on a 128-byte programming unit block.
9. Before programming, check that the chip is correctly mounted in the PROM
programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer
socket, socket adapter, and chip are not correctly aligned.
10.Do not touch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 682 of 1042
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Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
φ
VCC
FWE
t
OSC1
Min 0 µs
t
MDS*3
t
MDS*3
MD2 to MD0
*1
RES
SWE1 bit
SWE1 set SWE1 cleared
Program-
ming/
erasing
possible
Wait time:
xWait time:
100 µs
Min 0 µs
Notes: 1. Except when switching modes, the level of the mode pins (MD2–MD0) must be fixed until power-
off by pulling the pins up or down.
2. See section 22.6, Flash Memory Characteristics.
3. Mode programming setup time t
MDS
(min) = 200 ns
Figure 19.26 Power-On/Off Timing (Boot Mode)
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 683 of 1042
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Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
φ
VCC
FWE
t
OSC1
Min 0 µs
MD2 to MD0
*1
RES
SWE1 bit
SWE1 set SWE1 cleared
Program-
ming/
erasing
possible
Wait time:
xWait time:
100 µs
t
MDS*3
Notes: 1. Except when switching modes, the level of the mode pins (MD2–MD0) must be fixed until power-
off by pulling the pins up or down.
2. See section 22.6, Flash Memory Characteristics.
3. Mode programming setup time t
MDS
(min) = 200 ns
Figure 19.27 Power-On/Off Timing (User Program Mode)
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 684 of 1042
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Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
φ
VCC
FWE
t
OSC1
Min 0µs
t
MDS
t
MDS*2
t
MDS
t
RESW
MD2 to MD0
RES
SWE1 bit
Mode
change
*1
User
mode
Boot
mode User program mode
SWE1 set SWE1
cleared
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Programming/
erasing possible
Wait time: x
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Wait time: 100 µs
Mode
change
*1
User
mode User program
mode
Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried
out by means of RES input. The state of ports with multiplexed address functions and bus control output pins
(
AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),
and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, a mode programming setup time, t
MDS
(min), of 200 ns
is necessary with respect to the RES clearance timing.
3. See section 22.6, Flash Memory Characteristics.
Figure 19.28 Mode Transition Timing
(Example: Boot Mode →
→→
→ User Mode ↔
↔↔
↔ User Program Mode)
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 685 of 1042
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19.14 Note on Switching from F-ZTAT Version to Mask ROM Version
The mask ROM version does not have the internal registers for flash memory control that are
provided in th e F-ZTAT ve r sion. Tab le 19.23 lists the registers that are present in the F-ZTAT
version but not in the mask ROM version. If a register listed in table 19.23 is read in the mask
ROM version, an undefined value will be returned. Therefore, if application software developed
on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure
that the registers in table 19.23 have no effect.
Table 19.23 Registers Present in F-ZTAT Version but Absent in Mask ROM Version
Register Abbreviation Address
Flash memory control register 1 FLMCR1 H'FFA8
Flash memory control register 2 FLMCR2 H'FFA9
Erase block register 1 EBR1 H'FFAA
Erase block register 2 EBR2 H'FFAB
RAM emulation register RAMER H'FEDB
Flash memory power control register FLPWCR H'FFAC
Section 19 ROM (Preliminary)
Rev. 5.00 Jan 10, 2006 page 686 of 1042
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Section 20 Clock Pulse Generator
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Section 20 Clock Pulse Generator
20.1 Overview
The H8S/2626 Group and H8S/2623 Group have an on-chip clock pulse generator (CPG) that
generates the system clock (φ), the bus master clock, and internal clocks.
The clock pulse gene r ator consists of an oscillator, PLL (phase- lo cked loop ) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator*, and waveform shaping circuit*. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
Note: * Supported only in the H8S/2626 Group; not available in the H8S/2623 Group.
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 688 of 1042
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20.1.1 Block Diagram
Figure 20.1 shows a block diagram of the clock pulse generator.
Legend:
LPWRCR:
SCKCR:
Note: * Supported only in the H8S/2626 Group, not available in the H8S/2623 Group.
Low-power control register
System clock control register
EXTAL
XTAL
PLL circuit
(×1, ×2, ×4) Medium-
speed
clock divider
System
clock
oscillator Clock
selection
circuit
φSUB
WDT1 count clock
System clock
to ø pin Internal clock to
supporting modules Bus master cloc
k
to CPU and DTC
φ/2 to
φ/32
φ
SCK2 to SCK0
SCKCR
STC1, STC0
OSC1
OSC2
Waveform
shaping
circuit*
Subclock
oscillator*
LPWRCR
Bus
master
clock
selection
circuit
Figure 20.1 Block Diagram of Clock Pulse Generator
20.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 20.1 shows the register
configuration.
Table 20.1 Clock Pulse Generator Register
Name Abbreviation R/W Initial Value Address*
System clo ck con tro l regi ster SCKCR R/W H'00 H' FDE 6
Low-power control r egi ster LPWRCR R/W H'00 H'FDEC
Note: *Lower 16 bits of the address .
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 689 of 1042
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20.2 Register Descriptions
20.2.1 System Clock Control Register (SCKCR)
7
PSTOP
0
R/W
6
—
0
—
5
—
0
—
4
—
0
—
3
STCS
0
R/W
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
R/W
:
:
:
SCKCR is an 8-bit readable/writab le r egister that performs φ clock output control, selection of
operation when th e PLL cir cuit fr equen c y multiplication factor is chang ed, and medium-speed
mode control.
SCKCR is in itialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ
φφ
φ Clock Output Disable (PSTOP) : Controls φ output.
Description
Bit 7
PSTOP High-speed Mode,
Medium-Speed Mode Sleep Mode Software
Standby Mode Hardware
Standby Mode
0φ output (initial value) φ output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operatio n
when the PLL circu it frequency multiplication factor is changed.
Bit 3
STCS Description
0 Specified multiplication factor is valid afte r transition to software standby mode
(Initial value)
1 Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master
clock.
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 690 of 1042
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Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master is in high-speed mode (Initial value)
1 Medium-speed clock is φ/2
1 0 Medium-spe ed clock is φ/4
1 Medium-speed clock is φ/8
1 0 0 Medium-speed clock is φ/16
1 Medium-speed clock is φ/32
1——
20.2.2 Low-Power Co ntro l Register (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
SUBSTP
0
R/W
3
RFCUT
0
R/W
0
STC0
0
R/W
2
—
0
R/W
1
STC1
0
R/W
Bit
Initial value
Read/Write
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized b y a
manual reset or in software standby mode.
Bits 7 to 2—Reserved: The function of these bits differs between the H8S/2623 Group and
H8S/2626 Group.
For details see sections 21A.2.3, 21B.2.3, Low-Power Control Register (LPWRCR).
Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the
frequen cy multiplication factor of the PLL cir cuit.
Bit 1 Bit 0
STC1 STC0 Description
00×1 (Initial val ue)
1×2
10×4
1 Setting prohibited
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 691 of 1042
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Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should
not exceed the maximum operating frequency defined in sections 21A and 21B, Electrical
Characteristics.
20.3 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
In either case, the input clock should not exceed 20 MHz.
20.3.1 Connecting a Crystal Resonator
Circuit Configura tion: A crystal resonator can be connected as shown in the example in figure
20.2. Select the damping resistance Rd according to table 20.2. An AT-cut parallel-resonance
crystal should be used.
EXTAL
XTAL R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22pF
Figure 20.2 Connection of Crystal Resonator (Example)
Table 20.2 Damping Resistance Value
Frequency (MHz) 4 8 12 16 20
Rd (Ω) 500 200 0 0 0
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 692 of 1042
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Crystal Resonator: Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal
resonator that has the characteristics shown in table 20.3. The crystal resonator frequency should
not exceed 20 MHz.
XTAL
C
L
AT-cut parallel-resonance type
EXTAL
C
0
LR
s
Figure 20.3 Crystal Resonator Equivalent Circuit
Table 20.3 Crystal Resonator Parameters
Frequency (MHz) 4 8 12 16 20
RS max (Ω) 120 80 60 50 40
C0 max (pF) 77777
Note on Board Design: When a crystal resonator is connected, the following points should be
noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 20. 4.
When designing the board, place the crystal resonator and its load capacitors as close as possible
to the XTAL and EXTAL pins.
C
L2
Signal A Signal B
C
L1
H8S/2626 Group or
H8S/2623 Group
XTAL
EXTAL
Avoid
Figure 20.4 Example of Incorrect Board Design
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 693 of 1042
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External circuitry such as that shown below is recommended around the PLL.
PLLCAP
PLLVCC
PLLVSS
PVCC1 to PVCC4
VCC
VSS
R1: 3 kΩC1: 470 pF
Rp: 200 Ω
CPB: 0.1 µF*
CB: 1000pF*CB: 300pF*
Note: * CB and CPB are laminated ceramic capacitors.
(Values are preliminary recommended values.)
Figure 20.5 Points fo r Attention when Using PLL Oscillatio n Circuit
Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP p in , and ensure
that no other signal lines cross this line. Supply the C1 ground from PLLVSS.
Separate PLLVCC and PLLVSS from the other VCC/VSS and PVCC/PVSS lines at the board power
supply source, and be sure to insert bypass capacitors CPB and CB close to the pins.
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 694 of 1042
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20.3.2 External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
20.6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF.
In example (b), make sure that the external clock is held high in standby mode.
EXTAL
XTAL
External clock input
Open
(a) XTAL pin left open
EXTAL
XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 20.6 External Clock Input (Ex amples)
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 695 of 1042
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External Clock: Use an external clock frequency of 20 MHz or less.
Table 20.4 and figure 20.7 show the input conditions for the external clock.
Table 20.4 External Clock Input Conditions
V
CC
= 3.0 V to 3.6 V,
PVCC = 5.0 V ±10%
Item Symbol Min Max Unit Test Conditions
External clo ck input
low pulse width tEXL 15 —ns Figure 20.7
External clo ck inp ut high
pulse width tEXH 15 —ns
External clock rise time tEXr —5ns
External clock fall time tEXf —5ns
tCL 0.4 0.6 tcyc φ ≥ 5 MHz Figure 22.2Clock low pulse
width level 80 —ns φ < 5 MHz
tCH 0.4 0.6 tcyc φ ≥ 5 MHzClock high pulse
width level 80 —ns φ < 5 MHz
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 20. 7 External Clock Input Timing
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 696 of 1042
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20.4 PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The mu ltiplication factor is set with the STC bits in LPWRCR. The p h a se of
the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.
When setting the multiplication factor, ensure that the clock frequency after multiplication d oes
not exceed the maximum operating frequency of the chip.
When the multip licatio n factor of the PLL circuit is changed, the operation varies according to th e
setting of the STCS bit in SCKCR.
When STCS = 0 (initial value), the setting beco mes valid after a transition to software standby
mode. The transition time count is p erformed in accordan ce with the setting o f bits STS2 to STS0
in SBYCR.
[1] The initial PLL circuit multiplication factor is 1.
[2] A value is set in b its STS2 to STS0 to give the specified transitio n time.
[3] The target value is set in STC1 and STC0, and a transition is made to software standby mode.
[4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
[5] Software standby mode is cleared, and a transition time is secured in accordance with the
setting in STS2 to STS0.
[6] After the set tran sition time has elap sed, the LSI resumes operation using th e tar get
multiplication factor.
If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in
[3], software standby mode is entered and break exception hand ling is executed after the
oscillation stabilization time. In this case, the instruction following the SLEEP instruction is
executed after execution of the RTE instruction.
When STCS = 1, th e LSI operates on the chang ed multiplication factor immediately after bits
STC1 and STC0 ar e rewritten.
20.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 697 of 1042
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20.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings of
the SCK2 to SCK0 bits in SCKCR.
20.7 Subclock Oscillator (H8S/2626 Group Only)
(1) Connecting 32.768kHz Crystal Oscilla t or
To supply a clock to the subclock oscillator, connect a 32.768kHz crystal oscillator, as shown in
figure 20.8. See section 20.3.1, Connecting a Crystal Resonator.
OSC1
OSC2
C
1
C
2
C
1
= C
2
= 15 pF (typ)
Figure 20.8 Example Connection of 32.768 kHz Crystal Oscillator
Figure 20 .9 sh ows the equivalence circuit for a 32.768kHz oscillator.
OSC1 OSC2
C
s
L
s
R
s
C
o
C
o
= 1.5 pF (typ)
R
s
= 14 kΩ (typ)
f
w
= 32.768 kHz
Type No.: MX38T (Nihon Dempa Kogyo)
Figure 20.9 Equivalence Circuit for 32.768 kHz Oscillator
Section 20 Clock Pulse Generator
Rev. 5.00 Jan 10, 2006 page 698 of 1042
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(2) Handling pins when subclock no t required
If no subclock is required, connect the OSC1 pin to Vcc and leave OSC2 open, as shown in figure
20.10.
OSC1
OSC2
V
CC
Open
Figure 20.10 Pin Handling When Subclock Not Required
20.8 Subclock Waveform Shaping Circuit (H8S/2626 Group Only)
To eliminate no ise f rom the subclock input to OSC1, the subclock is samp led using the dividing
clock φ. The sampling frequen cy is set usin g the NESEL bit of LPWRCR. For details, see section
21B.2.3, Low Power Control Register (LPWRCR).
No sampling is performed in sub-active mode, sub-sleep mode, or watch mode.
20.9 Note on Crystal Resonator
Since various characteristics related to the crystal resonator are closely linked to the user’s board
design, thorough evaluation is necessary on the user’s part, for both the mask versions and
F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As
the resonator circuit ratings will de pend on the floating capacitan ce of the resonator and the
mounting circuit, the ratings should be determined in consultation with the resonator
manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied
to the oscillator pin.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 699 of 1042
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Section 21A Power-D own Modes
[H8 S/262 3 Group]
Subclock functions are not available in the H8S/2623 Group.
21A.1 Overview
In addition to the normal program executio n state, the H8S/2623 Group h as five power-down
modes in which operation of the CPU an d oscillator is halted and power dissipation is reduced.
Low-power operation can be achieved by individually controlling the CPU, on-chip supporting
modules, and so on.
The H8S/2623 operating modes are as follows:
(1) High-speed mode
(2) Medium-speed mode
(3) Sleep mode
(4) Module stop mode
(5) Software standby mode
(6) Hardware standby mode
(2) to (6) are power-down modes. Sleep mode is CPU states, medium-speed mode is a CPU and
bus master state, and module stop mode is an internal peripheral function (including bus masters
other than the CPU) state. Some of these states can be comb ined.
After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop
mode.
Note: Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in
the H8S/2623 Group.
Table 21A.1 shows the internal state of the LSI in the respective modes.
Figure 21A.1 is a mode transition diagram.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 700 of 1042
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Table 21A.1 LSI Internal States in Each Mode
Function High-
Speed Medium-
Speed Sleep Module Stop Software
Standby Hardware
Standby
System clock pulse
generator Functioning Functioning Functioning Functioning Halted Halted
CPU Instructions
Registers Functioning Medium-speed
operation Halted
(retained) High/medium-
speed
operation
Halted
(retained) Halted
(undefined)
NMIExternal
interrupts IRQ0–IRQ5
Functioning Functioning Functioning Functioning Functioning Halted
Peripheral
functions WDT0 Functioning Functioning Functioning Halted
(retained) Halted (reset)
DTC Functioning Medium-speed
operation Functioning Halted
(retained) Halted
(retained) Halted (reset)
TPU
PBC
PPG
Functioning Functioning
(PBC medium-
speed
operation)
Functioning Halted
(retained) Halted
(retained) Halted (reset)
SCI0
SCI1
SCI2
PWM
A/D
Functioning Functioning Functioning Halted (reset) Halted (reset) Halted (reset)
RAM Functioning Functioning Functioning
(DTC) Functioning Retained Retained
I/O Functioning Functioning Functioning Functioning Retained High impedance
HCAN Functioning Functioning*Functioning Halted (reset) Halted (reset) Halted (reset)
Notes: “Halted (retained)” means that internal register values are retained. The internal state is
“operation su spe nde d.”
“Halted (reset)” means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
* Note, however, that registers cannot be read or written to.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 701 of 1042
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Program-halted state
Program execution state
SCK2 to
SCK0= 0 SCK2 to
SCK0 0
SLEEP command
SLEEP
command
External
interrupt*
Any interrupt
STBY pin = High
RES pin = Low
STBY pin = Low
SSBY = 0
SSBY = 1
RES pin = High
: Transition after exception processing : Low power dissipation mode
Reset state
High-speed mode
(main clock)
Medium-speed
mode
(main clock)
Hardware
standby mode
Software
standby mode
Sleep mode
(main clock)
Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs when RES is
driven low.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
* NMI and IRQ0 to IRQ5
Figure 21A.1 Mode Transition Diagram
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 702 of 1042
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21A.1.1 Register Configuration
Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, and MSTPCR registers.
Table 21A.2 summarizes these registers.
Table 21A.2 Power-Down Mode Registers
Name Abbreviation R/W Initial Value Address*
Standby control register SBYCR R/W H'08 H'FDE4
System clo ck con tro l regi ster SCKCR R/W H'00 H'FD E6
Low power control register LPWRCR R/W H'00 H'FDEC
MSTPCRA R/W H'3F H'FDE8Module stop control register
A, B, C MSTPCRB R/W H'FF H'FDE9
MSTPCRC R/W H'FF H'FDEA
Note: *Lower 16 bits of the address.
21A.2 Register Desc riptions
21A.2.1 Standby Control Register (SBYCR)
Bit:76543210
SSBY STS2 STS1 STS0 OPE ———
Initial value:00001000
R/W : R/W R/W R/W R/W R/W ———
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is in itialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by
executing the SLEEP instruction, the operating mode is determined in combination with other
contro l bits.
Note that the value of the SSBY bit does not change even when shifting between modes using
interrupts.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 703 of 1042
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Bit 7
SSBY Description
0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed
mode or medium-speed mode. (Initial value)
1 Shifts to software standby mode when the SLEEP instru ction is executed in high-
speed mode or medium-speed mode.
Bits 6 to 4— St andby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time
for clock stabilization when shifting to high-speed mode or medium-speed mode by using a
specific interru pt or command to cancel software standby mod e . With a quartz oscillator (table
21A.4), select a wait time of 8ms (oscillation stabilization time) o r mo r e , depending o n the
operating frequency. With an external clock, there are no specific wait requirements.
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Standby time = 8192 states (Initial value)
1 Standby time = 16384 states
1 0 Standby time = 32768 states
1 Standby time = 65536 states
1 0 0 Standby time = 131072 states
1 Standby time = 262144 states
10Reserved
1 Standby time = 16 states
Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode.
Bit 3
OPE Description
0 In software standby mode, address bus and bus control signals are high-impedance.
1 In software standby mode, the output state of the address bus and bus control signals
is retained. (Initial value)
Bits 2 to 0—Reserved: These bits always return 0 when r ead, and cannot be written to.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 704 of 1042
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21A.2.2 Sy stem Clock Control Register (SCKCR)
Bit:76543210
PSTOP ———STCS SCK2 SCK1 SCK0
Initial value:00000000
R/W : R/W ———R/W R/W R/W R/W
SCKCR is an 8-bit readable/writab le r egister that performs φ clock output control and medium-
speed mode control.
SCKCR is in itialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ
φφ
φ Clock Output Disable (PSTOP) : I n combination with the DDR of the applicable port,
this bit con trols φ output. See section 21A.8, φ Clock Output Disable Function, for details.
Description
Bit 7
PSTOP High-Speed Mode,
Medium-Speed Mode Sleep Mode Software Standby
Mode Hardware Standby
Mode
0φ output (initial value) φ output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplicatio n F actor Switching Mode Select (STCS): Selects the operation
when the PLL circu it frequency multiplication factor is changed.
Bit 3
STCS Description
0 Specified multiplication factor is valid after transition to software standby mode
(Initial value)
1 Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, and medium-s peed mode.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 705 of 1042
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Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master in high-speed mode (Initial value)
1 Medium-speed clock is φ/2
1 0 Medium-spe ed clock is φ/4
1 Medium-speed clock is φ/8
1 0 0 Medium-speed clock is φ/16
1 Medium-speed clock is φ/32
1——
21A.2.3 Low-Power Control Reg ister (LPWRCR)
Bit:76543210
DTON LSON NESEL SUBSTP RFCUT —STC1 STC0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
The LPWRCR is an 8-bit read/write register that contro ls the low power dissipation modes.
The LPWRCR is initialized to H'00 at a reset and when in hardware stan dby mod e . It is not
initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,
see section 20.2.2, Low-Power Control Register (LPWRCR).
Bits 7 to 4—Reserved: Bits DTON, LSON, NESEL, and SUBSTP m ust always be written with 0
in the H8S/2623 Group, as this version does not support subclock operation.
Bit 3—Oscillation Circuit Feedback Resistance Contro l Bit (RFCUT): This bit tu rns the
internal feed back resistance of the main clock oscillation circuit ON/OFF.
Bit 3
RFCUT Description
0 When the main clock is oscillating, sets the feedback resistance ON. When the main
clock is stopped, sets the feedback resistance OFF. (Initial value)
1 Sets the feedback resistance OFF.
Bit 2—Reserved: Only write 0 to this bit.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 706 of 1042
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21A.2.4 Mo dule St op Control Register ( MSTPCR)
MSTPCRA
Bit:76543210
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value:00111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRB
Bit:76543210
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value:11111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRC
Bit:76543210
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value:11111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.
MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode.
They are not initialized in software standby mode.
MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0, MSTPC7 to MSTP C 0, MS TPD7 a nd MSTP D6): These bits specify
module stop mode. See table 21A.3 for the method of selecting the on-chip peripheral functions.
MSTPCRA/MSTPCRB/
MSTPCRC Bits 7 to 0
MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0,
MSTPC7 to MSTPC0 Description
0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)
1 Module stop mode is set (init ial value of MSTPA5–0, MSTPB7–0,
MSTPC7–0)
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 707 of 1042
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21A.3 Medium-Speed Mode
In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode
changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the
CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0
bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip
supporting modules other than the bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software
standby mode. When software standby mode is cleared by an external interrupt, medium-speed
mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 21A.2 shows the timing for transition to and clearance of medium-speed mode.
φ,
Bus master clock
supporting module clock
Internal address bus
Internal write signal
Medium-speed mode
SBYCRSBYCR
Figure 21A.2 Medium-Speed Mode Transition and Clearance Timing
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 708 of 1042
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21A.4 Sleep Mode
21A.4.1 Sleep Mode
When the SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the
sleep mode. In sleep mode, CPU operation stops but the contents of the CPUís internal registers
are retained. Other supporting modules do not stop.
21A.4.2 Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
Exiting Sleep Mode by Interrupts: When an interrupt occu r s, sleep m ode is exited and interrupt
exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other
than NMI are masked by the CPU.
Exiting Sleep Mode by RES
RESRES
RES pin: Setting th e RES pin level Lo w selects the reset state. After the
stipulated reset input duration, driving the RES pin High starts the CPU performing reset
exception processing.
Exiting Sleep Mode by STBY
STBYSTBY
STBY Pin: When the STBY pin level is driven Low, a transition is made
to hardware standby mode.
21A.5 Module Stop Mode
21A.5.1 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 21A.3 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI, A/D converter and HCAN are retained.
After reset clearance, all modules other than DTC are in module stop mode.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 709 of 1042
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When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Table 21A.3 MSTP Bits and Correspo nding On-Chip S upporting Modules
Register Bit Module
MSTPCRA MSTPA7*
MSTPA6 Data transfer controller (DTC)
MSTPA5 16-bit timer pulse unit (TPU)
MSTPA4*
MSTPA3 Programmable pul se gener ator (PPG)
MSTPA2*
MSTPA1 A/D converter
MSTPA0*
MSTPCRB MSTPB7 Serial communication inter f ace 0 (SCI0)
MSTPB6 Serial communication inter face 1 (SCI1)
MSTPB5 Serial communication inter face 2 (SCI2)
MSTPB4*
MSTPB3*
MSTPB2*
MSTPB1*
MSTPB0*
MSTPCRC MSTPC7*
MSTPC6*
MSTPC5*
MSTPC4 PC break controller (PBC)
MSTPC3 HCAN
MSTPC2*
MSTPC1*
MSTPC0*
Note: *MSTPA7 is a readable/writable bit with an init ial val ue of 0.
MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, and
MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should
always be written with 1.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 710 of 1042
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21A.5.2 Usage Notes
DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6
bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when
the respective m odule is not activated.
For details, ref e r to section 8, Data Transfer Con tr oller (DTC).
On-Chip Supporting Module Interrupt: Relevant interrupt op erations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt sou r ce or th e DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
21A.6 Software Standby Mode
21A.6.1 So ftware Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SBYCR SSBY bit = 1. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI, A/D converter, HCAN and I/O ports, are retained.
Whether the address bus and bus control signals are placed in the high-impedance state or retain
the output state can be specified by the OPE bit in SBYCR.
In this mo de the oscillator stops, and therefore power dissipation is significantly reduced.
21A.6.2 Clea ring Software St andby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by
means of the RES pin or STBY pin.
• Clearing with an interrupt
When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensur e that no interrupt with a higher prio r ity than interrupts I RQ0 to IRQ5
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 711 of 1042
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• Clearing with the RES pin
When the RES pin is dr iven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held
low until cloc k oscillation stabilizes. Wh en the RES pin goes high, the CPU begins reset
exception handling.
• Clearing with the STBY pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
21A.6.3 Set t ing Oscillation Sta biliza tion Time after Clea ring Software St andby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crysta l Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 m s ( th e
oscillation stabilizatio n time).
Table 21A.4 shows the standby times for different operating frequencies and settings of bits STS2
to STS0.
Table 21A.4 Oscillation Stabiliza t ion Time Settings
STS2 STS1 STS0 Standby Time 20
MHz 16
MHz 12
MHz 10
MHz 8
MHz 6
MHz 4
MHz Unit
0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 ms
1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1
1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2
1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4
1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8
1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6
10Reserved ———————µs
1 16 states*0.8 1.0 1.3 1.6 2.0 1.7 4.0
: Recommended time setting
Note: *Do not use this setting.
Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore,
the standby time should be set to a value of 2 ms or greater.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 712 of 1042
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21A.6.4 Software Sta ndby Mode Applicatio n Example
Figure 21A.3 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG = 1
SSBY = 1
SLEEP instruction
Software standby mode
(power-down mode) Oscillation
stabilization
time t
OSC2
NMI exception
handling
Figure 21A.3 Soft ware Standby Mode Application Example
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 713 of 1042
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21A.6.5 Usage Notes
I/O Port St atus: In software standby mode, I/O port states are retained. If the OPE bit is set to 1,
the address bus and bus control signal output is also retained. Therefore, there is no reduction in
current dissipation for the output current when a high-level signal is output.
Current Dissipation during Oscillation Stabilizat ion Wait Period: Current dissipation
increases dur ing the oscillation stabilization wait period.
Write Data Buffer Function: The write data buffer function and software standby mode cannot
be used at the sa me time. When the write data buffer function is used, th e WD BE bit in BCRL
should be cleared to 0 to cancel the write data buffer function before entering software standby
mode. Also check that external writes have finished, by reading external addresses, etc., before
executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer
Function, for details of the write data buffer function.
21A.7 Hardware Standby Mode
21A.7.1 H ardware Standby Mo de
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resu lting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I /O ports are set to the high -impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD2 to MD0) while the H8S/2623 Group is in
hardware standby mode.
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set an d clock oscillation is started.
Ensure that th e RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the
oscillation stabilizatio n time—when using a cr ystal oscillator). When the RES pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
Section 21A Power-Down Modes [H8S/2623 Group]
Rev. 5.00 Jan 10, 2006 page 714 of 1042
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21A.7.2 H ardware Standby Mode Timing
Figure 21A.4 shows an example of hardware standby mode timing.
When the STBY pin is dr iven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation stabilization time, then ch angin g the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 21A.4 Hardwa re Standby Mode Timing
21A.8 φ
φφ
φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
correspo nding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 21A.5 shows the state of the φ pin in each processing state.
Table 21A.5 φ
φφ
φ Pin State in Each P r ocessing State
DDR 0 1 1
PSTOP —01
Hardware standby mode High impedance High impedance High impedance
Software standby High impedance Fixed high Fixed high
Sleep mode High impedance φ output Fixed high
High-speed mode, medium-speed
mode High impedance φ output Fixed high
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 715 of 1042
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Section 21B Power-Do w n Mo des
[H8 S/262 6 Group]
21B.1 Overview
In addition to the normal program executio n state, the H8S/2626 Group h as nine power-do wn
modes in which operation of the CPU an d oscillator is halted and power dissipation is reduced.
Low-power operation can be achieved by individually controlling the CPU, on-chip supporting
modules, and so on.
The H8S/2626 operating modes are as follows:
(1) High-speed mode
(2) Medium-speed mode
(3) Subactive mode*
(4) Sleep mode
(5) Subsleep mode*
(6) Watch mode*
(7) Module stop mode
(8) Software standby mode
(9) Hardware standby mode
(2) to (9) are power-down modes. Sleep mode and sub-sleep mode are CPU states, medium-speed
mode is a CPU and bus master state, sub-active mode is a CPU and bus master and internal
peripheral function state, and module stop mode is an internal peripheral function (including bus
masters other than the CPU) state. Some of these states can be combined .
After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop
mode.
Note: * Subclock functions are available in the H8S/2626 Group.
See section 20.7, Subclock Oscillator (H8S/2626 Group Only), for the method of fixing
pins OSC1 and OSC2 when not used.
Table 21B.1 shows the internal state of the LSI in the respective modes. Table 21B.2 shows the
conditions for shifting between the power-down modes.
Figure 21B.1 is a mode transition diagram.
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 716 of 1042
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Table 21B.1 LSI Internal States in Each Mode
Function High-
Speed Medium-
Speed Sleep Module
Stop Watch Sub-
active Subsleep Software
Standby Hardware
Standby
System clock pulse
generator Function-
ing Function-
ing Function-
ing Function-
ing Halted Halted Halted Halted Halted
Subclock pulse
generator Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Halted
CPU Instructions
Registers Function-
ing Medium-
speed
operation
Halted
(retained) High/
medium-
speed
operation
Halted
(retained) Subclock
operation Halted
(retained) Halted
(retained) Halted
(undefined)
NMIExternal
interrupts IRQ0–IRQ5
Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Function-
ing Halted
Peripheral
functions WDT1 Function-
ing Function-
ing Function-
ing Subclock
operation Subclock
operation Subclock
operation Halted
(retained) Halted
(reset)
WDT0 Function-
ing Function-
ing Function-
ing Halted
(retained) Subclock
operation Subclock
operation Halted
(retained) Halted
(reset)
DTC Function-
ing Medium-
speed
operation
Function-
ing Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained) Halted
(reset)
TPU
PBC
PPG
D/A2, 3
Function-
ing Function-
ing (PBC
medium-
speed
operation)
Function-
ing Halted
(retained) Halted
(retained) Halted
(retained)
(PBC
subclock
operation)
Halted
(retained) Halted
(retained) Halted
(reset)
SCI0
SCI1
SCI2
PWM
A/D
Function-
ing Function-
ing Function-
ing Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
RAM Function-
ing Function-
ing Function-
ing (DTC) Function-
ing Retained Function-
ing Retained Retained Retained
I/O Function-
ing Function-
ing Function-
ing Function-
ing Retained Function-
ing Retained Retained High
impedance
HCAN Function-
ing Function-
ing*Function-
ing Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
Notes: “Halted (retained)” means that internal register values are retained. The internal state is
“operation su spe nde d.”
“Halted (reset)” means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
* Note, however, that registers cannot be read or written to.
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 717 of 1042
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Program-halted state
Program execution state
SCK2 to
SCK0= 0 SCK2 to
SCK0 0
SLEEP command
SSBY = 1, PSS = 1
DTON = 1, LSON = 1
Clock switching
exception processing
SLEEP command
SSBY = 1, PSS = 1
DTON = 1, LSON = 0
After the oscillation
stabilization time
(STS2 to 0), clock
switching exception
processing
SLEEP command
SLEEP
command
External
interrupt*
3
Any interrupt
SLEEP
command
SLEEP
command
SLEEP command
Interrupt*
1
LSON bit = 0
Interrupt*
2
Interrupt*
1
LSON bit = 1
STBY pin = High
RES pin = Low
STBY pin = Low
SSBY = 0, LSON = 0
SSBY = 1,
PSS = 0, LSON = 0
SSBY = 0,
PSS = 1, LSON = 1
SSBY = 1,
PSS = 1, DTON = 0
RES pin = High
: Transition after exception processing : Power-down mode
Reset state
High-speed mode
(main clock)
Medium-speed
mode
(main clock)
Sub-active mode
(subclock) Sub-sleep mode
(subclock)
Hardware
standby mode
Software
standby mode
Sleep mode
(main clock)
Watch mode
(subclock)
Notes:
1.
2.
3.
When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs when RES is
driven Low.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
Always select high-speed mode before making a transition to watch mode or sub-active mode.
NMI, IRQ0 to IRQ5, and WDT1 interrupts
NMI, IRQ0 to IRQ5, WDT0 interrupts, and WDT1 interrupt.
NMI and IRQ0 to IRQ5
Figure 21B.1 Mode Transition Diagram
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 718 of 1042
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Table 21B.2 Power-Down Mode Transition Conditions
Status of Control Bit at
Transition
Pre-Transition
State SSBY PSS LSON DTON
State After Transition
Invoked by SLEEP
Command
State After Transition
Back from Power-Down
Mode Invoked by
Interrupt
0*0*Sleep High-speed/Medium-speedHigh-speed/
Medium-speed 0*1*——
100*Software standb y High-speed/Medium-s pee d
101*——
1100Watch High-speed
1110Watch Sub-active
1101——
1111Sub-active —
Sub-active 0 0 **——
010*——
011*Sub-sleep Sub-active
10**——
1100Watch High-speed
1110Watch Sub-active
1101High-speed —
1111——
Legend:
—: Do not set.
*:Don’t care
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 719 of 1042
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21B.1.1 Register Configuration
Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and
MSTPCR registers. Table 21B.3 summarizes these registers.
Table 21B.3 Power-Down Mode Registers
Name Abbreviation R/W Initial Value Address*
Standby control register SBYCR R/W H'08 H'FDE4
System clo ck con tro l regi ster SCKCR R/W H'00 H'FDE6
Low-power control r egi ster LPWRCR R/W H'00 H'FDEC
Timer control/status register TCSR R/W H'00 H'FFA2
MSTPCRA R/W H'3F H'FDE8
MSTPCRB R/W H'FF H'FDE9
Module stop control register
A, B, C
MSTPCRC R/W H'FF H'FDEA
Note: *Lower 16 bits of the address .
21B.2 Register Descriptions
21B.2.1 Standby Control Register (SBYCR)
Bit:76543210
SSBY STS2 STS1 STS0 OPE ———
Initial value:00001000
R/W : R/W R/W R/W R/W R/W ———
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is in itialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by
executing the SLEEP instruction, the operating mode is determined in combination with other
contro l bits.
Note that the value of the SSBY bit does not change even when shifting between modes using
interrupts.
Bit 7
SSBY Description
0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed
mode or medium-speed mode.
Shifts to sub-sleep mode when the SLEEP instruction is executed in
sub-active mode. (Initial value)
1 Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP
instruction is executed in high-speed mode or medium-speed mode.
Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in
sub-active mode .
Bits 6 to 4— St andby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time
for clock stabilization when shifting to high-speed mode or medium-speed mode by using a
specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode.
With a quartz o scillato r (table 21B.5), select a wait time of 8ms (oscillation stab ilization time) or
more, depending on the operating frequency. With an external clock, there are no specific wait
requirements.
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Standby time = 8192 states (Initial value)
1 Standby time = 16384 states
1 0 Standby time = 32768 states
1 Standby time = 65536 states
1 0 0 Standby time = 131072 states
1 Standby time = 262144 states
10Reserved
1 Standby time = 16 states
Section 21B Power-Down Modes [H8S/2626 Group]
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Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode, watch mode, and when making a direct transition.
Bit 3
OPE Description
0 In software standby mode, watch mode, and when making a direct transition, address
bus and bus control signa ls are high-impedance.
1 In software standby mode, watch mode, and when making a direct transition, the
output state of the address bus and bus control signals is retained. (Initial value)
Bits 2 to 0—Reserved: These bits always return 0 when r ead, and cannot be written to.
21B.2.2 System Clock Control Register (SCKCR)
Bit:76543210
PSTOP ———STCS SCK2 SCK1 SCK0
Initial value:00000000
R/W : R/W ———R/W R/W R/W R/W
SCKCR is an 8-bit readable/writab le r egister that performs φ clock output control and medium-
speed mode control.
SCKCR is in itialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ
φφ
φ Clock Output Disable (PSTOP) : I n combination with th e DDR of the applicable port,
this bit con trols φ output. See section 21B.12, φ Clock Output Disabling Function, for details.
Description
Bit 7
PSTOP
High-Speed Mode,
Medium-Speed Mode,
Sub-Active Mode Sleep Mode,
Sub-Sleep Mode
Software Standby
Mode, Watch Mode,
Direct Transition Hardware
Standby Mode
0φ output (initial value) φ output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Section 21B Power-Down Modes [H8S/2626 Group]
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Bit 3—Frequency Multiplicatio n F actor Switching Mode Select (STCS): Selects the operation
when the PLL circu it frequency multiplication factor is changed.
Bit 3
STCS Description
0 Specified multiplication factor is valid afte r transition to software standby mode, watch
mode, or subactive mode (Initial value)
1 Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, medium-speed mode, and sub-active mode.
Set SCK2 to SCK0 all to 0 when shif ting to operation in watch mode or sub -active mode.
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master in high-speed mode (Initial value)
1 Medium-speed clock is φ/2
1 0 Medium-spe ed clock is φ/4
1 Medium-speed clock is φ/8
1 0 0 Medium-speed clock is φ/16
1 Medium-speed clock is φ/32
1——
21B.2.3 Low-Power Control Register (LPWRCR)
Bit:76543210
DTON LSON NESEL SUBSTP RFCUT —STC1 STC0
Initial value:00000000
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
The LPWRCR is an 8-bit read/write register that contro ls the low power dissipation modes.
The LPWRCR is in itialized to H'00 at a reset and when in hardware standby mod e . It is not
initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,
see section 20.2.2, Low-Power Control Register (LPWRCR).
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Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by
executing the SLEEP instruction, this bit specifies whether or not to make a direct transition
between high-speed mode or medium-speed mode and the sub-active modes. The selected
operating mode after executing the SLEEP instruction is determined by the combination of other
contro l bits.
Bit 7
DTON Description
0• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, software standby mode, or watch mode*.
• When the SLEEP instruction is executed in sub-active mode, operation shifts
to sub-sleep mode or watch mode. (Initial value)
1• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shif ts dire ctly to sub-active mode*, or shifts to sleep mode or
software standby mode.
• When the SLEEP instruction is executed in sub-active mode, operation shifts di rectly
to high-speed mode, or shifts to sub-sleep mode.
Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.
Bit 6—Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing
the SLEEP instruction, this bit specifies the operating mode, in combination with other control
bits. This bit also controls whethe r to shif t to high-speed mode or su b-activ e m ode wh en watch
mode is cancelled.
Bit 6
LSON Description
0• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, software standby mode, or watch mode*.
• When the SLEEP instruction is executed in sub-active mode, operation shifts to
watch mode or shifts directly to high-speed mode.
• Operation shifts to high-speed mode when watch mode is cancelled. (Initial value)
1• When the SLEEP instruction is executed in high-speed mode, operation shifts to
watch mode or sub-active mode.
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
sleep mode or watch mode.
• Operation shifts to sub-active mode when watch mode is cancelled.
Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.
Section 21B Power-Down Modes [H8S/2626 Group]
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Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the samp ling
frequency of the subclock (φSUB) gener a ted by the subclock oscillator is sampled by the clock (φ)
generated by the system clock oscillator . Set this bit to 0 when φ=5MHz or more.
Bit 5
NESEL Description
0 Sampling using 1/32 xφ (Initial value)
1 Sampling using 1/4 xφ
Bit 4—Subc lock enable (SUBSTP) : This bit enables/disables subclock generation.
Bit 4
SUBSTP Description
0 Enables subclo ck generat ion (Initial val ue)
1 Disables subclock generation
Bit 3—Oscillation Circuit Feedback Resistance Contro l Bit (RFCUT): This bit tu rns the
internal feed back resistance of the main clock oscillation circuit ON/OFF.
Bit 3
RFCUT Description
0 When the main clock is oscillating, sets the feedback resistance ON. When the main
clock is stopped, sets the feedback resistance OFF. (Initial value)
1 Sets the feedback resistance OFF.
Bit 2—Reserved: Only write 0 to this bit.
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.2.4 Timer Control/Status Register (TCSR)
Bit:76543210
OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0
Initial value:00000000
R/W : R/(W)*R/W R/W R/W R/W R/W R/W R/W
Note: *Only write 0 to clear the flag.
TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.
Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer
Contro l/Status Register (T CSR).
The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized
in software standby mode.
Bit 4—Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT.
It also controls operation when shifting low power dissipation modes. Th e operating mode
selected after the SLEEP instruction is executed is determined in combination with other control
bits.
For details, see the description for clock selection in section 12 .2.2, Timer Control/Statu s Register
(TCSR), and this section.
Bit 4
PSS Description
0• TCNT counts the divided clock from the φ -based prescaler (PSM).
• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode or software standby mode. (Initial value)
1• TCNT counts the divided clock from the φsubclock-based prescaler (PSS).
• When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, watch mode*, or sub-active mode*.
• When the SLEEP instruction is executed in sub-active mode*, o perat ion sh ifts to
sub-sleep mode*, watch mode*, or high-speed mode.
Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.2.5 Module Stop Control Register (MSTPCR)
MSTPCRA
Bit:76543210
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value:00111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRB
Bit:76543210
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value:11111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCRC
Bit:76543210
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value:11111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.
MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode.
They are not initialized in software standby mode.
MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0, MSTPC 7 to MSTPC0): These bits specify module stop mode. See table
21B.4 for the method of selecting the on-chip peripheral functions.
MSTPCRA/MSTPCRB/
MSTPCRC Bits 7 to 0
MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0,
MSTPC7 to MSTPC0 Description
0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)
1 Module stop mode is set (init ial value of MSTPA5–0, MSTPB7–0,
MSTPC7–0)
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.3 Medium-Speed Mode
In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode
changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the
CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0
bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip
supporting modules other than the bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in
LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an
interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and
TCSR (WDT1) PSS bit = 0, operation shif ts to the software standby mode. When software
standby mode is cleared by an external interrupt, medium-speed mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 21B.2 shows the timing for transition to and clearance of medium-speed mode.
φ,
Bus master clock
supporting module clock
Internal address bus
Internal write signal
Medium-speed mode
SBYCRSBYCR
Figure 21B.2 Medium-Speed Mode Transition and Clearance Timing
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.4 Sleep Mode
21B.4.1 Sleep Mode
When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR
LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU’s internal registers are retained. Other supporting modules do not stop.
21B.4.2 Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
Exiting Sleep Mode by Interrupts: When an interrupt occu r s, sleep m ode is exited and interrupt
exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other
than NMI are masked by the CPU.
Exiting Sleep Mode by RES
RESRES
RES pin: Setting th e RES pin level Lo w selects the reset state. After the
stipulated reset input duration, driving the RES pin High starts the CPU performing reset
exception processing.
Exiting Sleep Mode by STBY
STBYSTBY
STBY Pin: When the STBY pin level is driven Low, a transition is made
to hardware standby mode.
21B.5 Module Stop Mode
21B.5.1 Module St op Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 21B.4 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI, A/D converter and HCAN are retained.
After reset clearance, all modules other than DTC are in module stop mode.
Section 21B Power-Down Modes [H8S/2626 Group]
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When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Table 21B.4 MSTP Bits and Corresponding On-Chip Supporting Modules
Register Bit Module
MSTPCRA MSTPA7*
MSTPA6 Data transfer controller (DTC)
MSTPA5 16-bit timer pulse unit (TPU)
MSTPA4*
MSTPA3 Programmable pul se gener ator (PPG)
MSTPA2*
MSTPA1 A/D converter
MSTPA0*
MSTPCRB MSTPB7 Serial communication inter f ace 0 (SCI0)
MSTPB6 Serial communication inter face 1 (SCI1)
MSTPB5 Serial communication inter face 2 (SCI2)
MSTPB4*
MSTPB3*
MSTPB2*
MSTPB1*
MSTPB0*
MSTPCRC MSTPC7*
MSTPC6*
MSTPC5 D/A converter (channels 2, 3)
MSTPC4 PC break controller (PBC)
MSTPC3 HCAN
MSTPC2*
MSTPC1*
MSTPC0*
Note: *MSTPA7 is a readable/writable bit with an init ial val ue of 0.
MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC4, and
MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should
always be written with 1.
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 730 of 1042
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21B.5.2 Usage Notes
DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6
bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when
the respective m odule is not activated.
For details, ref e r to section 8, Data Transfer Con tr oller (DTC).
On-Chip Supporting Module Interrupt: Relevant interrupt op erations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt sou r ce or th e DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
21B.6 Software Standby Mode
21B.6.1 Soft ware Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SBYCR SSBY bit = 1 and the LPWRCR LSON b it = 0, and the TCSR (WDT1) PSS bit = 0. In
this mode, the CPU, on-chip supporting modules, and oscillator all sto p. However, the contents of
the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than
the SCI, A/D converter, HCAN and I/O ports, are retained. Whether the address bus and bus
control signals are placed in the high-impedance state or retain the output state can be specified by
the OPE bit in SBYC R.
In this mo de the oscillator stops, and therefore power dissipation is significantly reduced.
21B.6.2 Clearing Software Sta ndby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by
means of the RES pin or STBY pin.
• Clearing with an interrupt
When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensur e that no interrupt with a higher prio r ity than interrupts I RQ0 to IRQ5
Section 21B Power-Down Modes [H8S/2626 Group]
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is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
• Clearing with the RES pin
When the RES pin is dr iv en Low, clock oscillation is started. At the sam e tim e as clock
oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held
Low until clock oscillation stabilizes. When th e RES pin goes high, the CPU begins reset
exception handling.
• Clearing with the STBY pin
When the STBY pin is driven Low, a transition is made to hardware standby mode.
21B.6.3 Setting Oscillation Stabilization Time after Clea ring Software St andby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crysta l Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 m s ( th e
oscillation stabilizatio n time).
Table 21B.5 shows the standby times for different operating frequencies and settings of bits STS2
to STS0.
Table 21B.5 O scilla t ion Stabilizatio n Time Set tings
STS2 STS1 STS0 Standby Time 20
MHz 16
MHz 12
MHz 10
MHz 8
MHz 6
MHz 4
MHz Unit
0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 ms
1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1
1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2
1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4
1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8
1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6
10Reserved ———————µs
1 16 states*0.8 1.0 1.3 1.6 2.0 1.7 4.0
: Recommended time setting
Note: *Do not use this setting.
Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore,
the standby time should be set to a value of 2 ms or greater.
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.6.4 Software Standby Mode Application Ex ample
Figure 21B.3 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG = 1
SSBY = 1
SLEEP instruction
Software standby mode
(power-down mode) Oscillation
stabilization
time t
OSC2
NMI exception
handling
Figure 21B.3 So ftwa re Standby Mode Application Example
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.6.5 Usage Notes
I/O Port St atus: In software standby mode, I/O port states are retained. If the OPE bit is set to 1,
the address bus and bus control signal output is also retained. Therefore, there is no reduction in
current dissipation for the output current when a high-level signal is output.
Current Dissipation during Oscillation Stabilizat ion Wait Period: Current dissipation
increases dur ing the oscillation stabilization wait period.
Write Data Buffer Function: The write data buffer function and software standby mode cannot
be used at the sa me time. When the write data buffer function is used, th e WD BE bit in BCRL
should be cleared to 0 to cancel the write data buffer function before entering software standby
mode. Also check that external writes have finished, by reading external addresses, etc., before
executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer
Function, for details of the write data buffer function.
21B.7 Hardware Standby Mode
21B.7.1 Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I /O ports are set to the high -impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD2 to MD0) while the H8S/2626 Group is in
hardware standby mode.
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set an d clock oscillation is started.
Ensure that th e RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the
oscillation stabilizatio n time—when using a cr ystal oscillator). When the RES pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.7.2 Hardware Standby Mode Timing
Figure 21B.4 shows an example of hardware standby mode timing.
When the STBY pin is dr iven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation stabilization time, then ch angin g the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 21B.4 Hardware St andby Mode Timing
21B.8 Watch Mode
21B.8.1 Watch Mode
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or sub- active mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR
(WDT1) PSS = 1.
In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped.
The contents of the CPU is internal registers, th e data in internal RAM, and th e statuses of the
internal supporting modules (excluding the SCI, ADC, HCAN) and I/O ports are retained.
Section 21B Power-Down Modes [H8S/2626 Group]
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21B.8.2 Exiting Watch Mo de
Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at
the RES, or STBY pins.
(1) Exiting Watch Mode by Interrupts
When an interr upt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit
= 1. When a transitio n is made to h igh- speed mode, a stable clock is supplied to all LSI circu its
and interrup t exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed.
In the case of IRQ0 to IRQ5 in terru p ts, no tr ansition is made from watch mo de if the
corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal
supporting modules, the interrupt enable register has been set to disable the reception of that
interrupt, or is masked by the CPU.
See section 21B.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode,
for how to set the oscillation stabilization tim e when making a transition from watch mode to
high-speed mode.
(2) Ex iting Watch Mode by RES
RESRES
RES pins
For exiting watch mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2,
Clearing Software Standby Mode.
(3) Ex iting Watch Mode by STBY
STBYSTBY
STBY pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
21B.8.3 Notes
(1) I/O Port Status
The status of the I /O ports is r etained in watch mode. Also, when the OPE bit is set to 1, the
address bus and bus control signals continue to be output. Therefore, when a High level is output,
the current consumption is not diminished by the amount of current to support the High level
output.
(2) Current Consumption when Waiting for Oscillation Sta bilization
The current consu mptio n increases during stabilization of oscillation.
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 736 of 1042
REJ09B0275-0500
21B.9 Sub-Sleep Mode
21B.9.1 Sub-Sleep Mode
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR (WDT1) PSS bit = 1, CPU ope r a tion shifts to sub-sleep mode .
In sub-sleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are
also stopped. The contents of the CPUís internal registers, the data in internal RAM, and the
statuses of the internal supporting modules (excluding the SCI, ADC, HCAN) and I/O ports are
retained.
21B.9.2 Exiting Sub-Slee p Mode
Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or
IRQ0 to IRQ5), or signals at the RES or STBY pins.
(1) Exiting Sub-Sleep Mode by Interrupts
When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts.
In the case of IRQ0 to IRQ5 interrupts, sub-sleep mode is not cancelled if the corresponding
enable bit has been cleared to 0, and, in the case of interrupts fr om the internal supporting
modules, the interrupt enable register has been set to disable the reception of that interrupt, or is
masked by the CPU.
(2) Exiting Sub-Sleep Mode by RES
RESRES
RES
For exiting sub-sleep mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2,
Clearing Software Standby Mode.
(3) Exiting Sub-Sleep Mode by STBY
STBYSTBY
STBY Pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 737 of 1042
REJ09B0275-0500
21B.10 Sub-Active Mode
21B.10.1 Sub-Active Mo de
When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU o peration sh if ts to
sub-active m o de. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1,
a transition is m ade to sub-active mode. An d if an interrupt occurs in sub-sleep m ode, a tr ansition
is made to sub-active mode.
In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Supporting modules other than WDT0, and WDT1 are also stopped.
When op erating the CPU in sub -active mode, the SCKCR SCK2 to SCK0 bits must be set to 0.
21B.10 . 2 Exiting Sub-Act ive Mode
Sub-active mode is exited by the SLEEP instruction or the RES or STBY pins.
(1) Exiting Sub-Activ e Mode by SLEEP Instruction
When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit =
0, and TCSR (WDT1) PSS bit = 1, the CPU exits sub-active mode and a transition is made to
watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR
LSON bit = 1, and TCSR ( WDT1 ) PSS bit = 1, a transition is made to sub - sleep mode. Finally,
when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1,
LSON bit = 0, and TCSR ( WDT1 ) PSS bit = 1, a direct tran sition is made to high - sp eed mode
(SCK0 to SCK2 all 0).
See section 21B.11, Direct Transitions, for details of direct transitions.
(2) Exiting Sub-Activ e Mode by RES
RESRES
RES Pins
For exiting sub-active mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2,
Clearing Software Standby Mode.
(3) Exiting Sub-Activ e Mode by STBY
STBYSTBY
STBY Pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 738 of 1042
REJ09B0275-0500
21B.11 Direct Transitions
21B.11.1 Overview of Direct Transitions
There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution when
shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the
LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
(1) Direct Transitions from High-Speed Mode to Sub-Active Mode
Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 1, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a tran sition to sub-
active mode.
(2) Direct Transitions from Sub-Active Mode to High-Speed Mode
Execute the SLEEP instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 0, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct tr ansition to
high-speed mode after the tim e set in SBYCR STS2 to STS0 has elapsed.
21B.12 φ
φφ
φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
correspo nding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 21B.6 shows the state of the φ pin in each processing state.
Table 21B.6 φ
φφ
φ Pin State in Each Pr ocessing State
DDR 0 1 1
PSTOP —01
Hardware standby mode High impedance High impedance High impedance
Software standby mode, watch
mode, and direct transition High impedance Fixed high Fixed high
Sleep mode and subsleep mode High impedance φ output Fixed high
High-speed mode, medium-speed
mode, and subactive mode High impedance φ output Fixed high
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 739 of 1042
REJ09B0275-0500
21B.13 Usage Notes
1. When making a transition to sub-active mode or watch mode, set the DTC to enter module
stop mod e ( write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm
that they are set to 1 before m ode tr ansition. Do not clear module stop mod e (write 0 to the
relevant b its in MSTPCR) until a tran sition from sub-active mode to high-speed mode or
medium-speed mode has been performed.
If a DTC activation source occurs in sub-activ e mod e , the DTC will be activated only after
module stop mode has been cleared and high-speed mode or medium-speed mode has been
entered.
2. The on-chip peripheral modules (DTC and TPU) which halt operation in sub-active mode
cannot clear an interrupt in sub-active mode. Therefore, if a transition is made to sub-active
mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the
interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter
sub-active mode or watch mode.
Section 21B Power-Down Modes [H8S/2626 Group]
Rev. 5.00 Jan 10, 2006 page 740 of 1042
REJ09B0275-0500
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 741 of 1042
REJ09B0275-0500
Section 22 Electrical Characteristics (Preliminary)
22.1 Absolute Maximum Ratings
Table 22.1 lists the ab solute maximum ratings.
Table 22.1 Absolute Maximum Ratings — Preliminary —
Item Symbol Value Unit
Power supply voltage VCC
PLLVCC
–0.3 to +4.3 V
PVCC1–4 –0.3 to +7.0 V
Input voltage (XTAL, EXTAL,
OSC1, OSC2) Vin –0.3 to VCC +0.3 V
Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V
Input voltage (except ports 4 and 9) Vin –0.3 to PVCC +0.3 V
Reference volt age Vref –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 742 of 1042
REJ09B0275-0500
22.2 DC Characteristics
Table 22.2 lists the DC characteristics. Table 22.3 lists the permissible output currents.
Table 22.2 DC Characteristics — Preliminary —
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)*1
Item Symbol Min Typ Max Unit Test
Conditions
IRQ0 to IRQ5 VT–PVCC × 0.2——V
VT+——PV
CC × 0.7 V
Schmitt
trigger input
voltage VT+ – VT–PVCC × 0.05 — — V
Input high
voltage RES, STBY,
NMI, MD2
to MD0, FWE
VIH PVCC × 0.9 — PVCC + 0.3 V
EXTAL, OSC1 VCC × 0.7 — VCC + 0.3 V
Ports 1, A to
F, HRxD PVCC × 0.7 — PVCC + 0.3 V
Port 4 and 9 AVCC × 0.7 — AVCC + 0.3 V
Input low
voltage RES, STBY,
NMI,
MD2 to MD0,
FWE
VIL –0.3 — PVCC × 0.1 V
EXTAL, OSC1 –0.3 — VCC × 0.2 V
Ports 1, A to
F, HRxD –0.3 — PVCC × 0.2 V
Ports 4 and 9 –0.3 — AVCC × 0.2 V
All output pins VOH PVCC – 0.5 — — V IOH = –200 µAOutput high
voltage PVCC – 1.0 — — V IOH = –1 mA
Output low
voltage All output pins VOL ——0.4VI
OL = 1.6 mA
RES | Iin | — — 1.0 µAInput leakage
current STBY, NMI,
HRxD, MD2 to
MD0, FW E
——1.0µA
Vin = 0.5 to
PVCC – 0.5 V
Ports 4 and 9 — — 1.0 µA Vin = 0.5 to
AVCC – 0.5 V
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 743 of 1042
REJ09B0275-0500
Item Symbol Min Typ Max Unit Test
Conditions
Three-state
leakage
current
(off state)
Ports 1, A to F ITSI——1.0µAV
in = 0.5 to
PVCC – 0.5 V
MOS input
pull-up curre nt Ports A to E –IP30 — 300 µA Vin = 0 V
RES Cin — — 30 pFInput
capacitance NMI — — 30 pF
All input pins
except RES
and NMI
— — 15 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Current
dissipation*2Normal
operation ICC*4—55
VCC = 3.3 V 65
VCC = 3.6 V mA f = 20 MHz
Sleep mode — 40
VCC = 3.3 V 50
VCC = 3.6 V mA f = 20 MHz
All modules
stopped — 40 — mA f = 2 0 MHz,
VCC = 3.3 V
(reference
values)
Medium-
speed mode
(φ/32)
— 30 — mA f = 20 MHz,
VCC = 3.3 V
(reference
values)
Subactive
mode —90
VCC = 3.3 V 200 µA Using 32.768
kHz crystal
resonator
Subsleep
mode —60
VCC = 3.3 V 120 µA Using 32.768
kHz crystal
resonator
Watch mode — 12
VCC = 3.3 V 30 µA Using 32.768
kHz crystal
resonator
—2.05.0µAT
a ≤ 50°CStandby
mode*3— — 20 µA 50°C < Ta
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 744 of 1042
REJ09B0275-0500
Item Symbol Min Typ Max Unit Test
Conditions
Port power
supply
current
During
operation PICC —15
PVCC =
5.0 V
20
PVCC =
5.5 V
mA
In standby
mode*3——5.0
PVCC =
5.5 V
µA
Analog
power supply
current
During A/D
and D/A
conversion
AlCC —1.02.0mAAV
CC = 5.0 V
Idle — — 5.0 µA
Reference
power supply
current
During A/D
and D/A
conversion
AlCC —2.54.0mAV
ref = 5.0 V
Idle — — 5.0 µA
RAM standby voltage VRAM 2.0——V
Notes: 1. If the A/D and D/A converter is not used, do not leave the AVCC, Vref , and AVSS pins
open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pi ns by con nec ting
them to PVCC, for instance. Set Vref ≤ AVCC.
2. Current dissipation values are for VIH = VCC (EXTAL, OSC1), AVCC (ports 4 and 9), or
PVCC (other), and VIL = 0 V, with all output pins unloaded and the on-chip MOS pull-up
transistors in the off state.
3. The values are for VRAM ≤ PVCC < 3. 0 V, VIH min = VCC – 0.1 V, and VIL max = 0.1 V.
4. ICC depends on VCC and f as follows:
ICC max = 8.0 (mA) + 0.8 (mA/(MHz × V)) × VCC × f (normal operation)
ICC max = 8.0 (mA) + 0.58 (mA/(MHz × V)) × VCC × f (sleep mode)
5. Applies to the mask ROM version only.
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 745 of 1042
REJ09B0275-0500
Table 22.3 Permissible Output C urrents — Preliminary —
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)*
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) All output
pins PVCC = 4.5 V to 5.5 V IOL ——10mA
Permissible output
low current (total) Total of all
output pins PVCC = 4.5 V to 5.5 V ∑ IOL — — 100 mA
Permissible output
high current (per pin) All output
pins PVCC = 4.5 V to 5.5 V –IOH ——2.0mA
Permissible output
high current (total) Total of all
output pins PVCC = 4.5 V to 5.5 V ∑ –IOH ——30mA
Note: *To protect chip reliability, do not exceed the output current values in table 22.3.
22.3 AC Characteristics
Figure 22.1 show, the test conditions for the AC characteristics.
3V
RL
RH
C
LSI output pin
C = 50 pF: Ports 10 to 13, A to F
(In case of expansion bus control signal output pin setting)
C = 30 pF: All ports
RL = 2.4 kΩ
RH = 12 kΩ
Input/output timing measurement levels
• Low level : 0.8 V
• High level : 2.0 V
Figure 22.1 Output Load Circuit
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 746 of 1042
REJ09B0275-0500
22.3.1 Clock Timing
Table 22.4 lists the clo ck timing
Table 22.4 Clock Timing — Preliminary —
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
Clock cycle time tcyc 50 250 ns Figure 22.2
Clock high pulse width tCH 15 —ns
Clock low pulse width tCL 15 —ns
Clock rise time tCr —5ns
Clock fall time tCf —5ns
Oscillation stabilization time at
reset (crystal) tOSC1 20 —ms Figure 22.3
Oscillation stabilization time in
software standby (crystal) tOSC2 8 — ms Figure 21A.3,
Figure 21B.3
External clock output stabili zati on
delay time tDEXT 2 — ms Figure 22.3
32-kHz clock oscillation settling
time tOSC3 —2s
Sub clock oscillator frequency fSUB 32.768 —kHz
Sub clock (φSUB) cycle time tSUB 30.5 —µs
t
CH
t
Cf
t
cyc
t
CL
t
Cr
φ
Figure 22.2 System Clock Timing
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 747 of 1042
REJ09B0275-0500
t
OSC1
t
OSC1
EXTAL
VCC
STBY
RES
φ
tDEXT tDEXT
Figure 22.3 Oscillation Stabilization Timing
22.3.2 Control Signal Timing
Table 22.5 lists the control signal timing.
Table 22.5 Control Signal Timing
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
RES setup time tRESS 200 —ns Figure 22.4
RES pulse width tRESW 20 — tcyc
NMI setup time tNMIS 150 —ns Figure 22.5
NMI hold time tNMIH 10 —
NMI pulse width (exiting
software standby mode) tNMIW 200 —ns
IRQ setup time tIRQS 150 —ns
IRQ hold time tIRQH 10 —ns
IRQ pulse width (exiting
software standby mode) tIRQW 200 —ns
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 748 of 1042
REJ09B0275-0500
tRESW
tRESS
φ
tRESS
RES
Figure 22.4 Reset Input Timing
t
IRQS
φ
t
NMIS
t
NMIH
IRQ
Edge input
NMI
t
IRQS
t
IRQH
IRQi
(i = 0 to 2)
IRQ
Level input
t
NMIW
t
IRQW
Figure 22. 5 Interrupt Input Timi ng
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 749 of 1042
REJ09B0275-0500
22.3.3 Bus Timing
Table 22.6 lists the bus timing.
Table 22.6 Bus Timing — Preliminary —
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
Address delay time tAD —25 ns
Address setup time tAS 0.5 × tcyc – 20 —ns Figure 22.6 to
Figure 22.10
Address hold time tAH 0.5 × tcyc – 15 —ns
AS delay time tASD —20 ns
RD delay time 1 tRSD1 —20 ns
RD delay time 2 tRSD2 —20 ns
Read data setup time tRDS 15 —ns
Read data hold time tRDH 0 — ns
Read data access time 1 tACC1 —1.0 × tcyc – 35 ns
Read data access time 2 tACC2 —1.5 × tcyc – 25 ns
Read data access time 3 tACC3 —2.0 × tcyc – 35 ns
Read data access
time 4 tACC4 —2.5 × tcyc – 25 ns
Read data access
time 5 tACC5 —3.0 × tcyc – 35 ns
WR delay time 1 tWRD1 —20 ns
WR delay time 2 tWRD2 —20 ns
WR pulse width 1 tWSW1 1.0 × tcyc – 20 —ns
WR pulse width 2 tWSW2 1.5 × tcyc – 20 —ns
Write data delay time tWDD —30 ns
Write data setup time tWDS 0.5 × tcyc – 20 —ns
Write data hold time tWDH 0.5 × tcyc – 10 —ns
WAIT setup time tWTS 30 —ns Figure 22.8
WAIT hold time tWTH 5 — ns
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 750 of 1042
REJ09B0275-0500
Item Symbol Min Max Unit Test Conditions
BREQ setup time tBRQS 30 —ns Figure 22.11
BACK delay time tBACD —15 ns
Bus-floating time tBZD —50 ns
BREQO delay time tBRQOD —25 ns Figure 22.12
φ
A23 to A0
AS
t
RSD2
t
AS
t
AH
t
ACC2
t
RSD1
t
ASD
t
ASD
t
AD
t
ACC3
t
WRD2
t
WRD2
t
WSW1
t
WDD
t
WDH
T
1
T
2
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
t
RDS
t
AH
t
AS
t
AS
t
RDH
Figure 22.6 Basic Bus Timing ( Two-State Access)
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 751 of 1042
REJ09B0275-0500
φ
A23 to A0
AS
t
RSD2
t
AS
t
AH
t
ACC4
t
RSD1
t
ASD
t
ASD
t
AD
t
ACC5
t
WRD2
t
WRD1
t
WSW2
t
WDD
t
WDH
T
1
T
3
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
t
WDS
T
2
t
RDS
t
AS
t
AH
t
RDH
Figure 22.7 Basic Bus Timing (Three-State Access)
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 752 of 1042
REJ09B0275-0500
φ
TW
AS
A23 to A0
RD
(read)
T3
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
T2
tWTS
T1
tWTH tWTS tWTH
WAIT
Figure 22.8 Basic Bus Timing (Three-State Access with One Wait State)
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 753 of 1042
REJ09B0275-0500
t
RSD2
φ
T
1
AS
A23 to A0
T
2
t
AH
t
ACC3
t
RDS
D15 to D0
(read)
T
2
or T
3
t
AS
T
1
t
ASD
t
ASD
t
RDH
t
AD
RD
(read)
Figure 22.9 Burst ROM Access Timing (Two-State Access)
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 754 of 1042
REJ09B0275-0500
tRSD2
φ
T1
AS
A23 to A0
T1
tACC1
D15 to D0
(read)
T2 or T3
tRDH
tAD
RD
(read) tRDS
Figure 22.10 Burst ROM Access Timing (One-State Access)
φ
BREQ
A23 to A0,
AS, RD,
HWR, LWR
t
BRQS
t
BACD
t
BZD
t
BACD
t
BZD
t
BRQS
BACK
Figure 22.11 External Bus Release Timing
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 755 of 1042
REJ09B0275-0500
φ
BREQO
t
BRQOD
t
BRQOD
Figure 22.12 External Bus Request Output Timing
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 756 of 1042
REJ09B0275-0500
22.3 .4 Timing o f On-Chip Supporting Modules
Table 22.7 lists the timing of on-chip supporting modules.
Table 22.7 Timing of On-C hip Supporting Modules — P reliminary —
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
I/O port Output data delay time tPWD —50 ns Figure 22.13
Input data setup time tPRS 30 —
Input data hold time tPRH 30 —
TPU Timer output delay time tTOCD —50 ns Figure 22.14
Timer input setup time tTICS 30 —
Timer clock input setup
time tTCKS 30 —ns Figure 22.15
Single edge tTCKWH 1.5 — tcyc
Timer clock
pulse width Both edges tTCKWL 2.5 —
SCI Input clock
cycle Asynchro-
nous tScyc 4 — tcyc Figure 22.16
Synchronous 6 —
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr —1.5 tcyc
Input clock fall time tSCKf —1.5
Transmit data delay time tTXD —50 ns Figure 22.17
Receive data set up tim e
(synchronous) tRXS 50 —
Receive data hol d time
(synchronous) tRXH 50 —
A/D
converter Trigger input setup time tTRGS 30 —ns Figure 22.18
HCAN*Transmit data delay time tHTXD —100 ns Figure 22.19
Transmit data setup time tHRXS 100 —
Transmit data hold time tHRXH 100 —
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 757 of 1042
REJ09B0275-0500
Item Symbol Min Max Unit Test Conditions
PPG Pulse output delay time tPOD —50 ns Figure 22.20
WDT0 Overflow output delay time tWOVD —50 ns Figure 22.21
WDT1 Buzz output delay time tBUZD —50 ns Figure 22.22
Note: *The HCAN input signal is asynchronous. However, its state is judged to have changed
at the leading edge (two clock cycles) of the CK clock signal shown in figure 22.19. The
HCAN output signal is also asynchronous. Its state changes based on the leading edge
(two clock cycles) of the CK clock signal shown in figure 22.19.
φ
Ports 1, 4, 9
A to F (read)
T
2
T
1
t
PWD
t
PRH
t
PRS
Ports 1, A to F
(write)
Figure 22. 13 I/O Port Input/Out put Timing
φ
t
TICS
t
TOCD
Output compare
output*
Input capture
input*
Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 22 . 14 TPU Input/Out put Timing
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 758 of 1042
REJ09B0275-0500
t
TCKS
φ
t
TCKS
TCLKA to TCLKD
t
TCKWH
t
TCKWL
Figure 22 . 15 TPU Clock Input Timing
SCK0 to SCK3
t
SCKW
t
SCKr
t
SCKf
t
Scyc
Figure 22. 16 SCK Clock Input Timing
TxD0 to TxD3
(transit data)
RxD0 to RxD3
(receive data)
SCK0 to SCK3
tRXS tRXH
tTXD
Figure 22 . 17 SCI Input/Output Timing (Clock Synchronous Mode)
φ
ADTRG
tTRGS
Figure 22.18 A/D Converter Ext ernal Trigger Input Timing
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 759 of 1042
REJ09B0275-0500
(Preliminary)
VOL VOL
CK
TX
(transmit data )
RX
(receive data)
tHTXD
tHRXS tHRXH
Figure 22.19 HCAN Input/O utput Timing
φ
PO15 to 8
tPOD
Figure 22.20 PPG Output Timing
φ
tWOVD
WDTOVF
tWOVD
Figure 22.21 WDT0 Output Timing
φ
t
BUZD
BUZZ
t
BUZD
Figure 22.22 WDT1 Output Timing
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 760 of 1042
REJ09B0275-0500
22.4 A/D Conversion Characteristics
Table 22.8 lists the A/D conversion characteristics.
Table 22.8 A/D Conv ersion Characterist ics — Preliminary —
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 4 to 20 MHz, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Min Typ Max Unit Test Conditions
Resolution 10 10 10 bits
Conversion time ———µs AVCC < 4.5 V
10 —— AVCC ≥ 4.5 V
Analog input capacitance ——20 pF
Permissible signal-source
impedance ——5kΩ
Nonlineari ty error ——±3.5 LSB
Offset error ——±3.5 LSB
Full-sca le error ——±3.5 LSB
Quantization —±0.5 —LSB
Absolute ac curacy ——±4.0 LSB
22.5 D/A Conversion Characteristics
Table 22.9 shows the D/A conversion characteristics.
Table 22.9 D/A Conversion Characteristics
Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 4 to 20 MHz, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Min Typ Max Unit Test Conditions
Resolution 888bits
Conversion time ——10 µs 20-pF capacitiv e load
Absolute ac curacy —±1.5 ±2.0 LSB 2-MΩ resistive load
——±1.5 LSB 4-MΩ resistive load
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 761 of 1042
REJ09B0275-0500
22.6 Flash Memory Characteristics
Table 22.10 Flash Memory Characteristics
Conditions: VCC = 3.0 to 3.6 V, AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to +75°C
(regular specifications), Ta = –40 to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Programming time*1 *2 *4tP—10 200 m s/ 128 bytes
Erase time*1 *3 *5tE—100 1000 ms/block
Number of rewrit es NWEC ——100 Times
Programming Wait time after SWE1 bit setting*1x0 1 ——µs
Wait time after PSU1 bit setting*1y50——µs
Wait time after P1 bit setting*1 *4z0 ——30 µs
z1 ——10 µs
z2 ——200 µs
Wait time after P1 bit clearing*1α5——µs
Wait time after PSU1 bit clearing*1β5——µs
Wait time after PV1 bit setting*1γ4——µs
Wait time after H'FF dummy write*1ε2——µs
Wait time after PV1 bit clearing*1η2——µs
Maximum number of writes*1 *4N1 ——6Times
N2 ——994 Times
Common Wait time after SWE1 bit clearing*1x1 100 ——µs
Erasing Wait time after SWE1 bit setting*1x1——µs
Wait time after ESU1 bit setting*1y 100 ——µs
Wait time after E1 bit setting*1 *5z——10 ms
Wait time after E1 bit clearing*1α10 ——µs
Wait time after ESU1 bit clearing*1β10 ——µs
Wait time after EV1 bit setting*1γ6——µs
Wait time after H'FF dummy write*1ε2——µs
Wait time after EV1 bit clearing*1η4——µs
Maximum number of erases*1 *5N——100 Times
Notes: 1. Foll ow the program/erase algorithms when making the time setti ngs.
2. Program ming time per 128 bytes. (Indicates the total time during whic h the P1 bit is set in flash
memory control regis ter 1 (FLMCR1). Does not include the program-verify t ime.)
3. Tim e to erase one block. (Indicat es the time during which t he E1 bit is set in FLMCR1. Does not
include the erase-verify time.)
4. Maximum programming time
(tP(max) = Wait time after P1 bit setting (z) × maximum number of writes (N))
(z0 + z1) × 6 + z2 × 994
5. Maximum erase time
(tE(max) = Wait time after E1 bit setting (z) × maximum number of erases (N))
Section 22 Electrical Characteristics (Preliminary)
Rev. 5.00 Jan 10, 2006 page 762 of 1042
REJ09B0275-0500
22.7 Usage Note
Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed
in this manual, there may be differences in the actual values of the electrical characteristics,
operating margins, noise margins, and so forth, due to differences in the fabrication process, the
on-chip ROM, and the layout patterns.
Therefore, if a system is evaluated using the F-ZTAT version, a similar evaluation should also be
performed using the mask ROM version.
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 763 of 1042
REJ09B0275-0500
Appendi x A Instructi on Set
A.1 Instruction List
Operand Notation
Rd General register (des tination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
MAC Multiply-and-accumulate register (32-bit register)
(EAd) Destina tion operand
(EAs) Source operand
EXR Extended control r egi ster
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+Add
– Subtract
×Multiply
÷ Divide
∧Logical AND
∨Logical OR
⊕Logical exclusive OR
→Transfer from the operand on the left to the operand on the right, or
transition from the state on the left to the state on the right
¬ Logical NOT (logical complement)
( ) < > Contents of operand
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 764 of 1042
REJ09B0275-0500
Condition Code Notatio n
Symbol
Changes according to the result of instruction
*Undetermined (no guaranteed value)
0 Always cleared to 0
1 Always set to 1
— Not affected by execution of the instruction
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 765 of 1042
REJ09B0275-0500
Table A.1 Instruction Set
(1) Data Transfer Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
MOV MOV.B #xx:8,Rd B 2
MOV.B Rs,Rd B 2
MOV.B @ERs,Rd B 2
MOV.B @(d:16,ERs),Rd B 4
MOV.B @(d:32,ERs),Rd B 8
MOV.B @ERs+,Rd B 2
MOV.B @aa:8,Rd B 2
MOV.B @aa:16,Rd B 4
MOV.B @aa:32,Rd B 6
MOV.B Rs,@ERd B 2
MOV.B Rs,@(d:16,ERd) B 4
MOV.B Rs,@(d:32,ERd) B 8
MOV.B Rs,@-ERd B 2
MOV.B Rs,@aa:8 B 2
MOV.B Rs,@aa:16 B 4
MOV.B Rs,@aa:32 B 6
MOV.W #xx:16,Rd W 4
MOV.W Rs,Rd W 2
MOV.W @ERs,Rd W 2
#xx:8→Rd8 — — 0 — 1
Rs8→Rd8 — — 0 — 1
@ERs→Rd8 — — 0 — 2
@(d:16,ERs)→Rd8 — — 0 — 3
@(d:32,ERs)→Rd8 — — 0 — 5
@ERs→Rd8,ERs32+1→ERs32 — — 0 — 3
@aa:8→Rd8 — — 0 — 2
@aa:16→Rd8 — — 0 — 3
@aa:32→Rd8 — — 0 — 4
Rs8→@ERd — — 0 — 2
Rs8→@(d:16,ERd) — — 0 — 3
Rs8→@(d:32,ERd) — — 0 — 5
ERd32-1→ERd32,Rs8→@ERd — — 0 — 3
Rs8→@aa:8 — — 0 — 2
Rs8→@aa:16 — — 0 — 3
Rs8→@aa:32 — — 0 — 4
#xx:16→Rd16 — — 0 — 2
Rs16→Rd16 — — 0 — 1
@ERs→Rd16 — — 0 — 2
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 766 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
MOV MOV.W @(d:16,ERs),Rd W 4
MOV.W @(d:32,ERs),Rd W 8
MOV.W @ERs+,Rd W 2
MOV.W @aa:16,Rd W 4
MOV.W @aa:32,Rd W 6
MOV.W Rs,@ERd W 2
MOV.W Rs,@(d:16,ERd) W 4
MOV.W Rs,@(d:32,ERd) W 8
MOV.W Rs,@-ERd W 2
MOV.W Rs,@aa:16 W 4
MOV.W Rs,@aa:32 W 6
MOV.L #xx:32,ERd L 6
MOV.L ERs,ERd L 2
MOV.L @ERs,ERd L 4
MOV.L @(d:16,ERs),ERd L 6
MOV.L @(d:32,ERs),ERd L 10
MOV.L @ERs+,ERd L 4
MOV.L @aa:16,ERd L 6
MOV.L @aa:32,ERd L 8
@(d:16,ERs)→Rd16 — — 0 — 3
@(d:32,ERs)→Rd16 — — 0 — 5
@ERs→Rd16,ERs32+2→ERs32 — — 0 — 3
@aa:16→Rd16 — — 0 — 3
@aa:32→Rd16 — — 0 — 4
Rs16→@ERd — — 0 — 2
Rs16→@(d:16,ERd) — — 0 — 3
Rs16→@(d:32,ERd) — — 0 — 5
ERd32-2→ERd32,Rs16→@ERd — — 0 — 3
Rs16→@aa:16 — — 0 — 3
Rs16→@aa:32 — — 0 — 4
#xx:32→ERd32 — — 0 — 3
ERs32→ERd32 — — 0 — 1
@ERs→ERd32 — — 0 — 4
@(d:16,ERs)→ERd32 — — 0 — 5
@(d:32,ERs)→ERd32 — — 0 — 7
@ERs→ERd32,ERs32+4→ERs32
— — 0 — 5
@aa:16→ERd32 — — 0 — 5
@aa:32→ERd32 — — 0 — 6
Operation
Condition Code
IHNZVC Advanced
No. of States*1
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 767 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
MOV
POP
PUSH
LDM
STM
MOVFPE
MOVTPE
MOV.L ERs,@ERd L 4
MOV.L ERs,@(d:16,ERd) L 6
MOV.L ERs,@(d:32,ERd) L 10
MOV.L ERs,@-ERd L 4
MOV.L ERs,@aa:16 L 6
MOV.L ERs,@aa:32 L 8
POP.W Rn W 2
POP.L ERn L 4
PUSH.W Rn W 2
PUSH.L ERn L 4
LDM @SP+,(ERm-ERn) L 4
STM (ERm-ERn),@-SP L 4
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
ERs32→@ERd — — 0 — 4
ERs32→@(d:16,ERd) — — 0 — 5
ERs32→@(d:32,ERd) — — 0 — 7
ERd32-4
→
ERd32,ERs32
→@
ERd
— — 0 — 5
ERs32→@aa:16 — — 0 — 5
ERs32→@aa:32 — — 0 — 6
@SP→Rn16,SP+2→SP — — 0 — 3
@SP→ERn32,SP+4→SP — — 0 — 5
SP-2→SP,Rn16→@SP — — 0 — 3
SP-4→SP,ERn32→@SP — — 0 — 5
(@SP→ERn32,SP+4→SP) — — — — — — 7/9/11 [1]
Repeated for each register restored
(SP-4→SP,ERn32→@SP) — — — — — — 7/9/11 [1]
Repeated for each register saved
[2]
[2]
Operation
Condition Code
IHNZVC Advanced
No. of States*1
↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔
Cannot be used in the H8S/2626 Group or H8S/2623 Group
Cannot be used in the H8S/2626 Group or H8S/2623 Group
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 768 of 1042
REJ09B0275-0500
(2) Arithmetic Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
ADD
ADDX
ADDS
INC
DAA
SUB
ADD.B #xx:8,Rd B 2
ADD.B Rs,Rd B 2
ADD.W #xx:16,Rd W 4
ADD.W Rs,Rd W 2
ADD.L #xx:32,ERd L 6
ADD.L ERs,ERd L 2
ADDX #xx:8,Rd B 2
ADDX Rs,Rd B 2
ADDS #1,ERd L 2
ADDS #2,ERd L 2
ADDS #4,ERd L 2
INC.B Rd B 2
INC.W #1,Rd W 2
INC.W #2,Rd W 2
INC.L #1,ERd L 2
INC.L #2,ERd L 2
DAA Rd B 2
SUB.B Rs,Rd B 2
SUB.W #xx:16,Rd W 4
Rd8+#xx:8→Rd8 — 1
Rd8+Rs8→Rd8 — 1
Rd16+#xx:16→Rd16 — [3] 2
Rd16+Rs16→Rd16 — [3] 1
ERd32+#xx:32→ERd32 — [4] 3
ERd32+ERs32→ERd32 — [4] 1
Rd8+#xx:8+C→Rd8 — [5] 1
Rd8+Rs8+C→Rd8 — [5] 1
ERd32+1→ERd32 — — — — — — 1
ERd32+2→ERd32 — — — — — — 1
ERd32+4→ERd32 — — — — — — 1
Rd8+1→Rd8 — — — 1
Rd16+1→Rd16 — — — 1
Rd16+2→Rd16 — — — 1
ERd32+1→ERd32 — — — 1
ERd32+2→ERd32 — — — 1
Rd8 decimal adjust→Rd8 — * * 1
Rd8-Rs8→Rd8 — 1
Rd16-#xx:16→Rd16 — [3] 2
Operation
Condition Code
IHNZVC Advanced
No. of States*1
↔↔↔
↔
↔↔↔↔↔↔↔↔
↔↔ ↔↔↔↔↔
↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔
↔↔↔↔↔↔
↔↔↔↔↔↔↔↔
↔↔ ↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 769 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
SUB
SUBX
SUBS
DEC
DAS
MULXU
MULXS
SUB.W Rs,Rd W 2
SUB.L #xx:32,ERd L 6
SUB.L ERs,ERd L 2
SUBX #xx:8,Rd B 2
SUBX Rs,Rd B 2
SUBS #1,ERd L 2
SUBS #2,ERd L 2
SUBS #4,ERd L 2
DEC.B Rd B 2
DEC.W #1,Rd W 2
DEC.W #2,Rd W 2
DEC.L #1,ERd L 2
DEC.L #2,ERd L 2
DAS Rd B 2
MULXU.B Rs,Rd B 2
MULXU.W Rs,ERd W 2
MULXS.B Rs,Rd B 4
MULXS.W Rs,ERd W 4
Rd16-Rs16→Rd16 — [3] 1
ERd32-#xx:32→ERd32 — [4] 3
ERd32-ERs32→ERd32 — [4] 1
Rd8-#xx:8-C→Rd8 — [5] 1
Rd8-Rs8-C→Rd8 — [5] 1
ERd32-1→ERd32 — — — — — — 1
ERd32-2→ERd32 — — — — — — 1
ERd32-4→ERd32 — — — — — — 1
Rd8-1→Rd8 — — — 1
Rd16-1→Rd16 — — — 1
Rd16-2→Rd16 — — — 1
ERd32-1→ERd32 — — — 1
ERd32-2→ERd32 — — — 1
Rd8 decimal adjust→Rd8 — * * — 1
Rd8
×
Rs8
→
Rd16 (unsigned multiplication)
— — — — — — 3
Rd16×Rs16→ERd32 — — — — — — 4
(unsigned multiplication)
Rd8
×
Rs8
→
Rd16 (signed multiplication)
— — — — 4
Rd16×Rs16→ERd32 — — — — 5
(signed multiplication)
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔
↔↔ ↔↔↔↔↔↔
↔↔↔↔↔↔
↔↔↔↔↔ ↔↔↔
↔↔↔↔↔
↔↔↔↔↔
↔↔↔↔↔
↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 770 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
DIVXU
DIVXS
CMP
NEG
EXTU
DIVXU.B Rs,Rd B 2
DIVXU.W Rs,ERd W 2
divxs.B Rs,Rd B 4
DIVXS.W Rs,ERd W 4
CMP.B #xx:8,Rd B 2
CMP.B Rs,Rd B 2
CMP.W #xx:16,Rd W 4
CMP.W Rs,Rd W 2
CMP.L #xx:32,ERd L 6
CMP.L ERs,ERd L 2
NEG.B Rd B 2
NEG.W Rd W 2
NEG.L ERd L 2
EXTU.W Rd W 2
EXTU.L ERd L 2
Rd16÷Rs8→
Rd16 (RdH: remainder,
— — [6] [7] — — 12
RdL: quotient) (unsigned division)
ERd32÷Rs16
→
ERd32 (Ed: remainder,
— — [6] [7] — — 20
Rd: quotient) (unsigned division)
Rd16÷Rs8→
Rd16 (RdH: remainder,
— —
[8] [7] — — 13
RdL: quotient) (signed division)
ERd32
÷Rs16→
ERd32 (Ed: remainder,
— — [8] [7] — — 21
Rd: quotient) (signed division)
Rd8-#xx:8 — 1
Rd8-Rs8 — 1
Rd16-#xx:16 — [3] 2
Rd16-Rs16 — [3] 1
ERd32-#xx:32 — [4] 3
ERd32-ERs32 — [4] 1
0-Rd8→Rd8 — 1
0-Rd16→Rd16 — 1
0-ERd32→ERd32 — 1
0→(<bit 15 to 8> of Rd16) — — 0 0 — 1
0→(<bit 31 to 16> of ERd32) — — 0 0 — 1
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔↔ ↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 771 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
EXTS.W Rd W 2
EXTS.L ERd L 2
TAS @ERd *
3
B 4
MAC @ERn+,@ERm+ — 4
CLRMAC — 2
LDMAC ERs,MACH L 2
LDMAC ERs,MACL L 2
STMAC MACH,ERd L 2
STMAC MACL,ERd L 2
(<bit 7> of Rd16)→ — — 0 — 1
(<bit 15 to 8> of Rd16)
(<bit 15> of ERd32)→ — — 0 — 1
(<bit 31 to 16> of ERd32)
@ERd-0→CCR set, (1)→ — — 0 — 4
(<bit 7> of @ERd)
@ERn×@ERm+MAC→MAC — — — — — — 4
(signed multiplication)
[10] [10] [10]
ERn+2→ERn,ERm+2→ERm
0→MACH,MACL — — — — — — 2 [11]
ERs→MACH — — — — — — 2 [11]
ERs→MACL — — — — — — 2 [11]
MACH→ERd — — — 1 [11]
MACL→ERd — — — 1 [11]
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔
↔↔
↔↔ ↔ ↔ ↔
↔ ↔ ↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 772 of 1042
REJ09B0275-0500
(3) Logical Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
AND
OR
XOR
NOT
AND.B #xx:8,Rd B 2
AND.B Rs,Rd B 2
AND.W #xx:16,Rd W 4
AND.W Rs,Rd W 2
AND.L #xx:32,ERd L 6
AND.L ERs,ERd L 4
OR.B #xx:8,Rd B 2
OR.B Rs,Rd B 2
OR.W #xx:16,Rd W 4
OR.W Rs,Rd W 2
OR.L #xx:32,ERd L 6
OR.L ERs,ERd L 4
XOR.B #xx:8,Rd B 2
XOR.B Rs,Rd B 2
XOR.W #xx:16,Rd W 4
XOR.W Rs,Rd W 2
XOR.L #xx:32,ERd L 6
XOR.L ERs,ERd L 4
NOT.B Rd B 2
NOT.W Rd W 2
NOT.L ERd L 2
Rd8∧#xx:8→Rd8 — — 0 — 1
Rd8∧Rs8→Rd8 — — 0 — 1
Rd16∧#xx:16→Rd16 — — 0 — 2
Rd16∧Rs16→Rd16 — — 0 — 1
ERd32∧#xx:32→ERd32 — — 0 — 3
ERd32∧ERs32→ERd32 — — 0 — 2
Rd8∨#xx:8→Rd8 — — 0 — 1
Rd8∨Rs8→Rd8 — — 0 — 1
Rd16∨#xx:16→Rd16 — — 0 — 2
Rd16∨Rs16→Rd16 — — 0 — 1
ERd32∨#xx:32→ERd32 — — 0 — 3
ERd32∨ERs32→ERd32 — — 0 — 2
Rd8⊕#xx:8→Rd8 — — 0 — 1
Rd8⊕Rs8→Rd8 — — 0 — 1
Rd16⊕#xx:16→Rd16 — — 0 — 2
Rd16⊕Rs16→Rd16 — — 0 — 1
ERd32⊕#xx:32→ERd32 — — 0 — 3
ERd32⊕ERs32→ERd32 — — 0 — 2
¬ Rd8→Rd8 — — 0 — 1
¬ Rd16→Rd16 — — 0 — 1
¬ ERd32→ERd32 — — 0 — 1
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 773 of 1042
REJ09B0275-0500
(4) Shift Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
SHAL
SHAR
SHLL
SHAL.B Rd B 2
SHAL.B #2,Rd B 2
SHAL.W Rd W 2
SHAL.W #2,Rd W 2
SHAL.L ERd L 2
SHAL.L #2,ERd L 2
SHAR.B Rd B 2
SHAR.B #2,Rd B 2
SHAR.W Rd W 2
SHAR.W #2,Rd W 2
SHAR.L ERd L 2
SHAR.L #2,ERd L 2
SHLL.B Rd B 2
SHLL.B #2,Rd B 2
SHLL.W Rd W 2
SHLL.W #2,Rd W 2
SHLL.L ERd L 2
SHLL.L #2,ERd L 2
— — 1
— — 1
— — 1
— — 1
— — 1
— — 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
CMSB LSB
MSB LSB
0
C
MSB LSB
C
0
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 774 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
SHLR
ROTXL
ROTXR
SHLR.B Rd B 2
SHLR.B #2,Rd B 2
SHLR.W Rd W 2
SHLR.W #2,Rd W 2
SHLR.L ERd L 2
SHLR.L #2,ERd L 2
ROTXL.B Rd B 2
ROTXL.B #2,Rd B 2
ROTXL.W Rd W 2
ROTXL.W #2,Rd W 2
ROTXL.L ERd L 2
ROTXL.L #2,ERd L 2
ROTXR.B Rd B 2
ROTXR.B #2,Rd B 2
ROTXR.W Rd W 2
ROTXR.W #2,Rd W 2
ROTXR.L ERd L 2
ROTXR.L #2,ERd L 2
— — — 0 0 1
— — — 0 0 1
— — — 0 0 1
— — — 0 0 1
— — — 0 0 1
— — — 0 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔
C
MSB LSB
0
CMSB LSB
C
MSB LSB
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 775 of 1042
REJ09B0275-0500
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — 0 1
— — — 0 1
— — — 0 1
— — — 0 1
— — 0 1
— — — 0 1
1 — — 0 1
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
ROTL
ROTR
ROTL.B Rd B 2
ROTL.B #2,Rd B 2
ROTL.W Rd W 2
ROTL.W #2,Rd W 2
ROTL.L ERd L 2
ROTL.L #2,ERd L 2
ROTR.B Rd B 2
ROTR.B #2,Rd B 2
ROTR.W Rd W 2
ROTR.W #2,Rd W 2
ROTR.L ERd L 2
ROTR.L #2,ERd L 2
Operation
Condition Code
IHNZVC Advanced
No. of States*1
↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔↔
C
MSB LSB
CMSB LSB
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 776 of 1042
REJ09B0275-0500
(5) Bit-Manipulation Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
BSET
BCLR
BSET #xx:3,Rd B 2
BSET #xx:3,@ERd B 4
BSET #xx:3,@aa:8 B 4
BSET #xx:3,@aa:16 B 6
BSET #xx:3,@aa:32 B 8
BSET Rn,Rd B 2
BSET Rn,@ERd B 4
BSET Rn,@aa:8 B 4
BSET Rn,@aa:16 B 6
BSET Rn,@aa:32 B 8
BCLR #xx:3,Rd B 2
BCLR #xx:3,@ERd B 4
BCLR #xx:3,@aa:8 B 4
BCLR #xx:3,@aa:16 B 6
BCLR #xx:3,@aa:32 B 8
BCLR Rn,Rd B 2
BCLR Rn,@ERd B 4
BCLR Rn,@aa:8 B 4
BCLR Rn,@aa:16 B 6
(#xx:3 of Rd8)←1 — — — — — — 1
(#xx:3 of @ERd)←1 — — — — — — 4
(#xx:3 of @aa:8)←1 — — — — — — 4
(#xx:3 of @aa:16)←1 — — — — — — 5
(#xx:3 of @aa:32)←1 — — — — — — 6
(Rn8 of Rd8)←1 — — — — — — 1
(Rn8 of @ERd)←1 — — — — — — 4
(Rn8 of @aa:8)←1 — — — — — — 4
(Rn8 of @aa:16)←1 — — — — — — 5
(Rn8 of @aa:32)←1 — — — — — — 6
(#xx:3 of Rd8)←0 — — — — — — 1
(#xx:3 of @ERd)←0 — — — — — — 4
(#xx:3 of @aa:8)←0 — — — — — — 4
(#xx:3 of @aa:16)←0 — — — — — — 5
(#xx:3 of @aa:32)←0 — — — — — — 6
(Rn8 of Rd8)←0 — — — — — — 1
(Rn8 of @ERd)←0 — — — — — — 4
(Rn8 of @aa:8)←0 — — — — — — 4
(Rn8 of @aa:16)←0 — — — — — — 5
Operation
Condition Code
IHNZVC Advanced
No. of States*1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 777 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
BCLR
BNOT
BTST
BCLR Rn,@aa:32 B 8
BNOT #xx:3,Rd B 2
BNOT #xx:3,@ERd B 4
BNOT #xx:3,@aa:8 B 4
BNOT #xx:3,@aa:16 B 6
BNOT #xx:3,@aa:32 B 8
BNOT Rn,Rd B 2
BNOT Rn,@ERd B 4
BNOT Rn,@aa:8 B 4
BNOT Rn,@aa:16 B 6
BNOT Rn,@aa:32 B 8
BTST #xx:3,Rd B 2
BTST #xx:3,@ERd B 4
BTST #xx:3,@aa:8 B 4
BTST #xx:3,@aa:16 B 6
(Rn8 of @aa:32)←0 — — — — — — 6
(#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — — 1
(#xx:3 of @ERd)← — — — — — — 4
[¬ (#xx:3 of @ERd)]
(#xx:3 of @aa:8)← — — — — — — 4
[¬ (#xx:3 of @aa:8)]
(#xx:3 of @aa:16)← — — — — — — 5
[¬ (#xx:3 of @aa:16)]
(#xx:3 of @aa:32)← — — — — — — 6
[¬ (#xx:3 of @aa:32)]
(Rn8 of Rd8)←[¬ (Rn8 of Rd8)] — — — — — — 1
(Rn8 of @ERd)
←
[¬ (Rn8 of @ERd)]
— — — — — — 4
(Rn8 of @aa:8)
←
[¬ (Rn8 of @aa:8)]
— — — — — — 4
(Rn8 of @aa:16)← — — — — — — 5
[¬ (Rn8 of @aa:16)]
(Rn8 of @aa:32)← — — — — — — 6
[¬ (Rn8 of @aa:32)]
¬ (#xx:3 of Rd8)→Z — — — — — 1
¬ (#xx:3 of @ERd)→Z — — — — — 3
¬ (#xx:3 of @aa:8)→Z — — — — — 3
¬ (#xx:3 of @aa:16)→Z — — — — — 4
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 778 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
BTST
BLD
BILD
BST
BTST #xx:3,@aa:32 B 8
BTST Rn,Rd B 2
BTST Rn,@ERd B 4
BTST Rn,@aa:8 B 4
BTST Rn,@aa:16 B 6
BTST Rn,@aa:32 B 8
BLD #xx:3,Rd B 2
BLD #xx:3,@ERd B 4
BLD #xx:3,@aa:8 B 4
BLD #xx:3,@aa:16 B 6
BLD #xx:3,@aa:32 B 8
BILD #xx:3,Rd B 2
BILD #xx:3,@ERd B 4
BILD #xx:3,@aa:8 B 4
BILD #xx:3,@aa:16 B 6
BILD #xx:3,@aa:32 B 8
BST #xx:3,Rd B 2
BST #xx:3,@ERd B 4
BST #xx:3,@aa:8 B 4
¬ (#xx:3 of @aa:32)→Z — — — — — 5
¬ (Rn8 of Rd8)→Z — — — — — 1
¬ (Rn8 of @ERd)→Z — — — — — 3
¬ (Rn8 of @aa:8)→Z — — — — — 3
¬ (Rn8 of @aa:16)→Z — — — — — 4
¬ (Rn8 of @aa:32)→Z — — — — — 5
(#xx:3 of Rd8)→C — — — — — 1
(#xx:3 of @ERd)→C — — — — — 3
(#xx:3 of @aa:8)→C — — — — — 3
(#xx:3 of @aa:16)→C — — — — — 4
(#xx:3 of @aa:32)→C — — — — — 5
¬ (#xx:3 of Rd8)→C — — — — — 1
¬ (#xx:3 of @ERd)→C — — — — — 3
¬ (#xx:3 of @aa:8)→C — — — — — 3
¬ (#xx:3 of @aa:16)→C — — — — — 4
¬ (#xx:3 of @aa:32)→C — — — — — 5
C→(#xx:3 of Rd8) — — — — — — 1
C→(#xx:3 of @ERd24) — — — — — — 4
C→(#xx:3 of @aa:8) — — — — — — 4
Operation
Condition Code
IHNZVC Advanced
No. of States*1
↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 779 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
BST
BIST
BAND
BIAND
BOR
BST #xx:3,@aa:16 B 6
BST #xx:3,@aa:32 B 8
BIST #xx:3,Rd B 2
BIST #xx:3,@ERd B 4
BIST #xx:3,@aa:8 B 4
BIST #xx:3,@aa:16 B 6
BIST #xx:3,@aa:32 B 8
BAND #xx:3,Rd B 2
BAND #xx:3,@ERd B 4
BAND #xx:3,@aa:8 B 4
BAND #xx:3,@aa:16 B 6
BAND #xx:3,@aa:32 B 8
BIAND #xx:3,Rd B 2
BIAND #xx:3,@ERd B 4
BIAND #xx:3,@aa:8 B 4
BIAND #xx:3,@aa:16 B 6
BIAND #xx:3,@aa:32 B 8
BOR #xx:3,Rd B 2
BOR #xx:3,@ERd B 4
C→(#xx:3 of @aa:16) — — — — — — 5
C→(#xx:3 of @aa:32) — — — — — — 6
¬ C→(#xx:3 of Rd8) — — — — — — 1
¬ C→(#xx:3 of @ERd24) — — — — — — 4
¬ C→(#xx:3 of @aa:8) — — — — — — 4
¬ C→(#xx:3 of @aa:16) — — — — — — 5
¬ C→(#xx:3 of @aa:32) — — — — — — 6
C∧(#xx:3 of Rd8)→C — — — — — 1
C∧(#xx:3 of @ERd24)→C — — — — — 3
C∧(#xx:3 of @aa:8)→C — — — — — 3
C∧(#xx:3 of @aa:16)→C — — — — — 4
C∧(#xx:3 of @aa:32)→C — — — — — 5
C∧[¬ (#xx:3 of Rd8)]→C — — — — — 1
C∧[¬ (#xx:3 of @ERd24)]→C — — — — — 3
C∧[¬ (#xx:3 of @aa:8)]→C — — — — — 3
C∧[¬ (#xx:3 of @aa:16)]→C — — — — — 4
C∧[¬ (#xx:3 of @aa:32)]→C — — — — — 5
C∨(#xx:3 of Rd8)→C — — — — — 1
C∨(#xx:3 of @ERd24)→C — — — — — 3
Operation
Condition Code
IHNZVC Advanced
No. of States*1
↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 780 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
BOR
BIOR
BXOR
BIXOR
BOR #xx:3,@aa:8 B 4
BOR #xx:3,@aa:16 B 6
BOR #xx:3,@aa:32 B 8
BIOR #xx:3,Rd B 2
BIOR #xx:3,@ERd B 4
BIOR #xx:3,@aa:8 B 4
BIOR #xx:3,@aa:16 B 6
BIOR #xx:3,@aa:32 B 8
BXOR #xx:3,Rd B 2
BXOR #xx:3,@ERd B 4
BXOR #xx:3,@aa:8 B 4
BXOR #xx:3,@aa:16 B 6
BXOR #xx:3,@aa:32 B 8
BIXOR #xx:3,Rd B 2
BIXOR #xx:3,@ERd B 4
BIXOR #xx:3,@aa:8 B 4
BIXOR #xx:3,@aa:16 B 6
BIXOR #xx:3,@aa:32 B 8
C∨(#xx:3 of @aa:8)→C — — — — — 3
C∨(#xx:3 of @aa:16)→C — — — — — 4
C∨(#xx:3 of @aa:32)→C — — — — — 5
C∨[¬ (#xx:3 of Rd8)]→C — — — — — 1
C∨[¬ (#xx:3 of @ERd24)]→C — — — — — 3
C∨[¬ (#xx:3 of @aa:8)]→C — — — — — 3
C∨[¬ (#xx:3 of @aa:16)]→C — — — — — 4
C∨[¬ (#xx:3 of @aa:32)]→C — — — — — 5
C⊕(#xx:3 of Rd8)→C — — — — — 1
C⊕(#xx:3 of @ERd24)→C — — — — — 3
C⊕(#xx:3 of @aa:8)→C — — — — — 3
C⊕(#xx:3 of @aa:16)→C — — — — — 4
C⊕(#xx:3 of @aa:32)→C — — — — — 5
C⊕[¬ (#xx:3 of Rd8)]→C — — — — — 1
C⊕[¬ (#xx:3 of @ERd24)]→C — — — — — 3
C⊕[¬ (#xx:3 of @aa:8)]→C — — — — — 3
C⊕[¬ (#xx:3 of @aa:16)]→C — — — — — 4
C⊕[¬ (#xx:3 of @aa:32)]→C — — — — — 5
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 781 of 1042
REJ09B0275-0500
(6) Branch Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
Bcc Always — — — — — — 2
— — — — — — 3
Never — — — — — — 2
— — — — — — 3
C∨Z=0 — — — — — — 2
— — — — — — 3
C∨Z=1 — — — — — — 2
— — — — — — 3
C=0 — — — — — — 2
— — — — — — 3
C=1 — — — — — — 2
— — — — — — 3
Z=0 — — — — — — 2
— — — — — — 3
Z=1 — — — — — — 2
— — — — — — 3
V=0 — — — — — — 2
— — — — — — 3
Operation Condition Code
Branching
Condition
IHNZVC Advanced
No. of States*1
BRA d:8(BT d:8) — 2 if condition is true then
BRA d:16(BT d:16) — 4 PC←PC+d
BRN d:8(BF d:8) — 2 else next;
BRN d:16(BF d:16) — 4
BHI d:8 — 2
BHI d:16 — 4
BLS d:8 — 2
BLS d:16 — 4
BCC d:B(BHS d:8) — 2
BCC d:16(BHS d:16) — 4
BCS d:8(BLO d:8) — 2
BCS d:16(BLO d:16) — 4
BNE d:8 — 2
BNE d:16 — 4
BEQ d:8 — 2
BEQ d:16 — 4
BVC d:8 — 2
BVC d:16 — 4
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 782 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
Bcc V=1 — — — — — — 2
— — — — — — 3
N=0 — — — — — — 2
— — — — — — 3
N=1 — — — — — — 2
— — — — — — 3
N⊕V=0 — — — — — — 2
— — — — — — 3
N⊕V=1 — — — — — — 2
— — — — — — 3
Z∨(N⊕V)=0
— — — — — — 2
— — — — — — 3
Z∨(N⊕V)=1
— — — — — — 2
— — — — — — 3
Operation Condition Code
Branching
Condition IHNZVC Advanced
No. of States*
1
BVS d:8 — 2
BVS d:16 — 4
BPL d:8 — 2
BPL d:16 — 4
BMI d:8 — 2
BMI d:16 — 4
BGE d:8 — 2
BGE d:16 — 4
BLT d:8 — 2
BLT d:16 — 4
BGT d:8 — 2
BGT d:16 — 4
BLE d:8 — 2
BLE d:16 — 4
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 783 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
JMP
BSR
JSR
RTS
JMP @ERn — 2
JMP @aa:24 — 4
JMP @@aa:8 — 2
BSR d:8 — 2
BSR d:16 — 4
JSR @ERn — 2
JSR @aa:24 — 4
JSR @@aa:8 — 2
RTS — 2
PC←ERn — — — — — —
PC←aa:24 — — — — — —
PC←@aa:8 — — — — — —
PC→@-SP,PC←PC+d:8 — — — — — —
PC→@-SP,PC←PC+d:16 — — — — — —
PC→@-SP,PC←ERn — — — — — —
PC→@-SP,PC←aa:24 — — — — — —
PC→@-SP,PC←@aa:8 — — — — — —
PC←@SP+ — — — — — —
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
2
3
5
4
5
4
5
6
5
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 784 of 1042
REJ09B0275-0500
(7) System Control Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
TRAPA
RTE
SLEEP
LDC
TRAPA #xx:2 —
RTE —
SLEEP —
LDC #xx:8,CCR B 2
LDC #xx:8,EXR B 4
LDC Rs,CCR B 2
LDC Rs,EXR B 2
LDC @ERs,CCR W 4
LDC @ERs,EXR W 4
LDC @(d:16,ERs),CCR W 6
LDC @(d:16,ERs),EXR W 6
LDC @(d:32,ERs),CCR W 10
LDC @(d:32,ERs),EXR W 10
LDC @ERs+,CCR W 4
LDC @ERs+,EXR W 4
LDC @aa:16,CCR W 6
LDC @aa:16,EXR W 6
LDC @aa:32,CCR W 8
LDC @aa:32,EXR W 8
PC→@-SP,CCR→@-SP, 1 — — — — — 8 [13]
EXR→@-SP,<vector>→PC
EXR←@SP+,CCR←@SP+, 5 [13]
PC←@SP+
Transition to power-down state — — — — — — 2
#xx:8→CCR 1
#xx:8→EXR — — — — — — 2
Rs8→CCR 1
Rs8→EXR — — — — — — 1
@ERs→CCR 3
@ERs→EXR — — — — — — 3
@(d:16,ERs)→CCR 4
@(d:16,ERs)→EXR — — — — — — 4
@(d:32,ERs)→CCR 6
@(d:32,ERs)→EXR — — — — — — 6
@ERs→CCR,ERs32+2→ERs32 4
@ERs→EXR,ERs32+2→ERs32 — — — — — — 4
@aa:16→CCR 4
@aa:16→EXR — — — — — — 4
@aa:32→CCR 5
@aa:32→EXR — — — — — — 5
Operation
Condition Code
IHNZVC Advanced
No. of States
*
1
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 785 of 1042
REJ09B0275-0500
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
STC
ANDC
ORC
XORC
NOP
STC CCR,Rd B 2
STC EXR,Rd B 2
STC CCR,@ERd W 4
STC EXR,@ERd W 4
STC CCR,@(d:16,ERd) W 6
STC EXR,@(d:16,ERd) W 6
STC CCR,@(d:32,ERd) W 10
STC EXR,@(d:32,ERd) W 10
STC CCR,@-ERd W 4
STC EXR,@-ERd W 4
STC CCR,@aa:16 W 6
STC EXR,@aa:16 W 6
STC CCR,@aa:32 W 8
STC EXR,@aa:32 W 8
ANDC #xx:8,CCR B 2
ANDC #xx:8,EXR B 4
ORC #xx:8,CCR B 2
ORC #xx:8,EXR B 4
XORC #xx:8,CCR B 2
XORC #xx:8,EXR B 4
NOP — 2
CCR→Rd8 — — — — — — 1
EXR→Rd8 — — — — — — 1
CCR→@ERd — — — — — — 3
EXR→@ERd — — — — — — 3
CCR→@(d:16,ERd) — — — — — — 4
EXR→@(d:16,ERd) — — — — — — 4
CCR→@(d:32,ERd) — — — — — — 6
EXR→@(d:32,ERd) — — — — — — 6
ERd32-2→ERd32,CCR→@ERd — — — — — — 4
ERd32-2→ERd32,EXR→@ERd — — — — — — 4
CCR→@aa:16 — — — — — — 4
EXR→@aa:16 — — — — — — 4
CCR→@aa:32 — — — — — — 5
EXR→@aa:32 — — — — — — 5
CCR∧#xx:8→CCR 1
EXR∧#xx:8→EXR — — — — — — 2
CCR∨#xx:8→CCR 1
EXR∨#xx:8→EXR — — — — — — 2
CCR⊕#xx:8→CCR 1
EXR⊕#xx:8→EXR — — — — — — 2
PC←PC+2 — — — — — — 1
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 786 of 1042
REJ09B0275-0500
(8) Block Transfer Instructions
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@–ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Mnemonic
EEPMOV
Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory.
2. n is the initial value of R4L or R4.
3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
[1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers.
[2] Cannot be used in the H8S/2626 Group or H8S/2623 Group.
[3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
[4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
[5] Retains its previous value when the result is zero; otherwise cleared to 0.
[6] Set to 1 when the divisor is negative; otherwise cleared to 0.
[7] Set to 1 when the divisor is zero; otherwise cleared to 0.
[8] Set to 1 when the quotient is negative; otherwise cleared to 0.
[9] One additional state is required for execution when EXR is valid.
[10] MAC instruction results are indicated in the flags when the STMAC instruction is executed.
[11] A maximum of three additional states are required for execution of one of these instructions within three states after execution of a
MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions,
that instruction will be two states longer.
EEPMOV.B — 4
EEPMOV.W — 4
if R4L≠0 — — — — — — 4+2n*
2
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4L-1→R4L
Until R4L=0
else next;
if R4≠0 — — — — — — 4+2n*
2
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4-1→R4
Until R4=0
else next;
Operation
Condition Code
IHNZVC Advanced
No. of States*
1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 787 of 1042
REJ09B0275-0500
A.2 Instruction Codes
Table A.2 shows the instruction codes.
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 788 of 1042
REJ09B0275-0500
Table A.2 Instruction Codes
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
B
B
W
W
L
L
L
L
L
B
B
B
B
W
W
L
L
B
B
B
B
B
B
B
—
—
—
—
1
0
0
ers
IMM
erd
0
0
0
0
0
0
erd
erd
erd
erd
erd
erd
ers
IMM
IMM
0 erd
0 IMM
0 IMM
0
0
0
8
0
7
0
7
0
0
0
0
9
0
E
1
7
6
7
0
0
0
7
7
7
6
6
4
5
4
5
rd
8
9
9
A
A
B
B
B
rd
E
rd
6
9
6
A
1
6
1
6
C
E
A
A
0
8
1
8
rd
rd
rd
rd
rd
rd
rd
0
1
rd
0
0
0
0
0
6
0
7
7
6
6
6
6
0
0
76 0
76 0
IMM
IMM
IMM
IMM
abs
disp
disp
rs
1
rs
1
0
8
9
rs
rs
6
rs
6
F
4
1
3
0
1
IMM
IMM
abs
disp
disp
IMM
IMM
abs
IMM
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 789 of 1042
REJ09B0275-0500
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
Bcc —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
8
A
8
B
8
C
8
D
8
E
8
F
8
2
3
4
5
6
7
8
9
A
B
C
D
E
F
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 790 of 1042
REJ09B0275-0500
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
BCLR
BIAND
BILD
BIOR
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
0
0
0
1
0
1
0
1
0
IMM
erd
erd
IMM
erd
IMM
erd
IMM
erd
0
1
1
1
IMM
IMM
IMM
IMM
0
1
1
1
IMM
IMM
IMM
IMM
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
2
D
F
A
A
2
D
F
A
A
6
C
E
A
A
7
C
E
A
A
4
C
E
A
A
1
3
rn
1
3
1
3
1
3
1
3
rd
0
8
8
rd
0
8
8
rd
0
0
0
rd
0
0
0
rd
0
0
0
7
7
6
6
7
7
7
7
7
7
2
2
2
2
6
6
7
7
4
4
rn
rn
0
0
0
0
0
0
0
0
0
0
7
6
7
7
7
2
2
6
7
4
rn
0
0
0
0
0
7
6
7
7
7
2
2
6
7
4
rn
0
0
0
0
0
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
0
0
1
1
1
1
1
1
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 791 of 1042
REJ09B0275-0500
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
BIST
BIXOR
BLD
BNOT
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
1
0
1
0
0
0
0
0
0
IMM
erd
IMM
erd
IMM
erd
IMM
erd
erd
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
1
1
0
0
IMM
IMM
IMM
IMM
1
1
0
0
IMM
IMM
IMM
IMM
1
1
1
1
0
0
0
0
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
7
D
F
A
A
5
C
E
A
A
7
C
E
A
A
1
D
F
A
A
1
D
F
A
A
1
3
1
3
1
3
1
3
rn
1
3
rd
0
8
8
rd
0
0
0
rd
0
0
0
rd
0
8
8
rd
0
8
8
6
6
7
7
7
7
7
7
6
6
7
7
5
5
7
7
1
1
1
1
rn
rn
0
0
0
0
0
0
0
0
0
0
6
7
7
7
6
7
5
7
1
1rn
0
0
0
0
0
6
7
7
7
6
7
5
7
1
1rn
0
0
0
0
0
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
abs
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 792 of 1042
REJ09B0275-0500
BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BSR d:8
BSR d:16
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
BOR
BSET
BSR
BST
BTST
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
—
—
B
B
B
B
B
B
B
B
B
B
B
B
0
0
0
0
0
0
0
0
0
0
IMM
erd
IMM
erd
erd
IMM
erd
IMM
erd
erd
abs
abs
abs
disp
abs
abs
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
0
0
0
0
IMM
IMM
IMM
IMM
0
0
0
0
IMM
IMM
IMM
IMM
0
0
0
0
0
0
0
0
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
5
5
6
7
7
6
6
7
7
7
6
6
6
7
4
C
E
A
A
0
D
F
A
A
0
D
F
A
A
5
C
7
D
F
A
A
3
C
E
A
A
3
C
1
3
1
3
rn
1
3
0
1
3
1
3
rn
rd
0
0
0
rd
0
8
8
rd
0
8
8
0
rd
0
8
8
rd
0
0
0
rd
0
7
7
7
7
6
6
6
6
7
7
6
4
4
0
0
0
0
7
7
3
3
3
rn
rn
rn
0
0
0
0
0
0
0
0
0
0
0
7
7
6
6
7
4
0
0
7
3
rn
0
0
0
0
0
7
7
6
6
7
4
0
0
7
3
rn
0
0
0
0
0
abs
abs
abs
disp
abs
abs
abs
abs
abs
abs
abs
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 793 of 1042
REJ09B0275-0500
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
CLRMAC
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
DAA Rd
DAS Rd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
EEPMOV.B
EEPMOV.W
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
BTST
BXOR
CLRMAC
CMP
DAA
DAS
DEC
DIVXS
DIVXU
EEPMOV
B
B
B
B
B
B
B
B
—
B
B
W
W
L
L
B
B
B
W
W
L
L
B
W
B
W
—
—
0
0
1
IMM
erd
ers
0
0
0
0
0
erd
erd
erd
erd
erd
IMM
IMM
0 erd
0 IMM
0 IMM
0
0
7
6
6
7
7
7
6
6
0
A
1
7
1
7
1
0
1
1
1
1
1
1
0
0
5
5
7
7
E
A
A
5
C
E
A
A
1
rd
C
9
D
A
F
F
F
A
B
B
B
B
1
1
1
3
B
B
1
3
1
3
A
rs
2
rs
2
0
0
0
5
D
7
F
D
D
rs
rs
5
D
0
0
rd
0
0
0
0
rd
rd
rd
rd
rd
rd
rd
rd
0
0
rd
C
4
6
7
7
5
5
5
5
3
5
5
1
3
9
9
rn
rs
rs
8
8
0
0
0
rd
F
F
6
7
3
5
rn 0
0
6
7
3
5
rn 0
0
abs
abs
IMM
abs
abs
IMM
abs
abs
IMM
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 794 of 1042
REJ09B0275-0500
EXTS.W Rd
EXTS.L ERd
EXTU.W Rd
EXTU.L ERd
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
JMP @ERn
JMP @aa:24
JMP @@aa:8
JSR @ERn
JSR @aa:24
JSR @@aa:8
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
EXTS
EXTU
INC
JMP
JSR
LDC
W
L
W
L
B
W
W
L
L
—
—
—
—
—
—
B
B
B
B
W
W
W
W
W
W
W
W
W
W
0
0
ern
ern
0
0
0
0
erd
erd
erd
erd
ers
ers
ers
ers
ers
ers
ers
ers
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
5
5
5
5
5
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
7
7
A
B
B
B
B
9
A
B
D
E
F
7
1
3
3
1
1
1
1
1
1
1
1
1
1
D
F
5
7
0
5
D
7
F
4
0
1
4
4
4
4
4
4
4
4
4
4
rd
rd
rd
rd
rd
0
0
1
rs
rs
0
1
0
1
0
1
0
1
0
1
0
6
6
6
6
7
7
6
6
6
6
7
9
9
F
F
8
8
D
D
B
B
0
0
0
0
0
0
0
0
0
0
0
0
6
6
B
B
2
2
0
0
abs
abs
abs
abs
IMM
IMM
disp
disp
disp
disp
disp
disp
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 795 of 1042
REJ09B0275-0500
0
0
rd
abs
rs
rd
LDC @aa:32,CCR
LDC @aa:32,EXR
LDM.L @SP+, (ERn-ERn+1)
LDM.L @SP+, (ERn-ERn+2)
LDM.L @SP+, (ERn-ERn+3)
LDMAC ERs,MACH
LDMAC ERs,MACL
MAC @ERn+,@ERm+
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa :16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
LDC
LDM
LDMAC
MAC
MOV
W
W
L
L
L
L
L
—
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
0
0
0
0
1
1
0
1
0
0
0
ers
ers
ers
ers
erd
erd
erd
erd
ers
ers
ers
0
0
ers
ers
ern
0
0
0
0
ern+1
ern+2
ern+3
erm0
0
0
0
0
0
0
0
0
F
0
6
6
7
6
2
6
6
6
6
7
6
3
6
6
7
0
6
6
7
1
1
1
1
1
3
3
1
rd
C
8
E
8
C
rd
A
A
8
E
8
C
rs
A
A
9
D
9
F
8
4
4
1
2
3
2
3
6
rs
0
2
8
A
0
rs
0
1
0
0
0
0
rd
rd
rd
0
rd
rd
rd
rs
rs
0
rs
rs
rs
rd
rd
rd
rd
0
6
6
6
6
6
6
6
6
6
B
B
D
D
D
D
A
A
B
2
2
7
7
7
2
A
2
IMM
abs
abs
disp
abs
disp
abs
IMM
disp
abs
abs
abs
abs
disp
disp
disp
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 796 of 1042
REJ09B0275-0500
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,Rd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16 ,ERd
MOV.L @aa:32 ,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd)
*
1
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
MULXS.B Rs,Rd
MULXS.W Rs,ERd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
MOV
MOVFPE
MOVTPE
MULXS
MULXU
W
W
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
B
B
B
W
B
W
0
1
1
0
1
1
ers
erd
erd
erd
erd
ers
0
0
0
erd
erd
erd
ers
ers
ers
ers
erd
erd
erd
erd
0
0
0
0
0
0
0
0
0
0
0
erd
erd
erd
erd
erd
ers
ers
ers
ers
ers
erd
0
0
erd
ers
0
0
0
0
1
1
0
1
6
6
6
6
6
7
6
6
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
5
D
B
B
9
F
8
D
B
B
A
F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
0
2
8
A
0
0
0
0
0
0
0
0
0
0
0
0
0
C
C
rs
rs
rd
rd
rd
rs
rs
0
rs
rs
rs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rd
6
6
6
7
6
6
6
6
6
7
6
6
6
5
5
B
9
F
8
D
B
B
9
F
8
D
B
B
0
2
A
0
2
8
A
rs
rs
rs
0
0
rd
6
6
B
B
2
A
abs
abs
IMM
Cannot be used in the H8S/2626 Group or H8S/2623 Group.
disp
abs
disp
abs
disp
abs
abs
disp
disp
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 797 of 1042
REJ09B0275-0500
NEG.B Rd
NEG.W Rd
NEG.L ERd
NOP
NOT.B Rd
NOT.W Rd
NOT.L ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
ORC #xx:8,CCR
ORC #xx:8,EXR
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
ROTL.B Rd
ROTL.B #2, Rd
ROTL.W Rd
ROTL.W #2, Rd
ROTL.L ERd
ROTL.L #2, ERd
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
NEG
NOP
NOT
OR
ORC
POP
PUSH
ROTL
B
W
L
—
B
W
L
B
B
W
W
L
L
B
B
W
L
W
L
B
B
W
W
L
L
0
0
0
0
0
erd
erd
erd
erd
erd
1
1
1
0
1
1
1
C
1
7
6
7
0
0
0
6
0
6
0
1
1
1
1
1
1
7
7
7
0
7
7
7
rd
4
9
4
A
1
4
1
D
1
D
1
2
2
2
2
2
2
8
9
B
0
0
1
3
rs
4
rs
4
F
4
7
0
F
0
8
C
9
D
B
F
rd
rd
0
rd
rd
rd
rd
rd
0
1
rn
0
rn
0
rd
rd
rd
rd
IMM
IMM
6
0
6
6
4
4
D
D
ers 0
0
0
erd
ern
ern
0
7
F
IMM
IMM
IMM
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 798 of 1042
REJ09B0275-0500
ROTR.B Rd
ROTR.B #2, Rd
ROTR.W Rd
ROTR.W #2, Rd
ROTR.L ERd
ROTR.L #2, ERd
ROTXL.B Rd
ROTXL.B #2, Rd
ROTXL.W Rd
ROTXL.W #2, Rd
ROTXL.L ERd
ROTXL.L #2, ERd
ROTXR.B Rd
ROTXR.B #2, Rd
ROTXR.W Rd
ROTXR.W #2, Rd
ROTXR.L ERd
ROTXR.L #2, ERd
RTE
RTS
SHAL.B Rd
SHAL.B #2, Rd
SHAL.W Rd
SHAL.W #2, Rd
SHAL.L ERd
SHAL.L #2, ERd
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
ROTR
ROTXL
ROTXR
RTE
RTS
SHAL
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
—
B
B
W
W
L
L
0
0
0
0
0
0
0
0
erd
erd
erd
erd
erd
erd
erd
erd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
1
1
1
1
1
1
3
3
3
3
3
3
2
2
2
2
2
2
3
3
3
3
3
3
6
4
0
0
0
0
0
0
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
7
7
8
C
9
D
B
F
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
0
0
rd
rd
rd
rd
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 799 of 1042
REJ09B0275-0500
SHAR.B Rd
SHAR.B #2, Rd
SHAR.W Rd
SHAR.W #2, Rd
SHAR.L ERd
SHAR.L #2, ERd
SHLL.B Rd
SHLL.B #2, Rd
SHLL.W Rd
SHLL.W #2, Rd
SHLL.L ERd
SHLL.L #2, ERd
SHLR.B Rd
SHLR.B #2, Rd
SHLR.W Rd
SHLR.W #2, Rd
SHLR.L ERd
SHLR.L #2, ERd
SLEEP
STC.B CCR,Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:16,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:32,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-ERd
STC.W EXR,@-ERd
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
SHAR
SHLL
SHLR
SLEEP
STC
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
B
B
W
W
W
W
W
W
W
W
0
0
0
0
0
0
erd
erd
erd
erd
erd
erd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
8
0
1
4
4
4
4
4
4
4
4
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
rd
0
rd
rd
0
1
0
1
0
1
0
1
erd
erd
erd
erd
erd
erd
erd
erd
1
1
1
1
0
0
1
1
6
6
6
6
7
7
6
6
9
9
F
F
8
8
D
D
0
0
0
0
0
0
0
0
6
6
B
B
A
A
0
0
disp
disp
disp
disp
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 800 of 1042
REJ09B0275-0500
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
STM.L(ERn-ERn+1), @-SP
STM.L (ERn-ERn+2), @-SP
STM.L (ERn-ERn+3), @-SP
STMAC MACH,ERd
STMAC MACL,ERd
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
TAS @ERd*
2
TRAPA #x:2
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
STC
STM
STMAC
SUB
SUBS
SUBX
TAS
TRAPA
XOR
W
W
W
W
L
L
L
L
L
B
W
W
L
L
L
L
L
B
B
B
—
B
B
W
W
L
L
1
00
ers
IMM
0
0
0
0
0
0
0
0
ers
ers
erd
erd
erd
erd
erd
erd
erd
ers
0
0
0
0
ern
ern
ern
erd
0
0
0
0
0
0
0
0
0
0
0
1
7
1
7
1
1
1
1
B
1
0
5
D
1
7
6
7
0
1
1
1
1
1
1
1
2
2
8
9
9
A
A
B
B
B
rd
E
1
7
rd
5
9
5
A
1
4
4
4
4
1
2
3
2
3
rs
3
rs
3
0
8
9
rs
E
rs
5
rs
5
F
0
1
0
1
0
0
0
rd
rd
rd
rd
0
0
rd
rd
rd
0
6
6
6
6
6
6
6
7
6
B
B
B
B
D
D
D
B
5
8
8
A
A
F
F
F
0
0
0
0
C
abs
abs
abs
abs
IMM
IMM
IMM
IMM
IMM
IMM
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 801 of 1042
REJ09B0275-0500
XORC #xx:8,CCR
XORC #xx:8,EXR
Mnemonic Size Instruction Format
1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Instruc-
tion
XORC B
B
0
0
5
1
4
1 0 5
IMM
IMM
Notes: 1. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Legend:
Address Register
32-Bit Register
Register
Field General
Register Register
Field General
Register Register
Field General
Register
000
001
•
•
•
111
ER0
ER1
•
•
•
ER7
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
R0
R1
•
•
•
R7
E0
E1
•
•
•
E7
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
R0H
R1H
•
•
•
R7H
R0L
R1L
•
•
•
R7L
16-Bit Register 8-Bit Register
IMM:
abs:
disp:
rs, rd, rn:
ers, erd, ern, erm:
The register fields specify general registers as follows.
Immediate data (2, 3, 8, 16, or 32 bits)
Absolute address (8, 16, 24, or 32 bits)
Displacement (8, 16, or 32 bits)
Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.)
Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand
symbols ERs, ERd, ERn, and ERm.)
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 802 of 1042
REJ09B0275-0500
A.3 Operation Code Map
Table A.3 shows the operation code map.
Table A.3 Operation Code Map (1)
Instruction code 1st byte 2nd byte
AH AL BH BL
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
0
NOP
BRA
MULXU
BSET
AH AL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
BRN
DIVXU
BNOT
2
BHI
MULXU
BCLR
3
BLS
DIVXU
BTST
STC
**
STMAC
LDC
LDMAC
4
ORC
OR
BCC
RTS
OR
BORBIOR
6
ANDC
AND
BNE
RTE
AND
5
XORC
XOR
BCS
BSR
XOR
BXOR
BIXOR
BAND
BIAND
7
LDC
BEQ
TRAPA
BST BIST
BLD BILD
8
BVC
MOV
9
BVS
A
BPL
JMP
B
BMI
EEPMOV
C
BGE
BSR
D
BLT
MOV
E
ADDX
SUBX
BGT
JSR
F
BLE
MOV.B
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
ADD
SUB
MOV
MOV
CMP
Table
A.3(2)
Table
A.3(2)
Table
A.3(2) Table
A.3(2) Table
A.3(2) Table
A.3(2) Table
A.3(2)
Table
A.3(2) Table
A.3(2)
Table
A.3(2) Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table
A.3(2)
Table A.3(3)
Note: * Cannot be used in the H8S/2626 Group or H8S/2623 Group.
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 803 of 1042
REJ09B0275-0500
Table A.3 Operation Code Map (2)
Instruction code 1st byte 2nd byte
AH AL BH BL
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
6A
79
7A
0
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
MOV
SHLL
SHLR
ROTXL
ROTXR
NOT
1
LDM
BRN
ADD
ADD
2
BHI
MOV
CMP
CMP
3
STM
NOT
BLS
SUB
SUB
4
SHLL
SHLR
ROTXL
ROTXR
BCC
MOVFPE
OR
OR
5
INC
EXTU
DEC
BCS
XOR
XOR
6
MAC
BNE
AND
AND
7
INC
SHLL
SHLR
ROTXL
ROTXR
EXTU
DEC
BEQ
LDCSTC
8
SLEEP
BVC
MOV
ADDS
SHAL
SHAR
ROTL
ROTR
NEG
SUBS
9
BVS
A
CLRMAC
BPL
MOV
B
NEG
BMI
ADD
MOV
SUB
CMP
C
SHAL
SHAR
ROTL
ROTR
BGE
MOVTPE
D
INC
EXTS
DEC
BLT
E
TAS
BGT
F
INC
SHAL
SHAR
ROTL
ROTR
EXTS
DEC
BLE
BH
AH AL
Table
A.3(3) Table
A.3(3) Table
A.3(3)
Table
A.3(4) Table
A.3(4)
**
Note: * Cannot be used in the H8S/2626 Group or H8S/2623 Group.
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 804 of 1042
REJ09B0275-0500
Table A.3 Operation Code Map (3)
Instruction code 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
r is the register specification field.
aa is the absolute address specification.
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Notes:
AH AL BH BL CH
CL
01C05
01D05
01F06
7Cr06 *
1
7Cr07 *
1
7Dr06 *
1
7Dr07 *
1
7Eaa6 *
2
7Eaa7 *
2
7Faa6 *
2
7Faa7 *
2
0
MULXS
BSET
BSET
BSET
BSET
1
DIVXS
BNOT
BNOT
BNOT
BNOT
2
MULXS
BCLR
BCLR
BCLR
BCLR
3
DIVXS
BTST
BTST
BTST
BTST
4
OR
5
XOR
6
AND
789ABCDEF
1.
2.
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 805 of 1042
REJ09B0275-0500
Table A.3 Operation Code Map (4)
Instruction code 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
Instruction when most significant bit of FH is 0.
Instruction when most significant bit of FH is 1.
5th byte 6th byte
EH EL FH FL
Instruction code 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
Instruction when most significant bit of HH is 0.
Instruction when most significant bit of HH is 1.
Note: * aa is the absolute address specification.
5th byte 6th byte
EH EL FH FL
7th byte 8th byte
GH GL HH HL
6A10aaaa6*
6A10aaaa7*
6A18aaaa6*
6A18aaaa7*
AHALBHBLCHCLDHDLEH
EL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
6A30aaaaaaaa6
*
6A30aaaaaaaa7
*
6A38aaaaaaaa6
*
6A38aaaaaaaa7
*
AHALBHBL ... FHFLGH
GL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 806 of 1042
REJ09B0275-0500
A.4 Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. Table A.4 indicates the number of states required for
each cycle. The number of states required for execution of an instruction can be calculated from
these two tables as fo llows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: Advanced mode, program code and stack located in external memory, on-chip
supporting modules accessed in two states with 8-bit bus width, external devices accessed in three
states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
From table A.5:
I = L = 2, J = K = M = N = 0
From table A.4:
SI = 4, SL = 2
Number of states required for execution = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A.5:
I = J = K = 2, L = M = N = 0
From table A.4:
SI = SJ = SK = 4
Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 807 of 1042
REJ09B0275-0500
Table A.4 Number of States per Cycle
Access Conditions
External DeviceOn-Chip
Supporting
Module 8-Bit Bus 16-Bit Bus
Cycle On-Chip
Memory
8-Bit
Bus 16-Bit
Bus 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI
Branch address read SJ
Stack operation SK
4 4 6 + 2m
Byte data access SL223 + m
Word data access SM
1
4
2
46 + 2m
23 + m
Internal operation SN1 111111
Legend:
m: Number of wait states inserted into external device access
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 808 of 1042
REJ09B0275-0500
Table A.5 Number of Cycles in Instruction Execution
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8,Rd 1
ADD.B Rs,Rd 1
ADD.W #xx:16,Rd 2
ADD.W Rs,Rd 1
ADD.L #xx:32,ERd 3
ADD.L ERs,ERd 1
ADDS ADDS #1/2/4,ERd 1
ADDX ADDX #xx:8,Rd 1
ADDX Rs,Rd 1
AND AND.B #xx:8,Rd 1
AND.B Rs,Rd 1
AND.W #xx:16,Rd 2
AND.W Rs,Rd 1
AND.L #xx:32,ERd 3
AND.L ERs,ERd 2
ANDC ANDC #xx:8,CCR 1
ANDC #xx:8,EXR 2
BAND BAND #xx:3,Rd 1
BAND #xx:3,@ERd 2 1
BAND #xx:3,@aa:8 2 1
BAND #xx:3,@aa:16 3 1
BAND #xx:3,@aa:32 4 1
Bcc BRA d:8 (BT d:8) 2
BRN d:8 (BF d:8) 2
BHI d:8 2
BLS d:8 2
BCC d:8 (BHS d:8) 2
BCS d:8 (BLO d:8) 2
BNE d:8 2
BEQ d:8 2
BVC d:8 2
BVS d:8 2
BPL d:8 2
BMI d:8 2
BGE d:8 2
BLT d:8 2
BGT d:8 2
BLE d:8 2
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 809 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Bcc BRA d:16 (BT d:16) 2 1
BRN d:16 (BF d:16) 2 1
BHI d:16 2 1
BLS d:16 2 1
BCC d:16 (BHS d:16) 2 1
BCS d:16 (BLO d:16) 2 1
BNE d:16 2 1
BEQ d:16 2 1
BVC d:16 2 1
BVS d:16 2 1
BPL d:16 2 1
BMI d:16 2 1
BGE d:16 2 1
BLT d:16 2 1
BGT d:16 2 1
BLE d:16 2 1
BCLR BCLR #xx:3,Rd 1
BCLR #xx:3,@ERd 2 2
BCLR #xx:3,@aa:8 2 2
BCLR #xx:3,@aa:16 3 2
BCLR #xx:3,@aa:32 4 2
BCLR Rn,Rd 1
BCLR Rn,@ERd 2 2
BCLR Rn,@aa:8 2 2
BCLR Rn,@aa:16 3 2
BCLR Rn,@aa:32 4 2
BIAND BIAND #xx:3,Rd 1
BIAND #xx:3,@ERd 2 1
BIAND #xx:3,@aa:8 2 1
BIAND #xx:3,@aa:16 3 1
BIAND #xx:3,@aa:32 4 1
BILD BILD #xx:3,Rd 1
BILD #xx:3,@ERd 2 1
BILD #xx:3,@aa:8 2 1
BILD #xx :3,@aa:16 3 1
BILD #xx :3,@aa:32 4 1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 810 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BIOR BIOR #xx:8,Rd 1
BIOR #xx:8,@ERd 2 1
BIOR #xx:8,@aa:8 2 1
BIOR #xx:8,@aa:16 3 1
BIOR #xx:8,@aa:32 4 1
BIST BIST #xx:3,Rd 1
BIST #xx:3,@ERd 2 2
BIST #xx:3,@aa:8 2 2
BIST #xx:3,@ aa:16 3 2
BIST #xx:3,@ aa:32 4 2
BIXOR BIXOR #xx:3,Rd 1
BIXOR #xx:3,@ERd 2 1
BIXOR #xx:3,@aa:8 2 1
BIXOR #xx:3,@aa:16 3 1
BIXOR #xx:3,@aa:32 4 1
BLD BLD #xx:3,Rd 1
BLD #xx:3,@ERd 2 1
BLD #xx:3,@aa:8 2 1
BLD #xx:3,@aa:16 3 1
BLD #xx:3,@aa:32 4 1
BNOT BNOT #xx:3,Rd 1
BNOT #xx:3,@ER d 2 2
BNOT #xx:3,@aa:8 2 2
BNOT #xx:3,@aa:16 3 2
BNOT #xx:3,@aa:32 4 2
BNOT Rn,Rd 1
BNOT Rn,@ERd 2 2
BNOT Rn,@aa:8 2 2
BNOT Rn,@aa:16 3 2
BNOT Rn,@aa:32 4 2
BOR BOR #xx:3,Rd 1
BOR #xx:3,@ERd 2 1
BOR #xx:3,@aa:8 2 1
BOR #xx:3,@aa:16 3 1
BOR #xx:3,@aa:32 4 1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 811 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BSET BSET #xx:3,Rd 1
BSET #xx:3, @ERd 2 2
BSET #xx:3,@aa:8 2 2
BSET #xx:3,@aa:16 3 2
BSET #xx:3,@aa:32 4 2
BSET Rn,Rd 1
BSET Rn,@ERd 2 2
BSET Rn,@aa:8 2 2
BSET Rn,@aa:16 3 2
BSET Rn,@aa:32 4 2
BSR BSR d:8 2 2
BSR d:16 2 2 1
BST BST #xx:3,Rd 1
BST #xx:3,@ERd 2 2
BST #xx:3,@aa:8 2 2
BST #xx:3,@aa:16 3 2
BST #xx:3,@aa:32 4 2
BTST BTST #xx:3,Rd 1
BTST #xx:3,@ERd 2 1
BTST #xx:3,@ aa: 8 2 1
BTST #xx:3,@ aa: 16 3 1
BTST #xx:3,@ aa: 32 4 1
BTST Rn,Rd 1
BTST Rn,@ERd 2 1
BTST Rn,@aa:8 2 1
BTST Rn,@aa:16 3 1
BTST Rn,@aa:32 4 1
BXOR BXOR #xx:3,Rd 1
BXOR #xx:3,@ERd 2 1
BXOR #xx:3,@aa:8 2 1
BXOR #xx:3,@aa:16 3 1
BXOR #xx:3,@aa:32 4 1
CLRMAC CLRMAC 1 1*3
CMP CMP.B #xx:8,Rd 1
CMP.B Rs,Rd 1
CMP.W #xx:16,Rd 2
CMP.W Rs,Rd 1
CMP.L #xx:32 ,E Rd 3
CMP.L ERs,ERd 1
DAA DAA Rd 1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 812 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
DAS DAS Rd 1
DEC DEC.B Rd 1
DEC.W #1/2,Rd 1
DEC.L #1/2,ERd 1
DIVXS DIVXS.B Rs,Rd 2 11
DIVXS.W Rs,ERd 2 19
DIVXU DIVXU.B Rs,Rd 1 11
DIVXU.W Rs,ERd 1 19
EEPMOV EEPMOV.B 2 2n + 2*2
EEPMOV.W 2 2n + 2*2
EXTS EXTS.W Rd 1
EXTS.L ERd 1
EXTU EXTU.W Rd 1
EXTU.L ERd 1
INC INC.B Rd 1
INC.W #1/2,Rd 1
INC.L #1/2,E R d 1
JMP JMP @ERn 2
JMP @aa:24 2 1
JMP @@aa:8 2 2 1
JSR JSR @ERn 2 2
JSR @aa:24 2 2 1
JSR @@aa:8 2 2 2
LDC LDC #xx:8,CCR 1
LDC #xx:8,EXR 2
LDC Rs,CCR 1
LDC Rs,EXR 1
LDC @ERs,CCR 2 1
LDC @ERs,EXR 2 1
LDC @(d:16,ERs),CCR 3 1
LDC @(d:16,ERs),EXR 3 1
LDC @(d:32,ERs),CCR 5 1
LDC @(d:32,ERs),EXR 5 1
LDC @ERs+,CCR 2 1 1
LDC @ERs+,EXR 2 1 1
LDC @aa:16,CCR 3 1
LDC @aa:16,EXR 3 1
LDC @aa:32,CCR 4 1
LDC @aa:32,EXR 4 1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 813 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
LDM LDM.L @SP+, (ERn-ERn+1) 2 4 1
LDM.L @SP+, (ERn-ERn+2) 2 6 1
LDM.L @SP+, (ERn-ERn+3) 2 8 1
LDMAC LDMAC ERs,MACH 1 1*3
LDMAC ERs,MACL 1 1*3
MAC MAC @ERn+,@ERm+ 2 2
MOV MOV.B #xx: 8,Rd 1
MOV.B Rs,Rd 1
MOV.B @ERs,Rd 1 1
MOV.B @(d:16,ERs),Rd 2 1
MOV.B @(d:32,ERs),Rd 4 1
MOV.B @ERs+,Rd 1 1 1
MOV.B @aa:8,Rd 1 1
MOV.B @aa:16,Rd 2 1
MOV.B @aa:32,Rd 3 1
MOV.B Rs,@ERd 1 1
MOV.B Rs,@(d:16,ERd) 2 1
MOV.B Rs,@(d:32,ERd) 4 1
MOV.B Rs,@-ERd 1 1 1
MOV.B Rs,@aa: 8 1 1
MOV.B Rs,@aa: 16 2 1
MOV.B Rs,@aa: 32 3 1
MOV.W #xx:16,Rd 2
MOV.W Rs,Rd 1
MOV.W @ERs ,R d 1 1
MOV.W @(d:16,ERs),Rd 2 1
MOV.W @(d:32,ERs),Rd 4 1
MOV.W @ERs+,Rd 1 1 1
MOV.W @aa:16,Rd 2 1
MOV.W @aa:32,Rd 3 1
MOV.W Rs,@ERd 1 1
MOV.W Rs,@(d:16,E R d) 2 1
MOV.W Rs,@(d:32,E R d) 4 1
MOV.W Rs,@-ERd 1 1 1
MOV.W Rs,@aa:16 2 1
MOV.W Rs,@aa:32 3 1
MOV.L #xx:32,ERd 3
MOV.L ERs,ERd 1
MOV.L @ERs,ERd 2 2
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 814 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOV MOV.L @(d:16,ERs),ERd 3 2
MOV.L @(d:32,ERs),ERd 5 2
MOV.L @ERs+,ERd 2 2 1
MOV.L @aa:16,ERd 3 2
MOV.L @aa:32,ERd 4 2
MOV.L ERs,@ERd 2 2
MOV.L ERs,@(d:16,ERd) 3 2
MOV.L ERs,@(d:32,ERd) 5 2
MOV.L ERs,@-ERd 2 2 1
MOV.L ERs,@aa:16 3 2
MOV.L ERs,@aa:32 4 2
MOVFPE MOVFPE @:aa:16,Rd
MOVTPE MOVTPE Rs,@:aa:16
Can not be used in the H8S/2626 Group or H8S/2623 Group.
MULXS MULXS. B Rs,Rd 2 2*3
MULXS.W Rs,ERd 2 3*3
MULXU MULXU.B Rs,Rd 1 2*3
MULXU.W Rs,ERd 1 3*3
NEG NEG.B Rd 1
NEG.W Rd 1
NEG.L ERd 1
NOP NOP 1
NOT NOT.B Rd 1
NOT.W Rd 1
NOT.L ERd 1
OR OR.B #xx:8,Rd 1
OR.B Rs,Rd 1
OR.W #xx:16,Rd 2
OR.W Rs,Rd 1
OR.L #xx:32,ER d 3
OR.L ERs,ERd 2
ORC ORC #xx:8,CCR 1
ORC #xx:8,EXR 2
POP POP.W Rn 1 1 1
POP.L ERn 2 2 1
PUSH PUSH.W Rn 1 1 1
PUSH.L ERn 2 2 1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 815 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ROTL ROTL.B Rd 1
ROTL.B #2,Rd 1
ROTL.W Rd 1
ROTL.W #2,R d 1
ROTL.L ERd 1
ROTL.L #2,ERd 1
ROTR ROTR.B Rd 1
ROTR.B #2,Rd 1
ROTR.W Rd 1
ROTR.W #2,Rd 1
ROTR.L ERd 1
ROTR.L #2,ERd 1
ROTXL ROTXL.B Rd 1
ROTXL.B #2,Rd 1
ROTXL.W Rd 1
ROTXL.W #2,Rd 1
ROTXL.L ERd 1
ROTXL .L #2,E R d 1
ROTXR ROTXR.B Rd 1
ROTXR.B #2,Rd 1
ROTXR.W Rd 1
ROTXR.W #2,Rd 1
ROTXR.L ERd 1
ROTXR.L #2,ERd 1
RTE RTE 2 2/3*11
RTS RTS 2 2 1
SHAL SHAL.B Rd 1
SHAL.B #2,Rd 1
SHAL.W Rd 1
SHAL.W #2,Rd 1
SHAL.L ERd 1
SHAL.L #2,ERd 1
SHAR SHAR.B Rd 1
SHAR.B #2,Rd 1
SHAR.W Rd 1
SHAR.W #2,Rd 1
SHAR.L ERd 1
SHAR.L #2,ERd 1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 816 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SHLL SHLL.B Rd 1
SHLL.B #2,R d 1
SHLL.W Rd 1
SHLL.W #2, Rd 1
SHLL.L ERd 1
SHLL.L #2,ERd 1
SHLR SHLR.B Rd 1
SHLR.B #2,Rd 1
SHLR.W Rd 1
SHLR.W #2,R d 1
SHLR.L ERd 1
SHLR.L #2 ,ER d 1
SLEEP SLEEP 1 1
STC STC.B CCR,Rd 1
STC.B EXR,Rd 1
STC.W CCR,@ERd 2 1
STC.W EXR,@ERd 2 1
STC.W CCR,@(d:16,ERd) 3 1
STC.W EXR,@(d:16,ERd) 3 1
STC.W CCR,@(d:32,ERd) 5 1
STC.W EXR,@(d:32,ERd) 5 1
STC.W CCR,@-ERd 2 1 1
STC.W EXR,@-ERd 2 1 1
STC.W CCR,@aa:16 3 1
STC.W EXR,@aa:16 3 1
STC.W CCR,@aa:32 4 1
STC.W EXR,@aa:32 4 1
STM STM.L (ERn-ERn+1),@-SP 2 4 1
STM.L (ERn-ERn+2),@-SP 2 6 1
STM.L (ERn-ERn+3),@-SP 2 8 1
STMAC*3STMAC MACH,ERd 1 *3
STMAC MACL,ERd 1 *3
SUB SUB.B Rs,Rd 1
SUB.W #xx:16,Rd 2
SUB.W Rs,Rd 1
SUB.L #xx:32,ERd 3
SUB.L ERs,ERd 1
SUBS SUBS #1/2/4,ERd 1
SUBX SUBX #xx:8,Rd 1
SUBX Rs,Rd 1
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 817 of 1042
REJ09B0275-0500
Instruction Mnemonic
Instruction
Fetch
I
Branch
Address Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
TAS TAS @ERd *422
TRAPA TRAPA #x:2 2 2 2/3*12
XOR XOR.B #xx:8,Rd 1
XOR.B Rs,Rd 1
XOR.W #xx:16,Rd 2
XOR.W Rs,Rd 1
XOR.L #xx:32,E R d 3
XOR.L ERs,ERd 2
XORC XORC #xx:8,CCR 1
XORC #xx:8,EXR 2
Notes: 1. 2 when EXR is invalid, 3 when EXR is valid.
2. 5 for concatenated execution, 4 otherwise.
3. An internal operation may require between 0 and 3 additional states, depending on the
preceding instruction.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
A.5 Bus States during Instruction Execution
Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See
table A.4 for the number of states per cycle.
How to Read the Table:
Instruction
JMP@aa:24 R:W 2nd
Internal operation
2 state
R:W EA
12345678
End of instruction
Order of execution
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 818 of 1042
REJ09B0275-0500
Legend:
R:B Byte-size read
R:W Word-size read
W:B Byte-size wri te
W:W Word-size write
:M Transfer of the bus is not performed immediately after this cycle
2nd Address of 2nd word (3rd and 4th bytes)
3rd Address of 3rd word (5th and 6th bytes)
4th Address of 4th word (7th and 8th bytes)
5th Address of 5th word (9th and 10th bytes)
NEXT Address of next instruction
EA Effective address
VEC Vector address
Figure A.1 shows timing waveform s for the address bus and the RD, HWR, and LWR signals
during execution of th e above instruction with an 8-bit bus, using three-state access with no wait
states.
φ
Address bus
RD
HWR, LWR
R:W 2nd
Fetching
2nd byte of
instruction at
jump address
Fetching
1nd byte of
instruction at
jump address
Fetching
4th byte
of instruction
Fetching
3rd byte
of instruction
R:W EA
High level
Internal
operation
Figure A.1 Address Bus, RD
RDRD
RD, HWR
HWRHWR
HWR, and LWR
LWRLWR
LWR Timing
(8-Bit Bus, Three-State Access, No Wait States)
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 819 of 1042
REJ09B0275-0500
Table A.6 Instruction Execution Cycles
Instruction
ADD.B #xx:8,Rd R:W NEXT
ADD.B Rs,Rd R:W NEXT
ADD.W #xx:16,Rd R:W 2nd R:W NEXT
ADD.W Rs,Rd R:W NEXT
ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
ADD.L ERs,ERd R:W NEXT
ADDS #1/2/4,ERd R:W NEXT
ADDX #xx:8,Rd R:W NEXT
ADDX Rs,Rd R:W NEXT
AND.B #xx:8,Rd R:W NEXT
AND.B Rs,Rd R:W NEXT
AND.W #xx:16,Rd R:W 2nd R:W NEXT
AND.W Rs,Rd R:W NEXT
AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
AND.L ERs,ERd R:W 2nd R:W NEXT
ANDC #xx:8,CCR R:W NEXT
ANDC #xx:8,EXR R:W 2nd R:W NEXT
BAND #xx:3,Rd R:W NEXT
BAND #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BRA d:8 (BT d:8) R:W NEXT R:W EA
BRN d:8 (BF d:8) R:W NEXT R:W EA
BHI d:8 R:W NEXT R:W EA
BLS d:8 R:W NEXT R:W EA
BCC d:8 (BHS d:8) R:W NEXT R:W EA
BCS d:8 (BLO d:8) R:W NEXT R:W EA
BNE d:8 R:W NEXT R:W EA
BEQ d:8 R:W NEXT R:W EA
BVC d:8 R:W NEXT R:W EA
BVS d:8 R:W NEXT R:W EA
BPL d:8 R:W NEXT R:W EA
BMI d:8 R:W NEXT R:W EA
BGE d:8 R:W NEXT R:W EA
BLT d:8 R:W NEXT R:W EA
BGT d:8 R:W NEXT R:W EA
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 820 of 1042
REJ09B0275-0500
Instruction
BLE d:8 R:W NEXT R:W EA
BRA d:16 (BT d:16) R:W 2nd
Internal operation,
R:W EA
1 state
BRN d:16 (BF d:16) R:W 2nd
Internal operation,
R:W EA
1 state
BHI d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BLS d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BCC d:16 (BHS d:16) R:W 2nd
Internal operation,
R:W EA
1 state
BCS d:16 (BLO d:16) R:W 2nd
Internal operation,
R:W EA
1 state
BNE d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BEQ d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BVC d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BVS d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BPL d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BMI d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BGE d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BLT d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BGT d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BLE d:16 R:W 2nd
Internal operation,
R:W EA
1 state
BCLR #xx:3,Rd R:W NEXT
BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 821 of 1042
REJ09B0275-0500
Instruction
BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,Rd R:W NEXT
BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BIAND #xx:3,Rd R:W NEXT
BIAND #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BIAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BIAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BIAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BILD #xx:3,Rd R:W NEXT
BILD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BIOR #xx:3,Rd R:W NEXT
BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BIOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BIOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BIST #xx:3,Rd R:W NEXT
BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BIXOR #xx:3,Rd R:W NEXT
BIXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BIXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BIXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BIXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BLD #xx:3,Rd R:W NEXT
BLD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BNOT #xx:3,Rd R:W NEXT
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 822 of 1042
REJ09B0275-0500
Instruction
BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BNOT Rn,Rd R:W NEXT
BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BNOT Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BNOT Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BNOT Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BOR #xx:3,Rd R:W NEXT
BOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BSET #xx:3,Rd R:W NEXT
BSET #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BSET Rn,Rd R:W NEXT
BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BSR d:8 R:W NEXT R:W EA
W:W
:M
stack (H)
W:W stack (L)
BSR d:16 R:W 2nd
Internal operation,
R:W EA
W:W
:M
stack (H)
W:W stack (L)
1 state
BST #xx:3,Rd R:W NEXT
BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA
BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA
BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA
BTST #xx:3,Rd R:W NEXT
BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 823 of 1042
REJ09B0275-0500
Instruction 1 2 3 4 5 6 7 8 9
BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BTST Rn,Rd R:W NEXT
BTST Rn,@ERd R:W 2nd R:B EA R:W:M NEXT
BTST Rn,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
BXOR #xx:3,Rd R:W NEXT
BXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT
BXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT
BXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT
BXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT
CLRMAC R:W NEXT
Internal operation,
1 state
CMP.B #xx:8,Rd R:W NEXT
CMP.B Rs,Rd R:W NEXT
CMP.W #xx:16,Rd R:W 2nd R:W NEXT
CMP.W Rs,Rd R:W NEXT
CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
CMP.L ERs,ERd R:W NEXT
DAA Rd R:W NEXT
DAS Rd R:W NEXT
DEC.B Rd R:W NEXT
DEC.W #1/2,Rd R:W NEXT
DEC.L #1/2,ERd R:W NEXT
DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states
DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 19 states
DIVXU.B Rs,Rd R:W NEXT Internal operation, 11 states
DIVXU.W Rs,ERd R:W NEXT Internal operation, 19 states
EEPMOV.B R:W 2nd R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:W NEXT
EEPMOV.W R:W 2nd R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:W NEXT
EXTS.W Rd R:W NEXT ← Repeated n times*2 →
EXTS.L ERd R:W NEXT
EXTU.W Rd R:W NEXT
EXTU.L ERd R:W NEXT
INC.B Rd R:W NEXT
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 824 of 1042
REJ09B0275-0500
Instruction
INC.W #1/2,Rd R:W NEXT
INC.L #1/2,ERd R:W NEXT
JMP @ERn R:W NEXT R:W EA
JMP @aa:24 R:W 2nd
Internal operation,
R:W EA
1 state
JMP @@aa:8 R:W NEXT R:W:M aa:8 R:W aa:8
Internal operation,
R:W EA
1 state
JSR @ERn R:W NEXT R:W EA
W:W
:M
stack (H)
W:W stack (L)
JSR @aa:24
R:W 2nd
Internal operation,
R:W EA
W:W
:M
stack (H) W:W stack (L)
1 state
JSR @@aa:8 R:W NEXT R:W:M aa:8 R:W aa:8
W:W
:M
stack (H)
W:W stack (L)
R:W EA
LDC #xx:8,CCR R:W NEXT
LDC #xx:8,EXR R:W 2nd R:W NEXT
LDC Rs,CCR R:W NEXT
LDC Rs,EXR R:W NEXT
LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA
LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA
LDC @(d:16,ERs),CCR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC @(d:16,ERs),EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC @(d:32,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LDC @(d:32,ERs),EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LDC @ERs+,CCR R:W 2nd R:W NEXT
Internal operation,
R:W EA
1 state
LDC @ERs+,EXR R:W 2nd R:W NEXT
Internal operation,
R:W EA
1 state
LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LDC @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LDM.L @SP+, R:W 2nd R:W:M NEXT
Internal operation,
R:W:M stack (H)
*
3
R:W stack (L)
*
3
(ERn–ERn+1)
1 state
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 825 of 1042
REJ09B0275-0500
Instruction
LDM.L @SP+,(ERn–ERn+2)
R:W 2nd R:W NEXT
Internal operation,
R:W:M stack (H)
*
3
R:W stack (L)
*
3
1 state
LDM.L @SP+,(ERn–ERn+3)
R:W 2nd R:W NEXT
Internal operation,
R:W:M stack (H)
*
3
R:W stack (L)
*
3
1 state
LDMAC ERs,MACH R:W NEXT
Internal operation,
← Repeated n times
*
3
→
1 state
LDMAC ERs,MACL R:W NEXT
Internal operation,
1 state
MAC @ERn+,@ERm+ R:W 2nd R:W NEXT R:W EAn R:W EAm
MOV.B #xx:8,Rd R:W NEXT
MOV.B Rs,Rd R:W NEXT
MOV.B @ERs,Rd R:W NEXT R:B EA
MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA
MOV.B @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA
MOV.B @ERs+,Rd R:W NEXT
Internal operation,
R:B EA
1 state
MOV.B @aa:8,Rd R:W NEXT R:B EA
MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA
MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.B Rs,@ERd R:W NEXT W:B EA
MOV.B Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:B EA
MOV.B Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA
MOV.B Rs,@–ERd R:W NEXT
Internal operation,
W:B EA
1 state
MOV.B Rs,@aa:8 R:W NEXT W:B EA
MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA
MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:B EA
MOV.W #xx:16,Rd R:W 2nd R:W NEXT
MOV.W Rs,Rd R:W NEXT
MOV.W @ERs,Rd R:W NEXT R:W EA
MOV.W @(d:16,ERs),Rd R:W 2nd R:W NEXT R:W EA
MOV.W @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
MOV.W @ERs+, Rd R:W NEXT
Internal operation,
R:W EA
1 state
MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA
MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.W Rs,@ERd R:W NEXT W:W EA
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 826 of 1042
REJ09B0275-0500
Instruction 1 2 3 4 5 6 7 8 9
MOV.W Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:W EA
MOV.W Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:E 4th R:W NEXT W:W EA
MOV.W Rs,@–ERd R:W NEXT
Internal operation,
W:W EA
1 state
MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA
MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:W EA
MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
MOV.L ERs,ERd R:W NEXT
MOV.L @ERs,ERd R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2
MOV.L @(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2
MOV.L @(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT R:W:M EA R:W EA+2
MOV.L @ERs+,ERd R:W 2nd R:W:M NEXT
Internal operation,
R:W:M EA R:W EA+2
1 state
MOV.L @aa:16,ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2
MOV.L @aa:32,ERd R:W 2nd R:W:M 3rd R:W 4th R:W NEXT R:W:M EA R:W EA+2
MOV.L ERs,@ERd R:W 2nd R:W:M NEXT W:W:M EA W:W EA+2
MOV.L ERs,@(d:16,ERd) R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@(d:32,ERd) R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@–ERd R:W 2nd R:W:M NEXT
Internal operation,
W:W:M EA W:W EA+2
1 state
MOV.L ERs,@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 2 states
MULXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation, 3 states
MULXU.B Rs,Rd R:W NEXT Internal operation, 2 states
MULXU.W Rs,ERd R:W NEXT Internal operation, 3 states
NEG.B Rd R:W NEXT
NEG.W Rd R:W NEXT
NEG.L ERd R:W NEXT
NOP R:W NEXT
NOT.B Rd R:W NEXT
NOT.W Rd R:W NEXT
NOT.L ERd R:W NEXT
OR.B #xx:8,Rd R:W NEXT
OR.B Rs,Rd R:W NEXT
Cannot be used in the H8S/2626 Group or H8S/2623 Group.
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 827 of 1042
REJ09B0275-0500
Instruction
OR.W #xx:16,Rd R:W 2nd R:W NEXT
OR.W Rs,Rd R:W NEXT
OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
OR.L ERs,ERd R:W 2nd R:W NEXT
ORC #xx:8,CCR R:W NEXT
ORC #xx:8,EXR R:W 2nd R:W NEXT
POP.W Rn R:W NEXT
Internal operation,
R:W EA
1 state
POP.L ERn R:W 2nd R:W:M NEXT
Internal operation,
R:W:M EA R:W EA+2
1 state
PUSH.W Rn R:W NEXT
Internal operation,
W:W EA
1 state
PUSH.L ERn R:W 2nd R:W:M NEXT
Internal operation,
W:W:M EA W:W EA+2
1 state
ROTL.B Rd R:W NEXT
ROTL.B #2,Rd R:W NEXT
ROTL.W Rd R:W NEXT
ROTL.W #2,Rd R:W NEXT
ROTL.L ERd R:W NEXT
ROTL.L #2,ERd R:W NEXT
ROTR.B Rd R:W NEXT
ROTR.B #2,Rd R:W NEXT
ROTR.W Rd R:W NEXT
ROTR.W #2,Rd R:W NEXT
ROTR.L ERd R:W NEXT
ROTR.L #2,ERd R:W NEXT
ROTXL.B Rd R:W NEXT
ROTXL.B #2,Rd R:W NEXT
ROTXL.W Rd R:W NEXT
ROTXL.W #2,Rd R:W NEXT
ROTXL.L ERd R:W NEXT
ROTXL.L #2,ERd R:W NEXT
ROTXR.B Rd R:W NEXT
ROTXR.B #2,Rd R:W NEXT
ROTXR.W Rd R:W NEXT
ROTXR.W #2,Rd R:W NEXT
ROTXR.L ERd R:W NEXT
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 828 of 1042
REJ09B0275-0500
Instruction
ROTXR.L #2,ERd R:W NEXT
RTE R:W NEXT
R:W stack (EXR) R:W stack (H) R:W stack (L)
Internal operation,
R:W
*4
1 state
RTS R:W NEXT
R:W:M stack (H) R:W stack (L)
Internal operation,
R:W
*4
1 state
SHAL.B Rd R:W NEXT
SHAL.B #2,Rd R:W NEXT
SHAL.W Rd R:W NEXT
SHAL.W #2,Rd R:W NEXT
SHAL.L ERd R:W NEXT
SHAL.L #2,ERd R:W NEXT
SHAR.B Rd R:W NEXT
SHAR.B #2,Rd R:W NEXT
SHAR.W Rd R:W NEXT
SHAR.W #2,Rd R:W NEXT
SHAR.L ERd R:W NEXT
SHAR.L #2,ERd R:W NEXT
SHLL.B Rd R:W NEXT
SHLL.B #2,Rd R:W NEXT
SHLL.W Rd R:W NEXT
SHLL.W #2,Rd R:W NEXT
SHLL.L ERd R:W NEXT
SHLL.L #2,ERd R:W NEXT
SHLR.B Rd R:W NEXT
SHLR.B #2,Rd R:W NEXT
SHLR.W Rd R:W NEXT
SHLR.W #2,Rd R:W NEXT
SHLR.L ERd R:W NEXT
SHLR.L #2,ERd R:W NEXT
SLEEP R:W NEXT
Internal operation:M
STC CCR,Rd R:W NEXT
STC EXR,Rd R:W NEXT
STC CCR,@ERd R:W 2nd R:W NEXT W:W EA
STC EXR,@ERd R:W 2nd R:W NEXT W:W EA
STC CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 829 of 1042
REJ09B0275-0500
Instruction
STC EXR,@(d:16,ERd)
R:W 2nd R:W 3rd R:W NEXT W:W EA
STC CCR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA
STC EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA
STC CCR,@–ERd R:W 2nd R:W NEXT
Internal operation,
W:W EA
1 state
STC EXR,@–ERd R:W 2nd R:W NEXT
Internal operation,
W:W EA
1 state
STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA
STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA
STC CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
STM.L(ERn–ERn+1),@–SP
R:W 2nd R:W:M NEXT
Internal operation,
W:W:M stack (H)
*
3
W:W stack (L)
*
3
1 state
STM.L(ERn–ERn+2),@–SP
R:W 2nd R:W:M NEXT
Internal operation,
W:W:M stack (H)
*
3
W:W stack (L)
*
3
1 state
STM.L(ERn–ERn+3),@–SP
R:W 2nd R:W:M NEXT
Internal operation,
W:W:M stack (H)
*
3
W:W stack (L)
*
3
1 state
STMAC MACH,ERd R:W NEXT
STMAC MACL,ERd R:W NEXT
SUB.B Rs,Rd R:W NEXT
SUB.W #xx:16,Rd R:W 2nd R:W NEXT
SUB.W Rs,Rd R:W NEXT
SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
SUB.L ERs,ERd R:W NEXT
SUBS #1/2/4,ERd R:W NEXT
SUBX #xx:8,Rd R:W NEXT
SUBX Rs,Rd R:W NEXT
TAS @ERd
*
8
R:W 2nd R:W NEXT R:B:M EA W:B EA
TRAPA #x:2 R:W NEXT
Internal operation,
W:W stack (L) W:W stack (H) W:W stack (EXR)
R:W:M VEC R:W VEC+2
Internal operation,
R:W
*
7
1 state
1 state
XOR.B #xx8,Rd R:W NEXT
XOR.B Rs,Rd R:W NEXT
XOR.W #xx:16,Rd R:W 2nd R:W NEXT
XOR.W Rs,Rd R:W NEXT
XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 830 of 1042
REJ09B0275-0500
Instruction
XOR.L ERs,ERd R:W 2nd R:W NEXT
XORC #xx:8,CCR R:W NEXT
XORC #xx:8,EXR R:W 2nd R:W NEXT
Reset exception
R:W VEC R:W VEC+2
Internal operation,
R:W*5
1 state
Interrupt exception
R:W*6
Internal operation,
W:W stack (L) W:W stack (H)
W:W stack (EXR)
R:W:M VEC R:W VEC+2
Internal operation,
R:W*8
1 state
1 state
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.
2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial
value of R4L or R4. If n = 0, these bus cycles are not executed.
3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers.
4. Start address after return.
5. Start address of the program.
6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read
operation is replaced by an internal operation.
7. Start address of the interrupt-handling routine.
8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
1 2 3 4 5 6 7 8 9
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 831 of 1042
REJ09B0275-0500
A.6 Condition Code Modification
This section ind icates th e effect of each CPU instruction on the condition code. The notation used
in the table is def ined below.
m =
31 for longword operands
15 for word operands
7 for byte operands
Si
Di
Ri
Dn
—
0
1
*
Z'
C'
The i-th bit of the source operand
The i-th bit of th e destination operand
The i-th bit of th e r esult
The specified bit in the destination operand
Not affected
Modified according to the resu lt of th e in struction (see definition)
Always cleared to 0
Always set to 1
Undetermined (no guara nt eed value)
Z flag before instruction execution
C flag before instruction execution
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 832 of 1042
REJ09B0275-0500
Table A.7 Conditio n Code Modificatio n
Instruction H N Z V C Definition
ADD H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
ADDS —————
ADDX H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Z' · Rm · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
AND — 0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
ANDC Stores the corresponding bits of the result.
No flags change when the operand is EXR.
BAND ———— C = C' · Dn
Bcc —————
BCLR —————
BIAND ———— C = C' · Dn
BILD ———— C = Dn
BIOR ———— C = C' + Dn
BIST —————
BIXOR ———— C = C' · Dn + C' · Dn
BLD ———— C = Dn
BNOT —————
BOR ———— C = C' + Dn
BSET —————
BSR —————
BST —————
BTST —— —— Z = Dn
BXOR ———— C = C' · Dn + C' · Dn
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 833 of 1042
REJ09B0275-0500
Instruction H N Z V C Definition
CLRMAC —————
CMP H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
DAA * * N = Rm
Z = Rm · Rm–1 · ...... · R0
C: decimal arithmetic carry
DAS * * N = Rm
Z = Rm · Rm–1 · ...... · R0
C: decimal arithmetic borrow
DEC — — N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Dm · Rm
DIVXS ——— N = Sm · Dm + Sm · Dm
Z = Sm · Sm–1 · ...... · S0
DIVXU ——— N = Sm
Z = Sm · Sm–1 · ...... · S0
EEPMOV —————
EXTS — 0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
EXTU — 0 0 — Z = Rm · Rm–1 · ...... · R0
INC — — N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Dm · Rm
JMP —————
JSR —————
LDC Stores the corresponding bits of the result.
No flags change when the operand is EXR.
LDM —————
LDMAC —————
MAC —————
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 834 of 1042
REJ09B0275-0500
Instruction H N Z V C Definition
MOV —0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
MOVFPE Can not be used in the H8S/2626 Group or H8S/2623
Group.
MOVTPE
MULXS ——— N = R2m
Z = R2m · R2m–1 · ...... · R0
MULXU —————
NEG H = Dm–4 + Rm–4
N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Dm · Rm
C = Dm + Rm
NOP —————
NOT — 0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
OR — 0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
ORC Stores the corresponding bits of the result.
No flags change when the operand is EXR.
POP — 0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
PUSH — 0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
ROTL — 0 N = Rm
Z = Rm · Rm–1 · ...... · R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
ROTR — 0 N = Rm
Z = Rm · Rm–1 · ...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit sh ift)
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 835 of 1042
REJ09B0275-0500
Instruction H N Z V C Definition
ROTXL —0N = Rm
Z = Rm · Rm–1 · ...... · R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
ROTXR — 0 N = Rm
Z = Rm · Rm–1 · ...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit sh ift)
RTE Stores the corresponding bits of the result.
RTS —————
SHAL —N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Dm · Dm–1 + Dm · Dm–1 (1-bit shift)
V = Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2 (2-bit shift)
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
SHAR — 0 N = Rm
Z = Rm · Rm–1 · ...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit sh ift)
SHLL — 0 N = Rm
Z = Rm · Rm–1 · ...... · R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
SHLR — 0 0 N = Rm
Z = Rm · Rm–1 · ...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit sh ift)
SLEEP —————
STC —————
STM —————
STMAC — — N = 1 if MAC instruction resulted in negative value in MAC
register
Z = 1 if MAC instruction resu lted in zero value in MAC
register
V = 1 if MAC instruction resulted in overflow
Appendix A Instruction Set
Rev. 5.00 Jan 10, 2006 page 836 of 1042
REJ09B0275-0500
Instruction H N Z V C Definition
SUB H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
SUBS —————
SUBX H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Z' · Rm · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
TAS — 0 — N = Dm
Z = Dm · Dm–1 · ...... · D0
TRAPA —————
XOR — 0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
XORC Stores the corresponding bits of the result.
No flags change when the operand is EXR.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 837 of 1042
REJ09B0275-0500
Appendix B Internal I/O Register
B.1 Address
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
MRA SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz DTC
MRB CHNE DISEL — — — — — —
16/32*1
bits
H'EBC0
to
H'EFBF SAR
DAR
CRA
CRB
H'F800 MCR MCR7 — MCR5 — — MCR2 MCR1 MCR0 HCAN 8 16
H'F801 GSR — — — — GSR3 GSR2 GSR1 GSR0 8
H'F802 BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 8, 16
H'F803 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8
H'F804 MBCR MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 —
H'F805 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8
H'F806 TXPR TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —
H'F807 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8
H'F808 TXCR TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —
H'F809 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
H'F80A TXACK TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 —
H'F80B TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8
H'F80C ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 —
H'F80D ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8
H'F80E RXPR RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0
H'F80F RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8
H'F810 RFPR RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0
H'F811 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8
H'F812 IRR IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
H'F813 — — — IRR12 — — IRR9 IRR8
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 838 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F814 MBIMR MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 HCAN 8, 16
H'F815 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8
H'F816 IMR IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 —
H'F817 — — — IMR12 — — IMR9 IMR8
H'F818 REC 816
H'F819 TEC 8
H'F81A UMSR UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 8, 1 6
H'F81B UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8
H'F81C LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0
H'F81D LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8
H'F81E LAFMH LAFMH7 LAFMH6 LAFMH5 — — — LAFMH1 LAFMH0
H'F81F LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8
H'F820 MC0[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F821MC0[2]————————
H'F822MC0[3]————————
H'F823MC0[4]————————
H'F824 MC0[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F825 MC0[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F826 MC0[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F827 MC0[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F828 MC1[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F829MC1[2]————————
H'F82AMC1[3]————————
H'F82BMC1[4]————————
H'F82C MC1[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F82D MC1[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F82E MC1[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F82F MC1[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F830 MC2[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F831MC2[2]————————
H'F832MC2[3]————————
H'F833MC2[4]————————
H'F834 MC2[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F835 MC2[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F836 MC2[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F837 MC2[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F838 MC3[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F839MC3[2]————————
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 839 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F83A MC3[3] — — — — — — — — HCAN 8, 16
H'F83BMC3[4]————————
H'F83C MC3[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F83D MC3[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F83E MC3[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F83F MC3[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F840 MC4[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F841MC4[2]————————
H'F842MC4[3]————————
H'F843MC4[4]————————
H'F844 MC4[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F845 MC4[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F846 MC4[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F847 MC4[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F848 MC5[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F849MC5[2]————————
H'F84AMC5[3]————————
H'F84BMC5[4]————————
H'F84C MC5[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F84D MC5[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F84E MC5[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F84F MC5[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F850 MC6[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F851MC6[2]————————
H'F852MC6[3]————————
H'F853MC6[4]————————
H'F854 MC6[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F855 MC6[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F856 MC6[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F857 MC6[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F858 MC7[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F859MC7[2]————————
H'F85AMC7[3]————————
H'F85BMC7[4]————————
H'F85C MC7[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F85D MC7[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F85E MC7[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 840 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F85F MC7[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ ID9 EXD_ID8 HCAN 8, 16
H'F860 MC8[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F861MC8[2]————————
H'F862MC8[3]————————
H'F863MC8[4]————————
H'F864 MC8[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F865 MC8[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F866 MC8[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F867 MC8[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F868 MC9[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F869MC9[2]————————
H'F86AMC9[3]————————
H'F86BMC9[4]————————
H'F86C MC9[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F86D MC9[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F86E MC9[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F86F MC9[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F870 MC10[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F871 MC10[2] — — — — — — — —
H'F872 MC10[3] — — — — — — — —
H'F873 MC10[4] — — — — — — — —
H'F874 MC10[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F875 MC10[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F876 MC10[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F877 MC10[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F878 MC11[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F879 MC11[2] — — — — — — — —
H'F87A MC11[3] — — — — — — — —
H'F87B MC11[4] — — — — — — — —
H'F87C MC11[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F87D MC11[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F87E MC11[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F87F MC11[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F880 MC12[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F881 MC12[2] — — — — — — — —
H'F882 MC12[3] — — — — — — — —
H'F883 MC12[4] — — — — — — — —
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 841 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F884 MC12[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 HCAN 8, 16
H'F885 MC12[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F886 MC12[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F887 MC12[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F888 MC13[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F889 MC13[2] — — — — — — — —
H'F88A MC13[3] — — — — — — — —
H'F88B MC13[4] — — — — — — — —
H'F88C MC13[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F88D MC13[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F88E MC13[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F88F MC13[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F890 MC14[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F891 MC14[2] — — — — — — — —
H'F892 MC14[3] — — — — — — — —
H'F893 MC14[4] — — — — — — — —
H'F894 MC14[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F895 MC14[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F896 MC14[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F897 MC14[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F898 MC15[1] — — — — DLC3 DLC2 DLC1 DLC0
H'F899 MC15[2] — — — — — — — —
H'F89A MC15[3] — — — — — — — —
H'F89B MC15[4] — — — — — — — —
H'F89C MC15[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16
H'F89D MC15[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3
H'F89E MC15[7] EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0
H'F89F MC15[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8
H'F8B0 MD0[1]
H'F8B1 MD0[2]
H'F8B2 MD0[3]
H'F8B3 MD0[4]
H'F8B4 MD0[5]
H'F8B5 MD0[6]
H'F8B6 MD0[7]
H'F8B7 MD0[8]
H'F8B8 MD1[1]
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 842 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F8B9 MD1[2] HCAN 8, 16
H'F8BA MD1[3]
H'F8BB MD1[4]
H'F8BC MD1[5]
H'F8BD MD1[6]
H'F8BE MD1[7]
H'F8BF MD1[8]
H'F8C0 MD2[1]
H'F8C1 MD2[2]
H'F8C2 MD2[3]
H'F8C3 MD2[4]
H'F8C4 MD2[5]
H'F8C5 MD2[6]
H'F8C6 MD2[7]
H'F8C7 MD2[8]
H'F8C8 MD3[1]
H'F8C9 MD3[2]
H'F8CA MD3[3]
H'F8CB MD3[4]
H'F8CC MD3[5]
H'F8CD MD3[6]
H'F8CE MD3[7]
H'F8CF MD3[8]
H'F8D0 MD4[1]
H'F8D1 MD4[2]
H'F8D2 MD4[3]
H'F8D3 MD4[4]
H'F8D4 MD4[5]
H'F8D5 MD4[6]
H'F8D6 MD4[7]
H'F8D7 MD4[8]
H'F8D8 MD5[1]
H'F8D9 MD5[2]
H'F8DA MD5[3]
H'F8DB MD5[4]
H'F8DC MD5[5]
H'F8DD MD5[6]
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 843 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F8DE MD5[7] HCAN 8, 16
H'F8DF MD5[8]
H'F8E0 MD6[1]
H'F8E1 MD6[2]
H'F8E2 MD6[3]
H'F8E3 MD6[4]
H'F8E4 MD6[5]
H'F8E5 MD6[6]
H'F8E6 MD6[7]
H'F8E7 MD6[8]
H'F8E8 MD7[1]
H'F8E9 MD7[2]
H'F8EA MD7[3]
H'F8EB MD7[4]
H'F8EC MD7[5]
H'F8ED MD7[6]
H'F8EE MD7[7]
H'F8EF MD7[8]
H'F8F0 MD8[1]
H'F8F1 MD8[2]
H'F8F2 MD8[3]
H'F8F3 MD8[4]
H'F8F4 MD8[5]
H'F8F5 MD8[6]
H'F8F6 MD8[7]
H'F8F7 MD8[8]
H'F8F8 MD9[1]
H'F8F9 MD9[2]
H'F8FA MD9[3]
H'F8FB MD9[4]
H'F8FC MD9[5]
H'F8FD MD9[6]
H'F8FE MD9[7]
H'F8FF MD9[8]
H'F900 MD10[1]
H'F901 MD10[2]
H'F902 MD10[3]
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 844 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F903 MD10[4] HCAN 8, 16
H'F904 MD10[5]
H'F905 MD10[6]
H'F906 MD10[7]
H'F907 MD10[8]
H'F908 MD11[1]
H'F909 MD11[2]
H'F90A MD11[3]
H'F90B MD11[4]
H'F90C MD11[5]
H'F90D MD11[6]
H'F90E MD11[7]
H'F90F MD11[8]
H'F910 MD12[1]
H'F911 MD12[2]
H'F912 MD12[3]
H'F913 MD12[4]
H'F914 MD12[5]
H'F915 MD12[6]
H'F916 MD12[7]
H'F917 MD12[8]
H'F918 MD13[1]
H'F919 MD13[2]
H'F91A MD13[3]
H'F91B MD13[4]
H'F91C MD13[5]
H'F91D MD13[6]
H'F91E MD13[7]
H'F91F MD13[8]
H'F920 MD14[1]
H'F921 MD14[2]
H'F922 MD14[3]
H'F923 MD14[4]
H'F924 MD14[5]
H'F925 MD14[6]
H'F926 MD14[7]
H'F927 MD14[8]
H'F928 MD15[1]
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 845 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'F929 MD15[2] HCAN 8, 16
H'F92A MD15[3]
H'F92B MD15[4]
H'F92C MD15[5]
H'F92D MD15[6]
H'F92E MD15[7]
H'F92F MD15[8]
H'FDAC DADR2*6Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8
H'FDAD DADR3*6Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
H'FDAE DACR23*6DAOE1 DAOE0 DAE — — — — —
D/A
converter
H'FDB4SCRX————FLSHE———ROM8
H'FDE4 SBYCR SSBY STS2 STS1 STS0 OPE — — — Power-
down state 8
H'FDE5 SYSCR MACS — INTM1 INTM0 NMIEG — — RAME MCU,
RAM
interrupt
controller
8
H'FDE6 SCKCR PSTOP — — — STCS SCK2 SCK1 SCK0 Clock
pulse
generator,
power-
down state
8
H'FDE7 MDCR — — — — — MDS2 MDS1 MDS0 MCU 8
H'FDE8 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 8
H'FDE9 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
H'FDEA MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Power-
down state
H'FDEB PFCR — — BUZZE*4— AE3 AE2 AE1 AE0 MCU, bus
controller 8
H'FDEC LPWRCR DTON*4LSON*4NESEL*4SUBSTP*4RFCUT — STC1 STC0 Clock
pulse
generator
8
H'FE00BARA———————— 8
BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16
PC break
controller
BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8
BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0
H'FE04BARB————————
BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16
BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8
BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0
H'FE08 BCRA CMFA CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA
H'FE09 BCRB CMFB CDB BAMRB2 BAMRB1 BAMRA0 CSELB1 CSELB0 BIEB
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 846 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'FE12 ISCRH — — — — IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA 8
H'FE13 ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Interrupt
controller
H'FE14 IER — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
H'FE15 ISR — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
H'FE16 DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC 8
H'FE17 DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0
H'FE18 DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0
H'FE19 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0
H'FE1A DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0
H'FE1B DTCERF DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0
H'FE1C DTCERG DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG3 DTCEG2 DTCEG1 DTCEG0
H'FE1F DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
H'FE26 PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG 8
H'FE27 PMR G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV
H'FE28 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
H'FE29 NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
H'FE2A PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8
H'FE2B PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0
H'FE2C NDRH*2NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8
H'FE2D NDRL*2NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
H'FE2E NDRH*2— — — — NDR11 NDR10 NDR9 NDR8
H'FE2F NDRL*2— — — — NDR3 NDR2 NDR1 NDR0
H'FE30 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR I/O port 8
H'FE39 PADDR — — PA5DDR*5PA4DDR*5PA3DDR PA2DDR PA1DDR PA0DDR
H'FE3A PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
H'FE3B PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
H'FE3C PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
H'FE3D PEDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
H'FE3E PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
H'FE40 PAPCR — — PA5PCR*5PA4PCR*5PA3PCR PA2PCR PA1PCR PA0PCR
H'FE41 PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
H'FE42 PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR
H'FE43 PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
H'FE44 PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
H'FE47 PAODR — — PA5ODR*5PA4ODR*5PA3ODR PA2ODR PA1ODR PA0ODR
H'FE48 PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
H'FE49 PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 847 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3 16
H'FE81 TMDR3 — — BFB BFA MD3 MD2 MD1 MD0
H'FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
H'FE84 TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA
H'FE85 TSR3 — — — TCFV TGFD TGFC TGFB TGFA
H'FE86 TCNT3
H'FE87
H'FE88 TGR3A
H'FE89
H'FE8A TGR3B
H'FE8B
H'FE8C TGR3C
H'FE8D
H'FE8E TGR3D
H'FE8F
H'FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU4 16
H'FE91 TMDR4 — — — — MD3 MD2 MD1 MD0
H'FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FE94 TIER4 TTGE — TCIEU TCIEV — — TGIEB TGIEA
H'FE95 TSR4 TCFD — TCFU TCFV — — TGFB TGFA
H'FE96 TCNT4
H'FE97
H'FE98 TGR4A
H'FE99
H'FE9A TGR4B
H'FE9B
H'FEA0 TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU5 16
H'FEA1 TMDR5 — — — — MD3 MD2 MD1 MD0
H'FEA2 TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FEA4 TIER5 TTGE — TCIEU TCIEV — — TGIEB TGIEA
H'FEA5 TSR5 TCFD — TCFU TCFV — — TGFB TGFA
H'FEA6 TCNT5
H'FEA7
H'FEA8 TGR5A
H'FEA9
H'FEAA TGR5B
H'FEAB
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 848 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'FEB0 TSTR — — CST5 CST4 CST3 CST2 CST1 CST0 16
H'FEB1 TSYR — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
TPU
All
H'FEC0 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 8
H'FEC1 IPRB — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
Interrupt
controller
H'FEC2 IPRC — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FEC3 IPRD — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FEC4 IPRE — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FEC5 IPRF — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FEC6 IPRG — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FEC7 IPRH — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FEC8 IPRI — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FEC9 IPRJ — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FECA IPRK — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FECC IPRM — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0
H'FED0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 8
H'FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
Bus
controller
H'FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40
H'FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00
H'FED4 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — —
H'FED5 BCRL BRLE BREQOE — — — — WDBE WAITE
H'FEDB RAMER*3— — — — RAMS RAM2 RAM1 RAM0 ROM
H'FF00 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR I/O port 8
H'FF09 PADR — — PA5DR*5PA4DR*5PA3DR PA2DR PA1DR PA0DR
H'FF0A PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
H'FF0B PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR
H'FF0C PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR
H'FF0D PEDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR
H'FF0E PFDR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR
H'FF10 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU0 16
H'FF11 TMDR0 — — BFB BFA MD3 MD2 MD1 MD0
H'FF12 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FF13 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
H'FF14 TIER0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA
H'FF15 TSR0 — — — TCFV TGFD TGFC TGFB TGFA
H'FF16 TCNT0
H'FF17
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 849 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'FF18 TGR0A TPU0 16
H'FF19
H'FF1A TGR0B
H'FF1B
H'FF1C TGR0C
H'FF1D
H'FF1E TGR0D
H'FF1F
H'FF20 TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU1 16
H'FF21 TMDR1 — — — — MD3 MD2 MD1 MD0
H'FF22 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FF24 TIER1 TTGE — TCIEU TCIEV — — TGIEB TGIEA
H'FF25 TSR1 TCFD — TCFU TCFV — — TGFB TGFA
H'FF26 TCNT1
H'FF27
H'FF28 TGR1A
H'FF29
H'FF2A TGR1B
H'FF2B
H'FF30 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16
H'FF31 TMDR2 — — — — MD3 MD2 MD1 MD0
H'FF32 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FF34 TIER2 TTGE — TCIEU TCIEV — — TGIEB TGIEA
H'FF35 TSR2 TCFD — TCFU TCFV — — TGFB TGFA
H'FF36 TCNT2
H'FF37
H'FF38 TGR2A
H'FF39
H'FF3A TGR2B
H'FF3B
H'FF74 TCSR0 OVF WT/IT TME — — CKS2 CKS1 CKS0 WDT0 16
(Write) TCNT0
H'FF75
(Read) TCNT0
H'FF76
(Write) RSTCSR WOVF RSTE RSTS — — — — —
H'FF77
(Read) RSTCSR WOVF RSTE RSTS — — — — —
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 850 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'FF78 SMR0 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI0 8
GM BLK PE O/EBCP1 BCP0 CKS1 CKS0 Smart card
interface 0
H'FF79 BRR0
H'FF7A SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'FF7B TDR0
SCI0,
smart card
interface 0
H'FF7C SSR0 TDRE RDRF ORER FER PER TEND MPB MPBT SCI0
TDRE RDRF ORER ERS PER TEND MPB MPBT Smart card
interface 0
H'FF7D RDR0
H'FF7E SCMR0 — — — — SDIR SINV — SMIF
SCI0,
smart card
interface 0
H'FF80 SMR1 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI1 8
GM BLK PE O/EBCP1 BCP0 CKS1 CKS0 Smart card
interface 1
H'FF81 BRR1
H'FF82 SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'FF83 TDR1
SCI1,
smart card
interface 1
H'FF84 SSR1 TDRE RDRF ORER FER PER TEND MPB MPBT SCI1
SSR1 TDRE RDRF ORER ERS PER TEND MPB MPBT Smart card
interface 1
H'FF85 RDR1
H'FF86 SCMR1 — — — — SDIR SINV — SMIF
SCI1,
smart card
interface 1
H'FF88 SMR2 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI2 8
GM BLK PE O/EBCP1 BCP0 CKS1 CKS0 Smart ca rd
interface 2
H'FF89 BRR2
H'FF8A SCR2 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'FF8B TDR2
SCI2,
smart card
interface 2
H'FF8C SSR2 TDRE RDRF ORER FER PER TEND MPB MPBT SCI2
SSR2 TDRE RDRF ORER ERS PER TEND MPB MPBT Smart card
interface 2
H'FF8D RDR2
H'FF8E SCMR2 — — — — SDIR SINV — SMIF
SCI2,
smart card
interface 2
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 851 of 1042
REJ09B0275-0500
Address Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
Name Data Bus
Width
H'FF90 ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 16
H'FF91 AD1 AD0 — — — — — —
A/D
converter
H'FF92 ADDRB AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FF93 AD1 AD0 — — — — — —
H'FF94 ADDRC AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FF95 AD1 AD0 — — — — — —
H'FF96 ADDRD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'FF97 AD1 AD0 — — — — — —
H'FF98 ADCSR ADF ADIE ADST SCAN CH3 CH2 CH1 CH0
H'FF99 ADCR TRGS1 TRGS0 — — CKS1 CKS0 — —
H'FFA2 TCSR1*6OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 WDT1 16
(Write) TCNT1*6
H'FFA3
(Read) TCNT1*6
H'FFA8 FLMCR1*3FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 ROM 8
H'FFA9 FLMCR2*3FLER———————
H'FFAA EBR1*3EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
H'FFAB EBR2*3— — — — EB11 EB10 EB9 EB8
H'FFAC FLPWCR PDWND — — — — — — —
H'FFB0 PORT1 P17 P16 P15 P14 P13 P12 P11 P10 I/O port 8
H'FFB3 PORT4 P47 P46 P45 P44 P43 P42 P41 P40
H'FFB8 PORT9 P97 P96 P95 P94 P93 P92 P91 P90
H'FFB9 PORTA — — PA5 PA4 PA3 PA2 PA1 PA0
H'FFBA PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
H'FFBB PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
H'FFBC PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
H'FFBD PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
H'FFBE PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as
register information, and 16 bits otherwise.
2. The address depends on the output trigger setting.
3. These registers are present in the F-ZTAT version, but not in the mask ROM version.
An undefined value will be returned if these registers are read in the mask ROM
version.
4. Valid only in the H8S/2626 Group; reserved bits in the H8S/2623 Group. For the
handling of these bits in register writes, see the individual register descriptions the
respecti ve se ctio ns.
5. Valid only in the H8S/2623 Group; reserved bits in the H8S/2626 Group. For the
handling of these bits in register writes, see the individual register descriptions the
respecti ve se ctio ns.
6. These registers are not available, and must not be accessed, in the H8S/2623 Group.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 852 of 1042
REJ09B0275-0500
B.2 Functions
SBYCR—Standby Control Register
H'FDE4
Power-Down Modes
Register
name Address to which the
register is mapped Name of
on-chip
supporting
module
Register
acronym
Bit
numbers
Initial bit
values Names of the
bits. Dashes
(—) indicate
reserved bits.
Full name
of bit
Descriptions
of bit settings
Read only
Write only
Read and write
R
W
R/W
Possible types of access
Bit
Initial value
Read/Write
:
:
:
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
OPE
1
R/W
2
—
0
—
1
—
0
—
0
—
0
R/W
0 In software standby mode, address bus and
bus control signals are high-impedance
In software standby mode, address bus and
bus control signals retain their output state
Output port enable
1
0 0 Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states
Standby timer select
1
1
0
1
0
1
0
1
0
1
0
1
0
Software standby
1Transition to sleep mode after execution of SLEEP instruction
Transition to software standby mode after execution of SLEEP instruction
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 853 of 1042
REJ09B0275-0500
MRA—DTC Mode Register A H'EBC0–H'EF BF DTC
Bit
Initial value
Read/Write
:
:
:
7
SM1
Undefined
—
6
SM0
Undefined
—
5
DM1
Undefined
—
4
DM0
Undefined
—
3
MD1
Undefined
—
2
MD0
Undefined
—
1
DTS
Undefined
—
0
Sz
Undefined
—
0 Byte-size transfer
Word-size transfer
DTC data transfer size
1
0 Destination side is repeat
area or block area
Source side is repeat
area or block area
DTC transfer mode select
1
0 0 Normal mode
Repeat mode
DTC mode
1
10
1Block transfer mode
—
0 — DAR is fixed
Destination address mode
10
1
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
0 — SAR is fixed
Source address mode
10
1
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 854 of 1042
REJ09B0275-0500
MRB—DTC Mode Register B H'EBC0–H'EFBF DTC
Bit
Initial value
Read/Write
:
:
:
7
CHNE
Undefined
—
6
DISEL
Undefined
—
5
—
Undefined
—
4
—
Undefined
—
3
—
Undefined
—
2
—
Undefined
—
1
—
Undefined
—
0
—
Undefined
—
0 After a data transfer ends, the CPU interrupt is disabled
unless the transfer counter is 0
After a data transfer ends, the CPU interrupt is enabled
DTC interrupt select
1
0 End of DTC data transfer
DTC chain transfer
DTC chain transfer enable
1
SAR—DTC Source Address Register H'EBC0–H'EFBF DTC
Bit
Initial value
Read/Write
:
:
:
23
Unde-
fined
—
22
Unde-
fined
—
21
Unde-
fined
—
20
Unde-
fined
—
19
Unde-
fined
—
- - -
- - -
- - -
- - -
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
Specifies DTC transfer data source address
DAR—DTC Destination Address Register H'EBC0–H'EFBF DTC
Bit
Initial value
Read/Write
:
:
:
23
Unde-
fined
—
22
Unde-
fined
—
21
Unde-
fined
—
20
Unde-
fined
—
19
Unde-
fined
—
- - -
- - -
- - -
- - -
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
Specifies DTC transfer data destination address
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 855 of 1042
REJ09B0275-0500
CRA—DTC Transfer Count Reg ister A H'EBC0–H'EFBF DTC
Bit
Initial value
Read/Write
:
:
:
15
Unde-
fined
—
14
Unde-
fined
—
13
Unde-
fined
—
12
Unde-
fined
—
11
Unde-
fined
—
10
Unde-
fined
—
9
Unde-
fined
—
8
Unde-
fined
—
6
Unde-
fined
—
5
Unde-
fined
—
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
7
Unde-
fined
—
CRAH CRAL
Specifies the number of DTC data transfers
CRB—DTC Transfer Count Register B H'EBC0–H'EFBF DTC
Bit
Initial value
Read/Write
:
:
:
15
Unde-
fined
—
14
Unde-
fined
—
13
Unde-
fined
—
12
Unde-
fined
—
11
Unde-
fined
—
10
Unde-
fined
—
9
Unde-
fined
—
8
Unde-
fined
—
6
Unde-
fined
—
5
Unde-
fined
—
4
Unde-
fined
—
3
Unde-
fined
—
2
Unde-
fined
—
1
Unde-
fined
—
0
Unde-
fined
—
7
Unde-
fined
—
Specifies the number of DTC block data transfers
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 856 of 1042
REJ09B0275-0500
MCR—Master Control Register H'F800 HCAN
Bit
Initial value
Read/Write
:
:
:
7
MCR7
0
R/W
6
—
0
R
5
MCR5
0
R/W
4
—
0
R
3
—
0
R
2
MCR2
0
R/W
1
MCR1
0
R/W
0
MCR0
1
R/W
MCR
0 HCAN sleep mode release by CAN bus operation disabled
HCAN sleep mode release by CAN bus operation enabled
HCAN sleep mode release
1
0 HCAN sleep mode released
Transition to HCAN sleep mode enabled
HCAN sleep mode
1
0 Transmission order determined by
message identifier priority
Transmission order determined by
mailbox (buffer) number priority
(TXPR1 > TXPR15)
Message transmission method
1
0 Normal operating mode
(MCR0 = 0 and GSR3 = 0)
[Setting condition]
When 0 is written after
an HCAN reset
HCAN reset mode transition
request
Reset request
1
0 HCAN normal operating mode
HCAN halt mode transition request
Halt request
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 857 of 1042
REJ09B0275-0500
GSR—General Status Register H'F801 HCAN
Bit
Initial value
Read/Write
:
:
:
7
—
0
R
6
—
0
R
5
—
0
R
4
—
0
R
3
GSR3
1
R
2
GSR2
1
R
1
GSR1
0
R
0
GSR0
0
R
GSR
0 [Reset condition]
Recovery from
bus off state
When TEC ≥ 256
(bus off state)
Bus off flag
1
0 [Reset condition]
When TEC < 96 and
REC < 96 or TEC ≥ 256
When TEC ≥ 96 or
REC ≥ 96
Transmit/receive warning flag
1
0 Message transmission period
[Reset condition]
Idle period
Message transmission status flag
1
0 Normal operating state
[Setting condition]
After an HCAN internal reset
Configuration mode
[Reset condition]
MCR0 reset mode and sleep mode
Reset status bit
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 858 of 1042
REJ09B0275-0500
BCR—Bit Configuration Reg ister H'F802 HCAN
Bit
Initial value
Read/Write
:
:
:
15
BCR7
0
R/W
14
BCR6
0
R/W
13
BCR5
0
R/W
12
BCR4
0
R/W
11
BCR3
0
R/W
10
BCR2
0
R/W
9
BCR1
0
R/W
8
BCR0
0
R/W
BCR
00 2 × system clock
4 × system clock
Baud rate prescale
06 × system clock
:
00
0
::
11
0
0
0
:
1
0
0
0
:
1
0
1
0
:
1
0
0
1
:
1 128 × system clock
0 0 Max. bit synchronization width = 1 time quantum
Max. bit synchronization width = 2 time quanta
Resynchronization jump width
1
10
1Max. bit synchronization width = 3 time quanta
Max. bit synchronization width = 4 time quanta
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 859 of 1042
REJ09B0275-0500
Bit
Initial value
Read/Write
:
:
:
7
BCR15
0
R/W
6
BCR14
0
R/W
5
BCR13
0
R/W
4
BCR12
0
R/W
3
BCR11
0
R/W
2
BCR10
0
R/W
1
BCR9
0
R/W
0
BCR8
0
R/W
BCR
0 0 Setting prohibited
TSEG1 = 4 time quanta
Time segment 1
1 TSEG1 = 5 time quanta
:
00
0
::
11
1
0
1
:
1
0
0
1
:
1 TSEG1 = 16 time quanta
0 0 Setting prohibited01
0 0 Setting prohibited00
0
Time segment 2
Setting prohibited
TSEG2 = 2 time quanta
00
1TSEG2 = 3 time quanta10
TSEG2 = 4 time quanta1
1 TSEG2 = 5 time quanta00
TSEG2 = 6 time quanta1 TSEG2 = 7 time quanta10
TSEG2 = 8 time quanta1
0 Bit sampling at one point (end of time segment 1 (TSEG1))
Bit sampling at three points (end of time segment 1 (TSEG1), and 1 time
quantum before and after)
Bit sample point
1
Note: For details, see section 15.2.3, Bit Configuration Register (BCR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 860 of 1042
REJ09B0275-0500
MBCR—Mailbox Configuration Register H'F804 HCAN
Bit
Initial value
Read/Write
:
:
:
15
MBCR7
0
R/W
14
MBCR6
0
R/W
13
MBCR5
0
R/W
12
MBCR4
0
R/W
11
MBCR3
0
R/W
10
MBCR2
0
R/W
9
MBCR1
0
R/W
8
—
1
R
MBCR
Bit
Initial value
Read/Write
:
:
:
7
MBCR15
0
R/W
6
MBCR14
0
R/W
5
MBCR13
0
R/W
4
MBCR12
0
R/W
3
MBCR11
0
R/W
2
MBCR10
0
R/W
1
MBCR9
0
R/W
0
MBCR8
0
R/W
0 Corresponding mailbox is set for transmission
Corresponding mailbox is set for reception
Mailbox setting register
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 861 of 1042
REJ09B0275-0500
TXPR—Transmit Wait Register H'F806 HCAN
Bit
Initial value
Read/Write
:
:
:
15
TXPR7
0
R/W
14
TXPR6
0
R/W
13
TXPR5
0
R/W
12
TXPR4
0
R/W
11
TXPR3
0
R/W
10
TXPR2
0
R/W
9
TXPR1
0
R/W
8
—
0
R
TXPR
Bit
Initial value
Read/Write
:
:
:
7
TXPR15
0
R/W
6
TXPR14
0
R/W
5
TXPR13
0
R/W
4
TXPR12
0
R/W
3
TXPR11
0
R/W
2
TXPR10
0
R/W
1
TXPR9
0
R/W
0
TXPR8
0
R/W
0 Transmit message idle state in corresponding mailbox
[Clearing condition]
Message transmission completion and cancellation
completion
Transmit wait for transmit message in corresponding
mailbox (CAN bus arbitration)
Transmit wait register
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 862 of 1042
REJ09B0275-0500
TXCR—Transmit Wait Cancel Register H'F808 HCAN
Bit
Initial value
Read/Write
:
:
:
15
TXCR7
0
R/W
14
TXCR6
0
R/W
13
TXCR5
0
R/W
12
TXCR4
0
R/W
11
TXCR3
0
R/W
10
TXCR2
0
R/W
9
TXCR1
0
R/W
8
—
0
R
TXCR
Bit
Initial value
Read/Write
:
:
:
7
TXCR15
0
R/W
6
TXCR14
0
R/W
5
TXCR13
0
R/W
4
TXCR12
0
R/W
3
TXCR11
0
R/W
2
TXCR10
0
R/W
1
TXCR9
0
R/W
0
TXCR8
0
R/W
0 Transmit message cancellation idle state in
corresponding mailbox
[Clearing condition]
Completion of TXPR clearing (when transmit
message is canceled normally)
TXPR cleared for corresponding mailbox
(transmit message cancellation)
Transmit wait cancel register
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 863 of 1042
REJ09B0275-0500
TXACK—Transmit Acknowledge Register H'F80A HCAN
Bit
Initial value
Read/Write
:
:
:
15
TXACK7
0
R/(W)*
14
TXACK6
0
R/(W)*
13
TXACK5
0
R/(W)*
12
TXACK4
0
R/(W)*
11
TXACK3
0
R/(W)*
10
TXACK2
0
R/(W)*
9
TXACK1
0
R/(W)*
8
—
0
R
TXACK
Bit
Initial value
Read/Write
:
:
:
7
TXACK15
0
R/(W)*
6
TXACK14
0
R/(W)*
5
TXACK13
0
R/(W)*
4
TXACK12
0
R/(W)*
3
TXACK11
0
R/(W)*
2
TXACK10
0
R/(W)*
1
TXACK9
0
R/(W)*
0
TXACK8
0
R/(W)*
0 [Clearing condition]
Writing 1
Completion of message transmission
for corresponding mailbox
Transmit acknowledge register
1
Note: * Can only be written with 1 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 864 of 1042
REJ09B0275-0500
ABACK—Abort Acknowledge Reg ister H'F8 0C HCAN
Bit
Initial value
Read/Write
:
:
:
15
ABACK7
0
R/(W)*
14
ABACK6
0
R/(W)*
13
ABACK5
0
R/(W)*
12
ABACK4
0
R/(W)*
11
ABACK3
0
R/(W)*
10
ABACK2
0
R/(W)*
9
ABACK1
0
R/(W)*
8
—
0
R
ABACK
Bit
Initial value
Read/Write
:
:
:
7
ABACK15
0
R/(W)*
6
ABACK14
0
R/(W)*
5
ABACK13
0
R/(W)*
4
ABACK12
0
R/(W)*
3
ABACK11
0
R/(W)*
2
ABACK10
0
R/(W)*
1
ABACK9
0
R/(W)*
0
ABACK8
0
R/(W)*
0 [Clearing condition]
Writing 1
Completion of transmit message cancellation
for corresponding mailbox
Abort acknowledge register
1
Note: * Can only be written with 1 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 865 of 1042
REJ09B0275-0500
RXPR—Receive Complete Register H'F80E HCAN
Bit
Initial value
Read/Write
:
:
:
15
RXPR7
0
R/(W)*
14
RXPR6
0
R/(W)*
13
RXPR5
0
R/(W)*
12
RXPR4
0
R/(W)*
11
RXPR3
0
R/(W)*
10
RXPR2
0
R/(W)*
9
RXPR1
0
R/(W)*
8
RXPR0
0
R/(W)*
RXPR
Bit
Initial value
Read/Write
:
:
:
7
RXPR15
0
R/(W)*
6
RXPR14
0
R/(W)*
5
RXPR13
0
R/(W)*
4
RXPR12
0
R/(W)*
3
RXPR11
0
R/(W)*
2
RXPR10
0
R/(W)*
1
RXPR9
0
R/(W)*
0
RXPR8
0
R/(W)*
0 [Clearing condition]
Writing 1
Completion of message (data frame or remote frame)
reception in corresponding mailbox
Receive complete register
1
Note: * Can only be written with 1 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 866 of 1042
REJ09B0275-0500
RFPR—Remote Request Reg ister H'F810 HCAN
Bit
Initial value
Read/Write
:
:
:
15
RFPR7
0
R/(W)*
14
RFPR6
0
R/(W)*
13
RFPR5
0
R/(W)*
12
RFPR4
0
R/(W)*
11
RFPR3
0
R/(W)*
10
RFPR2
0
R/(W)*
9
RFPR1
0
R/(W)*
8
RFPR0
0
R/(W)*
RFPR
Bit
Initial value
Read/Write
:
:
:
7
RFPR15
0
R/(W)*
6
RFPR14
0
R/(W)*
5
RFPR13
0
R/(W)*
4
RFPR12
0
R/(W)*
3
RFPR11
0
R/(W)*
2
RFPR10
0
R/(W)*
1
RFPR9
0
R/(W)*
0
RFPR8
0
R/(W)*
0 [Clearing condition]
Writing 1
Completion of remote frame reception
in corresponding mailbox
Remote request wait register
1
Note: * Can only be written with 1 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 867 of 1042
REJ09B0275-0500
IRR—Interrupt Register H'F812 HCAN
Bit
Initial value
Read/Write
:
:
:
15
IRR7
0
R/(W)*
14
IRR6
0
R/(W)*
13
IRR5
0
R/(W)*
12
IRR4
0
R/(W)*
11
IRR3
0
R/(W)*
10
IRR2
0
R
9
IRR1
0
R
8
IRR0
0
R/(W)*
IRR
0 [Clearing condition]
Writing 1
Overload frame transmission or recovery
from bus off state
[Setting conditions]
• Error active/passive state
— When overload frame is transmitted
• Bus off state
— When 11 recessive bits are received
128 times (REC ≥ 128)
Overload frame/bus off recovery interrupt flag
1
0 [Clearing condition]
Writing 1
Bus off state caused by
transmit error
[Setting condition]
When TEC ≥ 256
Bus off interrupt flag
1
0 [Clearing condition]
Writing 1
Error passive state caused by transmit/receive error
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
Error passive interrupt flag
1
0 [Clearing condition]
Writing 1
Error warning state caused by receive error
[Setting condition]
When REC ≥ 96
Receive overload warning interrupt flag
1
0 [Clearing condition]
Writing 1
Error warning state caused by transmit error
[Setting condition]
When TEC ≥ 96
Transmit overload warning interrupt flag
1
0 [Clearing condition]
Clearing of all bits in RFPR (remote request
wait register) of mailbox for which receive interrupt
requests are enabled MBIMR
Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed
When corresponding MBIMR = 0
Remote frame request interrupt flag
1
0 [Clearing condition]
Clearing of all bits in RXPR (receive complete
register) of mailbox for which receive interrupt
requests are enabled MBIMR
Data frame or remote frame
received and stored in mailbox
[Setting conditions]
When data frame or remote frame
reception is completed
When corresponding MBIMR = 0
Receive message interrupt flag
1
0 [Clearing condition]
Writing 1
Reset interrupt flag
1Hardware reset (HCAN module stop,
software standby)
[Setting condition]
When reset processing is completed after
a hardware reset (HCAN module stop,
software standby)
Note: * Can only be written with 1 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 868 of 1042
REJ09B0275-0500
Bit
Initial value
Read/Write
Note: * Can only be written with 1 for flag clearing.
:
:
:
7
—
0
—
6
—
0
—
5
—
0
—
4
IRR12
0
R/(W)*
3
—
0
—
2
—
0
—
1
IRR9
0
R
0
IRR8
0
R/(W)*
IRR
0 [Clearing condition]
Writing 1
Transmit message has been transmitted
or aborted, and new message can be
stored
[Setting condition]
When TXPR (transmit wait register) is
cleared by completion of transmission or
completion of transmission abort
Mailbox empty interrupt flag
1
0 [Clearing condition]
Clearing of all bits in UMSR (unread message
status register)
Unread message overwrite
[Setting condition]
When UMSR (unread message status register)
is set
Unread interrupt flag
1
0 CAN bus idle state
[Clearing condition]
Writing 1
CAN bus operation in HCAN sleep mode
[Setting condition]
Bus operation (dominant bit detection) in HCAN sleep mode
Bus operation interrupt flag
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 869 of 1042
REJ09B0275-0500
MBIMR—Mailbox Interrupt Mask Register H'F814 HCAN
Bit
Initial value
Read/Write
:
:
:
15
MBIMR7
1
R/W
14
MBIMR6
1
R/W
13
MBIMR5
1
R/W
12
MBIMR4
1
R/W
11
MBIMR3
1
R/W
10
MBIMR2
1
R/W
9
MBIMR1
1
R/W
8
MBIMR0
1
R/W
MBIMR
Bit
Initial value
Read/Write
:
:
:
7
MBIMR15
1
R/W
6
MBIMR14
1
R/W
5
MBIMR13
1
R/W
4
MBIMR12
1
R/W
3
MBIMR11
1
R/W
2
MBIMR10
1
R/W
1
MBIMR9
1
R/W
0
MBIMR8
1
R/W
0 [Transmitting]
Interrupt request to CPU due to TXPR clearing
[Receiving]
Interrupt request to CPU due to RXPR setting
Interrupt requests to CPU disabled
Mailbox interrupt mask
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 870 of 1042
REJ09B0275-0500
IMR—Interrupt Mask Register H'F816 HCAN
Bit
Initial value
Read/Write
:
:
:
15
IMR7
1
R/W
14
IMR6
1
R/W
13
IMR5
1
R/W
12
IMR4
1
R/W
11
IMR3
1
R/W
10
IMR2
1
R/W
9
IMR1
1
R/W
8
—
0
R
IMR
0 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 enabled
Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 disabled
Overload frame/bus off recovery interrupt mask
1
0 Bus off interrupt request (ERS0) to CPU by IRR6 enabled
Bus off interrupt request (ERS0) to CPU by IRR6 disabled
Bus off interrupt mask
1
0 Error passive interrupt request to (ERS0) CPU by IRR5 enabled
Error passive interrupt request to (ERS0) CPU by IRR5 disabled
Error passive interrupt mask
1
0 REC error warning interrupt request
(OVR0) to CPU by IRR4 enabled
REC error warning interrupt request
(OVR0) to CPU by IRR4 disabled
Receive overload warning interrupt mask
1
0 TEC error warning interrupt request
(OVR0) to CPU by IRR3 enabled
TEC error warning interrupt request
(OVR0) to CPU by IRR3 disabled
Transmit overload warning interrupt mask
1
0 Message reception interrupt request
(RM1) to CPU by IRR1 enabled
Message reception interrupt request
(RM1) to CPU by IRR1 disabled
Receive message interrupt mask
1
0 Remote frame reception interrupt request
(OVR0) to CPU by IRR2 enabled
Remote frame reception interrupt request
(OVR0) to CPU by IRR2 disabled
Remote frame request interrupt mask
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 871 of 1042
REJ09B0275-0500
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
IMR12
1
R/W
3
—
1
—
2
—
1
—
1
IMR9
1
R/W
0
IMR8
1
R/W
IMR
0 Mailbox empty interrupt request (SLE0)
to CPU by IRR8 enabled
Mailbox empty interrupt request (SLE0)
to CPU by IRR8 disabled
Mailbox empty interrupt mask
1
0 Unread message overwrite interrupt
request (OVR0) to CPU by IRR9 enabled
Unread message overwrite interrupt
request (OVR0) to CPU by IRR9 disabled
Unread interrupt mask
1
0 Bus operation interrupt request (OVR0)
to CPU by IRR12 enabled
Bus operation interrupt request (OVR0)
to CPU by IRR12 disabled
Bus operation interrupt mask
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 872 of 1042
REJ09B0275-0500
REC—Receive Error Counter H'F818 HCAN
Bit
Initial value
Read/Write
:
:
:
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
REC
TEC—Transmit Error Counter H'F819 HCAN
Bit
Initial value
Read/Write
:
:
:
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
TEC
UMSR—Unread Message Status Register H'F81A HCAN
Bit
Initial value
Read/Write
Note: * Can only be written with 1 for flag clearing.
:
:
:
15
UMSR7
0
R/(W)*
14
UMSR6
0
R/(W)*
13
UMSR5
0
R/(W)*
12
UMSR4
0
R/(W)*
11
UMSR3
0
R/(W)*
10
UMSR2
0
R/(W)*
9
UMSR1
0
R/(W)*
8
UMSR0
0
R/(W)*
UMSR
Bit
Initial value
Read/Write
:
:
:
7
UMSR15
0
R/(W)*
6
UMSR14
0
R/(W)*
5
UMSR13
0
R/(W)*
4
UMSR12
0
R/(W)*
3
UMSR11
0
R/(W)*
2
UMSR10
0
R/(W)*
1
UMSR9
0
R/(W)*
0
UMSR8
0
R/(W)*
0 [Clearing condition]
Writing 1
Unread receive message is overwritten by a new message
[Setting condition]
When a new message is received before RXPR is cleared
Unread message status flags
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 873 of 1042
REJ09B0275-0500
LAFML—Local Acceptance Filter Mask H'F81C HCAN
LAFMH—Local Acceptance Filter Mask H'F81E HCAN
Bit
Initial value
Read/Write
:
:
:
15
LAFML7
0
R/W
14
LAFML6
0
R/W
13
LAFML5
0
R/W
12
LAFML4
0
R/W
11
LAFML3
0
R/W
10
LAFML2
0
R/W
9
LAFML1
0
R/W
8
LAFML0
0
R/W
LAFML
Bit
Initial value
Read/Write
:
:
:
7
LAFML15
0
R/W
6
LAFML14
0
R/W
5
LAFML13
0
R/W
4
LAFML12
0
R/W
3
LAFML11
0
R/W
2
LAFML10
0
R/W
1
LAFML9
0
R/W
0
LAFML8
0
R/W
Bit
Initial value
Read/Write
:
:
:
15
LAFMH7
0
R/W
14
LAFMH6
0
R/W
13
LAFMH5
0
R/W
12
—
0
R
11
—
0
R
10
—
0
R
9
LAFMH1
0
R/W
8
LAFMH0
0
R/W
LAFMH
Bit
Initial value
Read/Write
:
:
:
7
LAFMH15
0
R/W
6
LAFMH14
0
R/W
5
LAFMH13
0
R/W
4
LAFMH12
0
R/W
3
LAFMH11
0
R/W
2
LAFMH10
0
R/W
1
LAFMH9
0
R/W
0
LAFMH8
0
R/W
0 Stored in MC0, MD0 (receive-only mailbox) depending on bit match between
MC0 message identifier and receive message identifier (Care)
Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between
MC0 message identifier and receive message identifier (Don’t Care)
LAFMH Bits 7 to 0 and 15 to 13—11-bit identifier filter
1
0 Stored in MC0 (receive-only mailbox) depending on bit match between MC0
message identifier and receive message identifier (Care)
Stored in MC0 (receive-only mailbox) regardless of bit match between MC0
message identifier and receive message identifier (Don’t Care)
LAFMH bits 9 and 8, LAFML Bits 15 to 0—18-bit identifier filter
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 874 of 1042
REJ09B0275-0500
MC0—Message Control H'F820 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 0
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 875 of 1042
REJ09B0275-0500
MC1—Message Control H'F828 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 876 of 1042
REJ09B0275-0500
MC2—Message Control H'F830 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 2
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 877 of 1042
REJ09B0275-0500
MC3—Message Control H'F838 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 3
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 878 of 1042
REJ09B0275-0500
MC4—Message Control H'F840 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 4
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 879 of 1042
REJ09B0275-0500
MC5—Message Control H'F848 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 5
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 880 of 1042
REJ09B0275-0500
MC6—Message Control H'F850 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 6
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 881 of 1042
REJ09B0275-0500
MC7—Message Control H'F858 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 7
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 882 of 1042
REJ09B0275-0500
MC8—Message Control H'F860 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 8
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 883 of 1042
REJ09B0275-0500
MC9—Message Control H'F868 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 9
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 884 of 1042
REJ09B0275-0500
MC10—Message Control H'F870 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 10
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 885 of 1042
REJ09B0275-0500
MC11—Message Control H'F878 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 11
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 886 of 1042
REJ09B0275-0500
MC12—Message Control H'F880 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 12
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 887 of 1042
REJ09B0275-0500
MC13—Message Control H'F888 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 13
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 888 of 1042
REJ09B0275-0500
MC14—Message Control H'F890 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 14
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 889 of 1042
REJ09B0275-0500
MC15—Message Control H'F898 HCAN
MCx[1] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
DLC3
Undefined
R/W
2
DLC2
Undefined
R/W
1
DLC1
Undefined
R/W
0
DLC0
Undefined
R/W
MCx[2] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[3] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[4] Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
R/W
6
—
Undefined
R/W
5
—
Undefined
R/W
4
—
Undefined
R/W
3
—
Undefined
R/W
2
—
Undefined
R/W
1
—
Undefined
R/W
0
—
Undefined
R/W
MCx[5] Bit
Initial value
Read/Write
:
:
:
7
STD_ID2
Undefined
R/W
6
STD_ID1
Undefined
R/W
5
STD_ID0
Undefined
R/W
4
RTR
Undefined
R/W
3
IDE
Undefined
R/W
2
—
Undefined
R/W
1
EXD_ID17
Undefined
R/W
0
EXD_ID16
Undefined
R/W
MCx[6] Bit
Initial value
Read/Write
:
:
:
7
STD_ID10
Undefined
R/W
6
STD_ID9
Undefined
R/W
5
STD_ID8
Undefined
R/W
4
STD_ID7
Undefined
R/W
3
STD_ID6
Undefined
R/W
2
STD_ID5
Undefined
R/W
1
STD_ID4
Undefined
R/W
0
STD_ID3
Undefined
R/W
MCx[7] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID7
Undefined
R/W
6
EXD_ID6
Undefined
R/W
5
EXD_ID5
Undefined
R/W
4
EXD_ID4
Undefined
R/W
3
EXD_ID3
Undefined
R/W
2
EXD_ID2
Undefined
R/W
1
EXD_ID1
Undefined
R/W
0
EXD_ID0
Undefined
R/W
MCx[8] Bit
Initial value
Read/Write
:
:
:
7
EXD_ID15
Undefined
R/W
6
EXD_ID14
Undefined
R/W
5
EXD_ID13
Undefined
R/W
4
EXD_ID12
Undefined
R/W
3
EXD_ID11
Undefined
R/W
2
EXD_ID10
Undefined
R/W
1
EXD_ID9
Undefined
R/W
0
EXD_ID8
Undefined
R/W
Data length code Data length = 0 bytes
Data length = 1 byte
Data length = 2 bytes
Data length = 3 bytes
Data length = 4 bytes
Data length = 5 bytes
Data length = 6 bytes
Data length = 7 bytes
Data length = 8 bytes
0
1
0
1
0
1
0
1
0/1
0
1
0
1
0/1
0
1
0/1
0
1
Extended identifier
These bits set the identifier
(extended identifier) of data
frames and remote frames
0
1Standard format
Extended format
Identifier extension
0
1Data frame
Remote frame
Remote transmission request
Standard identifier
These bits set the identifier
(standard identifier) of data
frames and remote frames
Standard identifier
These bits set the identifier (standard identifier) of data frames and remote frames
Extended identifier
These bits set the identifier (extended identifier) of data frames and remote frames
x = 15
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 890 of 1042
REJ09B0275-0500
MD0—Message Data H'F8B0 HCAN
MD1—Message Data H'F8B8 HCAN
MD2—Message Data H'F8C0 HCAN
MD3—Message Data H'F8C8 HCAN
MD4—Message Data H'F8D0 HCAN
MD5—Message Data H'F8D8 HCAN
MD6—Message Data H'F8E0 HCAN
MD7—Message Data H'F8E8 HCAN
MD8—Message Data H'F8F0 HCAN
MD9—Message Data H'F8F8 HCAN
MD10—Message Data H'F900 HCAN
MD11—Message Data H'F908 HCAN
MD12—Message Data H'F910 HCAN
MD13—Message Data H'F918 HCAN
MD14—Message Data H'F920 HCAN
MD15—Message Data H'F928 HCAN
MDx [1]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [2]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [3]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 891 of 1042
REJ09B0275-0500
MDx [4]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [5]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [6]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [7]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
MDx [8]
Bit:76543210
Initial value: ********
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
x = 0 to 15
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 892 of 1042
REJ09B0275-0500
DADR2—D/A Data Register 2 H'FDAC D/A2
DADR3—D/A Data Register 3 H'FDAD D/A3
Bit
Initial value
Read/Write
:
:
:
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
DACR23—D/A Control Register 2 3 H'FDAE D/A2, 3
Bit
Initial value
Read/Write
:
:
:
7
DAOE1
0
R/W
6
DAOE0
0
R/W
5
DAE
0
R/W
4
—
1
—
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
0 0 Disables channel 2, 3 D/A conversion
Enables channel 2 D/A conversion
Disables channel 3 D/A conversion
Enables channel 2, 3 D/A conversion
Disables channel 2 D/A conversion
Enables channel 3 D/A conversion
Enables channel 2, 3 D/A conversion
Enables channel 2, 3 D/A conversion
D/A enable
10
1
*
DAOE1 DAOE0 DAE Description
0
1
1
0
1
*
0 Disables analog output DA2
Enables channel 2 D/A conversion. Also enables analog output DA2
D/A output enable 0
1
0 Disables analog output DA3
Enables channel 3 D/A conversion. Also enables analog output DA3
D/A output enable 1
1
*: Don’t care
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 893 of 1042
REJ09B0275-0500
SCRX—Serial Control Register X H'FDB4 ROM
Bit
Initial value
Read/Write
:
:
:
7
—
0
R/W
6
—
0
R/W
5
—
0
R/W
4
—
0
R/W
3
FLSHE
0
R/W
2
—
0
R/W
1
—
0
R/W
0
—
0
R/W
0Area H'FFFFA8 to H'FFFFAC flash control registers are not selected
Area H'FFFFA8 to H'FFFFAC flash control registers are selected
Flash memory control register enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 894 of 1042
REJ09B0275-0500
SBYCR—Standby Co ntrol Register H'FDE4 Power-Down Modes
Bit
Initial value
Read/Write
:
:
:
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
OPE
1
R/W
2
—
0
—
1
—
0
—
0
—
0
—
0 In software standby mode, address bus and
bus control signals are high-impedance
In software standby mode, address bus and
bus control signals retain their output state
Output port enable
1
0 0 Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states
Standby timer select
1
1
0
1
0
1
0
1
0
1
0
1
0 Transition to sleep mode after execution of SLEEP instruction
Transition to software standby mode after execution of SLEEP instruction
Software standby
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 895 of 1042
REJ09B0275-0500
SYSCR—Syst em Control Register H'F D E5 MCU
Bit
Initial value
Read/Write
:
:
:
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
2
—
0
R/W
1
—
0
—
0
RAME
1
R/W
0 On-chip RAM is disabled
On-chip RAM is enabled
RAM enable
1
0 Falling edge
Rising edge
NMI interrupt input edge select
1
0 Interrupt control mode 0
Setting prohibited
Interrupt control mode select
0 Non-saturating calculation for MAC instruction
Saturating calculation for MAC instruction
Mac saturation
1
0
1Interrupt control mode 210
Setting prohibited1
Note: When the DTC is used,
the RAME bit must be
set to 1.
Note: For details, see section 5.4.1
Interrupt Control Modes and
Interrupt Operation.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 896 of 1042
REJ09B0275-0500
SCKCR—System Clock Co ntro l Register H'FDE6 Clock Pulse Generator, Power-Down
Bit
Initial value
Read/Write
:
:
:
7
PSTOP
0
R/W
6
—
0
—
5
—
0
—
4
—
0
—
3
STCS
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
0
SCK0
0
R/W
0 0 Bus master is in high-speed mode
Medium-speed clock is φ/2
Medium-speed clock is φ/4
Medium-speed clock is φ/8
Medium-speed clock is φ/16
Medium-speed clock is φ/32
Bus master clock select
1
1
0
1 —
0
1
0
1
1
1
—
0 Specified multiplication factor is valid after
transition to software standby mode
Specified multiplication factor is valid immediately
after STC bits are rewritten
Frequency multiplication factor switching mode select
1
0
1
φ clock output control
Note: *Subclock functions (subactive mode, subsleep mode, and watch mode) and
direct transition are not available in the H8S/2623 Group, but are available
in the H8S/2626 Group.
φ output
Fixed high φ output
Fixed high Fixed high
Fixed high High impedance
High impedance
PSTOP High-Speed Mode,
Medium-Speed Mode,
Sub-Active Mode*Sleep Mode,
Sub-Sleep Mode*
Software
Standby Mode,
Watch Mode*,
Direct Transition*
Hardware
Standby Mode
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 897 of 1042
REJ09B0275-0500
MDCR—Mode Control Register H'FDE7 MCU
Bit
Initial value
Read/Write
:
:
:
7
—
1
R/W
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
2
MDS2
—*
R
1
MDS1
—*
R
0
MDS0
—*
R
Current mode pin operating mode
Note: * Determined by pins MD
2
to MD
0
.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 898 of 1042
REJ09B0275-0500
MSTPCRA—Module Stop Co ntrol Register H'FDE8 Power-Down Modes
MSTPCRB—Module Stop Contro l Register H'FDE9 Power-Down Modes
MSTPCRC—Module Stop Co ntrol Register H'FDEA Po wer-Down Modes
Bit
Initial value
Read/Write
:
:
:
7
MSTPA7
0
R/W
6
MSTPA6
0
R/W
5
MSTPA5
1
R/W
4
MSTPA4
1
R/W
3
MSTPA3
1
R/W
2
MSTPA2
1
R/W
1
MSTPA1
1
R/W
0
MSTPA0
1
R/W
MSTPCRA
Bit
Initial value
Read/Write
:
:
:
7
MSTPB7
1
R/W
6
MSTPB6
1
R/W
5
MSTPB5
1
R/W
4
MSTPB4
1
R/W
3
MSTPB3
1
R/W
2
MSTPB2
1
R/W
1
MSTPB1
1
R/W
0
MSTPB0
1
R/W
MSTPCRB
Bit
Initial value
Read/Write
:
:
:
7
MSTPC7
1
R/W
6
MSTPC6
1
R/W
5
MSTPC5
1
R/W
4
MSTPC4
1
R/W
3
MSTPC3
1
R/W
2
MSTPC2
1
R/W
1
MSTPC1
1
R/W
0
MSTPC0
1
R/W
MSTPCRC
0 Module stop mode is cleared
(initial value of MSTPA7 and MSTPA6)
Module stop mode is set
(initial value of MSTPA5–0, MSTPB7–0, and MSTPC7–0)
Module stop mode specification
1
Register
MSTPCRA MSTPA7
*
—
MSTPA6 Data transfer controller (DTC)
MSTPA5 16-bit timer pulse unit (TPU)
MSTPA4
*
—
MSTPA3 Programmable pulse generator (PPG)
MSTPA2
*
—
MSTPA1 A/D converter
MSTPA0
*
—
MSTPCRB MSTPB7 Serial communication interface 0 (SCI0)
MSTPB6 Serial communication interface 1 (SCI1)
MSTPB5 Serial communication interface 2 (SCI2)
MSTPB4
*
—
MSTPB3
*
—
MSTPB2
*
—
MSTPB1
*
—
MSTPB0
*
—
MSTPCRC MSTPC7
*
—
MSTPC6
*
—
MSTPC5 D/A converter (channels 2, 3)
MSTPC4 PC break controller (PBC)
MSTPC3 HCAN
MSTPC2
*
—
MSTPC1
*
—
MSTPC0
*
—
Module
MSTP bits and corresponding on-chip supporting modules
Bit
Notes: * MSTPA7 is a readable/writable bit with an initial value of 0.
MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC4, and MSTPC2 to
MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 899 of 1042
REJ09B0275-0500
PFCR—Pin Function Control Register H'FDEB MCU, Bus Controller
Bit
Initial value
Read/Write
:
:
:
7
—
0
R/W
6
—
0
R/W
5
BUZZE
0*2
R/W
4
—
0
R/W
3
AE3
1/0*1
R/W
2
AE2
1/0*1
R/W
1
AE1
0
R/W
0
AE0
1/0*1
R/W
0A8–A23 address output disabled
A8 address output enabled; A9–A23 address output disabled
A8, A9 address output enabled; A10–A23 address output disabled
A8–A10 address output enabled; A11–A23 address output disabled
A8–A11 address output enabled; A12–A23 address output disabled
A8–A12 address output enabled; A13–A23 address output disabled
A8–A13 address output enabled; A14–A23 address output disabled
A8–A14 address output enabled; A15–A23 address output disabled
A8–A15 address output enabled; A16–A23 address output disabled
A8–A16 address output enabled; A17–A23 address output disabled
A8–A17 address output enabled; A18–A23 address output disabled
A8–A18 address output enabled; A19–A23 address output disabled
A8–A19 address output enabled; A20–A23 address output disabled
A8–A20 address output enabled; A21–A23 address output disabled
A8–A21 address output enabled; A22, A23 address output disabled
A8–A23 address output enabled
Address output enable
0 0 0
1
10
1
100
1
10
1
1000
1
10
1
100
1
10
1
Notes: 1. In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding
DDR bits to 1.
2. This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be
written to this bit.
0 Functions as PF1 I/O pin
Functions as BUZZ output pin
BUZZ output enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 900 of 1042
REJ09B0275-0500
LPWRCR—Low-Power Control Register H'FDEC Clock Pulse Generator
Bit
Initial value
Read/Write
:
:
:
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
SUBSTP
0
R/W
3
RFCUT
0
R/W
2
—
0
R/W
1
STC1
0
R/W
0
STC0
0
R/W
00× 1 (initial value)
STC1 STC0
× 2
Frequency multiplier
1
10
1× 4
Do not set
Note: A system clock frequency multiplied
by the multiplication factor (STC1
and STC0) should not exceed the
maximum operating frequency
defined in section 22, Electrical
Characteristics.
Note: This bit is valid only in the H8S/2626 Group; in the
H8S/2623 Group, 0 must be written to this bit.
Notes: This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be written to this bit.
* Always select high-speed mode when transferring to watch mode or sub-active mode.
Note: This bit is valid only in the H8S/2626 Group; in the
H8S/2623 Group, 0 must be written to this bit.
0Feedback resistor ON when main clock operating;
OFF when not operation
Feedback resistor OFF
Oscillator circuit feedback resistor control bit
1
0Subclock generation enabled
Subclock generation disabled
Subclock enable
1
0Sampling uses φ/32 clock
Sampling uses φ/4 clock
Noise elimination sampling frequency select
1
0
Low-speed ON flag
1
• When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
transfers to sleep mode, software standby mode, or watch mode*
• When the SLEEP command is executed in sub-active mode, operation transfers to watch mode,
or directly to high-speed mode
• Operation transfers to high-speed mode after watch mode is canceled
• When the SLEEP command is executed in high-speed mode, operation transfers to watch mode
or sub-active mode
• When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep
mode or watch mode
• Operation transfers to sub-active mode immediately watch mode is canceled
Notes: This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be written to this bit.
* Always select high-speed mode when transferring to watch mode or sub-active mode.
0
Direct transfer ON flag
1
• When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
transfers to sleep mode, software standby mode, or watch mode*
• When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep
mode or watch mode
• When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
transfers directly to sub-active mode, or transfers to sleep mode or software standby mode
• When the SLEEP command is executed in sub-active mode, operation transfers directly to high-
speed mode or transfers to sub-sleep mode
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 901 of 1042
REJ09B0275-0500
BARA—Break Address Register A H'FE00 PBC
BARB—Break Address Register B H'FE04 PBC
Bit
Initial value
Read/Write
:
:
:
Break address specification
31
—
Unde-
fined
—
...
...
...
...
24
—
Unde-
fined
—
23
0
R/W
22
0
R/W
21
0
R/W
20
0
R/W
19
0
R/W
18
0
R/W
17
0
R/W
16
0
R/W
...
...
...
...
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
BAA
23 BAA
22 BAA
21 BAA
20 BAA
19 BAA
18 BAA
17 BAA
16 BAA
7BAA
6BAA
5BAA
4BAA
3BAA
1BAA
0
BAA
2
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 902 of 1042
REJ09B0275-0500
BCRA—Break Control Register A H'FE08 PBC
BCRB—Break Control Register B H'FE09 PBC
Bit
Initial value
Read/Write
:
:
:
7
CMFA
0
R/(W)*
6
CDA
0
R/W
5
BAMRA2
0
R/W
4
BAMRA1
0
R/W
3
BAMRA0
0
R/W
2
CSELA1
0
R/W
1
CSELA0
0
R/W
0
BIEA
0
R/W
0 0 Instruction fetch is used as break condition
Data read cycle is used as break condition
Break condition select
0 PC break interrupts are disabled
PC break interrupts are enabled
Break interrupt enable
1
1
10
1Data write cycle is used as break condition
Data read/write cycle is used as break condition
0 0 All BARA bits are unmasked and included in break
conditions
Break address mask register
1
1
0
1
0
1
0
1
0
1
0
1
0 PC break is performed when CPU is bus master
PC break is performed when CPU or DTC is bus master
CPU cycle/DTC cycle select A
1
0 [Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
When a condition set for channel A is satisfied
Condition match flag
1
BAA0 (lowest bit) is masked, and not included in break
conditions
BAA1–0 (lower 2 bits) are masked, and not included
in break conditions
BAA2–0 (lower 3 bits) are masked, and not included
in break conditions
BAA3–0 (lower 4 bits) are masked, and not included
in break conditions
BAA7–0 (lower 8 bits) are masked, and not included
in break conditions
BAA11–0 (lower 12 bits) are masked, and not included
in break conditions
BAA15–0 (lower 16 bits) are masked, and not included
in break conditions
Notes: The bit configuration of BCRB is the same as that of BCRA, except that BCRB performs break control
for channel B.
* Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 903 of 1042
REJ09B0275-0500
ISCRH—IRQ Sense Control Register H H'FE12 Interrupt Controller
ISCRL—IRQ Sense Control Register L H'FE13 Interrupt Co ntroller
Bit
Initial value
Read/Write
:
:
:
15
—
0
R/W
14
—
0
R/W
13
—
0
R/W
12
—
0
R/W
11
IRQ5SCB
0
R/W
10
IRQ5SCA
0
R/W
9
IRQ4SCB
0
R/W
8
IRQ4SCA
0
R/W
ISCRH
Bit
Initial value
Read/Write
:
:
:
7
IRQ3SCB
0
R/W
6
IRQ3SCA
0
R/W
5
IRQ2SCB
0
R/W
4
IRQ2SCA
0
R/W
3
IRQ1SCB
0
R/W
2
IRQ1SCA
0
R/W
1
IRQ0SCB
0
R/W
0
IRQ0SCA
0
R/W
ISCRL
IRQ5 and IRQ4 sense control
00
IRQ3 to IRQ0 sense control
1
10
1
IRQnSCB IRQnSCA Interrupt Request Generation
Low level of IRQn input
Falling edge of IRQn input
Rising edge of IRQn input
Rising and falling edges of IRQn input
(n = 5 to 0)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 904 of 1042
REJ09B0275-0500
IER—IRQ Enable Register H'FE14 Inter r upt Contro lle r
Bit
Initial value
Read/Write
:
:
:
7
—
0
R/W
6
—
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
0 IRQn interrupt is disabled
IRQn interrupt is enabled
IRQn enable
1(n = 5 to 0)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 905 of 1042
REJ09B0275-0500
ISR—IRQ Status Register H'FE15 Interrupt Controller
Bit
Initial value
Read/Write
:
:
:
7
—
0
R/(W)*
6
—
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
Note: * Can only be written with 0 for flag clearing. (n = 5 to 0)
0
IRQ5 to IRQ0 interrupt request status indication
1
[Clearing conditions]
• Cleared by reading IRQnF flag when IRQnF = 1, then writing 0
to IRQnF flag
• When interrupt exception handling is executed when low-level
detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is
high
• When IRQn interrupt exception handling is executed when
falling, rising, or both-edge detection is set (IRQnSCB = 1 or
IRQnSCA = 1)
• When the DTC is activated by an IRQn interrupt, and the DISEL
bit in MRB of the DTC is cleared to 0
[Setting conditions]
• When IRQn input goes low when low-level detection is set
(IRQnSCB = IRQnSCA = 0)
• When a falling edge occurs in IRQn input when falling edge
detection is set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input when rising edge
detection is set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input when both-
edge detection is set (IRQnSCB = IRQnSCA = 1)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 906 of 1042
REJ09B0275-0500
DTCER—DTC Enable Register H'FE16 to H'FE1C DTC
Bit
Initial value
Read/Write
:
:
:
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
0 DTC activation by interrupt is disabled
[Clearing conditions]
• When data transfer ends while the DISEL bit is 1
• When the specified number of transfers are completed
DTC activation by interrupt is enabled
[Maintenance condition]
When the DISEL bit is 0 and the specified number
of transfers have not been completed
DTC activation enable
1
Register Bit
7
IRQ0
—
TGI2A
—
—
RXI2
—
Interrupt Sources and DTCER Bits
DTCERA
DTCERB
DTCERC
DTCERD
DTCERE
DTCERF
DTCERG
6
IRQ1
ADI
TGI2B
—
—
TXI2
—
5
IRQ2
TGI0A
TGI3A
TGI5A
—
—
RM0
4
IRQ3
TGI0B
TGI3B
TGI5B
—
—
—
3
IRQ4
TGI0C
TGI3C
—
RXI0
—
—
2
IRQ5
TGI0D
TGI3D
—
TXI0
—
—
1
—
TGI1A
TGI4A
—
RXI1
—
—
0
—
TGI1B
TGI4B
—
TXI1
—
—
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 907 of 1042
REJ09B0275-0500
DTVECR—DTC Vector Register H'FE1F DTC
Bit
Initial value
Read/Write
:
:
:
7
SWDTE
0
R/(W)
*1
6
DTVEC6
0
R/(W)
*2
5
DTVEC5
0
R/(W)
*2
4
DTVEC4
0
R/(W)
*2
3
DTVEC3
0
R/(W)
*2
2
DTVEC2
0
R/(W)
*2
1
DTVEC1
0
R/(W)
*2
0
DTVEC0
0
R/(W)
*2
Sets vector number for DTC software activation
0 DTC software activation is disabled
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of transfers have not
been completed
• When 0 is written after a software-activated data transfer interrupt
(SWDTEND) request has been sent to the CPU
DTC software activation is enabled
[Maintenance conditions]
• When data transfer ends while the DISEL bit is 1
• When the specified number of transfers are completed
• During data transfer activated by software
DTC software activation enable
1
Notes: 1.
2. Only 1 can be written to the SWDTE bit.
Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 908 of 1042
REJ09B0275-0500
PCR—PPG Output Control Register H'FE26 PPG
Bit
Initial value
Read/Write
:
:
:
7
G3CMS1
1
R/W
6
G3CMS0
1
R/W
5
G2CMS1
1
R/W
4
G2CMS0
1
R/W
3
G1CMS1
1
R/W
2
G1CMS0
1
R/W
1
G0CMS1
1
R/W
0
G0CMS0
1
R/W
0 0 Compare match in TPU channel 0
Compare match in TPU channel 1
Group 0 compare match select
1
10
1Compare match in TPU channel 2
Compare match in TPU channel 3
0 0 Compare match in TPU channel 0
Compare match in TPU channel 1
Compare match in TPU channel 2
Compare match in TPU channel 3
Group 1 compare match select
1
10
1
0 0 Compare match in TPU channel 0
Compare match in TPU channel 1
Compare match in TPU channel 2
Compare match in TPU channel 3
Group 2 compare match select
1
10
1
0 0 Compare match in TPU channel 0
Compare match in TPU channel 1
Compare match in TPU channel 2
Compare match in TPU channel 3
Group 3 compare match select
1
10
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 909 of 1042
REJ09B0275-0500
PMR—PPG Output Mode Register H'FE27 PPG
Bit
Initial value
Read/Write
:
:
:
7
G3INV
1
R/W
6
G2INV
1
R/W
5
G1INV
1
R/W
4
G0INV
1
R/W
3
G3NOV
0
R/W
2
G2NOV
0
R/W
1
G1NOV
0
R/W
0
G0NOV
0
R/W
0 Normal operation in pulse output group
0 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 0 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
Group 0 non-overlap
1
0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
Group 3 invert
1
0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)
Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)
Group 2 invert
1
0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)
Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)
Group 1 invert
1
0 Normal operation in pulse output group
1 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 1 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
Group 1 non-overlap
1
0 Normal operation in pulse output group
2 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 2 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
Group 2 non-overlap
1
0 Normal operation in pulse output group
3 (output values updated at compare
match A in the selected TPU channel)
Non-overlapping operation in pulse
output group 3 (1 output and 0 output
can be performed independently at
compare match A and B in the selected
TPU channel)
Group 3 non-overlap
1
0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)
Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)
Group 0 invert
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 910 of 1042
REJ09B0275-0500
NDERH—Next Data Enable Register H H'FE28 PPG
Bit
Initial value
Read/Write
:
:
:
7
NDER15
0
R/W
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
2
NDER10
0
R/W
1
NDER9
0
R/W
0
NDER8
0
R/W
0 Pulse outputs PO15 to PO8 are disabled
(transfer from NDR15–NDR8 to POD15–POD8 is disabled)
Pulse outputs PO15 to PO8 are enabled
(transfer from NDR15–NDR8 to POD15–POD8 is enabled)
Next data enable
1
NDERL—Next Data Enable Register L H'FE29 PPG
Bit
Initial value
Read/Write
:
:
:
7
NDER7
0
R/W
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
0 Pulse outputs PO7 to PO0 are disabled
(transfer from NDR7–NDR0 to POD7–POD0 is disabled)
Pulse outputs PO7 to PO0 are enabled
(transfer from NDR7–NDR0 to POD7–POD0 is enabled)
Next data enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 911 of 1042
REJ09B0275-0500
PODRH—Output Data Register H H'FE2A PPG
Bit
Initial value
Read/Write
:
:
:
7
POD15
0
R/(W)*
6
POD14
0
R/(W)*
5
POD13
0
R/(W)*
4
POD12
0
R/(W)*
3
POD11
0
R/(W)*
2
POD10
0
R/(W)*
1
POD9
0
R/(W)*
0
POD8
0
R/(W)*
Note: * A bit that has been set for pulse output by NDER is read-only.
PODRL—Output Data Register L H'FE2B PPG
Bit
Initial value
Read/Write
:
:
:
7
POD7
0
R/(W)*
6
POD6
0
R/(W)*
5
POD5
0
R/(W)*
4
POD4
0
R/(W)*
3
POD3
0
R/(W)*
2
POD2
0
R/(W)*
1
POD1
0
R/(W)*
0
POD0
0
R/(W)*
Note: * A bit that has been set for pulse output by NDER is read-only.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 912 of 1042
REJ09B0275-0500
NDRH—Next Data Register H H'FE2C PPG
NDRH—Next Data Register H H'FE2E PPG
Bit
Initial value
Read/Write
:
:
:
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
H'FE2C
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
H'FE2E
When pulse output group output triggers are the same
Bit
Initial value
Read/Write
:
:
:
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
H'FE2C
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
H'FE2E
When pulse output group output triggers are different
Note: For details see section 11.2.4, Notes on NDR Access.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 913 of 1042
REJ09B0275-0500
NDRL—Next Data Register L H'FE2D PPG
NDRL—Next Data Register L H'FE2F PPG
Bit
Initial value
Read/Write
:
:
:
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
H'FE2D
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
H'FE2F
When pulse output group output triggers are the same
Bit
Initial value
Read/Write
:
:
:
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
H'FE2D
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
H'FE2F
When pulse output group output triggers are different
Note: For details see section 11.2.4, Notes on NDR Access.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 914 of 1042
REJ09B0275-0500
P1DDR—Port 1 Data Direction Register H'FE30 PPG
Bit
Initial value
Read/Write
:
:
:
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
Bit-by-bit specification of input or output for port 1 pins
PADDR—Port A Data Direction Register H'FE39 Port A
Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
—
6
—
Undefined
—
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
0
PA0DDR
0
W
Specification of input or output for port A pins
**
Note: * Reserved bits in the H8S/2626 Group.
PBDDR—Port B Data Direction Register H'FE3A Port B
Bit
Initial value
Read/Write
:
:
:
7
PB7DDR
0
W
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
Specification of input or output for port B pins
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 915 of 1042
REJ09B0275-0500
PCDDR—Port C Data Direction Register H'FE3B Port C
Bit
Initial value
Read/Write
:
:
:
7
PC7DDR
0
W
6
PC6DDR
0
W
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
Specification of input or output for port C pins
PDDDR—Port D Data Direction Register H'FE3C Port D
Bit
Initial value
Read/Write
:
:
:
7
PD7DDR
0
W
6
PD6DDR
0
W
5
PD5DDR
0
W
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Specification of input or output for port D pins
PEDDR—Port E Data Direction Register H'FE3D Port E
Bit
Initial value
Read/Write
:
:
:
7
PE7DDR
0
W
6
PE6DDR
0
W
5
PE5DDR
0
W
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
Specification of input or output for port E pins
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 916 of 1042
REJ09B0275-0500
PFDDR—Port F Data Direction Register H'FE3E Port F
Bit
Modes 4 to 6
Initial value
Read/Write
Mode 7
Initial value
Read/Write
:
:
:
:
:
7
PF7DDR
1
W
0
W
6
PF6DDR
0
W
0
W
5
PF5DDR
0
W
0
W
4
PF4DDR
0
W
0
W
3
PF3DDR
0
W
0
W
2
PF2DDR
0
W
0
W
1
PF1DDR
0
W
0
W
0
PF0DDR
0
W
0
W
Specification of input or output for port F pins
PAPCR—Port A MOS Pull-Up Control Register H'FE40 Port A
Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
—
6
—
Undefined
—
5
PA5PCR
0
R/W
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
Bit-by-bit control of port A MOS input pull-ups
**
Note: * Reserved bits in the H8S/2626 Group.
PBPCR—Port B MOS Pull-Up Control Register H'FE41 Port B
Bit
Initial value
Read/Write
:
:
:
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
5
PB5PCR
0
R/W
4
PB4PCR
0
R/W
3
PB3PCR
0
R/W
2
PB2PCR
0
R/W
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
Bit-by-bit control of port B MOS input pull-ups
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 917 of 1042
REJ09B0275-0500
PCPCR—Port C MOS Pull-Up Control Register H'FE42 Port C
Bit
Initial value
Read/Write
:
:
:
7
PC7PCR
0
R/W
6
PC6PCR
0
R/W
5
PC5PCR
0
R/W
4
PC4PCR
0
R/W
3
PC3PCR
0
R/W
2
PC2PCR
0
R/W
1
PC1PCR
0
R/W
0
PC0PCR
0
R/W
Bit-by-bit control of port C MOS input pull-ups
PDPCR—Port D MOS Pull-Up Control Register H'FE43 Port D
Bit
Initial value
Read/Write
:
:
:
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
Bit-by-bit control of port D MOS input pull-ups
PEPCR—Port E MOS Pull-Up Control Register H'FE44 Port E
Bit
Initial value
Read/Write
:
:
:
7
PE7PCR
0
R/W
6
PE6PCR
0
R/W
5
PE5PCR
0
R/W
4
PE4PCR
0
R/W
3
PE3PCR
0
R/W
2
PE2PCR
0
R/W
1
PE1PCR
0
R/W
0
PE0PCR
0
R/W
Bit-by-bit control of port E MOS input pull-ups
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 918 of 1042
REJ09B0275-0500
PAODR—Port A Open Drain Control Register H'FE47 Port A
Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
—
6
—
Undefined
—
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
PMOS on/off control for port A pins (PA5 to PA0)
**
Note: * Reserved bits in the H8S/2626 Group.
PBODR—Port B Open Drain Control Register H'FE48 Port B
Bit
Initial value
Read/Write
:
:
:
7
PB7ODR
0
R/W
6
PB6ODR
0
R/W
5
PB5ODR
0
R/W
4
PB4ODR
0
R/W
3
PB3ODR
0
R/W
2
PB2ODR
0
R/W
1
PB1ODR
0
R/W
0
PB0ODR
0
R/W
PMOS on/off control for port B pins (PB7 to PB0)
PCODR—Port C Open Drain Control Register H'FE49 Port C
Bit
Initial value
Read/Write
:
:
:
7
PC7ODR
0
R/W
6
PC6ODR
0
R/W
5
PC5ODR
0
R/W
4
PC4ODR
0
R/W
3
PC3ODR
0
R/W
2
PC2ODR
0
R/W
1
PC1ODR
0
R/W
0
PC0ODR
0
R/W
PMOS on/off control for port C pins (PC7 to PC0)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 919 of 1042
REJ09B0275-0500
TCR3—Timer Control Register 3 H'FE80 TPU3
Bit
Initial value
Read/Write
:
:
:
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
Internal clock: counts on φ/1024
Internal clock: counts on φ/256
Internal clock: counts on φ/4096
Timer prescaler
0
1
0
1
0
1
0
1
0
1
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
Input clock edge select
0 0 TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter clear
0
1
10
1
100
1
10
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture*2
TCNT cleared by TGRD compare match/input capture*2
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*1
Note: Internal clock edge selection is valid when the
input clock is φ/4 or slower. This setting is ignored
if is φ/1 is selected as the input clock.
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 920 of 1042
REJ09B0275-0500
TMDR3—Timer Mode Register 3 H'FE81 TPU3
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
BFB
0
R/W
4
BFA
0
R/W
3
MD3
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
MD0
0
R/W
0 0 Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
Mode
1
1
*
0
1
0
1
*
0
1
0
1
0
1
0
1
*
*: Don’t care
—
Notes: 1. MD3 is a reserved bit.
In a write, it should always be
written with 0.
2. Phase counting mode cannot
be set for channel 3. In this
case, 0 should always be
written to MD2.
0 TGRA operates normally
TGRA and TGRC used together for buffer
operation
Buffer operation setting A
1
0 TGRB operates normally
TGRB and TGRD used together for buffer
operation
Buffer operation setting B
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 921 of 1042
REJ09B0275-0500
TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3
Bit
Initial value
Read/Write
:
:
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
00
TGR3A I/O control
0 0
1
TGR3A
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR3A
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCA3 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
4/count clock
Input capture at TCNT4 count-up/
count-down
00
TGR3B I/O control
0 0
1
TGR3B
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR3B
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCB3 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
4/count clock
Input capture at TCNT4 count-up/
count-down
*1
Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as
the TCNT4 count clock, this setting is invalid and input capture is not
generated.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 922 of 1042
REJ09B0275-0500
TIOR3L—Timer I/O Control Register 3L H'FE83 TPU3
Bit
Initial value
Read/Write
:
:
:
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
00
TRG3C I/O control
0 0
1
TGR3C
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR3C
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCC3 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
4/count clock
Input capture at TCNT4 count-up/
count-down
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
00
TGR3D I/O control
0 0
1
TGR3D
is output
compare
register
*2
10
1
100
1
10
1
01 0 0 TGR3D
is input
capture
register
*2
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCD3 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
4/count clock
Input capture at TCNT4 count-up/
count-down
*1
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 923 of 1042
REJ09B0275-0500
TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3
Bit
Initial value
Read/Write
:
:
:
7
TTGE
0
R/W
6
—
1
—
5
—
0
—
4
TCIEV
0
R/W
3
TGIED
0
R/W
2
TGIEC
0
R/W
1
TGIEB
0
R/W
0
TGIEA
0
R/W
0 Interrupt requests (TGIA)
by TGFA bit disabled
Interrupt requests (TGIA)
by TGFA bit enabled
TGR interrupt enable A
1
0 Interrupt requests (TGIB)
by TGFB bit disabled
Interrupt requests (TGIB)
by TGFB bit enabled
TGR interrupt enable B
1
0 Interrupt requests (TGIC)
by TGFC bit disabled
Interrupt requests (TGIC)
by TGFC bit enabled
TGR interrupt enable C
1
0 Interrupt requests (TGID)
by TGFD bit disabled
Interrupt requests (TGID)
by TGFD bit enabled
TGR interrupt enable D
1
0 Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
Overflow interrupt enable
1
0 A/D conversion start request generation disabled
A/D conversion start request generation enabled
A/D conversion start request enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 924 of 1042
REJ09B0275-0500
TSR3—Timer Status Register 3 H'FE85 TPU3
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
0
—
4
TCFV
0
R/(W)*
3
TGFD
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
0
TGR input capture/output compare flag A
1
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt, and DISEL
bit in DTC’s MRB is 0
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
TGR input capture/output compare flag B
1
0 [Clearing conditions]
• When DTC is activated by TGIC interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while
TGRC is functioning as input capture register
TGR input capture/output compare flag C
1
Note: * Can only be written with 0 for flag clearing.
0 [Clearing conditions]
• When DTC is activated by TGID interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
TGR input capture/output compare flag D
1
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
Overflow flag
1
[Clearing conditions]
• When DTC is activated by TGIA interrupt, and DISEL
bit in DTC’s MRB is 0
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal while TGRA is functioning as input
capture register
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 925 of 1042
REJ09B0275-0500
TCNT3—Timer Counter 3 H'FE86 TPU3
Bit
Initial value
Read/Write
:
:
:
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Up-counter
TGR3A—Timer General Register 3A H'FE88 TPU3
TGR3B—Timer General Register 3B H'FE8A TPU3
TGR3C—Timer General Register 3C H'FE8C TPU3
TGR3D—Timer General Register 3D H'FE8E TPU3
Bit
Initial value
Read/Write
:
:
:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 926 of 1042
REJ09B0275-0500
TCR4—Timer Control Register 4 H'FE90 TPU4
Bit
Initial value
Read/Write
:
:
:
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on φ/1024
Counts on TCNT5 overflow/underflow
Time prescaler
0
1
0
1
0
1
0
1
0
1
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
Input clock edge select
00 TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter clear
0
1
10
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: This setting is invalid when channel 4 is in phase
counting mode.
Note: This setting is invalid when channel 4 is in phase
counting mode.
This setting is ignored if the input clock is φ/1, or when
overflow/underflow of another channel is selected.
Note: * Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 927 of 1042
REJ09B0275-0500
TMDR4—Timer Mode Register 4 H'FE91 TPU4
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
MD3
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
MD0
0
R/W
0 0 Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
Mode
1
1
*
0
1
0
1
*
0
1
0
1
0
1
0
1
*
*: Don’t care
—
Note: MD3 is a reserved bit. In a write,
it should always be written with 0.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 928 of 1042
REJ09B0275-0500
TIOR4—Timer I/O Control Register 4 H'FE92 TPU4
Bit
Initial value
Read/Write
:
:
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
00
TGR4A I/O control
0 0
1
TGR4A
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR4A
is input
capture
register
1
1*
Output disabled
Initial output is 1
output
Output disabled
Initial output is 0
output
Capture input
source is
TIOCA4 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is TGR3A
compare match/
input capture
Input capture at generation of
TGR3A compare match/input
capture
00
TGR4B I/O control
0 0
1
TGR4B
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR4B
is input
capture
register
1
1*
Output disabled
Initial output is 1
output
Output disabled
Initial output is 0
output
Capture input
source is
TIOCB4 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is TGR3C
compare match/
input capture
Input capture at generation of
TGR3C compare match/input
capture
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 929 of 1042
REJ09B0275-0500
TIER4—Timer Interrupt Enable Register 4 H'FE94 TPU4
Bit
Initial value
Read/Write
:
:
:
7
TTGE
0
R/W
6
—
1
—
5
TCIEU
0
R/W
4
TCIEV
0
R/W
3
—
0
—
2
—
0
—
1
TGIEB
0
R/W
0
TGIEA
0
R/W
0 Interrupt requests (TGIA)
by TGFA bit disabled
Interrupt requests (TGIA)
by TGFA bit enabled
TGI interrupt enable A
1
0 Interrupt requests (TGIB)
by TGFB bit disabled
Interrupt requests (TGIB)
by TGFB bit enabled
TGI interrupt enable B
1
0 Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
Overflow interrupt enable
1
0 A/D conversion start request generation disabled
A/D conversion start request generation enabled
A/D conversion start request enable
1
0 Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
Underflow interrupt enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 930 of 1042
REJ09B0275-0500
TSR4—Timer Status Register 4 H'FE95 TPU4
Bit
Initial value
Read/Write
:
:
:
7
TCFD
1
R
6
—
1
—
5
TCFU
0
R/(W)*
4
TCFV
0
R/(W)*
3
—
0
—
2
—
0
—
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFA after reading
TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is
functioning as output compare register
• When TCNT value is transferred to
TGRA by input capture signal while TGRA
is functioning as input capture register
TGR input capture/output compare flag A
1
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFB after reading
TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is
functioning as output compare register
• When TCNT value is transferred to
TGRB by input capture signal while TGRB
is functioning as input capture register
TGR input capture/output compare flag B
1
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
Overflow flag
1
0 [Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Underflow flag
1
0 TCNT counts down
TCNT counts up
Counter direction flag
1
Note: * Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 931 of 1042
REJ09B0275-0500
TCNT4—Timer Counter 4 H'FE96 TPU4
Bit
Initial value
Read/Write
:
:
:
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Up/down-counter*
Note: *This timer counter can be used as an up/down-counter only in phase counting mode or
when performing overflow/underflow counting on another channel. In other cases it
functions as an up-counter.
TGR4A—Timer General Register 4A H'FE98 TPU4
TGR4B—Timer General Register 4B H'FE9A TPU4
Bit
Initial value
Read/Write
:
:
:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 932 of 1042
REJ09B0275-0500
TCR5—Timer Control Register 5 H'FEA0 TPU5
Bit
Initial value
Read/Write
:
:
:
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on φ/256
External clock: counts on TCLKD pin input
Time prescaler
0
1
0
1
0
1
0
1
0
1
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
Input clock edge select
00 TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter clear
0
1
10
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: This setting is invalid when channel 5 is in phase
counting mode.
Note: This setting is invalid when channel 5 is
in phase counting mode, and also when
φ/1 is selected as the input clock.
Note: * Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 933 of 1042
REJ09B0275-0500
TMDR5—Timer Mode Register 5 H'FEA1 TPU5
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
MD3
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
MD0
0
R/W
0 0 Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
Mode
1
1
*
0
1
0
1
*
0
1
0
1
0
1
0
1
*
*: Don’t care
—
Note: MD3 is a reserved bit. In a write,
it should always be written with 0.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 934 of 1042
REJ09B0275-0500
TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5
Bit
Initial value
Read/Write
:
:
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
00
TGR5A I/O control
0 0
1
TGR5A
is output
compare
register
10
1
100
1
10
1
*1 0 0 TGR5A
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCA5 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
00
TGR5B I/O control
0 0
1
TGR5B
is output
compare
register
10
1
100
1
10
1
*1 0 0 TGR5B
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCB5 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 935 of 1042
REJ09B0275-0500
TIER5—Timer Interrupt Enable Register 5 H'FEA4 TPU5
Bit
Initial value
Read/Write
:
:
:
7
TTGE
0
R/W
6
—
1
—
5
TCIEU
0
R/W
4
TCIEV
0
R/W
3
—
0
—
2
—
0
—
1
TGIEB
0
R/W
0
TGIEA
0
R/W
0 Interrupt requests (TGIA)
by TGFA bit disabled
Interrupt requests (TGIA)
by TGFA bit enabled
TGI interrupt enable A
1
0 Interrupt requests (TGIB)
by TGFB bit disabled
Interrupt requests (TGIB)
by TGFB bit enabled
TGI interrupt enable B
1
0 Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
Overflow interrupt enable
1
0 A/D conversion start request generation disabled
A/D conversion start request generation enabled
A/D conversion start request enable
1
0 Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
Underflow interrupt enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 936 of 1042
REJ09B0275-0500
TSR5—Timer Status Register 5 H'FEA5 TPU5
Bit
Initial value
Read/Write
:
:
:
7
TCFD
1
R
6
—
1
—
5
TCFU
0
R/(W)*
4
TCFV
0
R/(W)*
3
—
0
—
2
—
0
—
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFA after reading
TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is
functioning as output compare register
• When TCNT value is transferred to
TGRA by input capture signal while TGRA
is functioning as input capture register
TGR input capture/output compare flag A
1
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFB after reading
TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is
functioning as output compare register
• When TCNT value is transferred to
TGRB by input capture signal while TGRB
is functioning as input capture register
TGR input capture/output compare flag B
1
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
Overflow flag
1
0 [Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Underflow flag
1
0 TCNT counts down
TCNT counts up
Counter direction flag
1
Note: * Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 937 of 1042
REJ09B0275-0500
TCNT5—Timer Counter 5 H'FEA6 TPU5
Bit
Initial value
Read/Write
:
:
:
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Up/down-counter*
Note: *This timer counter can be used as an up/down-counter only in phase counting mode or
when performing overflow/underflow counting on another channel. In other cases it
functions as an up-counter.
TGR5A—Timer General Register 5A H'FEA8 TPU5
TGR5B—Timer General Register 5B H'FEAA TPU5
Bit
Initial value
Read/Write
:
:
:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
TSTR—Timer Start Register H'FEB0 TPU
Bit
Initial value
Read/Write
:
:
:
7
—
0
—
6
—
0
—
5
CST5
0
R/W
4
CST4
0
R/W
3
CST3
0
R/W
2
CST2
0
R/W
1
CST1
0
R/W
0
CST0
0
R/W
0 TCNTn count operation is stopped
TCNTn performs count operation
Counter start
1
(n = 5 to 0)
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output,
the counter stops but the TIOC pin output compare output level is retained. If TIOR is
written to when the CST bit is cleared to 0, the pin output level will be changed to
the set initial output value.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 938 of 1042
REJ09B0275-0500
TSYR—Timer Sy nc Registe r H'FEB1 TPU
Bit
Initial value
Read/Write
:
:
:
7
—
0
—
6
—
0
—
5
SYNC5
0
R/W
4
SYNC4
0
R/W
3
SYNC3
0
R/W
2
SYNC2
0
R/W
1
SYNC1
0
R/W
0
SYNC0
0
R/W
0 TCNTn operates independently
(TCNT presetting/clearing is unrelated to other channels)
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
Timer synchronization
1
(n = 5 to 0)
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 939 of 1042
REJ09B0275-0500
IPRA—Interrupt Priority Register A H'FEC0 Interrupt Controller
IPRB—Interrupt Priority Register B H'FEC1 Interrupt Controller
IPRC—Interrupt Priority Register C H'FEC2 Interrupt Controller
IPRD—Interrupt Priority Register D H'FEC3 Interrupt Controller
IPRE—Interrupt Priority Register E H'FEC4 Interrupt Controller
IPRF—Interrupt Priority Register F H'FEC5 Interrupt Controller
IPRG—Interrupt Priority Register G H'FEC6 Interrupt Controller
IPRH—Interrupt Priority Register H H'FEC7 Interrupt Controller
IPRI—Interrupt Priority Register I H'FEC8 Interrupt Controller
IPRJ—Interrupt Priority Register J H 'FEC9 Interrupt Controller
IPRK—Interrupt Priority Register K H'FECA Interrupt Controller
IPRM—Interrupt Priority Register M H'FECC Interrupt Controller
Bit
Initial value
Read/Write
:
:
:
7
—
0
—
6
IPR6
1
R/W
5
IPR5
1
R/W
4
IPR4
1
R/W
3
—
0
—
2
IPR2
1
R/W
1
IPR1
1
R/W
0
IPR0
1
R/W
Register 2 to 0
IRQ1
IRQ4
IRQ5
DTC
—*1
A/D converter, WDT1*2
TPU channel 1
TPU channel 3
TPU channel 5
—*1
SCI channel 0
SCI channel 2
—*1
Interrupt Sources and IPR Settings
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
IPRM
6 to 4
IRQ0
IRQ2
IRQ3
—*1
WDT0
PC break
TPU channel 0
TPU channel 2
TPU channel 4
—*1
—*1
SCI channel 1
HCAN
Bits
Notes: 1. These bits are reserved. They are always read as 1 and cannot be
modified.
2. Valid only in the H8S/2626 Group.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 940 of 1042
REJ09B0275-0500
ABWCR—Bus Width Control Register H'FED0 Bus Controller
Bit
Modes 5 to 7
Initial value
Read/Write
Mode 4
Initial value
Read/Write
:
:
:
:
:
7
ABW7
1
R/W
0
R/W
6
ABW6
1
R/W
0
R/W
5
ABW5
1
R/W
0
R/W
4
ABW4
1
R/W
0
R/W
3
ABW3
1
R/W
0
R/W
2
ABW2
1
R/W
0
R/W
1
ABW1
1
R/W
0
R/W
0
ABW0
1
R/W
0
R/W
0 Area n is designated for 16-bit access
Area n is designated for 8-bit access
Area 7 to 0 bus width control
1(n = 7 to 0)
ASTCR—Access State Control Register H'FED1 Bus Controller
Bit
Initial value
Read/Write
:
:
:
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
1
R/W
0 Area n is designated for 2-state access
Wait state insertion in area n external space access is disabled
Area n is designated for 3-state access
Wait state insertion in area n external space access is enabled
Area 7 to 0 access state control
1
(n = 7 to 0)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 941 of 1042
REJ09B0275-0500
WCRH—Wait Control Register H H'FED2 Bus Controller
Bit
Initial value
Read/Write
:
:
:
7
W71
1
R/W
6
W70
1
R/W
5
W61
1
R/W
4
W60
1
R/W
3
W51
1
R/W
2
W50
1
R/W
1
W41
1
R/W
0
W40
1
R/W
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 4 wait control
1
10
1
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 5 wait control
1
10
1
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 6 wait control
1
10
1
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 7 wait control
1
10
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 942 of 1042
REJ09B0275-0500
WCRL—Wait Control Reg ister L H'FED3 Bus Controller
Bit
Initial value
Read/Write
:
:
:
7
W31
1
R/W
6
W30
1
R/W
5
W21
1
R/W
4
W20
1
R/W
3
W11
1
R/W
2
W10
1
R/W
1
W01
1
R/W
0
W00
1
R/W
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 0 wait control
1
10
1
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 1 wait control
1
10
1
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 2 wait control
1
10
1
0 0 Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
Area 3 wait control
1
10
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 943 of 1042
REJ09B0275-0500
BCRH—Bus Control Register H H'FED4 Bus Controller
Bit
Initial value
Read/Write
:
:
:
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
2
—
0
R/W
1
—
0
R/W
0
—
0
R/W
0 Basic bus interface
Burst ROM interface
Area 0 burst ROM enable
1
0 Idle cycle not inserted in case of successive external read cycles
in different areas
Idle cycle inserted in case of successive external read cycles
in different areas
Idle cycle insert 1
1
0 Idle cycle not inserted in case of successive external read
and external write cycles
Idle cycle inserted in case of successive external read
and external write cycles
Idle cycle insert 0
1
0 Burst cycle comprises 1 state
Burst cycle comprises 2 states
Burst cycle select 1
1
0 Max. 4 words in burst access
Max. 8 words in burst access
Burst cycle select 0
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 944 of 1042
REJ09B0275-0500
BCRL—Bus Control Register L H'FED5 Bus Controller
Bit
Initial value
Read/Write
:
:
:
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
—
0
—
4
—
0
R/W
3
—
1
R/W
2
—
0
R/W
1
WDBE
0
R/W
0
WAITE
0
R/W
0 Wait input by WAIT pin disabled
Wait input by WAIT pin enabled
WAIT pin enable
1
0 Write data buffer function not used
Write data buffer function used
Write data buffer enable
1
0BREQO output disabled
BREQO output enabled
BREQO pin enable
1
0 External bus release disabled
External bus release enabled
Bus release enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 945 of 1042
REJ09B0275-0500
RAMER—RAM Emulation Register*1H'FEDB ROM
Bit
Initial value
Read/Write
:
:
:
7
—
0
R
6
—
0
R
5
—
0
R/W
4
—
0
R/W
3
RAMS
0
R/W
2
RAM2
0
R/W
1
RAM1
0
R/W
0
RAM0
0
R/W
Flash memory area select
0 Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
RAM select
1
Addresses Block Name RAMS RAM2 RAM1 RAM0
H'FFD000–H'FFDFFF RAM area 4 kbytes 0 * * *
H'000000–H'000FFF EB0 (4 kbytes) 1 0 0 0
H'001000–H'001FFF EB1 (4 kbytes) 1 0 0 1
H'002000–H'002FFF EB2 (4 kbytes) 1 0 1 0
H'003000–H'003FFF EB3 (4 kbytes) 1 0 1 1
H'004000–H'004FFF EB4 (4 kbytes) 1 1 0 0
H'005000–H'005FFF EB5 (4 kbytes) 1 1 0 1
H'006000–H'006FFF EB6 (4 kbytes) 1 1 1 0
H'007000–H'007FFF EB7 (4 kbytes) 1 1 1 1
Flash memory area divisions
*: Don't care
Note: 1. This register is present only in the F-ZTAT version; it is not provided in the mask ROM
version.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 946 of 1042
REJ09B0275-0500
P1DR—Port 1 Data Register H'FF00 Port 1
Bit
Initial value
Read/Write
:
:
:
7
P17DR
0
R/W
6
P16DR
0
R/W
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
Stores output data for port 1 pins (P17 to P10)
PADR—Port A Data Register H'FF09 P o rt A
Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
—
6
—
Undefined
—
5
PA5DR*
0
R/W
4
PA4DR*
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
Stores output data for port A pins (PA5 to PA0)
Note: * Reserved bits in the H8S/2626 Group.
PBDR—Port B Data Register H'FF0A Port B
Bit
Initial value
Read/Write
:
:
:
7
PB7DR
0
R/W
6
PB6DR
0
R/W
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
Stores output data for port B pins (PB7 to PB0)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 947 of 1042
REJ09B0275-0500
PCDR—Port C Data Register H'FF0B Port C
Bit
Initial value
Read/Write
:
:
:
7
PC7DR
0
R/W
6
PC6DR
0
R/W
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
Stores output data for port C pins (PC7 to PC0)
PDDR—Port D Data Register H'FF0C Port D
Bit
Initial value
Read/Write
:
:
:
7
PD7DR
0
R/W
6
PD6DR
0
R/W
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
Stores output data for port D pins (PD7 to PD0)
PEDR—Port E Data Register H'FF0D Port E
Bit
Initial value
Read/Write
:
:
:
7
PE7DR
0
R/W
6
PE6DR
0
R/W
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
Stores output data for port E pins (PE7 to PE0)
PFDR—Port F Data Register H'FF0E Port F
Bit
Initial value
Read/Write
:
:
:
7
—
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
Stores output data for port F pins (PF6 to PF0)
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 948 of 1042
REJ09B0275-0500
TCR0—Timer Control Register 0 H'FF10 TPU0
Bit
Initial value
Read/Write
:
:
:
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
Time prescaler
0
1
0
1
0
1
0
1
0
1
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
Input clock edge select
0 0 TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter clear
0
1
10
1
100
1
10
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
*1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
*2
TCNT cleared by TGRD compare match/input capture
*2
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
*1
Note: Internal clock edge selection is valid when the input
clock is φ/4 or slower. This setting is ignored if is φ/1 is
selected as the input clock.
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because
the buffer register setting has priority, and compare match/input capture does not
occur.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 949 of 1042
REJ09B0275-0500
TMDR0—Timer Mode Register 0 H'FF11 TPU0
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
BFB
0
R/W
4
BFA
0
R/W
3
MD3
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
MD0
0
R/W
0 0 Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
Mode
1
1
*
0
1
0
1
*
0
1
0
1
0
1
0
1
*
*: Don’t care
—
Notes: 1. MD3 is a reserved bit.
In a write, it should always be
written with 0.
2. Phase counting mode cannot
be set for channel 0. In this
case, 0 should always be
written to MD2.
0 TGRA operates normally
TGRA and TGRC used together for buffer
operation
Buffer operation setting A
1
0 TGRB operates normally
TGRB and TGRD used together for buffer
operation
Buffer operation setting B
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 950 of 1042
REJ09B0275-0500
TIOR0H—Timer I/O Control Register 0H H'FF12 TPU0
Bit
Initial value
Read/Write
:
:
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
00
TGR0A I/O control
0 0
1
TGR0A
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR0A
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCA0 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
1/count clock
Input capture at TCNT1count-up/
count-down
00
TGR0B I/O control
0 0
1
TGR0B
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR0B
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCB0 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
1/count clock
Input capture at TCNT1 count-up/
count-down
*1
Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as
the TCNT1 count clock, this setting is invalid and input capture is not
generated.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 951 of 1042
REJ09B0275-0500
TIOR0L—Timer I/O Control Register 0L H'FF13 TPU0
Bit
Initial value
Read/Write
:
:
:
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
00
TGR0C I/O control
0 0
1
TGR0C
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR0C
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCC0 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
1/count clock
Input capture at TCNT1 count-up/
count-down
00
TGR0D I/O control
0 0
1
TGR0D
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR0D
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCD0 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is channel
1/count clock
Input capture at TCNT1 count-up/
count-down
*1
Note: When TGR0C or TGR0D is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 952 of 1042
REJ09B0275-0500
TIER0—Timer Interrupt Enable Register 0 H'FF14 TPU0
Bit
Initial value
Read/Write
:
:
:
7
TTGE
0
R/W
6
—
1
—
5
—
0
—
4
TCIEV
0
R/W
3
TGIED
0
R/W
2
TGIEC
0
R/W
1
TGIEB
0
R/W
0
TGIEA
0
R/W
0 Interrupt requests (TGIA)
by TGFA bit disabled
Interrupt requests (TGIA)
by TGFA bit enabled
TGR interrupt enable A
1
0 Interrupt requests (TGIB)
by TGFB bit disabled
Interrupt requests (TGIB)
by TGFB bit enabled
TGR interrupt enable B
1
0 Interrupt requests (TGIC)
by TGFC bit disabled
Interrupt requests (TGIC)
by TGFC bit enabled
TGR interrupt enable C
1
0 Interrupt requests (TGID)
by TGFD bit disabled
Interrupt requests (TGID)
by TGFD bit enabled
TGR interrupt enable D
1
0 Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
Overflow interrupt enable
1
0 A/D conversion start request generation disabled
A/D conversion start request generation enabled
A/D conversion start request enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 953 of 1042
REJ09B0275-0500
TSR0—Timer Status Register 0 H'FF15 TPU0
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
0
—
4
TCFV
0
R/(W)*
3
TGFD
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt, and DISEL
bit in DTC’s MRB is 0
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal while TGRA is functioning as input
capture register
TGRA input capture/output compare flag
1
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt, and DISEL
bit in DTC’s MRB is 0
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
TGRB input capture/output compare flag
1
0 [Clearing conditions]
• When DTC is activated by TGIC interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while
TGRC is functioning as input capture register
TGRC input capture/output compare flag
1
Note: * Can only be written with 0 for flag clearing.
0 [Clearing conditions]
• When DTC is activated by TGID interrupt, and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
TGRD input capture/output compare flag
1
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
Overflow flag
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 954 of 1042
REJ09B0275-0500
TCNT0—Timer Counter 0 H'FF16 TPU0
Bit
Initial value
Read/Write
:
:
:
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Up-counter
TGR0A—Timer General Register 0A H'FF18 TPU0
TGR0B—Timer General Register 0B H'FF1A TPU0
TGR0C—Timer General Register 0C H'FF1C TPU0
TGR0D—Timer General Register 0D H'FF1E TPU0
Bit
Initial value
Read/Write
:
:
:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 955 of 1042
REJ09B0275-0500
TCR1—Timer Control Register 1 H'FF20 TPU1
Bit
Initial value
Read/Write
:
:
:
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
Internal clock: counts on φ/256
Counts on TCNT2 overflow/underflow
Time prescaler
0
1
0
1
0
1
0
1
0
1
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
Input clock edge select
0 TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter clear
0
1
10
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: This setting is invalid when channel 1 is in phase
counting mode.
Note: This setting is invalid when channel 1 is in phase counting
mode, and also when φ/1 or overflow/underflow of another
channel is selected as the input clock.
Note: * Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 956 of 1042
REJ09B0275-0500
TMDR1—Timer Mode Register 1 H'FF21 TPU1
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
MD3
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
MD0
0
R/W
0 0 Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
Mode
1
1
*
0
1
0
1
*
0
1
0
1
0
1
0
1
*
*: Don’t care
—
Note: MD3 is a reserved bit. In a write,
it should always be written with 0.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 957 of 1042
REJ09B0275-0500
TIOR1—Timer I/O Control Register 1 H'FF22 TPU1
Bit
Initial value
Read/Write
:
:
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
00
TGR1A I/O control
0 0
1
TGR1A
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR1A
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCA1 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is TGR0A
compare match/
input capture
Input capture at generation of
channel 0/TGR0A compare match/
input capture
00
TGR1B I/O control
0 0
1
TGR1B
is output
compare
register
10
1
100
1
10
1
01 0 0 TGR1B
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCB1 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
**1 Capture input
source is TGR0C
compare match/
input capture
Input capture at generation of
TGR0C compare match/input
capture
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 958 of 1042
REJ09B0275-0500
TIER1—Timer Interrupt Enable Register 1 H'FF24 TPU1
Bit
Initial value
Read/Write
:
:
:
7
TTGE
0
R/W
6
—
1
—
5
TCIEU
0
R/W
4
TCIEV
0
R/W
3
—
0
—
2
—
0
—
1
TGIEB
0
R/W
0
TGIEA
0
R/W
0 Interrupt requests (TGIA)
by TGFA bit disabled
Interrupt requests (TGIA)
by TGFA bit enabled
TGI interrupt enable A
1
0 Interrupt requests (TGIB)
by TGFB bit disabled
Interrupt requests (TGIB)
by TGFB bit enabled
TGI interrupt enable B
1
0 Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
Overflow interrupt enable
1
0 A/D conversion start request generation disabled
A/D conversion start request generation enabled
A/D conversion start request enable
1
0 Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
Underflow interrupt enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 959 of 1042
REJ09B0275-0500
TSR1—Timer Status Register 1 H'FF25 TPU1
Bit
Initial value
Read/Write
:
:
:
7
TCFD
1
R
6
—
1
—
5
TCFU
0
R/(W)*
4
TCFV
0
R/(W)*
3
—
0
—
2
—
0
—
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFA after reading
TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is
functioning as output compare register
• When TCNT value is transferred to
TGRA by input capture signal while TGRA
is functioning as input capture register
TGR input capture/output compare flag A
1
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFB after reading
TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is
functioning as output compare register
• When TCNT value is transferred to
TGRB by input capture signal while TGRB
is functioning as input capture register
TGR input capture/output compare flag B
1
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
Overflow flag
1
0 [Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Underflow flag
1
0 TCNT counts down
TCNT counts up
Counter direction flag
1
Note: * Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 960 of 1042
REJ09B0275-0500
TCNT1—Timer Counter 1 H'FF26 TPU1
Bit
Initial value
Read/Write
:
:
:
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Up/down-counter*
Note: *This timer counter can be used as an up/down-counter only in phase counting mode or
when performing overflow/underflow counting on another channel. In other cases it
functions as an up-counter.
TGR1A—Timer General Register 1A H'FF28 TPU1
TGR1B—Timer General Register 1B H'FF2A TPU1
Bit
Initial value
Read/Write
:
:
:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 961 of 1042
REJ09B0275-0500
TCR2—Timer Control Register 2 H'FF30 TPU2
Bit
Initial value
Read/Write
:
:
:
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on φ/1024
Time prescaler
0
1
0
1
0
1
0
1
0
1
0
1
—
Count at rising edge
Count at falling edge
Count at both edges
Input clock edge select
0 TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter clear
0
1
10
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: This setting is invalid when channel 2 is in phase
counting mode.
Note: This setting is invalid when channel 2 is in phase
counting mode, and also when φ/1 is selected as
the input clock.
Note: * Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 962 of 1042
REJ09B0275-0500
TMDR2—Timer Mode Register 2 H'FF31 TPU2
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
MD3
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
0
MD0
0
R/W
0 0 Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
Mode
1
1
*
0
1
0
1
*
0
1
0
1
0
1
0
1
*
*: Don’t care
—
Note: MD3 is a reserved bit. In a write,
it should always be written with 0.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 963 of 1042
REJ09B0275-0500
TIOR2—Timer I/O Control Register 2 H'FF32 TPU2
Bit
Initial value
Read/Write
:
:
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
00
TGR2A I/O control
0 0
1
TGR2A
is output
compare
register
10
1
100
1
10
1
*1 0 0 TGR2A
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCA2 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
00
TGR2B I/O control
0 0
1
TGR2B
is output
compare
register
10
1
100
1
10
1
*1 0 0 TGR2B
is input
capture
register
1
1*
Output disabled
Initial output is
1 output
Output disabled
Initial output is
0 output
Capture input
source is
TIOCB2 pin
0 output at compare match
1 output at compare match
Toggle output at compare match
*: Don’t care
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 964 of 1042
REJ09B0275-0500
TIER2—Timer Interrupt Enable Register 2 H'FF34 TPU2
Bit
Initial value
Read/Write
:
:
:
7
TTGE
0
R/W
6
—
1
—
5
TCIEU
0
R/W
4
TCIEV
0
R/W
3
—
0
—
2
—
0
—
1
TGIEB
0
R/W
0
TGIEA
0
R/W
0 Interrupt requests (TGIA)
by TGFA bit disabled
Interrupt requests (TGIA)
by TGFA bit enabled
TGI interrupt enable A
1
0 Interrupt requests (TGIB)
by TGFB bit disabled
Interrupt requests (TGIB)
by TGFB bit enabled
TGI interrupt enable B
1
0 Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
Overflow interrupt enable
1
0 A/D conversion start request generation disabled
A/D conversion start request generation enabled
A/D conversion start request enable
1
0 Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
Underflow interrupt enable
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 965 of 1042
REJ09B0275-0500
TSR2—Timer Status Register 2 H'FF35 TPU2
Bit
Initial value
Read/Write
:
:
:
7
TCFD
1
R
6
—
1
—
5
TCFU
0
R/(W)*
4
TCFV
0
R/(W)*
3
—
0
—
2
—
0
—
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFA after reading
TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is
functioning as output compare register
• When TCNT value is transferred to
TGRA by input capture signal while TGRA
is functioning as input capture register
TGR input capture/output compare flag A
1
0 [Clearing conditions]
• When DTC is activated by TGIB interrupt,
and DISEL bit in DTC’s MRB is 0
• When 0 is written to TGFB after reading
TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is
functioning as output compare register
• When TCNT value is transferred to
TGRB by input capture signal while TGRB
is functioning as input capture register
TGR input capture/output compare flag B
1
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000)
Overflow flag
1
0 [Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Underflow flag
1
0 TCNT counts down
TCNT counts up
Counter direction flag
1
Note: * Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 966 of 1042
REJ09B0275-0500
TCNT2—Timer Counter 2 H'FF36 TPU2
Bit
Initial value
Read/Write
:
:
:
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Up/down-counter*
Note: *This timer counter can be used as an up/down-counter only in phase counting mode or
when performing overflow/underflow counting on another channel. In other cases it
functions as an up-counter.
TGR2A—Timer General Register 2A H'FF38 TPU2
TGR2B—Timer General Register 2B H'FF3A TPU2
Bit
Initial value
Read/Write
:
:
:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 967 of 1042
REJ09B0275-0500
TCSR0—Timer Control/Status Register 0 H'FF74 (W), H'FF74 (R) WDT0
Bit
Initial value
Read/Write
:
:
:
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
—
1
—
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
CKS2
Clock select
0
1
Clock
φ/2 (Initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
CKS2
0
1
0
1
CKS2
0
1
0
1
0
1
0
1
Overflow Period*
(when ø = 20 MHz)
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
0 TCNT is initialized to H'00 and halted
TCNT counts
Timer enable
1
Note: * The overflow period is the time from when TCNT
starts counting up until overflow occurs.
0 Interval timer mode: Sends the CPU an interval timer interrupt request
(WOVI) when TCNT overflows
Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows*
Timer mode select
1
0 [Clearing conditions]
When 0 is written to OVF after reading TCSR when OVF = 1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset
Overflow flag
1
Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 12.2.5, Notes on register access.
* Can only be written with 0 for flag clearing.
Note: * For details of the case where TCNT overflows in watchdog timer mode,
see section 12.2.3, Reset Control/Status Register (RSTCSR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 968 of 1042
REJ09B0275-0500
TCNT0—Timer Counter 0 H'FF74 (W), H'FF75 (R) WDT
Bit
Initial value
Read/Write
:
:
:
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Note: TCNT is write-protected by a password to prevent accidental overwriting. For details see
section 12.2.5, Notes on Register Access.
RSTCSR—Reset Control/Status Register H'FF76 (W), H'FF77 (R) WDT
Bit
Initial value
Read/Write
:
:
:
7
WOVF
0
R/(W)*
6
RSTE
0
R/W
5
RSTS
0
R/W
4
—
1
—
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
0 Power-on reset
Setting prohibited
Reset select
1
0 Internal reset is not performed when TCNT overflows*
Internal reset is performed when TCNT overflows
Reset enable
1
Note: *The modules within the chip are not reset, but TCNT and
TCSR within the WDT are reset.
0 [Clearing condition]
When 0 is written to WOVF after reading TCSR when WOVF = 1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00) in watchdog timer mode
Watchdog overflow flag
1
Notes: RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 12.2.5, Notes on Register Access.
* Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 969 of 1042
REJ09B0275-0500
SMR0—Serial Mode Register 0 H'FF78 SCI0
Bit
Initial value
Read/Write
:
:
:
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
00φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock select
1
10
1
0 Multiprocessor function disabled
Multiprocessor format selected
Multiprocessor mode
1
0 1 stop bit
2 stop bits
Stop bit length
1
0 Even parity
*1
Odd parity*2
Parity mode
1
0 Parity bit addition and checking disabled
Parity bit addition and checking enabled*
Parity enable
1
0 8-bit data
7-bit data*
Character length
1
0 Asynchronous mode
Synchronous mode
Asynchronous mode/synchronous mode select
1
Notes: 1. When even parity is set, parity bit addition is performed
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is even.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is even.
2. When odd parity is set, parity bit addition is performed
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is odd.
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the
O/E bit is added to transmit data before transmission. In reception, the
parity bit is checked for the parity (even or odd) specified by the O/E bit.
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 970 of 1042
REJ09B0275-0500
SMR0—Serial Mode Register 0 H'FF78 Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
GM
0
R/W
6
BLK
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
BCP1
0
R/W
2
BCP0
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
00φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock select
1
10
1
0 Even parity
*1
Odd parity
*2
Parity mode
1
0 Parity bit addition and checking disabled
Parity bit addition and checking enabled
Parity enable
1
0 Normal smart card interface mode operation
• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode operation
• Error signal transmission/detection and automatic data retransmission not performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode
1
0 Normal smart card interface mode operation
• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output on/off control only
GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output on/off control (set by SCR)
GSM mode
1
Note:
0 0 32 clock periods
64 clock periods
372 clock periods
256 clock periods
Basic clock pulse
1
10
1
etu: Elementary Time Unit (time for transfer of 1 bit)
Notes: 1. When even parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is even.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is odd.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is odd.
Note: When the smart card interface is used, be sure to make the 1 setting.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 971 of 1042
REJ09B0275-0500
BRR0—Bit Rate Register 0 H'FF79 SCI0, Sma rt Card Interface
Bit
Initial value
Read/Write
:
:
:
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Sets the serial transmit/receive bit rate
Note: For details see section 13.2.8, Bit Rate Register (BRR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 972 of 1042
REJ09B0275-0500
SCR0—Serial Control Register 0 H'FF7A SCI0
Bit
Initial value
Read/Write
:
:
:
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
0 Asynchronous
mode
Synchronous
mode
Clock enable
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
1
Synchronous
mode
Asynchronous
mode
Synchronous
mode
0
0
1
1
Internal clock/SCK pin functions as
I/O port
Internal clock/SCK pin functions as
serial clock output
Internal clock/SCK pin functions as
clock output
*1
Internal clock/SCK pin functions as
serial clock output
External clock/SCK pin functions as
clock input
*2
External clock/SCK pin functions as
serial clock input
External clock/SCK pin functions as
clock input
*2
External clock/SCK pin functions as
serial clock input
0 Transmit end interrupt (TEI) request disabled
Transmit end interrupt (TEI) request enabled
Transmit end interrupt enable
1
Notes: 1.
2.
0 Reception disabled
Reception enabled
Receive enable
1
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in SSR are
disabled until data with the multiprocessor bit set to 1 is received
Multiprocessor interrupt enable
1
0 Transmission disabled
Transmission enabled
Transmit enable
1
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Receive interrupt enable
1
0 Transmit data empty interrupt (TXI) request disabled
Transmit data empty interrupt (TXI) request enabled
Transmit interrupt enable
1
Outputs a clock of the same frequency as the bit rate.
Inputs a clock with a frequency 16 times the bit rate.
Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 973 of 1042
REJ09B0275-0500
SCR0—Serial Control Register 0 H'FF7A Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
SCMR SCK Pin Function
See the SCI specification
Clock enable
SMIF
0
1
C/A, GM
0
1
CKE1
0
1
CKE0
0
1
0
1
0
1
SMR SCR Setting
Operates as port I/O pin
Outputs clock as SCK
output pin
Operates as SCK output
pin, with output fixed low
Outputs clock as SCK
output pin
Operates as SCK output
pin, with output fixed high
Outputs clock as SCK
output pin
0 Transmit end interrupt (TEI) request disabled
Transmit end interrupt (TEI) request enabled
Transmit end interrupt enable
1
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to
1 is received
Multiprocessor interrupt enable
1
0 Reception disabled
Reception enabled
Receive enable
1
0 Transmission disabled
Transmission enabled
Transmit enable
1
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Receive interrupt enable
1
0 Transmit data empty interrupt (TXI) request disabled
Transmit data empty interrupt (TXI) request enabled
Transmit interrupt enable
1
Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 974 of 1042
REJ09B0275-0500
TDR0—Transmit Data Register 0 H'FF7B SCI0, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Stores data for serial transmission
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 975 of 1042
REJ09B0275-0500
SSR0—Serial Stat us Register 0 H'FF7C SCI0
Bit
Initial value
Read/Write
:
:
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
0
Data with a 0 multiprocessor
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor bit transfer
1
0
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Multiprocessor bit
1
0
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Transmit end
1
0
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data
plus the parity bit does not match the parity setting (even or
odd) specified by the O/E bit in SMR
Parity error
1
0
[Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0
Framing error
1
0
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Overrun error
1
0
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Receive data register full
1
0
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Transmit data register empty
1
Notes: For details, see section 13.2.7, Serial Status Register (SSR).
*
Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 976 of 1042
REJ09B0275-0500
SSR0—Serial Status Register 0 H'FF7C Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
0 Data with a 0 multiprocessor
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor bit transfer
1
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Multiprocessor bit
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 1
Transmit end
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Transmit data register empty
1
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Receive data register full
1
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Overrun error
1
0 [Clearing conditions]
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
[Setting condition]
When the low level of the error signal is sampled
Error signal status
1
Note:
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by
the O/E bit in SMR
Parity error
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Clearing the TE bit in SCR to 0 does not affect the ERS flag,
which retains its previous state.
Notes: For details, see section 14.2.2, Serial Status Register (SSR).
* Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 977 of 1042
REJ09B0275-0500
RDR0—Receive Data Register 0 H'FF7D SCI0, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
Stores received serial data
SCMR0—Smart Card Mode Register 0 H 'FF7E SCI0, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
2
SINV
0
R/W
1
—
1
—
0
SMIF
0
R/W
0 Smart card interface
function is disabled
Smart card interface
function is enabled
Smart card interface
mode select
1
0 TDR contents are transmitted as they are
Receive data is stored as it is in RDR
TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
Smart card data invert
1
0 TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Smart card data transfer direction
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 978 of 1042
REJ09B0275-0500
SMR1—Serial Mode Register 1 H'FF80 SCI1
Bit
Initial value
Read/Write
:
:
:
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
00φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock select
1
10
1
0 Multiprocessor function disabled
Multiprocessor format selected
Multiprocessor mode
1
0 1 stop bit
2 stop bits
Stop bit length
1
0 Even parity
*1
Odd parity*2
Parity mode
1
0 Parity bit addition and checking disabled
Parity bit addition and checking enabled*
Parity enable
1
0 8-bit data
7-bit data*
Character length
1
0 Asynchronous mode
Synchronous mode
Asynchronous mode/synchronous mode select
1
Notes: 1. When even parity is set, parity bit addition is performed
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is even.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is even.
2. When odd parity is set, parity bit addition is performed
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is odd.
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the
O/E bit is added to transmit data before transmission. In reception, the
parity bit is checked for the parity (even or odd) specified by the O/E bit.
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 979 of 1042
REJ09B0275-0500
SMR1—Serial Mode Register 1 H'FF80 Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
GM
0
R/W
6
BLK
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
BCP1
0
R/W
2
BCP0
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
00φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock select
1
10
1
0 Even parity
*1
Odd parity
*2
Parity mode
1
0 Parity bit addition and checking disabled
Parity bit addition and checking enabled
Parity enable
1
0 Normal smart card interface mode operation
• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode operation
• Error signal transmission/detection and automatic data retransmission not performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode
1
0 Normal smart card interface mode operation
• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output on/off control only
GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output on/off control (set by SCR)
GSM mode
1
Note:
0 0 32 clock periods
64 clock periods
372 clock periods
256 clock periods
Basic clock pulse
1
10
1
etu: Elementary Time Unit (time for transfer of 1 bit)
Notes: 1. When even parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is even.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is odd.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is odd.
Note: When the smart card interface is used, be sure to make the 1 setting.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 980 of 1042
REJ09B0275-0500
BRR1—Bit Rate Register 1 H'FF81 SCI1, Sma rt Card Interface
Bit
Initial value
Read/Write
:
:
:
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Sets the serial transmit/receive bit rate
Note: For details see section 13.2.8, Bit Rate Register (BRR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 981 of 1042
REJ09B0275-0500
SCR1—Serial Control Register 1 H'FF82 SCI1
Bit
Initial value
Read/Write
:
:
:
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
0 Asynchronous
mode
Synchronous
mode
Clock enable
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
1
Synchronous
mode
Asynchronous
mode
Synchronous
mode
0
0
1
1
Internal clock/SCK pin functions as
I/O port
Internal clock/SCK pin functions as
serial clock output
Internal clock/SCK pin functions as
clock output
*1
Internal clock/SCK pin functions as
serial clock output
External clock/SCK pin functions as
clock input
*2
External clock/SCK pin functions as
serial clock input
External clock/SCK pin functions as
clock input
*2
External clock/SCK pin functions as
serial clock input
0 Transmit end interrupt (TEI) request disabled
Transmit end interrupt (TEI) request enabled
Transmit end interrupt enable
1
Notes: 1.
2.
0 Reception disabled
Reception enabled
Receive enable
1
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in SSR are
disabled until data with the multiprocessor bit set to 1 is received
Multiprocessor interrupt enable
1
0 Transmission disabled
Transmission enabled
Transmit enable
1
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Receive interrupt enable
1
0 Transmit data empty interrupt (TXI) request disabled
Transmit data empty interrupt (TXI) request enabled
Transmit interrupt enable
1
Outputs a clock of the same frequency as the bit rate.
Inputs a clock with a frequency 16 times the bit rate.
Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 982 of 1042
REJ09B0275-0500
SCR1—Serial Control Register 1 H'FF82 Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
SCMR SCK Pin Function
See the SCI specification
Clock enable
SMIF
0
1
C/A, GM
0
1
CKE1
0
1
CKE0
0
1
0
1
0
1
SMR SCR Setting
Operates as port I/O pin
Outputs clock as SCK
output pin
Operates as SCK output
pin, with output fixed low
Outputs clock as SCK
output pin
Operates as SCK output
pin, with output fixed high
Outputs clock as SCK
output pin
0 Transmit end interrupt (TEI) request disabled
Transmit end interrupt (TEI) request enabled
Transmit end interrupt enable
1
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set
to 1 is received
Multiprocessor interrupt enable
1
0 Reception disabled
Reception enabled
Receive enable
1
0 Transmission disabled
Transmission enabled
Transmit enable
1
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Receive interrupt enable
1
0 Transmit data empty interrupt (TXI) request disabled
Transmit data empty interrupt (TXI) request enabled
Transmit interrupt enable
1
Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 983 of 1042
REJ09B0275-0500
TDR1—Transmit Data Register 1 H'FF83 SCI1, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Stores data for serial transmission
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 984 of 1042
REJ09B0275-0500
SSR1—Serial Stat us Register 1 H 'F F 84 SCI
Bit
Initial value
Read/Write
:
:
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
0 Data with a 0 multiprocessor
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor bit transfer
1
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Multiprocessor bit
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Transmit end
1
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data
plus the parity bit does not match the parity setting (even or
odd) specified by the O/E bit in SMR
Parity error
1
0 [Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0
Framing error
1
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Overrun error
1
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Receive data register full
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Transmit data register empty
1
Notes: For details, see section 13.2.7, Serial Status Register (SSR).
*
Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 985 of 1042
REJ09B0275-0500
SSR1—Serial Status Register 1 H'FF84 Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
0 Data with a 0 multiprocessor
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor bit transfer
1
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Multiprocessor bit
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 1
Transmit end
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Transmit data register empty
1
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Receive data register full
1
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Overrun error
1
0 [Clearing conditions]
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
[Setting condition]
When the low level of the error signal is sampled
Error signal status
1
Note:
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by
the O/E bit in SMR
Parity error
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Clearing the TE bit in SCR to 0 does not affect the ERS flag,
which retains its previous state.
Notes: For details, see section 14.2.2, Serial Status Register (SSR).
* Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 986 of 1042
REJ09B0275-0500
RDR1—Receive Data Register 1 H'FF85 SCI, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
Stores received serial data
SCMR1—Smart Card Mode Register 1 H'FF86 SCI, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
2
SINV
0
R/W
1
—
1
—
0
SMIF
0
R/W
0 Smart card interface
function is disabled
Smart card interface
function is enabled
Smart card interface
mode select
1
0 TDR contents are transmitted as they are
Receive data is stored as it is in RDR
TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
Smart card data invert
1
0 TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Smart card data transfer direction
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 987 of 1042
REJ09B0275-0500
SMR2—Serial Mode Register 2 H'FF88 SCI
Bit
Initial value
Read/Write
:
:
:
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
00φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock select
1
10
1
0 Multiprocessor function disabled
Multiprocessor format selected
Multiprocessor mode
1
0 1 stop bit
2 stop bits
Stop bit length
1
0 Even parity
*1
Odd parity*2
Parity mode
1
0 Parity bit addition and checking disabled
Parity bit addition and checking enabled*
Parity enable
1
0 8-bit data
7-bit data*
Character length
1
0 Asynchronous mode
Synchronous mode
Asynchronous mode/synchronous mode select
1
Notes: 1. When even parity is set, parity bit addition is performed
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is even.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is even.
2. When odd parity is set, parity bit addition is performed
in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total
number of 1 bits in the receive character plus the parity
bit is odd.
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the
O/E bit is added to transmit data before transmission. In reception, the
parity bit is checked for the parity (even or odd) specified by the O/E bit.
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 988 of 1042
REJ09B0275-0500
SMR2—Serial Mode Register 2 H'FF88 Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
GM
0
R/W
6
BLK
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
BCP1
0
R/W
2
BCP0
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
00φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Clock select
1
10
1
0 Even parity
*1
Odd parity
*2
Parity mode
1
0 Parity bit addition and checking disabled
Parity bit addition and checking enabled
Parity enable
1
0 Normal smart card interface mode operation
• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode operation
• Error signal transmission/detection and automatic data retransmission not performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode
1
0 Normal smart card interface mode operation
• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output on/off control only
GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/low fixing control possible in addition to clock output on/off control (set by SCR)
GSM mode
1
Note:
0 0 32 clock periods
64 clock periods
372 clock periods
256 clock periods
Basic clock pulse
1
10
1
etu: Elementary Time Unit (time for transfer of 1 bit)
Notes: 1. When even parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is even.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is odd.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is odd.
Note: When the smart card interface is used, be sure to make the 1 setting.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 989 of 1042
REJ09B0275-0500
BRR2—Bit Rate Register 2 H'FF89 SCI, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Sets the serial transmit/receive bit rate
Note: For details see section 13.2.8, Bit Rate Register (BRR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 990 of 1042
REJ09B0275-0500
SCR2—Serial Control Register 2 H'FF8A SCI
Bit
Initial value
Read/Write
:
:
:
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
0 Asynchronous
mode
Synchronous
mode
Clock enable
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
1
Synchronous
mode
Asynchronous
mode
Synchronous
mode
0
0
1
1
Internal clock/SCK pin functions as
I/O port
Internal clock/SCK pin functions as
serial clock output
Internal clock/SCK pin functions as
clock output
*1
Internal clock/SCK pin functions as
serial clock output
External clock/SCK pin functions as
clock input
*2
External clock/SCK pin functions as
serial clock input
External clock/SCK pin functions as
clock input
*2
External clock/SCK pin functions as
serial clock input
0 Transmit end interrupt (TEI) request disabled
Transmit end interrupt (TEI) request enabled
Transmit end interrupt enable
1
Notes: 1.
2.
0 Reception disabled
Reception enabled
Receive enable
1
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in SSR are
disabled until data with the multiprocessor bit set to 1 is received
Multiprocessor interrupt enable
1
0 Transmission disabled
Transmission enabled
Transmit enable
1
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Receive interrupt enable
1
0 Transmit data empty interrupt (TXI) request disabled
Transmit data empty interrupt (TXI) request enabled
Transmit interrupt enable
1
Outputs a clock of the same frequency as the bit rate.
Inputs a clock with a frequency 16 times the bit rate.
Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 991 of 1042
REJ09B0275-0500
SCR2—Serial Control Register 2 H'FF8A Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
0
CKE0
0
R/W
SCMR SCK Pin Function
See the SCI specification
Clock enable
SMIF
0
1
C/A, GM
0
1
CKE1
0
1
CKE0
0
1
0
1
0
1
SMR SCR Setting
Operates as port I/O pin
Outputs clock as SCK
output pin
Operates as SCK output
pin, with output fixed low
Outputs clock as SCK
output pin
Operates as SCK output
pin, with output fixed high
Outputs clock as SCK
output pin
0 Transmit end interrupt (TEI) request disabled
Transmit end interrupt (TEI) request enabled
Transmit end interrupt enable
1
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set
to 1 is received
Multiprocessor interrupt enable
1
0 Reception disabled
Reception enabled
Receive enable
1
0 Transmission disabled
Transmission enabled
Transmit enable
1
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Receive interrupt enable
1
0 Transmit data empty interrupt (TXI) request disabled
Transmit data empty interrupt (TXI) request enabled
Transmit interrupt enable
1
Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR).
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 992 of 1042
REJ09B0275-0500
TDR2—Transmit Data Register 2 H'FF8B SCI, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Stores data for serial transmission
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 993 of 1042
REJ09B0275-0500
SSR2—Serial Stat us Register 2 H 'F F 8C SCI
Bit
Initial value
Read/Write
:
:
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
0 Data with a 0 multiprocessor
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor bit transfer
1
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Multiprocessor bit
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Transmit end
1
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
Parity error
1
0 [Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0
Framing error
1
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Overrun error
1
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Receive data register full
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Transmit data register empty
1
Notes: For details, see section 13.2.7, Serial Status Register (SSR).
* Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 994 of 1042
REJ09B0275-0500
SSR2—Serial Status Register 2 H'FF8C Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
0 Data with a 0 multiprocessor
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor bit transfer
1
0 [Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Multiprocessor bit
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 1 and BLK = 1
Transmit end
1
0 [Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Transmit data register empty
1
0 [Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Receive data register full
1
0 [Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Overrun error
1
0 [Clearing conditions]
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
[Setting condition]
When the low level of the error signal is sampled
Error signal status
1
Note:
0 [Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by
the O/E bit in SMR
Parity error
1
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Clearing the TE bit in SCR to 0 does not affect the ERS flag,
which retains its previous state.
Notes: For details, see section 14.2.2, Serial Status Register (SSR).
* Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 995 of 1042
REJ09B0275-0500
RDR2—Receive Data Register 2 H'FF8D SCI, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
Stores received serial data
SCMR2—Smart Card Mode Register 2 H'FF8E SCI, Smart Card Interface
Bit
Initial value
Read/Write
:
:
:
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
2
SINV
0
R/W
1
—
1
—
0
SMIF
0
R/W
0 Smart card interface
function is disabled
Smart card interface
function is enabled
Smart card interface
mode select
1
0 TDR contents are transmitted as they are
Receive data is stored as it is in RDR
TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
Smart card data invert
1
0 TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Smart card data transfer direction
1
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 996 of 1042
REJ09B0275-0500
ADDRA—A/D Data Register A H'FF90 A/D Converter
ADDRB—A/D Data Register B H 'FF92 A/D Converter
ADDRC—A/D Data Register C H'FF94 A/D Converter
ADDRD—A/D Data Register D H'FF96 A/D Converter
Bit
Initial value
Read/Write
:
:
:
15
AD9
0
R
14
AD8
0
R
13
AD7
0
R
12
AD6
0
R
11
AD5
0
R
10
AD4
0
R
9
AD3
0
R
8
AD2
0
R
7
AD1
0
R
6
AD0
0
R
5
—
0
R
4
—
0
R
3
—
0
R
2
—
0
R
1
—
0
R
0
—
0
R
Analog Input Channel
Channel Set 0 (CH3 = 0)
Group 0 Group 1 Group 0 Group 1
Channel Set 1 (CH3 = 1) A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Analog input channels and corresponding ADDR registers
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
Note: The upper byte can be read directly, but for the lower byte, data transfer is performed via
a temporary register (TEMP). For details see section 16.3, Interface to Bus Master.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 997 of 1042
REJ09B0275-0500
ADCSR—A/D Control/Sta tus Reg ister H'FF98 A/D Converter
Bit
Initial value
Read/Write
:
:
:
7
ADF
0
R/W*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CH3
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
CH3
Channel select
CH2 CH1 CH0
AN0 (Initial value)
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
AN8
AN8, AN9
AN8 to AN10
AN8 to AN11
AN12
AN12, AN13
AN12 to AN14
AN12 to AN15
Single Mode
(SCAN = 0) Scan Mode
(SCAN = 1)
0 AN8 to AN11 are group 0 analog input pins, AN12 to AN15
are group 1 analog input pins
AN0 to AN3 are group 0 analog input pins, AN4 to AN7
are group 1 analog input pins
Channel select
1
0 Single mode
Scan mode
Scan mode
1
0 A/D conversion stopped
• Single mode: A/D conversion is started. Cleared to 0 automatically when
conversion on the specified channel ends
• Scan mode: A/D conversion is started. Conversion continues consecutively
on the selected channels until ADST is cleared to 0 by software, a reset,
or a transition to standby mode or module stop mode
A/D start
1
0 A/D conversion end interrupt (ADI) request disabled
A/D conversion end interrupt (ADI) request enabled
A/D interrupt enable
1
0 [Clearing conditions]
• When 0 is written to ADF after reading ADF = 1
• When the DTC is activated by an ADI interrupt and ADDR is read
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
A/D end flag
1
Note: * Can only be written with 0 for flag clearing.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 998 of 1042
REJ09B0275-0500
ADCR—A/D Control Register H'FF99 A/D Converter
Bit
Initial value
Read/Write
:
:
:
7
TRGS1
0
R/W
6
TRGS0
0
R/W
5
—
1
—
4
—
1
—
3
CKS1
0
R/W
2
CKS0
0
R/W
1
—
1
—
0
—
1
—
0 0 Conversion time = 530 states (max.)
Conversion time = 266 states (max.)
Conversion time = 134 states (max.)
Conversion time = 68 states (max.)
Clock select
1
10
1
0 0 A/D conversion start by software is enabled
A/D conversion start by TPU conversion start trigger is enabled
Timer trigger select
1
10
1Setting prohibited
A/D conversion start by external trigger pin (ADTRG) is enabled
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 999 of 1042
REJ09B0275-0500
TCSR1—Timer Co nt rol/Status Register 1*2H'FFA2 WDT1
7
OVF
0
R/(W)
*1
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Clock select 2 to 0
0
1
Overflow cycle*
(when φ = 20 MHz)
(when φSUB = 32.768 kHz)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
Reset or NMI
0NMI interrupt request
1 Internal reset request
Prescaler select
0TCNT counts the divided clock output by the ø-based prescaler
1 TCNT counts the divided clock output by the øSUB-based prescaler (PSS)
Timer enable
0Initializes TCNT to H’00 and disables the counting operation
1TCNT performs counting operation
Timer mode select
0Interval timer mode: Interval timer interrupt (WOVI) request sent to CPU
when overflow occurs at TCNT
1 Watchdog timer mode: Reset or NMI interrupt request sent to CPU when
overflow occurs at TCNT
Overflow flag
0[Clearing]
(1) When 0 is written to TME bit;
(2) When 0 is written to OVF bit after reading TCSR when OVF=1.
1[Setting]
When TCNT overflows (H'FF→ H'00).
When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.
PSS CKS2 CKS1 CKS0 Clock
Note: * The overflow cycle starts when TCNT starts counting from
H'00 and ends when an overflow occurs.
Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access.
1. Only 0 can be written to these bits (to clear these flags).
2. This register is not available, and must not be accessed, in the H8S/2623 Group.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1000 of 1042
REJ09B0275-0500
TCNT1—Timer Counter 1*H'FFA2 (W), H'FFA3 (R) WDT1
Bit
Initial value
Read/Write
:
:
:
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Notes: TCNT1 is write-protected by a password to prevent accidental overwriting.
For details see section 12.2.5, Notes on Register Access.
* This register is not available, and must not be accessed, in the H8S/2623 Group.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1001 of 1042
REJ09B0275-0500
FLMCR1—Flash Memory Control Register 1 H'FFA8 ROM
Bit
Initial value
Read/Write
:
:
:
7
FWE
—*
R
6
SWE1
0
R/W
5
ESU1
0
R/W
4
PSU1
0
R/W
3
EV1
0
R/W
2
PV1
0
R/W
1
E1
0
R/W
0
P1
0
R/W
0 Program mode cleared
Transition to program mode
[Setting condition]
When FWE = 1, SWE1 = 1,
and PSU1 = 1
Program 1
1
0 Erase mode cleared
Transition to erase mode
[Setting condition]
When FWE = 1, SWE1 = 1,
and ESU1 = 1
Erase 1
1
0 Program-verify mode cleared
Transition to program-verify mode
[Setting condition]
When FWE = 1 and SWE1 = 1
Program-verify 1
1
0 Erase-verify mode cleared
Transition to erase-verify mode
[Setting condition]
When FWE = 1 and SWE1 = 1
Erase-verify 1
1
0 Program setup cleared
Program setup
[Setting condition]
When FWE = 1 and SWE1 = 1
Program setup bit 1
1
0 Erase setup cleared
Erase setup
[Setting condition]
When FWE = 1 and SWE1 = 1
Erase setup bit 1
1
0 Writes disabled
Writes enabled
[Setting condition]
When FWE = 1
Software write enable bit 1
1
0 When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
Flash write enable bit
1
Notes: 1. This register is not present in the mask ROM version, and an attempt to read it will return an undefined value.
2. To access this register, set the FLSHE bit to 1 in serial control register X (SCRX). Even if FLSHE = 1, if the chip
is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes
to this register are also invalid when the FWE bit in FLMCR1 is not set to 1.
Note: * Determined by the state of the FWE pin.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1002 of 1042
REJ09B0275-0500
FLMCR2—Flash Memory Control Register 2 H'FFA9 ROM
Bit
Initial value
Read/Write
:
:
:
7
FLER
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
2
—
0
—
1
—
0
—
0
—
0
—
0 Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 19.8.3, Error Protection
Flash memory error
1
Notes: 1. This register is not present in the mask ROM version, and an
attempt to read it will return an undefined value.
2. To access this register, set the FLSHE bit to 1 in serial control
register X (SCRX). Even if FLSHE = 1, if the chip is in a mode
in which the on-chip flash memory is disabled, a read will return
H'00 and writes are invalid. Writes to this register are also
invalid when the FWE bit in FLMCR1 is not set to 1.
EBR1—Erase Block Register 1 H'FFAA ROM
Bit
Initial value
Read/Write
:
:
:
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
0
EB0
0
R/W
Sets flash memory erase area block by block
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1003 of 1042
REJ09B0275-0500
EBR2—Erase Block Register 2 H'FFAB ROM
Bit
Initial value
Read/Write
:
:
:
7
—
0
R/W
6
—
0
R/W
5
—
0
R/W
4
—
0
R/W
3
EB11
0
R/W
2
EB10
0
R/W
1
EB9
0
R/W
0
EB8
0
R/W
Sets flash memory erase area block by bloc
k
EB0 (4 kbytes) H'000000–H'000FFF
EB1 (4 kbytes) H'001000–H'001FFF
EB2 (4 kbytes) H'002000–H'002FFF
EB3 (4 kbytes) H'003000–H'003FFF
EB4 (4 kbytes) H'004000–H'004FFF
EB5 (4 kbytes) H'005000–H'005FFF
EB6 (4 kbytes) H'006000–H'006FFF
EB7 (4 kbytes) H'007000–H'007FFF
EB8 (32 kbytes) H'008000–H'00FFFF
EB9 (64 kbytes) H'010000–H'01FFFF
EB10 (64 kbytes) H'020000–H'02FFFF
EB11 (64 kbytes) H'030000–H'03FFFF
Flash memory erase blocks AddressesBlock (Size)
Notes: 1. This register is not present in the mask ROM version, and an
attempt to read it will return an undefined value.
2. To access this register, set the FLSHE bit to 1 in serial control
register X (SCRX). Even if FLSHE = 1, if the chip is in a mode
in which the on-chip flash memory is disabled, a read will return
H'00 and writes are invalid. Writes to this register are also
invalid when the FWE bit in FLMCR1 is not set to 1.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1004 of 1042
REJ09B0275-0500
FLPWCR—Flash Memory Power Control Register H'FFAC ROM
Bit
Initial value
Read/Write
:
:
:
7
PDWND
0
R/W
6
—
0
R
5
—
0
R
4
—
0
R
3
—
0
R
2
—
0
R
1
—
0
R
0
—
0
R
0 Transition to flash memory power-down mode enabled
Power-down disable
1 Transition to flash memory power-down mode disabled
PORT1—Port 1 Register H'FFB0 Port 1
Bit
Initial value
Read/Write
:
:
:
7
P17
—*
R
6
P16
—*
R
5
P15
—*
R
4
P14
—*
R
3
P13
—*
R
2
P12
—*
R
1
P11
—*
R
0
P10
—*
R
State of port 1 pins
Note: * Determined by the state of pins P17 to P10.
PORT4—Port 4 Register H'FFB3 Port 4
Bit
Initial value
Read/Write
:
:
:
7
P47
—*
R
6
P46
—*
R
5
P45
—*
R
4
P44
—*
R
3
P43
—*
R
2
P42
—*
R
1
P41
—*
R
0
P40
—*
R
State of port 4 pins
Note: * Determined by the state of pins P47 to P40.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1005 of 1042
REJ09B0275-0500
PORT9—Port 9 Register H'FFB8 Port 9
Bit
Initial value
Read/Write
:
:
:
7
P97
—*
R
6
P96
—*
R
5
P95
—*
R
4
P94
—*
R
3
P93
—*
R
2
P92
—*
R
1
P91
—*
R
0
P90
—*
R
State of port 9 pins
Note: * Determined by the state of pins P97 to P90.
PORTA—Port A Register H'FFB9 Port A
Bit
Initial value
Read/Write
:
:
:
7
—
Undefined
—
6
—
Undefined
—
5
PA5
*2
—
*1
R
4
PA4
*2
—
*1
R
3
PA3
—
*1
R
2
PA2
—
*1
R
1
PA1
—
*1
R
0
PA0
—
*1
R
State of port A pins
Notes: 1. Determined by the state of pins PA5 to PA0.
2. Reserved bits in the H8S/2626 Group.
PORTB—Port B Register H'FFBA Port B
Bit
Initial value
Read/Write
:
:
:
7
PB7
—*
R
6
PB6
—*
R
5
PB5
—*
R
4
PB4
—*
R
3
PB3
—*
R
2
PB2
—*
R
1
PB1
—*
R
0
PB0
—*
R
State of port B pins
Note: * Determined by the state of pins PB7 to PB0.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1006 of 1042
REJ09B0275-0500
PORTC—Port C Register H'FFBB Port C
Bit
Initial value
Read/Write
:
:
:
7
PC7
—*
R
6
PC6
—*
R
5
PC5
—*
R
4
PC4
—*
R
3
PC3
—*
R
2
PC2
—*
R
1
PC1
—*
R
0
PC0
—*
R
State of port C pins
Note: * Determined by the state of pins PC7 to PC0.
PORTD—Port D Register H'FFBC Port D
Bit
Initial value
Read/Write
:
:
:
7
PD7
—*
R
6
PD6
—*
R
5
PD5
—*
R
4
PD4
—*
R
3
PD3
—*
R
2
PD2
—*
R
1
PD1
—*
R
0
PD0
—*
R
State of port D pins
Note: * Determined by the state of pins PD7 to PD0.
PORTE—Port E Register H'FFBD P ort E
Bit
Initial value
Read/Write
:
:
:
7
PE7
—*
R
6
PE6
—*
R
5
PE5
—*
R
4
PE4
—*
R
3
PE3
—*
R
2
PE2
—*
R
1
PE1
—*
R
0
PE0
—*
R
State of port E pins
Note: * Determined by the state of pins PE7 to PE0.
Appendix B Internal I/O Register
Rev. 5.00 Jan 10, 2006 page 1007 of 1042
REJ09B0275-0500
PORTF—Port F Register H'FFBE Port F
Bit
Initial value
Read/Write
:
:
:
7
PF7
—*
R
6
PF6
—*
R
5
PF5
—*
R
4
PF4
—*
R
3
PF3
—*
R
2
PF2
—*
R
1
PF1
—*
R
0
PF0
—*
R
State of port F pins
Note: * Determined by the state of pins PF7 to PF0.
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1008 of 1042
REJ09B0275-0500
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagrams
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1n *
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
System controller
Address output enable
Pulse output
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Input capture input
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Notes: n = 0 or 1
* Priority order: address output > output compare output/PWM output > pulse output > DR output
Internal data bus
Internal address bus
Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1009 of 1042
REJ09B0275-0500
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1n
From internal
address bus
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
System controller
Address output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
External clock input
Input capture input
*
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Notes: n = 2 or 3
* Priority order: address output > output compare output/PWM output > pulse output > DR output
Internal data bus
Internal address bus
Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1010 of 1042
REJ09B0275-0500
R
P14DDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P14DR
C
QD
P14
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
Interrupt controller
IRQ0 interrupt input
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
Input capture input
*
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Note: * Priority order: output compare output/PWM output > pulse output > DR output
Internal data bus
Figure C.1 (c) Port 1 Block Diagram (Pin P14)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1011 of 1042
REJ09B0275-0500
R
P15DDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P15DR
C
QD
P15
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
Input capture input
External clock input
*
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Note: * Priority order: output compare output/PWM output > pulse output > DR output
Internal data bus
Figure C.1 (d) Port 1 Block Diagram (Pin P15)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1012 of 1042
REJ09B0275-0500
R
P16DDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P16DR
C
QD
P16
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
Input capture input
Interrupt controller
IRQ1 interrupt input
*
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Note: * Priority order: output compare output/PWM output > pulse output > DR output
Internal data bus
Figure C.1 (e) Port 1 Block Diagram (Pin P16)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1013 of 1042
REJ09B0275-0500
R
P17DDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P17DR
C
QD
P17
RDR1
RPOR1
PPG module
TPU module
Pulse output enable
Output compare output
/
PWM output enable
Output compare output
/
PWM output
Pulse output
Input capture input
External clock input
*
Legend:
WDDR1: Write to P1DDR
WDR1: Write to P1DR
RDR1: Read P1DR
RPOR1: Read port 1
Note: * Priority order: output compare output/PWM output > pulse output > DR output
Internal data bus
Figure C.1 (f) Port 1 Block Diagram (Pin P17)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1014 of 1042
REJ09B0275-0500
C.2 Port 4 Block Diagram
Legend:
RPOR4: Read port 4
Note: n = 0 to 7
P4n
RPOR4
A/D converter module
Analog input
Internal data bus
Figure C.2 Port 4 Block Diagram (Pins P40 to P47)
C.3 Port 9 Block Diagram
P9n
RPOR9
A/D converter module
Analog input
Internal data bus
Legend:
RPOR9: Read port 9
Note: n = 0 to 7
Figure C.3 Port 9 Block Diagram (Pins P90 to P97)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1015 of 1042
REJ09B0275-0500
C.4 Port A Block Diagrams
R
PA0PCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PA0
RDRA
RODRA
RPORA
Internal address bus
PA0DR
Reset
WDDRA
R
C
QD
PA0DDR
Reset
WODRA
RPCRA
R
C
QD
PA0ODR
*1
*2
Modes 4 to 6
Notes: 1. Output enable signal
2. Open drain control signal
Legend:
WDDRA: Write to PADDR
WDRA: Write to PADR
WODRA: Write to PAODR
WPCRA: Write to PAPCR
RDRA: Read PADR
RPORA: Read port A
RODRA: Read PAODR
RPCRA: Read PAPCR
Internal data bus
Address
enable
Figure C.4 (a) Port A Block Diagram (Pin PA0)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1016 of 1042
REJ09B0275-0500
R
PA1PCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PA1
RDRA
RODRA
RPORA
Internal address bus
PA1DR
Reset
Smart card
mode signal
TxD output
TxD output
enable
WDDRA
R
C
QD
PA1DDR
Reset
WODRA
RPCRA
R
C
QD
PA1ODR
*1
*2
Modes 4 to 6
Internal data bus
Address
enable
Notes: 1. Output enable signal
2. Open drain control signal
Legend:
WDDRA: Write to PADDR
WDRA: Write to PADR
WODRA: Write to PAODR
WPCRA: Write to PAPCR
RDRA: Read PADR
RPORA: Read port A
RODRA: Read PAODR
RPCRA: Read PAPCR
Figure C.4 (b) Port A Block Diagram (Pin PA1)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1017 of 1042
REJ09B0275-0500
R
PA2PCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PA2
RDRA
RODRA
RPORA
Internal address bus
PA2DR
Reset
RxD input
enable SCK output
RxD input
SCK output
enable
WDDRA
R
C
QD
PA2DDR
Reset
WODRA
RPCRA
R
C
QD
PA2ODR
*1
*2
Modes 4 to 6
Internal data bus
Address
enable
Notes: 1. Output enable signal
2. Open drain control signal
Legend:
WDDRA: Write to PADDR
WDRA: Write to PADR
WODRA: Write to PAODR
WPCRA: Write to PAPCR
RDRA: Read PADR
RPORA: Read port A
RODRA: Read PAODR
RPCRA: Read PAPCR
Figure C.4 (c) Port A Block Diagram (Pin PA2)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1018 of 1042
REJ09B0275-0500
R
PA3PCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PA3
RDRA
RODRA
RPORA
Internal address bus
PA3DR
Reset
SCK input
enable SCK output
SCK input
SCK output
enable
WDDRA
R
C
QD
PA3DDR
Reset
WODRA
RPCRA
R
C
QD
PA3ODR
*1
*2
Modes 4 to 6
Internal data bus
Address
enable
Notes: 1. Output enable signal
2. Open drain control signal
Legend:
WDDRA: Write to PADDR
WDRA: Write to PADR
WODRA: Write to PAODR
WPCRA: Write to PAPCR
RDRA: Read PADR
RPORA: Read port A
RODRA: Read PAODR
RPCRA: Read PAPCR
Figure C.4 (d) Port A Block Diagram (Pin PA3)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1019 of 1042
REJ09B0275-0500
R
PAnPCR
C
QD
Reset
WPCRA
Reset
WDRA
R
C
QD
PAn
RDRA
RODRA
RPORA
PAnDR
Reset
WDDRA
R
C
QD
PAnDDR
Reset
WODRA
RPCRA
R
C
QD
PAnODR
*1
*2
Internal data bus
Notes: n = 4 or 5
In the H8S/2626 Group, PA5 and PA4 are OSC2 and
OSC1, respectively.
1. Output enable signal
2. Open drain control signal
Legend:
WDDRA: Write to PADDR
WDRA: Write to PADR
WODRA: Write to PAODR
WPCRA: Write to PAPCR
RDRA: Read PADR
RPORA: Read port A
RODRA: Read PAODR
RPCRA: Read PAPCR
Figure C.4 (e) Port A Block Diagram (Pins PA4 and PA5)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1020 of 1042
REJ09B0275-0500
C.5 Port B Block Diagram
R
PBnPCR
C
QD
Reset
WPCRB
Reset
WDRB
R
C
QD
PBn
RDRB
RODRB
RPORB
Internal address bus
PBnDR
Reset
(Output compare)
TPU output
TPU output
enable
WDDRB
R
C
QD
PBnDDR
Reset
WODRB
RPCRB
R
C
QD
PBnODR
*1
*2
Modes 4 to 6
TPU input
(input capture)
Legend:
WDDRB: Write to PBDDR
WDRB: Write to PBDR
WODRB: Write to PBODR
WPCRB: Write to PBPCR
RDRB: Read PBDR
RPORB: Read port B
RODRB: Read PBODR
RPCRB: Read PBPCR
Internal data bus
Address
enable
Notes: n = 0 to 7
1. Output enable signal
2. Open drain control signal
Figure C.5 Port B Block Diagram (Pins PB0 to PB7)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1021 of 1042
REJ09B0275-0500
C.6 Port C Block Diagrams
R
PCnPCR
C
QD
Reset
WPCRC
Reset
WDRC
R
C
QD
PCn
RDRC
RODRC
RPORC
Internal address bus
PCnDR
Reset
Smart card mode
signal
TxD output
TxD output
enable
WDDRC
R
C
QD
PCnDDR
Reset
WODRC
RPCRC
R
C
QD
PCnODR
*1
*2
Modes 4 to 6
Legend:
WDDRC: Write to PCDDR
WDRC: Write to PCDR
WODRC: Write to PCODR
WPCRC: Write to PCPCR
RDRC: Read PCDR
RPORC: Read port C
RODRC: Read PCODR
RPCRC: Read PCPCR
Internal data bus
Address
enable
Notes: n = 0 or 3
1. Output enable signal
2. Open drain control signal
Figure C.6 (a) Port C Block Diagram (Pins PC0 and PC3)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1022 of 1042
REJ09B0275-0500
R
PCnPCR
C
QD
Reset
WPCRC
Reset
WDRA
R
C
QD
PCn
RDRC
RODRC
RPORC
Internal address bus
PCnDR
Reset
RxD input
enable
RxD input
WDDRC
R
C
QD
PCnDDR
Reset
WODRC
RPCRC
R
C
QD
PCnODR
*1
*2
Modes 4 to 6
Internal data bus
Address
enable
Legend:
WDDRC: Write to PCDDR
WDRC: Write to PCDR
WODRC: Write to PCODR
WPCRC: Write to PCPCR
RDRC: Read PCDR
RPORC: Read port C
RODRC: Read PCODR
RPCRC: Read PCPCR
Notes: n = 1 or 4
1. Output enable signal
2. Open drain control signal
Figure C.6 (b) Port C Block Diagram (Pins PC1 and PC4)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1023 of 1042
REJ09B0275-0500
R
PCnPCR
C
QD
Reset
WPCRC
Reset
WDRC
R
C
QD
PCn
RDRC
RODRC
RPORC
Internal address bus
PCnDR
Reset
SCK input
enable SCK output
SCK input
SCK output
enable
WDDRC
R
C
QD
PCnDDR
Reset
WODRC
RPCRC
R
C
QD
PCnODR
*1
*2
Modes 4 to 6
Internal data bus
IRQ interrupt input
Address
enable
Legend:
WDDRC: Write to PCDDR
WDRC: Write to PCDR
WODRC: Write to PCODR
WPCRC: Write to PCPCR
RDRC: Read PCDR
RPORC: Read port C
RODRC: Read PCODR
RPCRC: Read PCPCR
Notes: n = 2 or 5
1. Output enable signal
2. Open drain control signal
Figure C.6 (c) Port C Block Diagram (Pins PC2 and PC5)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1024 of 1042
REJ09B0275-0500
R
PCnPCR
C
QD
Reset
WPCRC
Reset
WDRA
R
C
QD
PCn
RDRC
RODRC
RPORC
Internal address bus
PCnDR
Reset
WDDRA
R
C
QD
PCnDDR
Reset
WODRC
RPCRC
R
C
QD
PCnODR
*1
*2
Modes 4 to 6
Internal data bus
Mode 6
PWM output
PWM output
enable
Legend:
WDDRC: Write to PCDDR
WDRC: Write to PCDR
WODRC: Write to PCODR
WPCRC: Write to PCPCR
RDRC: Read PCDR
RPORC: Read port C
RODRC: Read PCODR
RPCRC: Read PCPCR
Notes: n = 6 or 7
1. Output enable signal
2. Open drain control signal
Figure C.6 (d) Port C Block Diagram (Pins PC6 and PC7)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1025 of 1042
REJ09B0275-0500
C.7 Port D Block Diagram
R
PDnPCR
C
QD
Reset
WPCRD
Reset
WDRD
R
C
QD
PDn
RDRD
RPORD
External address
upper write
PDnDR
WDDRD
C
QD
PDnDDR
RPCRD
Mode 7
External address
write
Reset
R
External address
upper read
Legend:
WDDRD: Write to PDDDR
WDRD: Write to PDDR
WPCRD: Write to PDPCR
RDRD: Read PDDR
RPORD: Read port D
RPCRD: Read PDPCR
Internal upper data bus
Modes 4 to 6
Note: n = 0 to 7
Figure C.7 Port D Block Diagram (Pins PD0 to PD7)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1026 of 1042
REJ09B0275-0500
C.8 Port E Block Diagram
R
PEnPCR
C
QD
Reset
WPCRE
Reset
WDRE
R
C
QD
PEn
RDRE
RPORE
PEnDR
WDDRE
C
QD
PEnDDR
RPCRE
Mode 7
External address
write
Reset
R
External address
lower read
Legend:
WDDRE: Write to PEDDR
WDRE: Write to PEDR
WPCRE: Write to PEPCR
RDRE: Read PEDR
RPORE: Read port E
RPCRE: Read PEPCR
Internal upper data bus
Internal lower data bus
Modes 4 to 6
Note: n = 0 to 7
Figure C.8 Port E Block Diagram (Pins PE0 to PE7)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1027 of 1042
REJ09B0275-0500
C.9 Port F Block Diagrams
R
PF0DDR
C
QD
Reset
WDDRF
Reset
WDRF
R
C
QD
PF0
RDRF
RPORF
Bus request input
IRQ interrupt input
PF0DR
Bus controller
BRLE bit
Modes 4 to 6
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Internal data bus
Figure C.9 (a) Port F Block Diagram (Pin PF0)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1028 of 1042
REJ09B0275-0500
R
PF1DDR
C
QD
Reset
WDDRF
Modes 4 to 6
Reset
WDRF
R
PF1DR
C
QD
PF1
RDRF
RPORF
Bus controller
BRLE output
Internal data bus
Bus request input
acknowledge output
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Figure C.9 (b) Port F Block Diagram in the H8S/2623 Group (Pin PF1)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1029 of 1042
REJ09B0275-0500
R
PF1DDR
C
QD
Reset
WDDRF
Modes 4 to 6
Reset
BUZZ
output
enable
BUZZ output
WDRF
R
PF1DR
C
QD
PF1
RDRF
RPORF
Bus controller
BRLE output
Internal data bus
Bus request input
acknowledge output
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Figure C.9 (c) Port F Block Diagram in the H8S/2626 Group (Pin PF1)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1030 of 1042
REJ09B0275-0500
R
PF2DDR
C
QD
Reset
WDDRF
Reset
WDRF
R
PF2DR
C
QD
PF2
RDRF
RPORF
Bus request output
enable
Wait input
Bus controller
Wait enable
Modes 4 to 6
Modes 4 to 6
Modes 4 to 6
Internal data bus
Bus request output
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Figure C.9 (d) Port F Block Diagram (Pin PF2)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1031 of 1042
REJ09B0275-0500
R
PF3DDR
C
QD
Reset
WDDRF
Reset
WDRF
R
PF3DR
C
QD
PF3
RDRF
RPORF
Bus controller
ADTRG input
IRQ interrupt input
LWR output
Modes 4 to 6
Internal data bus
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Figure C.9 (e) Port F Block Diagram (Pin PF3)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1032 of 1042
REJ09B0275-0500
R
PF4DDR
C
QD
Reset
Modes 4 to 6
WDDRF
Reset
WDRF
R
PF4DR
C
QD
PF4
RDRF
RPORF
Bus controller
HWR output
Internal data bus
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Figure C.9 (f) Port F Block Diagram (Pin PF4)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1033 of 1042
REJ09B0275-0500
R
PF5DDR
C
QD
Reset
WDDRF
Reset
Modes 4 to 6
WDRF
R
PF5DR
C
QD
PF5
RDRF
RPORF
Bus controller
RD output
Internal data bus
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Figure C.9 (g) Port F Block Diagram (Pin PF5)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1034 of 1042
REJ09B0275-0500
R
PF6DDR
C
QD
Reset
WDDRF
Reset
Modes 4 to 6
WDRF
R
PF6DR
C
QD
PF6
RDRF
RPORF
Bus controller
AS output
Internal data bus
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Figure C.9 (h) Port F Block Diagram (Pin PF6)
Appendix C I/O Port Block Diagrams
Rev. 5.00 Jan 10, 2006 page 1035 of 1042
REJ09B0275-0500
D
WDDRF
PF7
RDRF
φ
RPORF
Reset
R
Modes 4 to 6
S
C
QD
PF7DDR
*
Internal data bus
Legend:
WDDRF: Write to PFDDR
WDRF: Write to PFDR
RDRF: Read PFDR
RPORF: Read port F
Note: * Set priority
Figure C.9 (i) Po rt F Block Diagram (Pin PF7)
Appendix D Pin States
Rev. 5.00 Jan 10, 2006 page 1036 of 1042
REJ09B0275-0500
Appendix D Pin States
D.1 Port States in Each Mode
Table D.1 I/O Port States in Each Processing State
Port Name
Pin Name
MCU
Operating
Mode
Power-
On
Reset
Hardware
Standby
Mode Software
Standby Mode Bus Release
State
Program
Execution State
Sleep Mode
Port 1 4, 5 L T [Address output,
OPE = 0]
T
[Address output]
T[Address output]
A23 to A20
6 T [A ddress output,
OPE = 1]
kept
[Otherwise]
kept
[Otherwise]
kept [Otherwise]
I/O port
7 T T kept kept I/O port
Port 4 4 to 7 T T T T Input port
Port 9 4 to 7 T T T T Input port
PA5
PA4
4 to 7 T T kept kept I/O port
4, 5 L T [Address output,
OPE = 0]
T
[Address output]
T[Address output]
A19 to A17
PA3/A19
PA2/A18
PA1/A17
PA0/A16 6 T [Address output,
OPE = 1]
kept
[Otherwise]
kept
[Otherwise]
kept [Otherwise]
I/O port
7 T T kept kept I/O port
Port B 4, 5 L T [Address output,
OPE = 0]
T
[Address output]
T[Address output]
A15 to A8
6 T [A ddress output,
OPE = 1]
kept
[Otherwise]
kept
[Otherwise]
kept [Otherwise]
I/O port
7 T T kept kept I/O port
Appendix D Pin States
Rev. 5.00 Jan 10, 2006 page 1037 of 1042
REJ09B0275-0500
Port Name
Pin Name
MCU
Operating
Mode
Power-
On
Reset
Hardware
Standby
Mode Software
Standby Mode Bus Release
State
Program
Execution State
Sleep Mode
Port C 4, 5 L T [OPE = 0]
T
[OPE = 1]
kept
T A7 to A0
6 T T [DDR = 1,
OPE = 0]
T
[DDR = 1,
OPE = 1]
kept
[DDR = 0]
kept
T [DDR = 1]
A7 to A0
[DDR = 0]
I/O port
7 T T kept kept I/O port
Port D 4 to 6 T T T T Data bus
7 T T kept kept I/O port
Port E 4 to 6 8-bit
bus T T k ept kept I/O port
16-bit
bus T T T T Data bus
7 T T kept kept I/O port
PF7/φ4 to 6 Clock
output T [ DDR = 0]
Tkept [DDR = 0]
T
7 T [DDR = 1]
H[DDR = 1]
Clock output
PF6/AS 4 to 6 H T [OPE = 0]
T
[OPE = 1]
H
TAS
7 T T kept kept I/O port
4 to 6 H T [OPE = 0]
T
[OPE = 1]
H
TRD, HWR, LWR
PF5/RD
PF4/HWR
PF3/LWR/
ADTRG/
IRQ3 7 T T kept kept I/O port
Appendix D Pin States
Rev. 5.00 Jan 10, 2006 page 1038 of 1042
REJ09B0275-0500
Port Name
Pin Name
MCU
Operating
Mode
Power-
On
Reset
Hardware
Standby
Mode Software
Standby Mode Bus Release
State
Program
Execution State
Sleep Mode
PF2/WAIT/
BREQO 4 to 6 T T [OPE = 0]
T
[OPE = 1]
kept
[BREQOE = 1]
BREQO
[WAITE = 1]
T
[BREQOE = 1]
BREQO
[WAITE = 1]
WAIT
7 T T kept kept I/O port
PF1/BACK 4 t o 6 T T [ B RLE = 0]
I/O port
[BRLE = 1]
H
[BRLE = 0]
I/O port
[BRLE = 1]
L
[BRLE = 0]
I/O port
[BRLE = 1]
BACK
7 T T kept kept I/O port
PF0/BREQ/
IRQ2 4 to 6 T T [ B RLE = 0]
kept
[BRLE = 1]
T
T[BRLE = 0]
I/O port
[BRLE = 1]
BREQ
7 T T kept kept I/O port
HTxD 4 t o 7 H T H H Output
HRxD 4 t o 7 Input T T Input Input
Legend:
H : High level
L : Low level
T : High impedance
kept : Input port becomes high-impedance, output port retains state
DDR : Data direction register
OPE : Output port enable
WAITE : Wait input enable
BRLE : Bus release enable
BREQOE : BREQO pin enable
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Rev. 5.00 Jan 10, 2006 page 1039 of 1042
REJ09B0275-0500
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Sta ndby Mode
(1) To retain RAM co ntents with the RAME bit set to 1 in SYSCR, driv e the RES signal low at
least 10 states before the STBY signal goes low, as shown below. RES mu st r e main low until
STBY signal goes low (delay from STBY low to RES high: 0 ns or more).
STBY
RES
t
2
≥ 0ns
t
1
≥ 10t
cyc
Figure E.1 Timing o f Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained, RES does not have to be driven low as in (1).
Timing of Recovery fro m H ardware Standby Mode
Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY
goes high to execute a power-on reset.
STBY
RES
t
OSC
t
NMIRH
t ≥ 100ns
NMI
Figure E.2 Timing of Recovery from Hardwa re St andby Mode
Appendix F Product Code Lineup
Rev. 5.00 Jan 10, 2006 page 1040 of 1042
REJ09B0275-0500
Appendix F Product Code Lineup
Table F.1 H8S/2626 Group and H8S/2623 Group Product Code Lineup
Product Type Product Code Mark Code Package
(Package Code)
H8S/2626 F-ZTAT version HD64F2626 HD64F2626FA 100-pin QFP (FP-100B)
Mask ROM version HD6432626 HD6432626FA 100-pin QFP (FP-100B)
H8S/2625 HD6432625 HD6432625FA 100-pin QFP (FP-100B)
H8S/2624 HD6432624 HD6432624FA 100-pin QFP (FP-100B)
H8S/2623 F-ZTAT version HD64F2623 HD64F2623FA 100-pin QFP (FP-100B)
Mask ROM version HD6432623 HD6432623FA 100-pin QFP (FP-100B)
H8S/2622 HD6432622 HD6432622FA 100-pin QFP (FP-100B)
H8S/2621 HD6432621 HD6432621FA 100-pin QFP (FP-100B)
Appendix G Package Dimensions
Rev. 5.00 Jan 10, 2006 page 1041 of 1042
REJ09B0275-0500
Appendix G Package Dimensions
Figure G.1 shows the FP-100B package dimensions of the H8S/2626 Group and H8S/2623 Group.
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
*2
*3p
E
D
E
D
F
100
125
26
76
75 51
50
xMy
Z
Z
D
H
E
H
b
Terminal cross section
p
1
1
c
b
c
b
2
1
1
Detail F
c
AA
L
L
A
1.0
1.0
0.08
0.10
0.5
8°0°
0.250.12
0.15
0.20
0.00
0.270.220.17
0.220.170.12
3.05
16.316.015.7
L
1
Z
E
Z
D
y
x
c
b
1
b
p
A
H
D
A
2
E
D
A
1
c
1
e
e
L
H
E
0.70.50.3
MaxNomMin
Dimension in Millimeters
Symbol
Reference
14
2.70
16.316.015.7
1.0
14
θ
θ
P-QFP100-14x14-0.50 1.2g
MASS[Typ.]
FP-100B/FP-100BVPRQP0100KA-A
RENESAS CodeJEITA Package Code Previous Code
Figure G.1 FP-100 B Package Dimensions
Appendix G Package Dimensions
Rev. 5.00 Jan 10, 2006 page 1042 of 1042
REJ09B0275-0500
Renesas 16Bit Single-Chip Microcomputer
Hardware Manual
H8S/2626 Group, H8S/2623 Group,
H8S/2626F-ZTAT
, H8S/2623F-ZTAT
Publication Date: 1st Edition, December 1998
Rev.5.00, January 10, 2006
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Cus tomer Support Dep artme nt
Global Strategic Communication Div.
Renesas Soluti ons Corp.
©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
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Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Colophon 5.0
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H8S/2626 Group, H8S/2623 Group,
H8S/2626F-ZTATTM, H8S/2623F-ZTATTM
REJ09B0275-0500
Hardware Manual