NT5TB128M8DE-3C - Nanya Technology Corporation

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

•VDD=VDDQ=1.5V +0.1275V/-0.075V

• Pseudo 1.8V I/O

• 8 internal memory banks

• Programmable CAS Latency: 3, 4, 5, and 6

• Programmable Additive Latency: 0, 1, 2, 3, 4 and 5

• Write Latency = Read Latency -1

• Programmable Burst Length: 4 and 8

• Programmable Sequential / Interleave Burst

• OCD (Off-Chip Driver Impedance Adjustment)

• ODT (On-Die Termination)

• 4 bit prefetch architecture

• 1k page size for x 4 & x 8,

2k page size for x16

• Data-Strobes: Bidirectional, Differential

• Strong and Weak Strength Data-Output Driver

• Auto-Refresh and Self-Refresh

• Power Saving Power-Down modes

• 7.8 µs max. Average Periodic Refresh Interval

• Packages:

60 Ball BGA for x4/x8 components

84 Ball BGA for x16 component

• RoHS Compliance

Description

The 1Gb Double-Data-Rate-2 (DDR2) DRAMs is a high-

speed CMOS Double Data Rate 2 SDRAM containing

1,073,741,824 bits. It is internally configured as a octal-bank

DRAM.

The 1Gb chip is organized as either 32Mbit x 4 I/O x 8 bank,

16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device.

The chip is designed to comply with all key DDR2 DRAM key

features: (1) posted CAS with additive latency, (2) write

latency = read latency -1, (3) normal and weak strength data-

output driver, (4) variable data-output impedance adjustment

and (5) an ODT (On-Die Termination) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS pair in a source synchronous fash-

ion. A 14 bit address bus for x4 and x8 organised compo-

nents and a 13 bit address bus for x16 components is used to

convey row, column, and bank address devices.

These devices operate with a single 1.5V +0.1275V/-0.075V

power supply and are available in BGA packages.

An Auto-Refresh and Self-Refresh mode is provided along

with various power-saving power-down modes.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 60 balls 0.8mmx0.8mm Pitch BGA Package (x4/x8)

See the balls through the package.

VDD

VSSQ

DQ1

VSSQ

VREF

CKE

A10/AP

VSS

VDDQ

DQ3

VSS

BA1

VDDQ

VDD

DQS

VSSQ

DQ0

VSSQ

DQS

VDDQ

VSSDL

RAS

CAS

VDD

VDDQ

VDDL

A12VDD

BA0

NC NC

A11

DQ2

A13

VDDQ

VSS

BA2

VSS

ODT

7 8 9321

x 4

x 8

VDD

DQ4

NU,/RDQS

VSSQ

DQ1

VSSQ

VREF

CKE

A10/AP

VSS

DM/RDQS

VDDQ

DQ3

VSS

BA1

3 7 8 9

VDDQ

VDD

DQS

VSSQ

DQ0

VSSQ

DQS

VDDQ

VSSDL

RAS

CAS

VDD

DQ6

VDDQ

VDDL

A12VDD

BA0

NC NC

A11

DQ2

A13

DQ7

VDDQ

DQ5

VSS

BA2

VSS

ODT

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 84 balls 0.8mmx0.8mm Pitch BGA Package (x16)

See the balls through the package.

x 16

VDD

DQ14

VDDQ

DQ12

VDD

DQ4

VSSQ

DQ9

VSSQ

DQ1

VSSQ

VREF

CKE

A10/AP

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

BA1

3 7 8 9

VDDQ

DQ15

VDDQ

DQ13

VDDQ

VDD

UDQS

VSSQ

DQ8

VSSQ

LDQS

VSSQ

DQ0

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

VSSDL

RAS

CAS

VDD

DQ6

VDDQ

VDDL

A12VDD

BA0

NC NC

A11

DQ2

DQ7

VDDQ

DQ5

VSS

BA2

VSS

ODT

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol Type Function

CK, CK Input

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-

enced to the crossings of CK and CK (both directions of crossing).

CKE Input

Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device

input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-

Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-

chronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-

Refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE

are disabled during Self-Refresh.

CS Input Chip Select: All command are masked when CS is registered high. CS provides for external rank

selection on systems with multiple memory ranks. CS is considered part of the command code.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

(LDM, UDM) Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled high coincident with that input data during a Write access. DM is sampled on both edges

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For

x8 device, the function of DM or RDQS / RQDS is enabled by EMRS command to EMR(1).

BA0-BA2 Input

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge com-

mand is being applied. Bank address also determines if the mode register or one of the extended

mode registers is to be accessed during a MRS or EMR command cycle.

A0 - A13 Input

Address Inputs: Provides the row address for Activate commands and the column address and

Auto-Precharge bit for Read/Write commands to select one location out of the memory array in the

respective bank. A10 is sampled during a Precharge command to determine whether the Pre-

charge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-

charged, the bank is selected by BA0 - BA2. The address inputs also provide the op-code during

MRS or EMRS command.

DQ Input/Output Data Inputs/Output: Bi-directional data bus.

DQS, (DQS),

(LDQS), (LDQS),

(UDQS), (UDQS),

(RDQS), (RDQS)

Input/Output

Data Strobe: output with read data, input with write data. Edge aligned with read data, centered

in write data. For the x16, LDQS corresponds to the data on DDQ0 - DQ7; UDQS corresponds to

the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMR(1)

to simplify reading time. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single

ended mode or paired with the optional complementary signals DQS, LDQS, UDQS, and RDQS to

provide differential pair signaling to the system during both reads and writes. A control bit at

EMR(1)[A10] control bit enables or disables the complementary data strobe signals.

ODT Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2

SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS and DM signal for x4 and DQ,

DQS, DQS, RDQS, RDQS and DM for x4/x8 configurations. For x16 configuration ODT is applied

to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if

the EMR(1) is programmed to disable ODT.

NC No Connect: No internal electrical connection is present.

VDDQ Supply DQ Power Supply: +1.5V +0.1275V/-0.075V

VSSQ Supply DQ Ground

VDDL Supply DLL Power Supply: +1.5V +0.1275V/-0.075V

VSSDL Supply DLL Ground

VDD Supply Power Supply: +1.5V +0.1275V/-0.075V

VSS Supply Ground

VREF Supply Vref = VDDQ/2

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Ordering Information

Org. Part Number Package

Speed

Clock (MHz) CL-tRCD-tRP

256M x 4

NT5TB256M4DE-37B

60ball BGA

0.8mmx0.8mm

Pitch

266 4-4-4

NT5TB256M4DE-3C 333 5-5-5

NT5TB256M4DE-AD 400 6-6-6

NT5TB256M4DE-AC 400 5-5-5

128M x 8

NT5TB128M8DE-37B 266 4-4-4

NT5TB128M8DE-3C 333 5-5-5

NT5TB128M8DE-AD 400 6-6-6

NT5TB128M8DE-AC 400 5-5-5

64M x 16

NT5TB64M16DG-37B

84ball BGA

0.8mmx0.8mm

Pitch

266 4-4-4

NT5TB64M16DG-3C 333 5-5-5

NT5TB64M16DG-AD 400 6-6-6

NT5TB64M16DG-AC 400 5-5-5

Note:

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (256Mb x 4)

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

I/O Gating

DM Mask Logic

Bank 7

Row-Address

Latch &

Decoder

Bank 6

Row-Address

Latch &

Decoder

Bank 5

Row-Address

Latch &

Decoder

Bank 4

Row-Address

Latch &

Decoder

Bank 3

Row-Address

Latch &

Decoder

Bank 2

Row-Address

Latch &

Decoder

Bank 1

Row-Address

Latch &

Decoder

Command

Decode

Mode

Registers

Control Logic

CKE

CAS

RAS

Address Register

Row-Address MUX

A0 – A13,

BA0 – BA2

Refresh Counter

Column-Address

Counter/Latch

Bank Control

Logic

Bank 0

Row-Address

Latch &

Decoder

Bank 7

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 6

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 5

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 4

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 3

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 2

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 1

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 0

Memory Array

(16384 x512 x16)

Sense Amplifier

16384

8192

512 (x16)

Read Latch

Write

FIFO

Drivers

MUX

COL0,1

Drivers

DQS

Generator

Data

DQS,

DQS

Mask

Data

COL0,1

CK,

Receivers

ODT Control

DQS,

DQS

DQ0 – DQ3

ODT

DLL

CK, CK

COL0,1

Notes:

1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the

device; it does not represent an actual circuit implementation.

2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the

bidirectional DQ and DQS signals.

Input

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (128Mb x 8)

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

I/O Gating

DM Mask Logic

Bank 7

Row-Address

Latch &

Decoder

Bank 6

Row-Address

Latch &

Decoder

Bank 5

Row-Address

Latch &

Decoder

Bank 4

Row-Address

Latch &

Decoder

Bank 3

Row-Address

Latch &

Decoder

Bank 2

Row-Address

Latch &

Decoder

Bank 1

Row-Address

Latch &

Decoder

Command

Decode

Mode

Registers

Control Logic

CKE

CAS

RAS

Address Register

Row-Address MUX

A0 – A13,

BA0 – BA2

Refresh Counter

Column-Address

Counter/Latch

Bank Control

Logic

Bank 0

Row-Address

Latch &

Decoder

Bank 7

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 6

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 5

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 4

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 3

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 2

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 1

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 0

Memory Array

(16384 x256 x32)

Sense Amplifier

16384

8192

256 (x32)

Read Latch

Write

FIFO

Drivers

MUX

COL0,1

Drivers

DQS

Generator

Data

DQS,

DQS

Mask

Data

COL0,1

CK,

Receivers

ODT Control

DQS,

DQS

DQ0 – DQ7

ODT

DLL

CK, CK

COL0,1

Input

Notes:

1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the

device; it does not represent an actual circuit implementation.

2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the

bidirectional DQ and DQS signals.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (64Mb x 16)

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

I/O Gating

DM Mask Logic

Bank 7

Row-Address

Latch &

Decoder

Bank 6

Row-Address

Latch &

Decoder

Bank 5

Row-Address

Latch &

Decoder

Bank 4

Row-Address

Latch &

Decoder

Bank 3

Row-Address

Latch &

Decoder

Bank 2

Row-Address

Latch &

Decoder

Bank 1

Row-Address

Latch &

Decoder

Command

Decode

Mode

Registers

Control Logic

CKE

CAS

RAS

Address Register

Row-Address MUX

A0 – A12,

BA0 – BA2

Refresh Counter

Column-Address

Counter/Latch

Bank Control

Logic

Bank 0

Row-Address

Latch &

Decoder

Bank 7

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 6

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 5

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 4

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 3

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 2

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 1

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 0

Memory Array

(8192 x 86 x 64)

Sense Amplifier

8192

16384

256 (x64)

Read Latch

Write

FIFO

Drivers

MUX

COL0,1

Drivers

DQS

Generator

Data

DQS,

DQS

Mask

Data

COL0,1

CK,

Receivers

ODT Control

UDM,

LDM

UDQS,

UDQS

DQ0 –

DQ15

ODT

DLL

CK, CK

COL0,1

Input

Notes:

1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the

device; it does not represent an actual circuit implementation.

2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the

bidirectional DQ and DQS signals.

LDQS,

LDQS

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Basic Functionality

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst

length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is then

followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the

bank and row to be accesses (BA0 & BA1 select the banks, A0-A13 select the row for x4 and x8 components, A0~A12 select

the row for x16 components). The address bits registered coincident with the Read or Write command are used to select the

starting column location for the burst access and to determine if the Auto-Precharge command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering

device initialization, register definition, command description and device operation.

Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified

may result in undefined operation.

For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/Extended Mode Register Set (MRS/EMR) commands.

Users must initialize all four mode Registers. The registers maybe initialized in any order.

The following sequence is required for POWER UP and Initialization.

1. Either one of the following sequence is required for Power-up.

1(a). While applying power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may be

undefined). The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min;

and during the VDD voltage ramp, lVDD-VDDQl<=0.3V. Once the ramping of the supply voltages is complete (when VDDQ

crosses VDDQ min).

- VDD,VDDL, and VDDQ are driven from a signle power converter output, AND

- VTT is limited to 0.95 V max, AND

- VREF tracks VDDQ/2, VREF must be within +/- 300mV with respect to VDDQ/2 during supply ramp time.

- VDDQ>=VREF must be met at all times.

1(b). While applying power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state, all other inputs may be

undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up.

During the ramping of the supply voltages, VDD>=VDDL>=VDDQ must be maintained and is applicable to both AC and DC

levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min.

- Apply VDD/VDDL before or at the same time as VDDQ,

- VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min.

- Apply VDDQ before or at the same time as VTT.

- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be

no greater than 500ms.

(Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.)

- Vref must track VDDQ/2, Vref must be within +/-300mV with respect to VDDQ/2 during supply ramp time.

- VDDQ>=VREF must be met at all times.

- Apply VTT.

- The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must be

greater than 500ms.

2. Start clock (CK, CK) and maintain stable condition.

3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and maxi

4. Wait minimum of 400ns, then issue Precharge-all command. NOP or Deselect applied during 400us period.

5. Issue EMR(2) command. (To issue EMR(2) command, provide “low” to BA0 and BA2 and “high” to BA1)

6. Issue EMR(3) command. (To issue EMR(3) command, provide “low” to BA2 and “high” to BA0 and BA1)

7. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “low” to A0 and

“high” to BA0 and “low” to BA1-BA2 and A13-A15. And A9=A8=A7=LOW must be used when issuing this command.)

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

8. Issue MRS command (Mode Register Set) for "DLL reset". (To issue DLL reset command, provide “high” to A8

and “low” to BA0 ~ BA2 and A13 ~ A15)

9. Issue Precharge-All command.

10. Issue 2 or more Auto-Refresh commands.

11. Issue a MRS command with LOW on A8 to initialize device operation. (i.e. to programm operating paramters with

out resetting the DLL)

12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD cali-

bration is not used, EMRS to EMR(1) to set OCD Default (A9=A8=A7=HIGH) followed by EMRS to EMR(1) OCD Calibra

tion Mode Exit command (A9=A8=A7=LOW) must be issued with other parameters of EMR(1).

13. The DDR2 SDRAM is now read for normal operation.

Example

Programming the Mode Register and Extended Mode Registers

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user defined

variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive

CAS latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjust-

ment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Con-

tents of the Mode Register (MR) and Extended Mode Registers (EMR(#)) can be altered by re-executing the MRS and EMRS

Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when

the MRS or EMRS commands are issued. MRS, EMRS and DLL Reset do not affect array contents, which means reinitializa-

zion including those can be executed any time after power-up without affecting array contents.

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It contorls CAS latency, burst

length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for vari-

ous applications. The default value of the mode register is not defined, therefore the mode register must be written after power-

up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling

the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharged (idle) mode with CKE already high

prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write oper-

ation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements

during normal operation as long as all banks are in the precharged state. The mode register is divided into various fields

depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst length. Burst address sequence

type is defined by A3 and CAS latency is defined by A4 ~ A6. A7 is used for test mode and must be set to low for normal MRS

operation. A8 is used for DLL reset. A9 ~ A11 are used for write recovery time (WR) definition for Auto-Precharge mode.

CK, CK

1st Auto

refresh

MRS

PRE

ALL

EMRS

CMD

2nd Auto

refresh

tRP tRP tRFC tRFC

Extended Mode

with DLL enable

Mode Register Set

with DLL reset

PRE

ALL

CMD

tMRS tMRS

min. 200 cycles

to lock the DLL

CKE

Command

400 ns

MRS

NOP

tMRS

EMRS

OCD

Follow OCD

flowchart

ODT "low"

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

MRS Mode Register Operation Table (Address Input For Mode Set)

A0A1A2A3A4A5A6A7A8A9A10A11A12A13BA0BA1BA2

Address Filed

BLA0A1A2

4010

8110

Burst Length

Burst TypeA3

Sequential0

Interleave

Burst Type

CAS LatencyA4A5A6

Reserved000

Reserved100

/CAS Latency

010

110

001

101

011

111

Reserved

MRS mode

BA0BA1

EMR(1)

MRS mode

11 EMR(3)

EMR(2)

Active power down

exit time

A12

Fast exit (use tXARD)0

Slow exit (use tXARDS)

Active power down exit

time

* *

WR(cycles)A9A10A11

Reserved000

2100

Write recovery for autoprecharge

010

110

001

101

011

111

Reserved

DDR2-533

DDR2-667

DLL ResetA8

NO0

YES

DLL Reset

ModeA7

Normal0

TEST

Mode

* BA2 and A13 are reserved for future use and must be

set to 0 when programming the MR.

DDR2-800

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

EMR(1) Extended Mode Register Set Programming

A0A1A2A3A4A5A6A7A8A9A10A11A12A13BA0BA1BA2

Address Filed

DLL

Enable

Disable1

DLL

Output Driver

Impedance Control

Full strength

Reduced strength

D.I.C

Rtt (Nominal)A2A6

ODT Disabled00

75 ohm10

Rtt

11 50 ohm

150 ohm

MRS mode

BA0BA1

EMR(1)

MRS mode

11 EMR(3)

EMR(2)

Qoff

* *

/DQSA10

Enable0

Disable

/DQS

* BA2 and A13 are reserved for future use and must be set to 0 when programming the MR.

*1 When Adjust mode is issued. AL from previously set value must be applied.

*2 After setting to default, OCD calibration mode needs to be exited by setting A9~A7 to 000.

*3 Output disabled – DQs, DQSs, /DQSs, RDQS, /RDQS. This feature is used in conjunction with DIMM IDD

measurements when IDDQ is not desired to be included.

*4 If RDQS is enabled, the DM function is disabled. RDQS is active for reads and do not care for writes.

Additive

Latency

A3A4A5

0000

1100

010

110

001

101

011

111

Reserved

Additive Latency

Qoff*3A12

Output buffer enabled0

Output buffer disabled

RDQS Enable*4A11

Enable0

Disable

RDQS

OCD Calibration ProgramA7A8

OCD Calibration mode

exit; maintain setting

Drive(1)10

00 Adjust mode *1

Drive(0)

11 OCD Calibration default*21

OCD Program

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Extended Mode Register Set (EMR(1))

The extended mode register EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency,

ODT, DQS disable, OCD program, RQDS enable. The default value of the extended mode register EMR(1) is not defined, there-

fore the extended mode register must be written after power-up for proper operation. The extended mode register is written by

asserting low on CS, RAS, CAS, WE, BA1 and high on BA0, while controlling the state of the address pins. The DDR2 SDRAM

should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set

command cycle time (tMRD) must be satisfied to complete the write operation to the EMR(1). Mode register contents can be

changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge

state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3-A5 determine the additive

latency, A7-A9 are used for OCD control, A10 is used for DQS disable and A11 is used for RDQS enable. A2 and A6 are used

for ODT setting.

Single-ended and Differential Data Strobe Signals

The following table lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by A10 & A11

address bits in EMRS. RDQS and RDQS are available in x8 components only. If RDQS is enabled in x8 components, the DM

function is disabled. RDQS is active for reads and don’t care for writes :

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-

mal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is

automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset, 200 clock cycles must occur

before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Less clock

cycles may result in a violation of the tAC or tDQSCK parameters.

Output Disable (Qoff)

Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMR(1) is set to

0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to measure IDD

currents during Read operations, without including the output buffer current.

EMR(2)

The Extended mode Register EMR(2) controls refresh related features. The default value of EMRS(2) is not defined; therefore,

EMR(2) must be writeen after power-up for proper operation. EMR(2) is written by asserting low on CS,RAS,CAS,WE, high on

BA1 and low on BA0, while controlloing the states of address pins A0~A15. The DDR2 SDRAM should be in all bank percharge

with CKE already high prior to writing into EMR(2). The mode register set command cycle time (tMRD) must be satisfied to

complete the write operation to EMR(2). Mode register contents can be changed using the same command and clock cycle

requirements during normal operation as long as all banks are in the percharge state.

EMRS Stobe Function Matrix Signaling

A11

(RDQS Enable)

A10

(DQS Enable) RDQS/DM RDQS DQS DQS

0 (Disable) 0 (Enable) DM Hi-Z DQS DQS differential DQS signals

0 (Disable) 1 (Disable) DM Hi-Z DQS Hi-Z single-ended DQS signals

1 (Enable) 0 (Enable) RDQS RDQS DQS DQS differential DQS signals

1 (Enable) 1 (Disable) RDQS Hi-Z DQS Hi-Z single-ended DQS signals

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

EMR(2) Extended Mode Register Operation Table (Address Input For Mode Set)

EMR(3) Extended Mode Registers

The Extended Mode Registers EMR(3) are reserved for future use and all bits except BA0 and BA1 must be programmed to 0

when setting the mode register during initialization.

Address Field

Extended Mode

1PASR***

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

A2 A1 A0 Partial Array Self Refresh

0 0 0 Full array

0 0 1 Half Array (BA[2:0]=000, 001, 010, &011)

0 1 0 Quarter Array (BA[2:0]=000&001)

0 1 1 1/8th array (BA[2:0] = 000)

1 0 0 3 / 4 array (BA[2:0]=010,011,100,101,110, &111)

1 0 1 Half array (BA[2:0]=100, 101, 110, & 111)

1 1 0 Quarter array (BA[2:0]=110&111)

1 1 1 1/8th array (BA[2:0]=111)

0SRF

0 Disable

1 Enable** (85C Tcase 95C)

High Temperature Self-Refresh Rate Enable

A12

BA2

BA0 MRS mode

0 MRS

1EMR(1)

BA1

0EMR(2)

EMR(3)

* The rest bits in EMRS(2) is reserved for future use and all bits in EMRS(2) except A0-A2,A7,BA0, and

BA1 must be programmed to 0 when setting EMRS(2) during initialization.

** DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0].

*** Optional. If PASR(Partial Array Self Refresh) is enabled, data located in areas of the array beyond the

spec. location will be lost if self refresh is entered.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being

issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be

carefully controlled depending on system environment.

Start

EMRS: Drive (1)

DQ & DQS High; DQSLow

Test

EMRS :

Enter Adjus t Mode

BL=4 cod e inpu t to all DQs

Inc, Dec, or NOP

EMRS: Drive(0)

DQ & DQS Low; DQS High

Test

EMRS :

Enter Adjust Mode

BL =4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

ALL OK ALL OK

Need Calibration

EMRS: OCD calibration mode exit

MRS should be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

EMRS: OCD calibration mode exit

Need Calibration

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the following EMR(1) mode. In drive mode all outputs are driven out by DDR2

SDRAM and drive of RDQS is dependent on EMR(1) bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS)

signals are driven high and all DQS (and RDQS) signals are driven low. In Drive(0) mode, all DQ, DQS (and RDQS) signals are

driven low and all DQS (and RDQS) signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In

case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal tem-

perature and voltage conditions. Output driver characteristics for OCD calibration default are specified in the following table.

OCD applies only to normal full strength output drive setting defined by EMR(1) and if half strength is set, OCD default driver

characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not

applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMR(1) commands not intended

to adjust OCD characteristics must specify A7~A9 as ’000’ in order to maintain the default or calibrated value.

Off- Chip-Driver program

OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMR(1) command along with a 4 bit burst code to DDR2

SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating

OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at bit time 0, DT1

at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD

calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for

adjustment can be up to 16 and when the limit is reached, further increment or decrement code has no effect. The default set-

ting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set

value must be applied.

Off- Chip-Driver Adjust Program

For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing dia-

gram. Input data pattern for adjustment, DT0 - DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or inter-

leave).

A9 A8 A7 Operation

000OCD calibration mode exit

001Drive(1) DQ, DQS, (RDQS) high and DQS, (RDQS) low

010Drive(0) DQ, DQS, (RDQS) low and DQS, (RDQS) high

100Adjust mode

111OCD calibration default

4 bit burst code inputs to all DQs Operation

DT0 DT1 DT2 DT3 Pull-up driver strength Pull-down driver strength

0 0 00NOP (no operation) NOP (no operation)

0 0 01Increase by 1 step NOP

0 0 10Decrease by 1 step NOP

0 1 00NOP Increase by 1 step

1 0 00NOP Decrease by 1 step

0 1 01Increase by 1 step Increase by 1 step

0 1 10Decrease by 1 step Increase by 1 step

1 0 01Increase by 1 step Decrease by 1 step

1 0 10Decrease by 1 step Decrease by 1 step

Other Combinations Reserved Reserved

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

OCD Adjust Mode

Drive Mode

Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance before

OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all

output drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.

OCD adjust mode

OCD calibration

mode exit

EMRS

CMD NOP NOP NOP NOP NOP

DQS

tDS tDH

DT0 DT1 DT2 DT3

EMRS NOP

DQS

NOP NOP NOPNOP EMRS

CMD

DQ_in

NOP

DQS_in

CK, CK

EMRS NOP

Enter Drive Mode OCD calibration

mode exit

NOP

DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0

DQS high for Drive(0)

DQS high for Drive(1)

tOIT tOIT

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

On-Die Termination (ODT)

ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQ, DQS, DQS,

RDQS, RDQS, and DM signal for x4/x8 configurations via the ODT control pin. For x16 configuration ODT is applied to each

DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via the ODT control pin. The ODT feature is designed to improve sig-

nal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any

or all DRAM devices.

The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode.

Funtional Prepresentation of ODT

Switch sw1, sw2, or sw3 is enabled by the ODT pin.

Selection between sw1, sw2, or sw3 is determined by “Rtt (nominal)” in EMR.

Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins.

DRAM

Input

Buffer

Input

Rval1

Rval2

sw1

sw2

VDDQ VDDQ

VSSQ VSSQ

Rval3

sw3

VDDQ

VSSQ

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

ODT related timings

MRS command to ODT update delay

During normal operation the value of the effective termination resistance can be changed with an EMRS command. The update

of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of tMOD win-

dow for proper operation. The timings are shown in the following timing diagram.

However, to prevent any impedance glitch on the channel, the following conditions must be met.

- tAOFD must be met before issuing the EMRS command.

- ODT must remain LOW for the entire duration of tMOD window, until tMOD ,max is met.

Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turned on the ODT. Fol-

lowing timing diagram shows the proper Rtt update procedure.

ntire duration of tMOD window for proper operation. The timings are shown in the following timing diagram.

CKE

Rtt

CK, CK

tIS

CMD

tAOFD

EMRS NOP NOP NOP NOP NOP

tMOD, min

tMOD, max

Old setting Updating New setting

EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)

Setting in this diagram is the Register and I/O setting, not what is measured from outside.

CKE

Rtt

CK, CK

tIS

CMD

tAOFD

EMRS NOP NOP NOP NOP

tMOD, max

Old setting New setting

EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)

Setting in this diagram is the Register and I/O setting, not what is measured from outside.

tAOND

NOP

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

ODT On/Off timings

ODT timing for active/standby mode

ODT Timing for Power-down mode

Rtt

tIS

tAOND tAOFD (2. 5 tck)

T-3 T-5

T-4T-0 T-2

T-1 T-6

CKE

Internal

Term Res.

ODT

CK, CK

tAON, min

tAON, max

tAOF, min

tAOF, max

tIS

tAOFPD,max

Rtt

tAONPD,min

tAOFPD,min

tAONPD,max

T5 T6

T4T3T2

T0 T1

CKE

ODT

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The

bank addresses BA0 ~ BA2 are used to select the desired bank. The row addresses A0 through A13 are used to determine

which row to activate in the selected bank for x4 and x8 organised components. For x16 components row addresses A0 through

A12 have to be applied. The Bank Activate command must be applied before any Read or Write operation can be executed.

Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Pre-

charge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then

additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The

additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, and 4 are supported. Once

a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The

bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive

Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to

any other bank, is the Bank A to Bank B delay time (tRRD).

In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain

restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the number of sequen-

tial ACTcommands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The

rules are list as follow:

* 8 bank device sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window. Con-

veting to clocks is done by dividing tFAW by tCK and rounding up to next integer value. As an example of the rolling window, if

(tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate com-

mands may be issued in clock N+1 through N+9.

*8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will equal to tRP+tCK, where

tRP is the value for a single bank pre-charge.

Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2

Address NOP

Command

T0 T2T1 T3 T4

Col. Addr.

Bank A

Row Addr.

Bank B

Col. Addr.

Bank B

Internal RAS-CAS delay tRCDmin.

Bank A to Bank B delay tRRD.

Activate

Bank B

Read A

Posted CAS

Activate

Bank A

Read B

Posted CAS

Read A

Begins

Row Addr.

Bank A

Addr.

Bank A

Precharge

Bank A NOP

Addr.

Bank B

Precharge

Bank B

Row Addr.

Bank A

Activate

Bank A

tRP Row Precharge Time (Bank A)

tRC Row Cycle Time (Bank A)

Tn Tn+1 Tn+2 Tn+3

ACT

RAS-RAS delay tRRD.

tRAS Row Active Time (Bank A)

additive latency AL=2

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read and Write Commands and Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS

low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation

(WE high) or a write operation (WE low). The DDR2 SDRAM provides a fast column access operation. A single Read or Write

Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is restricted to

specific segments of the page length.

A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL=8 set-

ting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a

write with 4 bit burst boundary respectively. The minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write

cycles.

Posted CAS

Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In

this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate com-

mand (or any time during the RAS to CAS delay time, tRCD, period). The command is held for the time of the Additive Latency

(AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the CAS latency (CL). Therefore if a user

chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0 must be written into the EMR(1). The

Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive

Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency

is also defined as RL = AL + CL.

Example of posted CAS operation:

Read followed by a write to the same bank:

AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4

Dout0 Dout1 Dout2

Dout3

CMD

023 4 5 6 7 8 9 10 11 12-1 1

>=tRCD

AL = 2

RL = AL + CL = 5

CL = 3

WL = RL -1 = 4

Din0 Din1 Din2 Din3

PostCAS1

DQS,

DQS

Activate Read Write

Bank A Bank A Bank A

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read followed by a write to the same bank:

AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4

Activate

Bank A

023 4 5 6 7 8 9 10 11 12-1 1

CMD

>=tRCD

RL = AL + CL = 3

WL = RL – 1 = 2

PostCAS5

DQS,

DQS

Read

Bank A

Din0 Din1 Din2 Din3

Dout0 Dout1 Dout2 Dout3

Write

Bank A

CK, CK

AL=0

CL=3

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory

locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address

ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst

type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seam-

less burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when

burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see

the “Burst Interruption “ section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM

devices.

Burst Length and Sequence

Burst Length Starting Address

(A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal)

x 0 0 0, 1, 2, 3 0, 1, 2, 3

x 0 1 1, 2, 3, 0 1, 0, 3, 2

x 1 0 2, 3, 0, 1 2, 3, 0, 1

x 1 1 3, 0, 1, 2 3, 2, 1, 0

0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Note: 1) Page length is a function of I/O organization

256Mb X 4 organization (CA0-CA9, CA11); Page Size = 1kByte; Page Length = 2048

128Mb X 8 organization (CA0-CA9 ); Page Size = 1kByte; Page Length = 1024

64Mb X 16 organization (CA0-CA9); Page Size = 2kByte; Page Length = 1024

2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR

or DDR components

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock.

The address inputs determine the starting column address for the burst. The delay from the start of the command until the data

from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven

low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising

edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source syn-

chronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register

Set (MRS). The AL is defined by the Extended Mode Register Set (EMR(1))

Basic Burst Read Timing

Examples:

Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)

DQS,

DQS

RPRE

DQSQmax

RPST

DQSCK

Dout Dout Dout Dout

CLK, CLK

CLK

DO-Read

DQSQmax

NOP NOP NOP NOP NOP NOP

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

<= tDQSCK

CMD

BRead523

DQS,

DQS

Post CAS

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8)

Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-

around time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation.

CMD

NOP NOP NOP NOP NOP NOP

DQ's

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 3

CL = 3

NOP

<= tDQSCK

BRead303

DQS,

DQS

Dout A4 Dout A5 Dout A6 Dout A7

CK, CK

NOP Posted CAS

WRITE A NOP NOP NOP NOP

NOP

READ A

Posted CAS

T0 T1

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

NOP

CMD

BRBW514

Tn-1 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5

Din A0 Din A1 Din A2 Din A3

DQS,

DQS

WL = RL - 1 = 4

tRTW(Read to Write turn around time)

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Seamless Burst Read Operation : RL = 5, AL = 2, CL = 3, BL = 4

The seamless burst read operation is supported by enabling a read command at every other clocks for BL=4 operation, and

every 4 clock for BL=8 operation. This operation is allowed regardless of same or different banks as long as the banks are acti-

vated.

NOP NOP NOP NOP NOP NOP

NOP

READ A

Post CAS

READ B

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3

RL = 5

AL = 2 CL = 3

SBR523

CMD

DQS,

DQS

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Write Command

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock.

The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and

is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first

data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS

specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until

the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins

will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst

write to bank precharge is named “write recovery time” (WR) .

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS

“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2

SDRAM pin timing are measured is mode dependent.

Basic Burst Write Timing

Example:.

Burst Write Operation : RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4

DQS,

DQS DQS

DQS

tDQSH tDQSL

tWPRE WPST

Din Din Din Din

tDS tDH

NOP NOP NOP NOP NOP Precharge

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 4

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

<= tDQSS

tWR

Completion of

the Burst Write

DQS,

DQS

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Write Operation : RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4

Burst Write followed by Burst Read : RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4

The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + tWTR

where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery

time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 2

BW322

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

tWR

Completion of

the Burst Write

<= tDQSS

Precharge Bank A

Activate

tRP

DQS,

DQS

CK, CK

NOP NOP NOP NOP

NOP READ A

Post CAS

BWBR

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

AL=2 CL=3

NOP NOP

tWTR

T0 T2T1 T3 T4 T5 T6 T7 T8 T9

Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6

DQS,

DQS

WL = RL - 1 = 4

RL=5

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Seamless Burst Write Operation : RL = 5, WL = 4, BL = 4

The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This operation is

allowed regardless of same or different banks as long as the banks are activated.

NOP NOP NOP NOP NOP NOP

NOP

DIN A0 DIN A1 DIN A2 DIN A3

WRITE A

Post CAS

WL = RL - 1 = 4

WRITE B

Post CAS

DIN B0 DIN B1 DIN B2 DIN B3

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

SBR

DQS,

DQS

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write Data Mask

One write data mask input (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, consistent with the imple-

mentation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional

manner, is internally loaded identically to data bits to insure matched system timing. DM of x4 and x16 bit organization is not

used during read cycles. However, DM of x8 bit organization can be used as RDQS during read cycles by EMR(1) setting.

Write Data Mask Timing

Burst Write Operation with Data Mask : RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3 , BL = 4

DQS,

DQS DQS

DQS

tDQSH tDQSL

tWPRE WPST

DQ Din Din Din Din

tDS DH

don't care

NOP NOP NOP NOP

NOP

WRITE A

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 2

CMD

NOP

tWR

<= tDQSS

Precharge Bank A

Activate

tRP

DQS,

DQS

DIN A0 DIN A1 DIN A3DIN A2

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Interruption

Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the

following conditions:

1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge

Command is prohibited.

2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge

Command is prohibited.

3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings

are prohibited.

4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings

are prohibited.

5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.

6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted.

7. Read burst interruption is allowed by a Read with Auto-Precharge command.

8. Write burst interruption is allowed by a Write with Auto-Precharge command.

9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For

example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the

actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts

with the rising clock after the un-interrupted burst end and not form the end of the actual burst end.

Examples:

Read Burst Interrupt Timing Example : (CL = 3, AL = 0, RL = 3, BL = 8)

NOP NOP NOP NOP NOP

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

RBI

DQS,

DQS

READ B NOP

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write Burst Interrupt Timing Example : ( CL = 3, AL = 0, WL = 2, BL = 8)

NOP NOP NOP NOP

NOP

WRITE A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

WBI

DQS,

DQS

NOP

Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7

WRITE B

CK, CK

NOP

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-

mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-charge

Command can be used to precharge each bank independently or all banks simultaneously. Three address bits

A10, BA0, BA1, and BA2 are used to define which bank to precharge when the command is issued.

Bank Selection for Precharge by Address Bit

Burst Read Operation Followed by a Precharge

Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(RTP,2) - 2 clocks.

For the earliest possible precharge, the Precharge command may be issued on the rising edge which is “Additive Latency (AL)

+ BL/2 clocks” after a Read Command, as long as the minimum tRAS timing is satisfied.

The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the

last 4-bit prefetch of a Read to Precharge command. This time is call tRTP (Read to Precharge). For BL=4 this is the time from

the actual read ( AL after the Read command) to Precharge command. For BL=8 this is the time from AL + 2 clocks after the

Read to the Precharge command.

A10 BA2 BA1 BA0 Precharge

Bank(s)

LOW LOW LOW LOW Bank 0 only

LOW LOW LOW HIGH Bank 1 only

LOW LOW HIGH LOW Bank 2 only

LOW LOW HIGH HIGH Bank 3 only

LOW HIGH LOW LOW Bank 4 only

LOW HIGH LOW HIGH Bank 5 only

LOW HIGH HIGH LOW Bank 6 only

LOW HIGH HIGH HIGH Bank 7 only

HIGH Don’t Care Don’t Care Don’t Care all banks

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Examples:

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP <= 2 clocks

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks

NOP Precharge NOP Bank A

Activate NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 1 CL = 3

RL = 4

>=tRAS CL = 3

>=tRP

DQS,

DQS

NOP

>=tRC

>=tRTP

CK, CK

NOP NOP NOP

Post CAS

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P413(8)

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 1 CL = 3

RL = 4

>=tRAS CL = 3

DQS,

DQS

NOP

>=tRC

>=tRTP

Dout A4 Dout A5 Dout A6 Dout A7

Precharge NOP NOP

first 4-bit prefetch second 4-bit prefetch

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks

Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP <= 2 clocks

NOP NOP NOP Bank A

Activate NOP

NOP

Post CAS

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P523

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 2 CL = 3

RL = 5

>=tRAS CL = 3

>=tRP

Precharge

DQS,

DQS

>=tRC

>=tRTP

CK, CK

NOP NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P624

NOP

AL + BL/2 clocks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 2

CL = 4

RL = 6

>=tRAS CL = 4

Precharge

Bank A

Activate

DQS,

DQS

NOP NOP

>=tRC

>=tRTP

CK, CK

>=tRP

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks

NOP NOP NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

BR-P404(8)

NOP

AL + BL/2 clks + 1

Dout A0 Dout A1 Dout A2 Dout A3

CL = 4

RL = 4

>=tRAS

>=tRP

DQS,

DQS

NOP

>=tRTP

Dout A4 Dout A5 Dout A6 Dout A7

Precharge NOP Bank A

Activate

first 4-bit prefetch second 4-bit prefetch

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Write followed by Precharge

Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay

must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This

delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the Precharge

command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support

any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this

datasheet) and is not the programmed value for tWR in the MRS.

Examples:

Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3

Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

WL = 3

BW-P3

CMD

NOP

DIN

>=tWR

Completion of

the Burst Write

Precharge

NOP

DQS,

DQS

CK, CK

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = 4

BW-P4

CMD

NOP

DIN A0 DIN A1 DIN A2 DIN A3

tWR

Completion of

the Burst Write

Precharge

NOP

DQS,

DQS

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-charge Command

or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS timing accepts one

extra address, column address A10, to allow the active bank to auto-matically begin precharge at the earliest possible moment

during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst

operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or

Write Com-mand is issued, then the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will exe-

cute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency

(CL) clock cycles before the end of the read burst. Auto-Precharge is also implemented for Write Commands.The precharge

operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly

stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read

cycles (dependent upon CAS Latency) thus improving system performance for random data access. The RAS lockout circuit

internally delays thepprecharge operation until the array restore operation has been completed so that the Auto-Precharge

command may be issued with any read or write command.

Burst Read with Auto-Precharge

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts

an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min)

and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until

tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until

tRTP(min) is satisfied.

In case the internal precharge is pushed out by tRTP

, tRP starts at the point where the internal precharge happens (not at the

next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate

command becomes AL + tRTP + tRP

. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL +

2 + tRTP + tRP

. Note that both parameters tRTP and tRP have to be rounded up to the next integer value. In any event internal pre-

charge does not start earlier than two clocks after the last 4-bit prefetch.

A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously:

(1) The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Examples:

Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit)

RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks

Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit):

RL = 5 ( AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

CMD

BR-AP5231

A10 ="high"

tRP

Auto-Precharge Begins

DQS,

DQS

tRAS

tRCmin.

NOP

AL + BL/2

CK, CK

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

CMD

BR-AP5232

A10 ="high"

tRP

Auto-Precharge Begins

DQS,

DQS

tRC

tRAS(min)

NOP

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks

Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 4, tRTP > 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

AL = 1 CL = 3

NOP

CMD

BR-AP413(8)2

A10 ="high" tRP

Auto-Precharge Begins

DQS,

DQS

NOP

Dout A4 Dout A5 Dout A6 Dout A7

first 4-bit prefetch second 4-bit prefetch

>= tRTP

AL + BL/2

CK, CK

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

AL = 1 CL = 3

NOP

CMD

BR-AP4133

A10 ="high"

Auto-Precharge Begins

DQS,

DQS

NOP

first 4-bit prefetch

tRTP

AL + tRTP + tRP

tRP

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM auto-

matically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR), pro-

grammed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of the

write burst may be reactivated if the following two conditions are satisfied.

(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Examples:

Burst Write with Auto-Precharge (tRC Limit) : WL = 2, tDAL = 6 (WR = 3, tRP = 3) , BL = 4

NOP NOP NOP NOP NOP Bank A

Activate

NOP

WRITE

w/AP

T0 T2T1 T3 T4 T5 T6 T7

NOP

CMD

BW-AP223

A10 ="high"

tRP

Auto-Precharge Begins

DIN A0 DIN A1 DIN A2 DIN A3

WL = RL-1 = 2 WR

tRCmin.

DQS,

DQS

Completion of the Burst Write

tDAL

>=tRASmin.

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Burst Write with Auto-Precharge (tWR + tRP Limit) : WL = 4, tDAL = 6 (tWR = 3, tRP = 3), BL = 4

Precharge & auto precharge clarification

From Command To Command Minimum Delay between “From

command” to “to command” Units Note

Read

Precharge (to same Bank as Read) AL + BL/2 + max(RTP,2) - 2 tCK 1,2

Precharge All AL + BL/2 + max(RTP,2) - 2 tCK 1,2

Read w/AP

Precharge ( to same Bank as Read wAP) AL + BL/2 + max(RTP,2) - 2 tCK 1,2

Precharge Al AL + BL/2 + max(RTP,2) - 2 tCK 1,2

Write

Precharge (to same Bank as Write) WL + BL/2 + tWR tCK 2

Precharge Al WL + BL/2 + tWR tCK 2

Write w/AP

Precharge (to same bank as Write w/AP) WL + BL/2 + WR tCK 2

Precharge Al WL + BL/2 + WR tCK 2

Precharge

Precharge (to same bank as Precharge) 1 tCK 2

Precharge Al 1 tCK 2

Precharge All

Precharge 1 tCK 2

Precharge Al 1 tCK 2

Note:

1) RTP[cycles] = RU{tRTP(ns)/tCK(ns)}, where RI stands for round up.

2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank pre-

charge or precharge all, issued to that bank. The precharge period is satisfied after tRP or tRPa depending on the latest

precharge command issued to that bank.

NOP NOP NOP NOP NOP Bank A

Activate

NOP

Posted CAS

WRITE w/AP

7T12

NOP

CMD

BW-AP423

A10 ="high"

tRP

Auto-Precharge Begins

DIN

WL = RL-1 = 4 tWR

>=tRC

Completion of the Burst Write

DQS,

DQS

tDAL

>=tRAS

CK, CK

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

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Refresh

SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways : by an explicit

Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows into the roll-

ing 64 ms interval defined the average refresh interval tREFI, which is a guideline to controlles for distributed refresh timing. For

example, a 512Mbit DDR2 SDRAM has 8192 rows resulting in a tREFI of 7,8 µs.

Auto-Refresh Command

Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must be issued each

time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits

”Don’t Care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an average periodic inter-

val of tREFI (maximum).

When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Auto-Refresh mode. All

banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the Auto-Refresh Com-

mand can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the external

address bus is required once this cycle has started.

When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto-

Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to

the Auto-Refresh cycle time (tRFC).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is

provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum

absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI.

T0 T2T1 T3

CK, CK

CMD

Precharge

> = t

NOP AUTO

REFRESH ANYNOP

> = t

RFC

> = t

RFC

AUTO

REFRESH

NOP NOP NOP

CKE

"high"

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

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Self-Refresh Command

The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh

mode, the DDR2 SDRAM retains data without external clocking.

The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined

by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing

Self Refresh command, by either driving ODT pin low or using EMR(1) command. Once the command is registered, CKE must

be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered Self-Refresh mode all of the exter-

nal control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The

user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, how-

ever, the clock must be restarted and stable before the device can exit Self-Refresh operation. Once Self-Refresh Exit com-

mand is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to

the device. CKE must remain high for the entire Self-Refresh exit period (tXSNR or tXSRD) for proper operation. NOP or DESE-

LECT commands must be registered on each positive clock edge during the Self-Refresh exit interval. Since the ODT function

is not supported during Self-Refresh operation, ODT has to be turned off tAOFD before entering Self-Refresh Mode and can be

turned on again when the tXSRD timing is satisfied.

* = Device must be in the “All banks idle” state to entering Self Refresh mode.

ODT must be turned off prior to entering Self Refresh mode.

tXSRD (>=200 tCK) has to be satisfied for a Read or a Read with Auto-Precharge command.

tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command,

CK/CK

T1 T3T2

CK/CK may

be halted

CK/CK must

be stable

CKE

>=tXSRD

>= tXSNR

Tn TrTmT5

tRP*

tis

tAOFD

CMD

Self Refresh

Entry NOP Non-Read

Command

Read

Command

tis

ODT

where tXSNR is defined as tRFC + 10ns.

The miminum CKE low time is defined by the tCKEmin. timing parameter.

Since CKE is an SSTL input, VREF must be maintained during Self Refresh.

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Power-Down

Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not allowed

to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is

allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is in progress,

but power-down IDD specification will not be applied until finishing those operations.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down

mode for proper read operation.

If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs

when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different

power saving modes can be selected within the MRS register, address bit A12. When A12 is set to “low” this mode is referred

as “standard active power-down mode” and a fast power-down exit timing defined by the tXARD timing parameter can be used.

When A12 is set to “high” this mode is referred as a power saving “low power active power-down mode”. This mode takes

longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied.

Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon

entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-

down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all

other input signals are “Don’t Care”. Power-down duration is limited by 9 times tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid,

executable command can be applied with power-down exit latency, tXP

, tXARD or tXARDS, after CKE goes high. Power-down exit

latencies are defined in the AC spec table of this data sheet.

Power-Down Entry

Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a pre-

charge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh command

or MRS / EMR(1) command when tMRD is satisfied.

Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the

burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge command is

allowed after RL + BL/2 is satisfied.

Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a

write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is satisfied.

In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command has

been executed, which is WL + BL/2 + WR starting from the write with Auto-Precharge command. In case the DDR2 SDRAM

enters the Precharge Power-down mode.

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Examples:

Active Power-Down Mode Entry and Exit after an Activate Command

Active Power-Down Mode Entry and Exit after a Read Burst: RL = 4 (AL = 1, CL =3), BL = 4

Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed

state in the MRS, address bit A12.

NOP NOP

Activate

T0 T2T1

CMD

NOP

Tn Tn+1

CKE

Active

Power-Down

Entry

NOP NOP

Act.PD 0

tIS

Tn+2

tIS

Active

Power-Down

Exit

Valid

Command

tXARD or

tXARDS *)

CK, CK

Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed

state in the MRS, address bit A12.

NOP NOP

READ

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

CL = 3

CMD

DQS,

DQS

NOP NOP NOP NOP NOP NOP

Tn Tn+1

CKE

AL = 1

Active

Power-Down

Entry

RL + BL/2

NOP NOP

Act.PD 1

tIS

Tn+2

tIS

Active

Power-Down

Exit

Valid

Command

tXARD or

tXARDS *)

CK, CK

READ w/AP

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1Gb DDR2 SDRAM D-Die

REV 1.3

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Active Power-Down Mode Entry and Exit after a Write Burst: WL = 2, tWTR = 2, BL = 4

Precharge Power Down Mode Entry and Exit

Note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed

state in the MRS, address bit A12.

NOP NOP

WRITE

T0 T2T1 T3 T4 T5 T6 T7

CMD

DQS,

DQS

NOP NOP NOP NOP NOP NOP

Tn Tn+1

CKE

WL = RL - 1 = 2

Active

Power-Down

Entry

WL + BL/2 + tWTR

NOP NOP

Act.PD 2

tWTR

tIS

Tn+2

tIS

Valid

Command

Active

Power-Down

Exit

tXARD or

tXARDS *)

CK, CK

DIN

tXP

NOP NOP

Precharge

T0 T2T1

CMD

NOP NOP

Tn Tn+1

CKE

Precharge

Power-Down

Entry

NOP NOP

PrePD

tIS

Tn+2

tIS

Precharge

Power-Down

Exit

Valid

Command

tRP

NOP

*) "Precharge" may be an external command or an internal

precharge following Write with AP.

CK, CK

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No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Oper-

ation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Com-

mand is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command

will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is

brought high, the RAS, CAS, and WE signals become don’t care.

Input Clock Frequency Change

During operation the DRAM input clock frequency can be changed under the following conditions:

a) During Self-Refresh operation

b) DRAM is in Precharge Power-down mode and ODT is completely turned off.

The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be allready turned off and CKE must be at

a logic “low” state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency can

be changed. A stable new clock frequency has to be provided, before CKE can be changed to a “high” logic level again. After

tXP has been satisfied a DLL RESET command via EMR(1) has to be issued. During the following DLL re-lock period of 200

clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency.

Example:

Input frequency change during Precharge Power-Down mode

NOP NOP

T0 T2T1 T3 T4 Tx Tx+1 Ty

NOP NOP NOP NOP NOP DLL

RESET

Ty+2 Ty+3

Frequency Change

occurs here

NOP NOP

Frequ.Ch.

tXP

Stable new clock

before power-down exit

CK, CK

tRP

tAOFD

Minimum 2 clocks

required before

changing the frequency

Ty+1

NOP Valid

Command

200 clocks

ODT is off during

DLL RESET

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1Gb DDR2 SDRAM D-Die

REV 1.3

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Asynchronous CKE Low Event

DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously drops

“low” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event occurs, the

memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the input of DRAM

before CKE is raised “high” again. The DRAM must be fully re-initialized as described the the initialization sequence (section

2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for

tdelay specification.

Asynchronous CKE Low Event

CKE

CKE drops low due to an

asynchronous reset event

Clocks can be turned off after

this point

tdelay

CK, CK

stable clocks

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Truth Table

Command Truth Table

Function

CKE

CS RAS CAS WE

BA0

BA2

A13-A11 A10 A9 - A0 Notes

Cycle

Current

Cycle

(Extended) Mode Register Set H H L L L L BA OP Code 1, 2

Auto-Refresh H H L L L H X X X X 1

Self-Refresh Entry H L L L L H X X X X 1,8

Self-Refresh Exit L H H X X X X X X X 1,7,8

Single Bank Precharge H H L L H L BA X L X 1,2

Precharge all Banks H H L L H L X X H X 1

Bank Activate H H L L H H BA Row Address 1,2

Write H H L H L L BA Column L Column 1,2,3

Write with Auto-Precharge H H L H L L BA Column H Column 1,2,3

Read H H L H L H BA Column L Column 1,2,3

Read with Auto-Precharge H H L H L H BA Column H Column 1,2,3

No Operation H X L H H H X X X X 1

Device Deselect H X H X X X X X X X 1

Power Down Entry H L

H X X X

X X X X 1,4

L H H H

Power Down Exit L H

H X X X

X X X X 1,4

L H H H

1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.

2. Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BxA selects an (Extended) Mode

3. Burst reads or writes at BL = 4 cannot be terminated. See sections “Reads interrupted by a Read” and “Writes inter-

rupted by a Write” insection for details.

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by

the refresh requirements outlined .

5. The state of ODT does not affect the states decribed in this table. The ODT function is not available during Self

Refresh.

6. “X” means “H or L (but a defined logic level)”.

7. Self refresh exit is asynchronous.

8. Vref must be maintained during Self Refresh operation.

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Clock Enable (CKE) Truth Table for Synchronous Transistions

Data Mask (DM) Truth Table

Current State2

CKE

Command (N) 3

RAS, CAS, WE, CS

Action (N) 3Notes

Cycle 1

(N-1)

Current

Cycle 1

(N)

Power-Down

L L X Maintain Power-Down 11, 13, 15

L H DESELECT or NOP Power-Down Exit 4, 8, 11, 13

Self Refresh

L L X Maintain Self Refresh 11, 15, 16

L H DESELECT or NOP Self Refresh Exit 4, 5, 9, 16

Bank(s)

Active H L DESELECT or NOP Active Power-Down Entry 4,8,10,11,13

All Banks Idle

H L DESELECT or NOP Precharge Power-Down Entry 4,8,10,11,13

H L AUTOREFRESH Self Refresh Entry 6, 9, 11,13

Any State other

than listed above H H Refer to the Command Truth Table 7

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.

3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).

4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.

5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occuring during the tXSNR

period.

Read commands may be issued only after tXSRD (200 clocks) is satisfied.

6. Self Refresh mode can only be entered from the All Banks Idle state.

7. Must be a legal command as defined in the Command Truth Table.

8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

9. Valid commands for Self Refresh Exit are NOP and DESELCT only.

10. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,

Precharge or Refresh operations are in progress. See section 2.8 “Power Down” and section 2.7.2 “Self Refresh Com-

mand” for a detailed list of restrictions.

11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by

the refresh requirements.

14. CKE must be maintained high while the device is in OCD calibration mode.

15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven

high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR(1)).

16. Vref must be maintained during Self Refresh operation.

Name (Function) DM DQs Notes

Write Enable L Valid 1

Write Inhibit H X 1

1. Used to mask write data; provided coincident with the corresponding data.

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Operating Conditions

Absolute Maximum Ratings

DRAM Component Operating Temperature Range

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to VSS -1.0 to + 2.3 V 1,3

VDDQ Voltage on VDDQ pin relative to VSS -0.5 to + 2.3 V 1,3

VDDL Voltage on VDDL pin relative to VSS -0.5 to + 2.3 V 1,3

VIN, VOUT Voltage on any pin relative to VSS -0.5 to + 2.3 V 1

TSTG Storage Temperature -55 to + 100 oC1, 2

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.

3. When VDD, VDDQ, and VDDL are less than 500mV, Vref may be equal to or less than 300mV.

Symbol Parameter Rating Units Notes

TOPER Operating Temperature 0 to 85 oC 1, 2

Note:

1. Operating temperature is the case surface temperature on the center/top side of the DRAM.

2. The operation temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature

range, even if it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During

operation, the DRAM case temperature must be maintained between 0-85 degree C under all other specification parameter. However,

in some applications, it is desirable to operate the DRAM up to 95 degree C case temperature. Therefore, two spec may exist.

Supporting 0-85C with full JEDEC AC & DC spec. This is the minimum requirements for all operating temperature options.

This is an optional feature and not required. Supporting 0-85C and being able to extend to 95C with doubling auto-refresh command in

frequency to a 32ms period (tRFI=3.9us)

Currently the period Self-Refresh interval is hard coded within the DRAM to a vendor specific value. There is a migration plan to support

higher temperature Self-Refresh entry via the control of EMR(2) bit A7.

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AC & DC Operating Conditions

DC Operating Conditions

Recommended DC Operating Conditions

ODT DC Electrical Characteristrics:

Symbol Parameter

Rating

Units Notes

Min. Typ. Max.

VDD Supply Voltage 1.425 1.5 1.6275 V 1

VDDDL Supply Voltage for DLL 1.425 1.5 1.6275 V 5

VDDQ Supply Voltage for Output 1.425 1.5 1.6275 V 1,5

VREF Input Reference Voltage 0.49 * VDDQ 0.5 * VDDQ 0.51 * VDDQ V 2, 3

VTT Termination Voltage VREF - 0.04 VREF VREF + 0.04 V 4

1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.

2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is

expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc).

4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF

and must track variations in die dc level of VREF.

5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ, and VDDL tied together.

Parameter / Condition Symbol min. nom. max. Units Notes

Rtt eff. impedance value for EMR(1)(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 ohms 1

Rtt eff. impedance value for EMR(1)(A6,A2)=0,1; 150 ohm Rtt2(eff) 120 150 180 ohms 1

Rtt eff. impedance value for EMR(1)(A6,A2)=1,1; 50 ohm Rtt3(eff) 40 50 60 ohms 1

Deviation of VM with respect to VDDQ / 2 delta VM- 6.00 +6.00 % 2

1) Measurement Definition for Rtt(eff):

Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively.

Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac))

2) Measurement Defintion for VM:

Measure voltage (VM) at test pin (midpoint) with no load:

delta VM =(( 2* VM / VDDQ) - 1 ) x 100%

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DC & AC Logic Input Levels

DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMR(1)

“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2

SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the

rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the

crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterisation.

In single ended mode, the DQS (and RDQS) signals are internally disabled and don’t care.

Single-ended DC & AC Logic Input Levels

Single-ended AC Input Test Conditions

Symbol Parameter

DDR2-533 DDR2-667

Units

Min. Max. Min. Max.

VIH (dc) DC input logic high VREF + 0.125 VDDQ * VREF + 0.125 VDDQ * V

VIL (dc) DC input low - 0.3 VREF - 0.125 - 0.3 VREF - 0.125 V

VIH (ac) AC input logic high VREF + 0.250 VDDQ * VREF + 0.200 VDDQ * V

VIL (ac) AC input low -0.3 VREF - 0.250 -0.3 VREF - 0.200 V

* VDDQ + 250mV is permitted, provided that 1.8V is not exceeded.

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1, 2

VSWING(max) Input signal maximum peak to peak swing 1.0 V 1, 2

SLEW Input signal minimum slew rate 1.0 V / ns 3, 4

1. This timing and slew rate definition is valid for all single-ended signls execpt tis, tih, tds, tdh.

2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.

3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges

and the range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure.

4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac)

to VIL(ac) on the negative transitions.

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Differential DC and AC Input and Output Logic Levels

Symbol Parameter min. max. Units Notes

VID(ac) AC differential input voltage 0.5 VDDQ + 0.6 V 1

VIX(ac) AC differential cross point input voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

VOX(ac) AC differential cross point output voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 3

Notes:

1) VID(ac) specifices the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS, and

UDQS.

2) VIX(ac) specifices the input differential voltage lVTR-VCPl required for switching, where VTR is the true input (such as CK, DQS,

LDQS, or UDQS) level and VCP is the complementary input (such CK, DQS, LDQS, or UDQS ) level. The minimum value is equal to

VIH(DC) - VIL(DC).

3) The typical value of VOX(AC) is expected to be about 0.5VDDQ of the transmitting device and VOX(AC) is expected to track varia-

tions in VDDQ. VOX(AC) indicates the voltage at which differential signals must cross.

Crossing Point

VDDQ

VSSQ

VID

VIX or VOX

VTR

VCP

SSTL18_3

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

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Output Buffer Levels

Output AC Test Conditions

Output DC Current Drive

OCD Default Setting Table

Symbol Parameter Units Notes

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

1. The VDDQ of the device under test is referenced.

Symbol Parameter Units Notes

IOH(dc) Output Minimum Source DC Current, nominal -13.4 mA 1, 3, 4

IOL(dc) Output Minimum Sink DC Current, nominal 13.4 mA 2, 3, 4

Symbol Description min. nominal max. Unit Notes

-Pull-up / Pull down mismatch 0 - 4 Ohms 6

-Output Impedance step size for OCD

calibration

0 - 1.5 Ohms 1,2,3

SOUT Output Slew Rate 0.8 - 5.0 V / ns 1,4,5,7,8

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

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Full Strength Pullup Driver Characteristics

-1 2 0 . 0 0

-1 0 0 . 0 0

-8 0 . 0 0

-6 0 . 0 0

-4 0 . 0 0

-2 0 . 0 0

0 . 0 0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

V o ut (V )

I out (mA)

M inim um

M a xim u m

Voltage (V) Minimum Maximum

0 0.00 0.00

0.1 -3.49 -7.95

0.2 -7.70 -15.90

0.3 -11.76 -23.85

0.4 -15.40 -31.80

0.5 -18.60 -39.75

0.6 -21.30 -47.70

0.7 -23.27 -55.55

0.8 -24.10 -62.95

0.9 -24.73 -69.55

1 -25.23 -75.35

1.1 -25.65 -80.35

1.2 -26.02 -84.55

1.3 -26.35 -87.95

1.4 -26.65 -90.70

1.5 -26.93 -93.00

1.6 -27.20 -95.05

1.7 -27.46 -97.05

1.8 -27.71 -99.05

1.9 -27.95 -101.05

Current (mA)

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Full Strength Pulldown Driver Characteristics

0.00

20.00

40.00

60.00

80.00

100.00

120.00

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Vout (V)

I out (mA)

Minimum

Maximum

Voltage (V) Minimum Maximum

0 0.00 0.00

0.1 3.49 7.95

0.2 7.70 15.90

0.3 11.76 23.85

0.4 15.40 31.80

0.5 18.60 39.75

0.6 21.30 47.70

0.7 23.27 55.55

0.8 24.10 62.95

0.9 24.73 69.55

1 25.23 75.35

1.1 25.65 80.35

1.2 26.02 84.55

1.3 26.35 87.95

1.4 26.65 90.70

1.5 26.93 93.00

1.6 27.20 95.05

1.7 27.46 97.05

1.8 27.71 99.05

1.9 27.95 101.05

Current (mA)

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Reduced Strength Pulldown Driver Characteristics

Voltage (V) Minimum Maximum

0 0.00 0.00

0.1 1.72 4.77

0.2 3.44 9.54

0.3 5.16 14.31

0.4 6.76 19.08

0.5 8.02 23.85

0.6 8.84 28.62

0.7 9.31 33.33

0.8 9.64 37.77

0.9 9.89 41.73

1 10.09 45.21

1.1 10.26 48.21

1.2 10.41 50.73

1.3 10.54 52.77

1.4 10.66 54.42

1.5 10.77 55.80

1.6 10.88 57.03

1.7 10.98 58.23

1.8 59.43

1.9 60.63

0.00

10.00

20.00

30.00

40.00

50.00

60.00

70.00

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

Vout (V)

I out (mA)

Minimum

Maximum

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Reduced Strength Pullup Driver Characteristics

Voltage (V) Minimum Maximum

0 0.00 0.00

0.1 -1.72 -4.77

0.2 -3.44 -9.54

0.3 -5.16 -14.31

0.4 -6.76 -19.08

0.5 -8.02 -23.85

0.6 -8.84 -28.62

0.7 -9.31 -33.33

0.8 -9.64 -37.77

0.9 -9.89 -41.73

1 -10.09 -45.21

1.1 -10.26 -48.21

1.2 -10.41 -50.73

1.3 -10.54 -52.77

1.4 -10.66 -54.42

1.5 -10.77 -55.80

1.6 -10.88 -57.03

1.7 -10.98 -58.23

1.8 -59.43

1.9 -60.63

-70.00

-60.00

-50.00

-40.00

-30.00

-20.00

-10.00

0.00

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

Vout (V)

I out (mA)

Minimum

Maximum

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Calibrated Output Driver V-I Characteristics

DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure out-

lined in the Off-Chip Driver (OCD) Impedance Adjustment. The following tables show the data in tabular format suitable for input

into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values rep-

resent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal condi-

tions only (i.e. perfect calibration procedire, 1.5 ohm maximum step size guarantedd by specification). Real system calibration

error needs to be added to these values. It must be understodd that these V-I curves are represented here or in supplier IBIS

models need to be adjusted to a wider range as a result of any system calibration error. Since this a system specific phenom-

ena, it cannot be quantified here. the values in the calibrated tables represent just the DRAM portion of uncertainty while looking

at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the

default device characterisitcs tables and figure. in such a situation, the timing paramters in the specification cannot be guaran-

teed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default

values at all times. If this can’t be guaranteed by the system calibration procedure, re-calibration policy and uncertainty with DQ

to DQ variation, the it is recommende that only the default values to be used. The nominal maximum ad minmum values repre-

sent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal con-

dition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much

as from the nominal minimum to the nominal maximum or vice versa.

Full Strength Calibrated Pulldown Driver Characteristics

Full Strength Calibrated Pullup Driver Characteristics

Voltage (V) Nominal Minimum

(21 Ohms)

Nominal Low

(18.75 Ohms)

Nominal

(18 ohms)

Nominal High

(17.25 Ohms)

Nominal Maximum

(15 Ohms)

0.2 9.5 10.7 11.5 11.8 13.3

0.3 14.3 16.0 16.6 17.4 20.0

0.4 18.7 21.0 21.6 23.0 27.0

The driver characteristics evaluetion conditions are:

Nominal 25oC (Tcase) , VDDQ = 1.55 V, typical process

Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.55V, any process

Nominal Minimum Toper(max), VDDQ = 1.475 V, any process

Nominal Maximum 0oC (Tcase), VDDQ = 1.625 V, any process

Voltage (V) Nominal Minimum

(21 Ohms)

Nomal Low

(18.75 Ohms)

Nominal

(18 ohms)

Nomal High

(17.25 Ohms)

Nominal Maximum

(15 Ohms)

0.2 -9.5 -10.7 -11.5 -11.8 -13.3

0.3 -14.3 -16.0 -16.6 -17.4 -20.0

0.4 -18.7 -21.0 -21.6 -23.0 -27.0

The driver characteristics evaluetion conditions are:

Nominal 25oC (Tcase) , VDDQ = 1.55 V, typical process

Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.55V, any process

Nominal Minimum Toper(max), VDDQ = 1.475 V, any process

Nominal Maximum 0oC (Tcase), VDDQ = 1.625 V, any process

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1Gb DDR2 SDRAM D-Die

REV 1.3

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Input / Output Capacitance

Symbol Parameter

DDR2-533 DDR2-667 DDR2-800

Units

min. max. min. max. min. max.

CCK Input capacitance, CK and CK 1.0 2.0 1.0 2.0 1.0 2.0 pF

CDCK Input capacitance delta, CK and CK - 0.25 - 0.25 - 0.25 pF

CI Input capacitance, all other input-only pins 1.0 2.0 1.0 2.0 1.0 1.75 pF

CDI Input capacitance delta, all other input-only pins - 0.25 - 0.25 - 0.25 pF

CIO Input/output capacitance,

DQ, DM, DQS, DQS, RDQS, RDQS 2.5 4.0 2.5 3.5 2.5 3.5 pF

CDIO Input/output capacitance delta,

DQ, DM, DQS, DQS, RDQS, RDQS - 0.5 - 0.5 - 0.5 pF

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

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IDD Specifications and Measurement Conditions

IDD Specifications

Symbol Parameter/Condition I/O

DDR2-533

4-4-4

DDR2-667

5-5-5

DDR2-800

6-6-6

DDR2-800

5-5-5 Unit Notes

max.

IDD0 Operating Current x4/x8

x16

110

110 mA 1, 2

IDD1 Operating Current x4/x8

x16

100

115

100

140

100

140 mA 1, 2

IDD2P Precharge Power-Down Current all 8 8 8 8 mA 1, 2

IDD2N Precharge Standby Current x4/x8

x16

70 mA 1, 2

IDD2Q Precharge Quiet Standby Current: x4/x8

x16

45 mA 1, 2

IDD3P

Active Power-

Down Standby

Current

MRS(12)=0 x4/x8

x16

29 mA 1, 2

MRS(12)=1 x4/x8

x16

13 mA 1, 2

IDD3N Active Standby Current x4/x8

x16

65 mA 1, 2

IDD4R Operating Current Burst Read x4/ x8

x16

100

125

115

140

130

160

130

160 mA 1, 2

IDD4W Operating Current Burst Write x4/ x8

x16

105

100

120

110

135

110

135 mA 1, 2

IDD5 Auto-Refresh Current

(tRFC=tREFI)

x4/ x8

x16

157

173

173 mA 1, 2

IDD6 Self-Refresh Current for standard

products all 9 9 9 9 mA 1, 2

IDD7 Operating Current x4/ x8

x16

132

182

181

215

200

240

200

240 mA 1

Note:

1. IDD specifications are tested after the device is properly initialized. IDD parameters are specified with ODT disabled.

2. Input slew rate = 1 V/ns.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

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IDD Measurement Conditions

Symbol Parameter/Condition

IDD0

Operating Current - One bank Active - Precharge

tCK =tCKmin.; tRC = tRCmin; tRAS = tRASmin; CKE is HIGH, CS is HIGH between valid commands.

Address and control inputs are SWITCHING; Data bus inputs are SWITCHING;

IDD1

Operating Current - One bank Active - Read - Precharge

IOUT = 0 mA; BL = 4, tCK = tCKmin, tRC = tRCmin; tRAS = tRASmin; tRCD = tRCDmin, CL = CLmin.;AL = 0;

CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING,Data bus inputs are SWITCHING;

IDD2P

Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address inputs are STABLE,

Data Bus inputs are FLOATING.

IDD2N

Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs

are SWICHTING; Data bus inputs are SWITCHING.

IDD2Q

Precharge Quiet Standby Current:All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING.

IDD3P(0)

Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE;

Data Bus inputs are FLOATING. MRS A12 bit is set to “0”( Fast Power-down Exit);

IDD3P(1)

Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE;

Data Bus inputs are FLOATING. MRS A12 bit is set to “1”( Slow Power-down Exit);

IDD3N

Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax.; tRP = tRPmin., CKE is HIGH; CS is HIGH

between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING.

IDD4R

Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;

tRAS = tRASmax., tRP = tRPmin., CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data

bus inputs are SWITCHING; IOUT = 0mA.

IDD4W

Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.;

tRAS = tRASmax., tRP = tRPmin.;CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data

Bus inputs are SWITCHING.

IDD5B Burst Auto-Refresh Current: tCK = tCKmin.; Refresh command every tRFC = tRFCmin interval; CKE is HIGH, CS is HIGH

between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD5D Distributed Auto-Refresh Current: tCK = tCKmin.; Refresh command every tREFI interval; CKE is HIGH, CS is HIGH

between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING

IDD6 Self-Refresh Current: CKE £ 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING;

Data Bus inputs are FLOATING.

IDD7

Operating Bank Interleave Read Current:

1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CLmin., AL = tRCDmin. - 1*tCK; tCK = tCKmin., tRC = TRCmin.;

tRRD = tRRDmin; tRCD = 1*tCK, CKE = HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE

during DESELECTS.

2. Timing pattern:

- DDR2 -533 4-4-4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

- DDR2 -667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D

- DDR2 -800 6-6-6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D

- DDR2 -800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D

3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT

1. IDD specifications are tested after the device is properly initialized.

2. IDD parameter are specified with ODT disabled.

3. Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.

4. Definitions for IDD :

LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.);

STABLE is defined as inputs are stable at a HIGH or LOW level

FLOATING is defined as inputs are VREF = VDDQ / 2

SWITCHING is defined as:

Inputs are changing between HIGH and LOW every other clock (once per two clocks) for adress and control signals, and

inputs changing between HIGH and LOW every other clock (once per two clocks) for DQ signals not including mask or strobes

5. Timing parameter minimum and maximum values for IDD current measurements are defined in the following table.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

IDD Measurement Conditions (cont’d)

For testing the IDD parameters, the following timing parameters are used:

Refresh parameters

Parameter Symbol

-37B

DDR2-533

-3C

DDR2-667

-AD

DDR2-800

-AC

DDR2-800 Unit

4-4-4 5-5-5 6-6-6 5-5-5

CAS Latency CL 4 5 6 5 tCK

Clock Cycle Time tCK 3.75 3 2.5 2.5 ns

Active to Read or Write delay tRCD 15 15 15 12.5 ns

Active to Active / Auto-Refresh command

period tRC 60 60 60 57.5 ns

Active bank A to Active

bank B command delay

x4 & x8 tRRD 7.5 7.5 7.5 7.5 ns

x16 tRRD 10 10 10 10 ns

Active to Precharge Command tRASmin 45 45 45 45 ns

tRASmax 70000 70000 70000 70000 ns

Precharge Command Period tRP 15 15 15 12.5 ns

Parameter Symbol 1Gb Unit

Auto-Refresh to Active / Auto-Refresh com-

mand period tRFC 127.5 ns

Average periodic Refresh interval tREFI 0C<=Tcase<=85C 7.8 µs

85C<Tcase<=95C 3.9

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

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Electrical Characteristics & AC Timing - Absolute Specification

Timing Parameter by Speed Grade

Symbol Parameter

-37B

DDR2 -533

-3C

DDR2 -667

-AD

DDR2 -800

-AC

DDR2 -800 Unit

min max min max min max min max

tCK

Clock cycle time, CL=x 3750 8000 ps

Clock cycle time, CL=x, (Average) 3000 8000 2500 8000 2500 8000 ps

tCH CK, CK high-level width 0.45 0.55 0.48 0.52 0.48 0.52 0.48 0.52 tCK

tCL CK, CK low-level width 0.45 0.55 0.48 0.52 0.48 0.52 0.48 0.52 tCK

WL Write command to DQS associated clock edge RL-1 RL-1 RL-1 RL-1 tCK

tDQSS Write command to 1st DQS latching transition -0.25 +0.25 -0.25 +0.25 -0.25 +0.25 -0.25 +0.25 tCK

tDSS DQS falling edge to CK setup time 0.2 - 0.2 - 0.2 - 0.2 - tCK

tDSH DQS falling edge hold time from CK 0.2 - 0.2 - 0.2 - 0.2 - tCK

tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - 0.35 - 0.35 - tCK

tWPRE Write preamble 0.35 - 0.35 - 0.35 - 0.35 - tCK

tWPST Write postamble 0.4 0.60 0.40 0.60 0.40 0.60 0.40 0.60 tCK

tIS Address and control input setup time 250 - 200 - 175 - 175 - ps

tIH Address and control input hold time 375 - 275 - 250 - 250 - ps

tIPW

Address and control input pulse width

(each input) 0.6 - 0.6 - 0.6 - 0.6 - tCK

tDS DQ and DM input setup time differential strobe 100 - 100 - 50 - 50 - ps

tDH DQ and DM input hold time differential strobe 225 - 175 - 125 - 125 - ps

tDIPW DQ and DM input pulse width (each input) 0.35 - 0.35 - 0.35 - 0.35 - tCK

tAC DQ output access time from CK / CK -500 +500 -450 +450 -400 +400 -400 +400 ps

tDQSCK DQS output access time from CK / CK -450 +450 -400 +400 -350 +350 -350 +350 ps

tHZ Data-out high-impedence time from CK / CK - tACmax - tACmax - tACmax - tACmax ps

tLZ(DQS) DQS(/DQS) low-impedence time from CK / CK tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ps

tLZ(DQ) DQ low-impedence time from CK / CK 2tACmin tACmax 2tACmin tACmax 2tACmin tACmax 2tACmin tACmax ps

tDQSQ

DQS-DQ skew

(for DQS & associated DQ signals) - 300 - 240 - 200 - 200 ps

tHP Clock half period min (tCL, tCH) min (tCL, tCH) min (tCL, tCH) min (tCL, tCH) ps

tQHS Data hold skew factor - 400 - 340 - 300 - 300 ps

tQH Data output hold time from DQS tHP-tQHS - tHP-tQHS - tHP-tQHS - tHP-tQHS - ps

tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK

tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

tRRD

Active bank A to Active bank

B command period

x4/x8 (1k page size) 7.5 - 7.5 - 7.5 - 7.5 - ns

x16 (2k page size) 10 - 10 - 10 - 10 - ns

tFAW Four Activate Window

x4/x8 (1k page size) 37.5 37.5 - 35 - 35 - ns

x16 (2k page size) 50 50 - 45 - 45 - ns

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

tCCD CAS A to CAS B command period 2 2 - 2 - 2 - tCK

tWR Write recovery time 15 - 15 - 15 - 15 - ns

tDAL Auto-Precharge write recovery + precharge time WR+tRP - WR+tRP - WR+tRP - WR+tRP - tCK

tWTR Internal Write to Read command delay 7.5 - 7.5 - 7.5 - 7.5 - ns

tRTP Internal Read to Precharge command delay 7.5 7.5 - 7.5 - 7.5 - ns

tCKE CKE minimum high and low pulse width 3 3 - 3 - 3 - tCK

tXSNR Exit Self-Refresh to non-Read command tRFC+10 - tRFC+10 - tRFC+10 - tRFC+10 - ns

tXSRD Exit Self-Refresh to Read command 200 200 - 200 - 200 - tCK

tXP

Exit precharge power-down to any valid com-

mand (other than NOP or Deselect) 2 - 2 - 2 - 2 - tCK

tXARD

Exit power down to any valid command

(other than NOP or Deselect) 2 - 2 - 2 - 2 - tCK

tXARDS

Exit active power-down mode to Read command

(slow exit, lower power) 6 - AL 7 - AL - 8 - AL - 8 - AL - tCK

tAOND ODT turn-on delay 2 2 2 2 2 2 2 2 tCK

tAON ODT turn-on tAC(min) tAC(max)

+1 tAC(min) tAC(max)

+0.7 tAC(min) tAC(max)

+0.7 ns

tAONPD ODT turn-on (Power-Down mode) tAC(min)

2tCK+tAC

(max)+1

tAC(min)

2tCK+tAC

(max)+1

tAC(min)

2tCK+tAC

(max)+1

tAC(min)

2tCK+tAC

(max)+1 ns

tAOFD ODT turn-off delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tCK

tAOF ODT turn-off tAC(min) tAC(max)

+0.6 tAC(min) tAC(max)

+0.6 ns

tAOFPD ODT turn-off (Power-Down mode) tAC(min)

2.5tCK+

tAC(max)

tAC(min)

2.5tCK+

tAC(max)

tAC(min)

2.5tCK+

tAC(max)

tAC(min)

2.5tCK+

tAC(max)

tANPD ODT to power down entry latency 3 3 - 3 - 3 - tCK

tAXPD ODT power down exit latency 8 8 8 8 tCK

tMRD Mode register set command cycle time 2 - 2 - 2 - 2 - tCK

tMOD MRS command to ODT update delay 0 12 0 12 0 12 0 12 ns

tOIT OCD drive mode output delay 0 12 0 12 0 12 0 12 ns

tDELAY

Minimum time clocks remain ON after CKE

asynchronously drops LOW

tIS+tCK

+tIH

-tIS+tCK

+tIH

-tIS+tCK

+tIH

-tIS+tCK

+tIH

- ns

Symbol Parameter

-37B

DDR2 -533

-3C

DDR2 -667

-AD

DDR2 -800

-AC

DDR2 -800 Unit

min max min max min max min max

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

General notes, which may apply for all AC parameters

Genernal Note 1 : DDR2 SDRAM AC timing reference load

The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended

to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production

tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environ-

ment. Manufacturers will correlate to their production test conditions, generally a coaxial transmission line terminated at the

tester electronics.

The output timing reference voltage level for single ended signals is the crosspoint with VTT.

The output timing reference voltage level for differential signals is the crosspoint of the true ( e.g. DQS) and the complement (e.g.

DQS) signal.

Gernal Note 2 : Slew Rate Measurement Levels

Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.

For differential signals (e.g. DQS / DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500

mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS

for differential strobe.

Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges from vref(dc) to VIL(ac),max

for falling edges. For differential signals (eg. CK - CK) slew rate for rising edges is measured from CK - CK = -250mV to CK - CK

=+500V (+250mV to -500mV for falling edges).

Genernal Note 3 : DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions in below figure.

D Q

D Q S

R D Q S

DUT

V D D Q

O u tp u t

2 5 o h m s

T im in g

re fe re nce

p o in t

V T T = V D D Q /2

D Q S

R D Q S

D U T

V D D Q

O utpu t

25 ohm s

Test poin t

VTT = V D D Q /2

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Genernal Note 4 : Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS

“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2

SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the

rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the

crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.

Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to

VSS through a 20 ohms to 10K ohms resistor to insure proper operation.

Genernal Note 5 :

AC timings are for linear signal transitions.

Genernal Note 6 :

All voltages are referenced to VSS.

Genernal Note 7 :

These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by

device design or tester correlation.

Genernal Note 8 :

Tests for AC timing, IDD, and electrial (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels,

but the related specifications and device operation are guaranteed for the full voltage range specified.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input and Data Setup and Hold Time

Timing Definition for Input Setup (tIS) and Hold Time (tIH)

Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal and

VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from the input

signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test

Timing Definition for Data Setup (tDS) and Hold Time (tDH)

1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the

VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac)

level tothe differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with

single-endeddata strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data

strobe crossing Vref for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe

crossing Vref for a falling signal applied to the device under test.

2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the

VIL(dc) level to the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint

for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled

MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing Vref

for a rising signal and VIH(dc) to the single-ended data strobe crossing Vref for a falling signal applied to the device under

test

DDQ

IH(ac)

min

IH(dc)

min

REF

IL(dc)

max

IL(ac)

max

tIS tIH

DDQ

IH(ac)

min

IH(dc)

min

REF

IL(dc)

max

IL(ac)

max

tDS tDH

tDS

REF

tDH

DQS

Differential Input

Waveform

Single-ended Input

Waveform

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Slew Rate Definition for Input and Data Setup and Hold Times

Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIH(dc)min and

the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VIL(dc)max and the first crossing of VIL(ac)max, (fig. A) If the actual signal is always earlier than the nominal

slew rate line between shaded ‘dc to ac region’, use nominal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded ‘dc to ac region’, the slew rate of a tangent line to the actual signal from the ac

level to dc level is used for derating value.(fig.B)

Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the

first crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing

of VIH(dc)min and the first crossing of Vref.(fig. A). If the actual signal is always later than the nominal slew rate line between

shaded ‘dc to Vref region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line

anywhere between shaded ‘dc to Vref region’, the slew rate of a tangent line to the actual signal from the dc level to Vref level is

used for derating value.(fig.B)

Setup Slew Rate =

VIL(dc)max - VIL(ac)max

Delta TFS falling signal

Setup Slew Rate =

VIH(dc)min - VIL(ac)min

Delta TRS rising signal

Hold Slew Rate =

VREF - VIL(dc)max

Delta TRH rising signal

Hold Slew Rate =

VIH(dc)min - VREF

Delta TFH falling signal

Setup Slew Rate =

VIL(dc)max - VIL(ac)max

Delta TFS falling signal

Setup Slew Rate =

VIH(dc)min - VIL(ac)min

Delta TRS rising signal

Hold Slew Rate =

VREF - VIL(dc)max

Delta TRH rising signal

Hold Slew Rate =

VIH(dc)min - VREF

Delta TFH falling signal

Setup Slew Rate =

tangent line [VIL(dc)max - VIL(ac)max]

Delta TFS

Setup Slew Rate =

tangent line [VIH(dc)min - VIL(ac)min]

Delta TRS

Hold Slew Rate =

tangent line [REF - VIL(dc)max]

Delta TRH

Hold Slew Rate =

tangent line [VIH(dc)min - VREF]

Delta TFH

falling

signal

falling

signal

rising

signal

rising

signal

IL(ac)

max

IL(dc)

max

REF

IH(dc)

min

DDQ

IH(ac)

min

Delta TFS Delta TRH Delta TFH

Delta TRS

tStH

dc to ac

region

dc to ac

region

dc to Vref

region

dc to Vref

region

Fig. A Fig. B

IL(ac)

max

IL(dc)

max

REF

IH(dc)

min

DDQ

IH(ac)

min

Delta TFS Delta TRH Delta TFH

Delta TRS

tStH

dc to ac

region

dc to ac

region

dc to Vref

region

dc to Vref

region

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input Setup (tIS) and Hold (tIH) Time DeratingTable

CK, CK Differential Slew Rate (DDR2-533)

2.0 V/ns 1.5 V/ns 1.0 V/ns

D tIS D tIH D tIS D tIH D tIS D tIH

Command / Address

Slew rate

4.0 +187 +94 +217 +124 +247 +154

3.5 +179 +89 +209 +119 +239 +149

3.0 +167 +83 +197 +113 +227 +143

2.5 +150 +75 +180 +105 +210 +135

2.0 +125 +45 +155 +75 +185 +105

1.5 +83 +21 +113 +51 +143 +81

1.0 0 0 +30 +30 +60 +60

0.9 -11 -14 +19 +16 +49 +46

0.8 -25 -31 +5 -1 +35 +29

0.7 -43 -54 -13 -24 +17 +6

0.6 -67 -83 -37 -53 -7 -23

0.5 -110 -125 -80 -95 -50 -65

0.4 -175 -188 -145 -158 -115 -128

0.3 -285 -292 -255 -262 -225 -232

0.25 -350 -375 -320 -345 -290 -315

0.2 -525 -500 -495 -470 -465 -440

0.15 -800 -708 -770 -678 -740 -648

0.1 -1450 -1125 -1420 -1095 1390 -1065

CK, CK Differential Slew Rate (DDR2-667/800)

2.0 V/ns 1.5 V/ns 1.0 V/ns

D tIS D tIH D tIS D tIH D tIS D tIH

Command / Address

Slew rate

4.0 +15- +94 +180 +124 +210 +154

3.5 +143 +89 +173 +119 +203 +149

3.0 +133 +83 +163 +113 +193 +143

2.5 +120 +75 +150 +!05 +180 +135

2.0 +100 +45 +!60 +75 +160 +105

1.5 +67 +21 +97 +51 +127 +81

1.0 0 0 +30 +30 +60 +60

0.9 -5 -14 +25 +16 +55 +46

0.8 -13 -31 +17 -1 +47 +29

0.7 -22 -54 +8 -24 +38 +6

0.6 -34 -83 -4 -53 +36 -23

0.5 -60 -125 -30 -95 0 -65

0.4 -100 -188 -70 -158 -40 -128

0.3 -168 -292 -138 -262 -108 -232

0.25 -200 -375 -170 -345 -140 -315

0.2 -325 -500 -295 -470 -265 -440

0.15 -517 -708 -487 -678 -457 -648

0.1 -1000 -1125 -970 -1095 -940 -1065

1. All units in ps.

2. For all input signals the total tIS (input setup time) and tIH (input hold time) required is calculated by

adding the individual datasheet value to the derating value listed in the previous table.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Data Setup (tDS) and Hold Time (tDH) Derating Table

DQS, DQS Differential Slew Rate (DDR2-533)

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

DQ Slewrate (V/ns)

2.0 125 45 125 45 125 45 - - - - - - - - - - - -

1.5 83 21 83 21 83 21 95 33 - - - - - - - - - -

1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - -

0.9 - - -11 -14 -11 -14 1 -2 13 10 25 22 - - - - - -

0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - -

0.7 - - - - - - -31 -42 -19 -30 -7 -18 5 -6 17 6 - -

0.6 - - - - - - - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11

0.5 - - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53

0.4 - - - - - - - - - - - - -127 -140 -115 -128 -103 -116

1. All units in ps.

2. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual

datasheet value to the derating value listed in the previous table.

DQS, DQS Differential Slew Rate (DDR2-667/800)

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tDH

DQ Slewrate (V/ns)

2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135

1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114

1.0 0 0 0 0 0 0 12 12 24 24 36 36 48 48 60 60 72 72

0.9 -5 -14 -5 -14 -5 -14 7 -2 19 10 31 22 43 34 55 46 67 58

0.8 -13 -31 -13 -31 -13 -31 -1 -19 11 -7 23 5 35 17 47 29 59 41

0.7 -22 -54 -22 -54 -22 -54 -10 -42 2 -30 14 -18 26 -6 38 6 50 18

0.6 -34 -83 -34 -83 -34 -83 -22 -71 -10 -59 2 -47 14 -35 26 -23 38 -11

0.5 -60 -125 -60 -125 -60 -125 -48 -113 -36 -101 -24 -89 -12 -77 0 -65 12 -53

0.4 -100 -188 -100 -188 -100 -188 -88 -176 -76 -164 -64 -152 -52 -140 -40 -128 -28 -116

1. All units in ps.

2. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual

datasheet value to the derating value listed in the previous table.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Overshoot and Undershoot Specification

AC Overshoot / Undershoot Specification for Address and Control Pins

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins

Parameter DDR2

-533

DDR2

-667

DDR2

-800 Units

Maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 V

Maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 V

Maximum overshoot area above VDD 1.0 0.8 0.66 V.ns

Maximum undershoot area below VSS 1.0 0.8 0.66 V.ns

Parameter DDR2

-533

DDR2

-667

DDR2

-800 Units

Maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 V

Maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 V

Maximum overshoot area above VDDQ 0.28 0.23 0.23 V.ns

Maximum undershoot area below VSSQ 0.28 0.23 0.23 V.ns

VDD

VSS

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts (V)

VDDQ

VSSQ

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts (V)

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Package Dimensions (x4/x8; 60 balls; 0.8mmx0.8mm Pitch; BGA Package)

0.8

6.4

0.8

9 +/- 0.1

13 +/- 0.1

Pin A1 Index

Min. 0.25

Max. 0.40

Max. 1.20

TOP VIEWBOTTOM VIEW

8.0

Max. 0.20

Min. 0.10 Min. 0.10

Min. 0.40

Max. 0.50

60Balls

Units: mm

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Package Dimensions (x16; 84 balls; 0.8mmx0.8mm Pitch; BGA Package)

0.8

6.4

0.8

9 +/- 0.1

13 +/- 0.1

Pin A1 Index

Min. 0.25

Max. 0.40

Max. 1.20

TOP VIEWBOTTOM VIEW

11.2

Max. 0.20

Min. 0.10 Min. 0.10

Min. 0.40

Max. 0.50

84Balls

Units: mm

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Revision Log

Rev Date Modification

0.00 01/2008 Draft

0.1 01/2008 Preliminary Edition

0.2 01/2008 IDD Current Information Update

1.0 01/2008 Official Release

1.1 04/2008 Change the power supply spec from 1.55V to 1.5V.

Correct typo.

1.2 05/2008

Change Volate supply upper limit from 1.5V+0.125V to 1.5V+0.1275V.

Update dimensions.

Update Pulldown & Pullup Driver Characteristics.

1.3 09/2009 Update IDD current P.64.

NT5TB256M4DE / NT5TB128M8DE /NT5TB64M16DG

1Gb DDR2 SDRAM D-Die

REV 1.3

09/2009

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Nanya Technology Corporation.

Printed in Taiwan, R.O.C., 2007

The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both NANYA logo.

Other company, product and service names may be trademarks or service marks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance

of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s

standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this

warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government

requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or

environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE

FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such

applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should

be directed to NTC through a local sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be

provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents

or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under

any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination,

machine, or process in which such semiconductor products or services might be or are used.

NANYA TECHNOLOGY CORPORATION

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669, FU HSING 3rd Rd., Kueishan,

Taoyuan, Taiwan, R.O.C.

The NANYA TECHNOLOGY CORPORATION

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