FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII 3.3 Volt Synchronous x36 First-In/First-Out Queue Memory Organization Device Memory Organization Device 131,072 x 36 65,536 x 36 32,768 x 36 16,384 x 36 FQV36110 FQV36100 FQV3690 FQV3680 8,192 x 36 4,096 x 36 2,048 x 36 1,024 x 36 FQV3670 FQV3660 FQV3650 FQV3640 Key Features * * * * * * * * * * * * * * * * * * * * * Industry leading First-In/First-Out Queues (up to 166MHz) Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns) Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns) User selectable input and output port bus-sizing Big Endian/Little Endian user selectable byte representation 3.3V power supply 5V input tolerant on all control and data input pins 5V output tolerant on all flags and data output pins Master Reset clears all previously programmed configurations including Write and Read pointers Partial Reset clears Write and Read pointers but maintains all previously programmed configurations First Word Fall Through (FWFT) and Standard Timing modes Presets for eight different Almost Full and Almost Empty offset values Parallel/Serial programming of PRAF and PRAE offset values Programmable 8-bit or 9-bit parallel programming modes for offset values Full, Empty, Almost Full, Almost Empty, and Half Full indicators PRAF and PRAE operates in either synchronous or asynchronous modes Asynchronous output enable tri-state data output drivers Data retransmission with programmable zero or normal latency modes Available package: 128 - pin Plastic Thin Quad Flat Pack (TQFP) (0C to 70C) Commercial operating temperature available for cycle time of 6.0ns and above (-40C to 85C) Industrial operating temperature available for cycle time of 7.5ns and above Product Description HBA's FlexQTM III offers industry leading FIFO queuing bandwidth (up to 6.0 Gbps), with a wide range of memory configurations (from 1,024 x 36 to 131,072 x 36). System designer has full flexibility of implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation of virtual queue depths. 5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching capability. Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will initialize Write and Read pointers to zero. In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively. In Standard mode, always assert REN for read operation. FULL and EMPTY are used instead of DRDY and QRDY respectively. 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 1 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Product Description (Continued) Bus matching feature is available with the following memory configurations: Input Bus Width x9 x18 x36 x36 x36 Output Bus Width x36 x36 x36 x18 x9 In addition, Endian Select is available for implementing byte re-ordering on data outputs. Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit parallel programming modes for offset values can be selected for convenience. PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either synchronous or asynchronous modes. At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit operation. These FlexQTM III devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 128 - pin Plastic TQFP is offered to save system board space. These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc. 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 2 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Block Diagram of Single Synchronous Queue 131,072 x 36 / 65,536 x 36 / 32,768 x 36 / 16,384 x 36 / 8,192 x 36 / 4,096 x 36 / 2,048 x 36 / 1,024 x 36 PARTIAL RESET (PRST ) MASTER RESET (MRST ) READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN ) WRITE ENABLE (WEN) LOAD ( LOAD) x36, x18, x9 DATA IN (D35 - 0) SERIAL DATA ENABLE (SDEN) FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG / INPUT READY ( FULL / DRDY) PROGRAMMABLE ALMOST-FULL (PRAF ) OUTPUT ENABLE (OE) FQV36110 FQV36100 FQV3690 FQV3680 FQV3670 FQV3660 FQV3650 FQV3640 x36, x18, x9 DATA OUT (Q35 - 0) RETRANSMIT ( RET ) EMPTY FLAG / OUTPUT READY ( EMPTY/ QRDY ) PROGRAMMABLE ALMOSTEMPTY ( PRAE ) HALF-FULL FLAG ( HALF ) BIG-ENDIAN / LITTLE-ENDIAN (ES) INTERSPERSED/NON-INTERSPERSED PARITY (IPAR) BUS MATCHING 2 (BM2) BUS MATCHING 1 (BM1) BUS MATCHING 0 (BM0) Figure 1. Single Device Configuration Signal Flow Diagram 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 3 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII WCLK IPAR WEN LOAD SDEN FWFT/SDI FULL / DRDY Write Control Logic PRAF EMPTY/ QRDY PRAE Offset Register Flag Logic HALF FWFT/SDI SFM Write Pointer PFS1 PFS0 D 35-0 x36, x18, x9 Input Register SRAM Output Register Output Buffer Q 35-0 x36, x18, x9 OE Read Pointer Read Control Logic RETZL RET RCLK REN Bus Configuration Reset MRST PRST ES BM2 BM1 BM0 Figure 2. Device Architecture 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 4 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 GND RCLK REN RET 104 103 RETZL 107 105 EMPTY/QRDY 108 106 PRAE SFM 109 Vcc 110 111 IPAR BM2 ES 114 112 GND PFS1 115 117 116 PFS0 HALF 118 121 GND PRAF 122 BM0 Vcc 123 119 FULL/DRDY 124 120 LOAD FWFT/SDI 125 PRST MRST 126 WCLK 127 128 FlexQTMIII 113 Index GND D23 21 82 Q23 GND 22 81 Q22 D22 23 80 Q21 Vcc 24 79 Q20 D21 25 78 Q19 D20 26 77 Q18 D19 27 76 GND D18 28 75 Q17 GND 29 74 Q16 D17 30 73 Vcc D16 31 72 Vcc D15 32 71 Q15 D14 33 70 Q14 D13 34 69 Q13 Vcc 35 68 Q12 D12 36 67 GND GND 37 66 Q11 D11 38 65 Q10 64 83 Q9 20 63 GND D24 Q8 Q24 84 62 85 19 Q7 18 D25 61 D26 Vcc Q25 Q6 86 60 17 59 Vcc D27 GND 87 58 16 Q5 Q26 D28 57 Q27 88 Q4 89 15 56 14 D29 Q3 GND 55 Q28 Q2 90 54 13 53 Q29 D30 Q1 Q30 91 Q0 92 12 52 11 D31 51 Vcc D0 Q31 GND 93 50 10 49 GND D32 D1 94 D2 9 48 GND D33 Vcc Q32 95 47 96 8 D3 7 D34 46 D35 D4 Q33 45 Q34 97 44 98 6 D5 5 BM1 GND DNC 1 43 Q35 42 Vcc 99 D7 100 4 D6 3 Vcc 41 DNC 1 D8 Vcc 40 OE 101 39 102 2 D9 1 D10 WEN SDEN TQFP - 128 (Drw No: PF-02A; Order code: PF) Top View NOTES: 1. DNC = Do Not Connect. Figure 3. Device Pin Out 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 5 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Pin # 126 Pin Name Master Reset Pin Symbol MRST Input/Output Description Input Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not be maintained. 127 Partial Reset PRST Input Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be maintained. 128 Write Clock WCLK Input Writes data into queue during low to high transitions of WCLK if WEN is set to low. 1 Write Enable WEN Input Controls write operation into queue or offset registers during low to high transition of WCLK. 125 Load Enable LOAD Input During Master Reset, set LOAD low to select parallel programming or one of eight default offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively. Use in conjunction with WEN / REN . 115 Default Programming 1 PFS1 Input During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0. 118 Default Programming 0 PFS0 Input During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1. 07,08,09, 10,12,13, 15,16,17, 18,19,20, 21,23,25, 26,27,28, 30,31,32, 33,34,36, 38,39,40, 41,42,43, 45,46,47, 49,50,51. Data Inputs D35-0 Input 36 - bit wide input data bus. 105 Read Clock RCLK Input Reads data from queue during low to high transitions of RCLK if REN is set to low. 104 Read Enable REN Input Controls read operation from queue or offset registers during low to high transition of RCLK. Table 1. Pin Descriptions 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 6 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Pin # Pin Name Pin Symbol Input/Output 102 Output Enable OE Input 99,98,97, 96,93,92, 91,90,89, 88,86,85, 82,81,80, 79,78,77, 75,74,71, 70,69,68, 66,65,64, 63,62,60, 58,57,56, 55,54,53 Data Outputs Q35-0 Output Description Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). 36 - bit wide output data bus. 124 First Word Fall Through/Serial Data Input FWFT/SDI Input Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . 2 Serial Data Input Enable SDEN Input If serial programming is selected, setting SDEN low and LOAD low enables serial data input to be written into offset registers during the low to high transition of WCLK. 112 Bus Matching 2 BM2 Input During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM1 and BM0. 6 Bus Matching 1 BM1 Input During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM0. 119 Bus Matching 0 BM0 Input During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM1. 114 Endian Select ES Input 103 Retransmit RET Input 107 Zero Latency Retransmit RETZL Input During Master Reset, set RETZL low to select zero latency retransmit or RETZL high to select normal latency retransmit. Output Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue. In FWFT mode, queue is full when DRDY goes high during low to high transition of WCLK. This prohibits further writes into the queue. 123 Full/Data Input Ready Flag FULL / DRDY During Master Reset, set ES high to select byte re-ordering on data outputs or ES low to select no byte re-ordering on data outputs. Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Table 1. Pin Descriptions (Continued) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 7 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Pin # Pin Name Pin Symbol Input/Output Description 108 Empty/Data Output Ready Flag EMPTY / QRDY Output Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue. In FWFT mode, queue is empty when QRDY goes high during the low to high transition of RCLK. This prohibits further reads from the queue. 113 Interspersed Parity IPAR Input During Master Reset, set IPAR low to select 9-bit parallel programming mode or IPAR high to select 8bit parallel programming mode. 109 Synchronous Partial Flag Mode SFM Input During Master Reset, set SFM high to select Synchronous Partial Flag mode or SFM low to select Asynchronous Partial Flag mode. Output Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . 121 Almost Full PRAF 110 Almost Empty PRAE Output Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty +offset) or programmed offset values determine the status of PRAE . 117 Half Full HALF Output Queue is more than half full when HALF goes low. Triggered by both WCLK and RCLK. 03, 05 Do Not Connect DNC N/A Do not connect. Power Vcc N/A 3.3V power supply. Ground GND N/A 0V Ground. 04,11,24, 35,48,61, 72,73,87, 100,101, 111,122. 14,22,29, 37,44,52, 59,67,76, 83,84,94, 95,106, 116,120 Table 1. Pin Descriptions (Continued) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 8 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage with respect to GND -0.5 to + 4.5 V NOTES: TSTG Storage Temperature -55 to +125 Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. IOUT DC Output Current -50 to +50 C mA Table 2. Absolute Maximum Ratings FQV36110, FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640 Commercial Clock = 6ns, 7.5ns, 10ns, 15ns Industrial Clock = 7.5ns, 10ns, 15ns Symbol Parameter Recommended Operating Conditions Min. Typ. Max. Min. Typ. Max. Unit Vcc Supply Voltage Com'l / Ind'l 3.15 3.3 3.45 3.15 3.3 3.45 V GND Supply Voltage 0 0 0 0 0 0 V 2.0 - 5.5 2.0 - 5.5 V - - 0.8 - - 0.8 V 0 - 70 0 - 70 -40 - 85 -40 - 85 Input High Voltage Com'l / Ind'l Input Low Voltage Com'l / Ind'l Operating Temperature Commercial Operating Temperature Industrial VIH VIL TA TA C C DC Electrical Characteristics ILI(1) Input Leakage Current (any input) -10 - 10 -10 - 10 A ILO Output Leakage Current -10 - 10 -10 - 10 A 2.4 - - 2.4 - - V - - 0.4 - - 0.4 V Output Logic "1" Voltage, IOH=-2mA Output Logic "0" Voltage, IOL = 8mA VOH VOL Power Consumption Icc1(2,3) Active Power Supply Current - - 40 - - 40 mA Icc2(4) Standby Current - - 15 - - 15 mA Capacitance at 100MHz Ambient Temperature (25C) Symbol Parameter CIN(2) Input Capacitance COUT(2,4) Output Capacitance Conditions Max. Unit VIN= 0V 10 pF VOUT= 0V 10 pF NOTES: 1. 2. 3. 4. Measurement with 0.4<=VIN<=Vcc With output tri-stated ( OE = High) Icc(1,2) is measured with WCLK and RCLK at 20 MHz Design simulated, not tested. Table 3. DC Specifications 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 9 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Commercial FQV36100-6 FQV36100-6 FQV3690-6 FQV3680-6 FQV3670-6 FQV3660-6 FQV3650-6 FQV3640-6 Symbol Parameter Commercial & Industrial FQV36100-7.5 FQV36100-7.5 FQV3690-7.5 FQV3680-7.5 FQV3670-7.5 FQV3660-7.5 FQV3650-7.5 FQV3640-7.5 FQV36100-10 FQV36100-10 FQV3690-10 FQV3680-10 FQV3670-10 FQV3660-10 FQV3650-10 FQV3640-10 FQV36100-15 FQV36100-15 FQV3690-15 FQV3680-15 FQV3670-15 FQV3660-15 FQV3650-15 FQV3640-15 Min. Max. Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency - 166 - 133 - 100 - 66 MHz tA Data Access Time 1 4 2 5 2 6.5 2 10 ns tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - 15 - ns tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - 15 - ns tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - 6 - ns tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - 6 - ns tDS Data Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns tDH Data Hold Time 0.5 - 0.5 - 0.5 - 1 - ns tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - 4 - ns tENH Enable Hold Time 0.5 - 0.5 - 0.5 - 1 - ns 8 - 10 - 10 - 15 - ns 15 - 15 - ns (1) tRST Reset Pulse Width tRSTS Reset Set-up Time 10 - 15 tRSTR Reset Recovery Time 10 - 10 - 10 - 15 - ns tRSTF Reset to Flag and Output Time - 10 - 15 - 15 - 15 ns 0 - 0 - 0 - 0 - ns (1) tOLZ Output Enable to Output in Low-Z tOE Output Enable to Output Valid 2 4 2 5 2 6 2 8 ns tOHZ Output Enable to Output in High-Z(1) 2 4 2 6 2 6 2 8 ns tFULL Write Clock to Full Flag - 4 - 5 - 6.5 - 10 ns tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 - 10 ns tPRAFS Write Clock to Synchronous Almost-Full Flag - 4 - 5 - 6.5 - 10 ns tPRAES Read Clock to Synchronous Almost-Empty Flag - 4 - 5 - 6.5 - 10 ns tSKEW1 Skew time between Read Clock & Write Clock for Full Flag / Empty Flag 4 - 5 - 7 - 9 - ns tSKEW2 Skew time between Read Clock & Write Clock for PRAE & PRAF 6 - 7 - 10 - 14 - ns tLOADS Load Setup Time 2.0 - 2.5 - 3.5 - 4 - ns tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - 1 - ns Table 4. AC Electrical Characteristics 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 10 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Commercial FQV36100-6 FQV36100-6 FQV3690-6 FQV3680-6 FQV3670-6 FQV3660-6 FQV3650-6 FQV3640-6 Symbol Parameter Commercial & Industrial FQV36100-7.5 FQV36100-7.5 FQV3690-7.5 FQV3680-7.5 FQV3670-7.5 FQV3660-7.5 FQV3650-7.5 FQV3640-7.5 FQV36100-10 FQV36100-10 FQV3690-10 FQV3680-10 FQV3670-10 FQV3660-10 FQV3650-10 FQV3640-10 FQV36100-15 FQV36100-15 FQV3690-15 FQV3680-15 FQV3670-15 FQV3660-15 FQV3650-15 FQV3640-15 Min. Max. Min. Max. Min. Max. Min. Max. Unit 2.5 - 3.5 - 3.5 - 4 - ns tRETS Retransmit Setup Time tHALF Clock to HALF - 12 - 12.5 - 16 - 20 ns tPRAFA Write Clock to Asynchronous Programmable Almost-Full Flag - 12 - 12.5 - 16 - 20 ns tPRAEA Read Clock to Asynchronous Programmable Almost-Empty Flag - 12 - 12.5 - 16 - 20 ns NOTES: 1. Design simulated, not tested. Table 4. AC Electrical Characteristics (Continued) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 11 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load, clock = 6ns, 7.5 ns Refer to Figure 4 Output Load*, clock = 10ns, 15ns Refer to Figure 5 & 6 * Include jig and scope capacitances Table 5. AC Test Condition 3.3V Vcc/2 330 50 D.U.T. 30pF* I/O 510 Z0 = 50 Figure 4. AC Test Load for clock = 6ns, 7.5ns Figure 5. Output Load for clock = 10ns, 15ns *Includes jig and scope capacitances. tCD (Typical, ns) 4 3 2 1 20 30 50 80 100 200 Capacitance (pF) Figure 6. Lumped Capacitive Load 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 12 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Pin Functions MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not be maintained. PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be maintained. WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other. WEN Controls write operation into queue or offset registers during low to high transition of WCLK. LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively for parallel programming. Use in conjunction with WEN / REN . During programming of offset registers, PRAF and PRAE flag status is invalid. For Serial programming, LOAD is used to enable serial loading of offset registers together with SDEN . Refer to Figure 7 & Table 13 for details. PFS1 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1. Refer to Table 13 for details. PFS0 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0. Refer to Table 13 for details. D35-0 36 - bit wide input data bus. RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the EMPTY / QRDY and PRAE flags. RCLK and WCLK are independent of each other. REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances the Read pointer of the queue. OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). OE does not control advancement of Read pointer. Q35-0 36 - bit wide output data bus. FWFT/SDI Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and EMPTY . Refer to Table 11 for all flags status. In Standard mode, FULL and EMPTY are used instead of DRDY and QRDY . Refer to Table 10 for all flags status. SDEN If serial programming is selected, setting SDEN and LOAD low enables serial data to be written into offset registers during the low to high transition of WCLK. During serial programming, PRAF and PRAE flags status is invalid. Refer to Figure 7 for details. 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 13 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Pin Functions (Continued) BM2 During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM1 and BM0. Refer to Table 12 for details. BM1 During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM0. Refer to Table 12 for details. BM0 During Master Reset, select one of five input and output bus width configurations. Use in conjunction with BM2 and BM1. Refer to Table 12 for details. ES During Master Reset, set ES high to select byte re-ordering on data outputs or set ES low to select no byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 12 for details. RET Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Refer to Diagram 7 & 8 for details. RETZL During Master Reset, set RETZL low to select zero latency retransmit or set RETZL high to select normal latency retransmit. FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode, queue is full when DRDY goes high during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 10 & 11 for behavior of FULL / DRDY . EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to 10 & 11 for behavior of EMPTY / QRDY . IPAR During Master Reset, set IPAR low to select 9-bit parallel programming mode or set IPAR high to select 8-bit parallel programming mode. In 9-bit mode, 9-bit wide data input/output bus width is used for storing/fetching offset values. In 8-bit mode, 8-bit wide data input/output bus is used for storing/fetching offset values. SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to WCLK and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and deassertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of PRAE . PRAF In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In Asynchronous mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 10 & 11 for behavior of PRAF . PRAE In Synchronous mode, queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . In Asynchronous timing mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 10 & 11 for behavior of PRAE . HALF Queue is more than half full when HALF goes low during the low to high transition of WCLK. HALF goes high during low to high transition of RCLK when queue is less than half full. Refer to Table 10 & 11 for details. 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 14 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII LOAD 0 0 WEN 0 1 REN 1 0 SDEN WCLK 1 RCLK X 1 X 0 1 1 0 X 1 1 1 1 0 X X 1 X 0 X X 1 1 1 X X X FQV36110 FQV36100 FQV3690 FQV3680 FQV3670 FQV3660 FQV3650 FQV3640 Selection / Sequence Parallel write to offset registers: Empty Offset Full Offset Parallel write to registers: 1. PRAE 2. PRAF Parallel read from offset registers: Empty Offset Full Offset Parallel read from registers: 1. PRAE 2. PRAF X Serial shift into registers: 34 bits for the FQV36110 32 bits for the FQV36100 30 bits for the FQV3690 28 bits for the FQV3680 26 bits for the FQV3670 24 bits for the FQV3660 22 bits for the FQV3650 20 bits for the FQV3640 1 bit for each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) X No Operation X Write Memory Read Memory X No Operation Figure 7. Programmable Flag Offset Programming Sequence (FQV36110, FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650 and FQV3640) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 15 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Device FQV36110 FQV36100 FQV3690 FQV3680 FQV3670 FQV3660 FQV3650 FQV3640 PRAF Programming (bits) PRAE Programming (bits) D/Q16 - 0 Non-IPAR D/Q16 - 0 Non-IPAR D/Q18 & D/Q16 - 9 & D/Q7 - 0 IPAR D/Q18 & D/Q17 - 9 & D/Q7 - 0 IPAR D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR D/Q15 - 9 & D/Q7 - 0 IPAR D/Q15 - 9 & D/Q7 - 0 IPAR D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR D/Q14 - 9 & D/Q7 - 0 IPAR D/Q14 - 9 & D/Q7 - 0 IPAR D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR D/Q13 - 9 & D/Q7 - 0 IPAR D/Q13 - 9 & D/Q7 - 0 IPAR D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR D/Q12 - 9 & D/Q7 - 0 IPAR D/Q12 - 9 & D/Q7 - 0 IPAR D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR D/Q11 - 9 & D/Q7 - 0 IPAR D/Q11 - 9 & D/Q7 - 0 IPAR D/Q9 - 0 Non-IPAR D/Q9 - 0 Non-IPAR D/Q10 - 9 & D/Q7 - 0 IPAR D/Q10 - 9 & D/Q7 - 0 IPAR Table 6. Parallel Offset Register Data Mapping Table for x36 Bus Width Device FQV36110 FQV36100 FQV3690 FQV3680 FQV3670 FQV3660 FQV3650 FQV3640 PRAF Programming (bits) PRAE Programming (bits) D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q16 - 9 & D/Q7 - 0 IPAR D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR D/Q15 - 9 & D/Q7 - 0 IPAR D/Q15 - 9 & D/Q7 - 0 IPAR D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR D/Q14 - 9 & D/Q7 - 0 IPAR D/Q14 - 9 & D/Q7 - 0 IPAR D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR D/Q13 - 9 & D/Q7 - 0 IPAR D/Q13 - 9 & D/Q7 - 0 IPAR D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR D/Q12 - 9 & D/Q7 - 0 IPAR D/Q12 - 9 & D/Q7 - 0 IPAR D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR D/Q11 - 9 & D/Q7 - 0 IPAR D/Q11 - 9 & D/Q7 - 0 IPAR D/Q9 - 0 Non-IPAR D/Q9 - 0 Non-IPAR D/Q10 - 9 & D/Q7 - 0 IPAR D/Q10 - 9 & D/Q7 - 0 IPAR Table 7. Parallel Offset Register Data Mapping Table for x18 Bus Width 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 16 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Device FQV36110 FQV36100 FQV3690 FQV3680 FQV3670 FQV3660 FQV3650 FQV3640 PRAF Programming (bits) PRAE Programming (bits) D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte D/Q0 High Byte D/Q0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 High Byte D/Q7 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q6- 0 High Byte D/Q6- 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q5 - 0 High Byte D/Q5 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q4 - 0 High Byte D/Q4 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q3 - 0 High Byte D/Q3 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q2 - 0 High Byte D/Q2 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q1 - 0 High Byte D/Q1 - 0 High Byte Table 8. Parallel Offset Register Data Mapping for Table x9 Bus Width Device FQV36100 Standard Mode 131,072 x 36 65,536 x 36 FWFT Mode 131,073 x 36 65,537 x 36 FQV3690 32,768 x 36 32,769 x 36 FQV3680 16,384 x 36 16,385 x 36 FQV3670 8,192 x 36 8,193 x 36 FQV3660 4,096 x 36 4,097 x 36 FQV3650 2,048 x 36 2,049 x 36 FQV3640 1,024 x 36 1,025 x 36 FQV36110 Table 9. Maximum Depth of Queue for Standard and FWFT Mode 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 17 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Data Width D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE 7 6 5 4 3 2 1 0 2nd Cycle PRAE 15 14 13 12 11 10 9 8 3rd Cycle PRAF 7 6 5 4 3 2 1 0 4th Cycle PRAF 15 14 13 12 11 10 9 8 FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640 Parallel Offset Write/Read Cycles for x9 Bus Width Data Width D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE 7 6 5 4 3 2 1 0 2nd Cycle PRAE 15 14 13 12 11 10 9 8 3rd Cycle PRAE 16 4th Cycle PRAF 7 6 5 4 3 2 1 0 5th Cycle PRAF 15 14 13 12 11 10 9 8 6th Cycle PRAF 16 FQV36110 Parallel Offset Write/Read Cycles for x9 Bus Width Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 8 7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity Data Width 15 D/Q17 D/Q16 15 14 13 12 11 10 9 14 13 12 11 10 9 8 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 2nd Cycle PRAF Non-Interspersed Parity Interspersed Parity 15 15 14 13 12 11 10 9 14 13 12 11 10 9 8 FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640 Parallel Offset Write/Read Cycles for x18 Bus Width Figure 8. Parallel Offset Write/Read Cycle Diagram 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 18 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity 15 15 14 13 12 11 10 9 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 2nd Cycle PRAE Non-Interspersed Parity 16 Interspersed Parity 16 Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 3rd Cycle PRAF Non-Interspersed Parity Interspersed Parity 15 15 14 13 12 11 10 9 14 13 12 11 10 9 8 4th Cycle PRAF Non-Interspersed Parity 16 Interspersed Parity 16 FQV36110 Parallel Offset Write/Read Cycles for x18 Bus Width Data Width D/Q35 D/Q35 D/Q~ D/Q~ D/Q~ D/Q~ D/Q~ D/Q~ D/Q19 D/Q19 D/Q18 D/Q18 D/Q17 D/Q17 D/Q16 D/Q16 D/Q15 D/Q15 D/Q14 D/Q14 D/Q13 D/Q13 D/Q12 D/Q12 D/Q11 D/Q11 D/Q10 D/Q10 D/Q9 D/Q9 D/Q8 D/Q8 D/Q7 D/Q7 D/Q6 D/Q6 D/Q5 D/Q5 D/Q4 D/Q4 D/Q3 D/Q3 D/Q2 D/Q2 D/Q1 D/Q1 D/Q0 D/Q0 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity Data Width 16 D/Q35 D/Q~ D/Q~ D/Q~ D/Q19 D/Q18 D/Q17 16 15 14 13 12 11 10 9 15 14 13 12 11 10 9 8 D/Q16 D/Q15 D/Q12 D/Q11 D/Q10 D/Q9 16 15 14 14 13 13 12 11 10 9 15 14 13 12 11 10 9 8 D/Q14 D/Q13 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 8 2nd Cycle PRAF Non-Interspersed Parity Interspersed Parity 16 FQV36110, FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640 Parallel Offset Write/Read Cycles for x36 Bus Width # of Bits for Offset Registers 17 bits for FQV36110 16 bits for FQV36100 15 bits for FQV3690 14 bits for FQV3680 13 bits for FQV3670 12 bits for FQV3660 11 bits for FQV3650 10 bits for FQV3640 Note: Don't Care applies to all unused bits Figure 8. Parallel Offset Write/Read Cycle Diagram (Continued) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 19 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII FQV36110 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 65,536 65,537 to [131,072-(x+1)] (131,072-x) to 131,071 131,072 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV36100 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 32,768 32,769 to [65,536-(x+1)] (65,536-x) to 65,535 65,536 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV3690 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 16,384 16,385 to [32,768-(x+1)] (32,768-x) to 32,767 32,768 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV3680 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 8,192 8,193 to [16,384-(x+1)] (16,384 -x) to 16,383 16,384 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV3670 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 4,096 4,097 to [8,192-(x+1)] (8,192 -x) to 8,191 8,192 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV3660 FULL PRAF HALF PRAE 0 1 to y(1) (y+1) to 2,048 2,049 to [4,096-(x+1)] (4,096 -x) to 4,095 4,096 H H H H H L H H H H L L H H H L L L L L H H H H EMPTY L H H H H H Table 10. Status Flags (Standard Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 20 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII FQV3650 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 1,024 1,025 to [2,048-(x+1)] (2,048 -x) to 2,047 2,048 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV3640 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 512 513 to [1,024-(x+1)] (1,024 -x) to 1,023 1,024 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H NOTES: 1. See Table 13 for values x, y. Table 10. Status Flags (Standard Mode) (Continued) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 21 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII FQV36110 DRDY PRAF HALF PRAE QRDY 0 1 to y+1(1) (y+2) to 65,537 65,538 to [131,073-(x+1)] (131,073-x) to 131,072 131,073 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV36100 DRDY PRAF HALF PRAE QRDY 0 1 to y+1(1) (y+2) to 32,769 32,770 to [65,537-(x+1)] (65,537-x) to 65,536 65,537 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV3690 DRDY PRAF HALF PRAE QRDY 0 1 to y+1(1) (y+2) to 16,385 16,386 to [32,769-(x+1)] (32,769-x) to 32,768 32,769 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV3680 DRDY PRAF HALF PRAE QRDY 0 1 to y+1(1) (y+2) to 8,193 8,194 to [16,385-(x+1)] (16,385 -x) to 16,384 16,385 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV3670 DRDY PRAF HALF PRAE QRDY 0 1 to y+1(1) (y+2) to 4,097 4,098 to [8,193-(x+1)] (8,193-x) to 8,192 8,193 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV3660 DRDY PRAF HALF PRAE QRDY 0 L H H L H L L L L H H H H L L H H L L L L H H H H L L L L L (1) 1 to y+1 (y+2) to 2,049 2,050 to [4,097-(x+1)] (4,097 -x) to 4,096 4,097 Table 11. Status Flags (FWFT Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 22 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII FQV3650 DRDY PRAF HALF PRAE QRDY 0 1 to y+1(1) (y+2) to 1,025 1,026 to [2,049-(x+1)] (2,049 -x) to 2,048 2,049 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV3640 DRDY PRAF HALF PRAE QRDY 0 1 to y+1(1) (y+2) to 513 514 to [1,025-(x+1)] (1,025 -x) to 1,024 1,025 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L NOTES: 1. See Table 13 for values x, y. Table 11. Status Flags (FWFT Mode) (Continued) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 23 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII ES BM2 BM1 BM0 I/O Width D/Q35-27 D/Q26-18 D/Q17-9 D/Q8-0 Sequence X 0 X X I O 36 36 Byte 4 Byte 4 Byte 3 Byte 3 Byte 2 Byte 2 Byte 1 Byte 1 1st Write 1st Read 0 1 0 0 I O 36 18 Byte 4 X X Byte 3 X X Byte 2 Byte 4 Byte 2 Byte 1 Byte 3 Byte 1 1st Write 1st Read 2nd Read 0 1 0 1 I O 36 9 Byte 4 X X X X Byte 3 X X X X Byte 2 X X X X Byte 1 Byte 4 Byte 3 Byte 2 Byte1 1st Write 1st Read 2nd Read 3rd Read 4th Read 0 1 1 0 I 18 O 36 X X Byte 4 X X Byte 3 Byte 4 Byte 2 Byte 2 Byte 3 Byte 1 Byte 1 1st Write 2nd Write 1st Read I 9 O 36 X X X X Byte 4 X X X X Byte 3 X X X X Byte 2 Byte 4 Byte 3 Byte 2 Byte1 Byte 1 1st Write 2nd Write 3rd Write 4th Write 1st Read 0 1 1 1 1 1 0 0 I O 36 18 Byte 4 X X Byte 3 X X Byte 2 Byte 2 Byte 4 Byte 1 Byte 1 Byte 3 1st Write 1st Read 2nd Read 1 1 0 1 I O 36 9 Byte 4 X X X X Byte 3 X X X X Byte 2 X X X X Byte 1 Byte 1 Byte 2 Byte 3 Byte4 1st Write 1st Read 2nd Read 3rd Read 4th Read 1 1 1 0 I 18 O 36 X X Byte 2 X X Byte 1 Byte 4 Byte 2 Byte 4 Byte 3 Byte 1 Byte 3 1st Write 2nd Write 1st Read I 9 O 36 X X X X Byte 1 X X X X Byte 2 X X X X Byte 3 Byte 4 Byte 3 Byte 2 Byte1 Byte 4 1st Write 2nd Write 3rd Write 4th Write 1st Read 1 1 1 1 Table 12. Bus-Matching Table 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 24 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII LOAD PFS1 PFS0 FQV3650 FQV3640 Default Offsets x, y(1) 0 0 0 127 0 0 1 255 0 1 0 511 0 1 1 63 1 0 0 31 1 0 1 7 1 1 0 15 1 1 1 3 LOAD PFS1 PFS0 FQV3650 FQV3640 Program Mode 1 X X Serial 0 X X Parallel LOAD PFS1 PFS0 FQV3690 FQV3680 FQV3670 FQV3660 Default Offsets x, y(1) 0 0 0 127 0 0 1 255 0 1 0 511 0 1 1 63 1 0 0 1,023 1 0 1 15 1 1 0 31 1 1 1 7 LOAD PFS1 PFS0 FQV3690 FQV3680 FQV3670 FQV3660 Program Mode 1 X X Serial 0 X X Parallel NOTES: 1. x = PRAF offset, y = PRAE offset. Table 13. Default Programmable Flag Offsets 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 25 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII LOAD PFS1 PFS0 FQV36110 FQV36100 Default Offsets x, y(1) 0 0 0 127 0 0 1 8,191 0 1 0 16,383 0 1 1 4,095 1 0 0 1,023 1 0 1 511 1 1 0 2,047 1 1 1 255 LOAD PFS1 PFS0 FQV36110 FQV36100 Program Mode 1 X X Serial 0 X X Parallel NOTES: 1. x = PRAF offset, y = PRAE offset. Table 13. Default Programmable Flag Offsets (Continued) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 26 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Timing Diagrams tRST MRST tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR REN WEN FWFT/SDI LOAD tRSTS PFS1/PFS0 tRSTS BM2/BM1/BM0 tRSTS ES tRSTS RETZL tRSTS SFM tRSTS IPAR tRSTS RET tRSTS SDEN tRSTF If FWFT = 1,QRDY = 1 EMPTY / QRDY If FWFT = 0, EMPTY = 0 tRSTF If FWFT = 0, FULL = 1 FULL / DRDY If FWFT = 1, DRDY = 0 tRSTF PRAE tRSTF PRAF / HALF tRSTF OE = 1 Q35- 0 OE = 0 Diagram 1. Master Reset Timing 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 27 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII tRST PRST tRSTS tRSTR tRSTS tRSTR REN WEN tRSTS RET tRSTS SDEN tRSTF If FWFT = 1,QRDY = 1 EMPTY / QRDY If FWFT = 0, EMPTY = 0 tRSTF If FWFT = 0, FULL = 1 FULL / DRDY If FWFT = 1, DRDY = 0 tRSTF PRAE tRSTF PRAF / HALF tRSTF OE = 1 Q35- 0 OE = 0 Diagram 2. Partial Reset Timing 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 28 of 42 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 1. tENS tA tENH Output Register Data tSKEW1 1 No Write tFULL 2 tDS tWCLKH DWi tENS tFULL tDH ___________ Data Read tWCLK tSKEW1 tWCLKL tA tENH 1 No Write tFULL 2 DWi + 1 __________ Next Data Read tDS tFULL tDH ______ LOAD = High, OE = Low. ___________ Diagram 3. Write Cycle and Full Flag Timing (Standard Mode) If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, FULL will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL will assert 1 or more WCLK cycles. NOTES: Q 35 - 0 REN RCLK WEN FULL D 35 - 0 WCLK No Write FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII JULY 2002 Page 29 of 42 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 3. 1. tENS tOLZ tA tEMPTY tENS tENH tDS tSKEW1 DW1 tOEN tDH tENH tOHZ Last Word 1 tDS tENS DW2 tEMPTY ______________ tDH tENH tOLZ 2 tRCLK Last Word tENS tA tRCLKL tENH tA ______________ DW1 tEMPTY tENS tENH DW2 Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode) LOAD = High. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY will assert 1 or more RCLK cycles. NOTES: D35 - 0 WEN WCLK OE Q35 - 0 EMPTY REN RCLK tRCLKH FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII JULY 2002 Page 30 of 42 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 6. 3. 2. 1. 1 DW2 tSKEW1 tDH Output Data Register DW1 2 DW3 3 DW4 tEMPTY tA tDS DW1 DW[y+2] 1 DW[y+3] tSKEW2 2 DW[y+4] tDS tPRAES DW[(D-1)/2+1] DW[(D-1)/2+2] ____________ tHALF DW[(D-1)/2+3] tDS DW[D-x-1] DW[D-x] DW[D-x+1] 1 DW[D-x+2] 2 tPRAFS DW[D-x+3] DW[D-1] DWD ____________ tFULL tENH ___________ ______ ___________ y = PRAE offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 9 for Depth. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK ___________ LOAD = High, OE = Low. ___________ Diagram 5. Write Timing (FWFT Mode) If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW1, QRDY will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY will assert 1 or more RCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 35 - 0 REN RCLK D 35 - 0 WEN WCLK FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII JULY 2002 Page 31 of 42 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 3. 2. 1. tDH DW1 tOHZ DWD tOE DW1 tSKEW1 tENS tFULL tENH tA DW2 1 DW3 tA 2 tFULL DWx+1 tSKEW2 tA 1 DWx+2 2 tPRAFS DWx+3 DW[(D-1)/2+1] DW[D-y+1] tPRAES DW[D-y+2] DW[D-1] tA ___________ DW[D-y] ___________ tA tENS ____________ DW[D-y-1] 2 ____________ tHALF DW[(D-1)/2+2] tA 1 DWD tEMPTY ___________ y = PRAE Offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 9 for Depth. ___________ LOAD = High ____________ Diagram 6. Read Timing (FWFT Mode) If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY will assert 1 or more WCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 35 - 0 OE REN RCLK D35 - 0 WEN WCLK FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII JULY 2002 Page 32 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII RCLK 1 tENS tENH 2 tRETS tENS tENH REN tA Q 35 - 0 tA DWi DWi+1 tA DW1 DW2 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET tEMPTY tEMPTY EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high. OE = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid. Diagram 7. Retransmit Timing (Standard Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 33 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII RCLK 1 t ENS t ENH 2 t RETS 3 4 t ENS t ENH REN tA Q 35 - 0 DW i DW i+1 tA DW 1 tA DW 2 tA DW 3 DW 4 t SKEW2 W CLK 1 2 t RETS W EN t ENS t ENH RET t EM PTY t EM PTY Q RDY t PRAES PRAE t HALF HALF t PRAFS PRAF NOTES: 1. 2. 3. 4. 5. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low. OE = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid. Please refer to Table 9 for Depth. Diagram 8. Retransmit Timing (FWFT Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 34 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII RCLK 1 2 3 tENS tENH REN tA Q 35 - 0 tA tA DWi+1 DWi tA DW1 DW2 tA DW3 DW4 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. OE = Low; enables data to be read on outputs Q35 - 0. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the retransmit setup procedure. Please refer to Table 9 for Depth. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked. RETZL is set Low during MRST . Diagram 9. Zero Latency Retransmit Timing (Standard Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 35 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII RCLK 1 2 3 4 5 tENH tENS REN tA tA DWi Q 35 - 0 tA DW i+1 DW1 tA DW2 tA tA DW3 DW4 DW5 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET QRDY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. No more than D-2 words may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout the retransmit setup procedure. Please refer to Table 9 for Depth. OE = Low. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset. There must be at least two words written to the queue before a retransmit operation can be invoked. RETZL is set low during MRST . Diagram 10. Zero Latency Retransmit Timing (FWFT Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 36 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII WCLK tENS tENH tENH tLOADH tLOADH SDEN tLOADS LOAD tDS SDI tDH BIT 0 BIT MSB BIT 0 BIT MSB PRAF offset PRAE offset *Refer to Table 14 Diagram 11. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode) MSB FQV36110 FQV36100 FQV3690 FQV3680 FQV3670 FQV3660 FQV3650 FQV3640 16 15 14 13 12 11 10 9 Table 14. Reference Table for Diagram 11 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 37 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII tWCLK tWCLKH tWCLKL WCLK tLOADS tLOADH tLOADH LOAD tENS tENH tENH WEN tDS tDH tDS tDH D 35 - 0 PRAE offset PRAF offset Diagram 12. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode) tRCLK tRCLKH tRCLKL RCLK tLOADS tLOADH tLOADH tENH tENH LOAD tENS REN tA Q 35 - 0 tA Output Register Data PRAE offset PRAF offset Diagram 13. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 38 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII tWCLKH tWCLKL WCLK 1 tENS 2 1 2 tENH WEN tPRAFS tPRAFS D - ( x + 1 ) words in Queue PRAF D-(x+1) words in Queue D - x words in Queue tSKEW2 RCLK tENS tENH REN NOTES:___________ 1. 2. 3. 4. x = PRAF offset. D = maximum queue depth. Please refer to Table 9 for Depth. ___________ If the time between a rising edge of___________ RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after on WCLK cycle plus t___________ PRAFS). If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. PRAF synchronizes to the rising edge of WCLK only. Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) tWCLKH tWCLKL WCLK tWCLKH tWCLKL WEN y words in Queue (2) ; y+1 words in Queue(3) PRAE tSKEW2 tPRAES 1 RCLK y words in Queue(2); y+1 words in Queue(3) y+1 words in Queue (2) ; y+2 words in Queue(3) tPRAES 2 1 tENS 2 tENH REN NOTES: 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. PRAE synchronizes to the rising edge of RCLK only. Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 39 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII tWCLKH tWCLKL WCLK tENS tENH WEN tPRAFA D - x words in Queue D - ( x + 1) words in Queue PRAF D - ( x + 1) words in Queue tPRAFA RCLK tENS REN NOTES: 1. 2. 3. 4. x = PRAF offset. D = maximum queue depth. Please refer to Table 9 for Depth. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition. Select this mode by setting SFM low during Master Reset. Diagram 16. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) tWCLKH tWCLKL WCLK tENS tENH WEN tPRAEA PRAE y+1 words in Queue(2); y+2 words in Queue (3) y words in Queue(2); y+1 words in Queue(3) y words in Queue(2); y+1 words in Queue(3) tPRAEA RCLK tENS REN NOTES: 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. PRAE is asserted to low on RCLK transition and reset to high on WCLK transition. Select this mode by setting SFM low during Master Reset. Diagram 17. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 40 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII tWCLKH tWCLKL WCLK tENS tENH WEN D/2 + 1 words in Queue(1); [(D+1)/2 + 1] words in Queue(2) tHALF HALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) tHALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) RCLK tENS tENH REN NOTES: 1. 2. 3. For Standard Mode. For FWFT Mode. Please refer to Table 9 for Depth. Diagram 18. Half-Full Flag Timing (Standard and FWFT Mode) 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 41 of 42 FQV36110 * FQV36100 * FQV3690 * FQV3680 * FQV3670 * FQV3660 * FQV3650 * FQV3640 FlexQTMIII Order Information: HBA Device Family Device Type Power Speed (ns) XX FQ XXXXX V36110 (131,072 x 36) X Low XX 6 - 166 MHz * V36100 (65,536 x 36) 7-5 - 133 MHz V3690 (32,768 x 36) 10 - 100 MHz V3680 (16,384 x 36) 15 - 66 MHz Package** Temperature Range XX PF X Blank - Commercial (0C to 70C) I - Industrial (-40 to 85C) V3670 (8,192 x 36) V3660 (4,096 x 36) V3650 (2,048 x 36) V3640 (1,024 x 36) *Speed - 6ns available only in Commercial temp (0C to 70C). Slower speeds available upon request. **Package - 128 pin Plastic Thin Quad Flat Pack (TQFP) Example: FQV3680L6PF FQV3670L10PFI (16k x 36, 6ns, Commercial temp) (8k x 36, 10ns, Industrial temp) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 3F336B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 886.3.516.9118 Fax: 886.3.516.9181 JULY 2002 Page 42 of 42