LTC1860/LTC1861
1
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TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
µPower, 12-Bit, 250ksps
1- and 2-Channel ADCs in MSOP
The LTC
®
1860/LTC1861 are 12-bit A/D converters that are
offered in MSOP and SO-8 packages and operate on a single
5V supply. At 250ksps, the supply current is only 850μA.
The supply current drops at lower speeds because the
LTC1860/LTC1861 automatically power down to a typical
supply current of 1nA between conversions. These 12-bit
switched capacitor successive approximation ADCs include
sample-and-holds. The LTC1860 has a differential analog
input with an adjustable reference pin. The LTC1861 offers
a software-selectable 2-channel MUX and an adjustable
reference pin on the MSOP version.
The 3-wire, serial I/O, MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
These ADCs can be used in ratiometric applications or
with external references. The high impedance analog in-
puts and the ability to operate with reduced spans down
to 1V full scale, allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
Single 5V Supply, 250ksps, 12-Bit Sampling ADC
n 12-Bit 250ksps ADCs in MSOP Package
n Single 5V Supply
n Low Supply Current: 850μA (Typ)
n Auto Shutdown Reduces Supply Current
to 2μA at 1ksps
n True Differential Inputs
n 1-Channel (LTC1860) or 2-Channel (LTC1861)
Versions
n SPI/MICROWIRE
TM
Compatible Serial I/O
n High Speed Upgrade to LTC1286/LTC1298
n Pin Compatible with 16-Bit LTC1864/LTC1865
n Guaranteed Operation to 125°C (MSOP Package)
n High Speed Data Acquisition
n
Portable or Compact Instrumentation
n
Low Power Battery-Operated Instrumentation
n Isolated and/or Remote Data Acquisition
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Supply Current vs Sampling Frequency
1
2
3
4
8
7
6
5
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
LTC1860
1860 TA01
ANALOG INPUT
0V TO 5V
5V
1MF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
SAMPLING FREQUENCY (kHz)
0.01
SUPPLY CURRENT (MA)
1000
100
10
1
0.1
0.01 100
1860 TA02
0.1 110 1000
LTC1860/LTC1861
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) .................................................7V
Ground Voltage Difference
AGND, DGND LTC1861 MSOP Package .............±0.3V
Analog Input ....................(GND – 0.3V) to (VCC + 0.3V)
Digital Input .................................... (GND – 0.3V) to 7V
Digital Output ................... (GND – 0.3V) to (VCC + 0.3V)
(Notes 1, 2)
1
2
3
4
VREF
IN+
IN¯
GND
8
7
6
5
VCC
SCK
SDO
CONV
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
1
2
3
4
5
CONV
CH0
CH1
AGND
DGND
10
9
8
7
6
VREF
VCC
SCK
SDO
SDI
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
TJMAX = 150°C, θJA = 175°C/W
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
CONV
CH0
CH1
GND
VCC
SCK
SDO
SDI
TJMAX = 150°C, θJA = 175°C/W
PIN CONFIGURATION
Power Dissipation .............................................. 400mW
Operating Temperature Range
LTC1860C/LTC1861C ...............................0°C to 70°C
LTC1860I/LTC1861I .......................... –40°C to 85°C
LTC1860H/LTC1861H .........................–40°C to 125°C
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C
LTC1860 LTC1861
LTC1860 LTC1861
LTC1860/LTC1861
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LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1860CMS8#PBF LTC1860CMS8#TRPBF LTWR 8-Lead Plastic MSOP 0°C to 70°C
LTC1860IMS8#PBF LTC1860IMS8#PBF LTWS 8-Lead Plastic MSOP –40°C to 85°C
LTC1860HMS8#PBF LTC1860HMS8#PBF LTWS 8-Lead Plastic MSOP –40°C to 125°C
LTC1860CS8#PBF LTC1860CS8#PBF 1860 8-Lead Plastic SO 0°C to 70°C
LTC1860IS8#PBF LTC1860IS8#PBF 1860I 8-Lead Plastic SO –40°C to 85°C
LTC1861CMS#PBF LTC1861CMS#PBF LTWT 10-Lead Plastic MSOP 0°C to 70°C
LTC1861IMS#PBF LTC1861IMS#PBF LTWU 10-Lead Plastic MSOP –40°C to 85°C
LTC1861HMS#PBF LTC1861HMS#PBF LTWU 10-Lead Plastic MSOP –40°C to 125°C
LTC1861CS8#PBF LTC1861CS8#PBF 1861 8-Lead Plastic SO 0°C to 70°C
LTC1861IS8#PBF LTC1861IS8#PBF 1861I 8-Lead Plastic SO –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1860CMS8 LTC1860CMS8 LTWR 8-Lead Plastic MSOP 0°C to 70°C
LTC1860IMS8 LTC1860IMS8 LTWS 8-Lead Plastic MSOP –40°C to 85°C
LTC1860HMS8 LTC1860HMS8 LTWS 8-Lead Plastic MSOP –40°C to 125°C
LTC1860CS8 LTC1860CS8 1860 8-Lead Plastic SO 0°C to 70°C
LTC1860IS8 LTC1860IS8 1860I 8-Lead Plastic SO –40°C to 85°C
LTC1861CMS LTC1861CMS LTWT 10-Lead Plastic MSOP 0°C to 70°C
LTC1861IMS LTC1861IMS LTWU 10-Lead Plastic MSOP –40°C to 85°C
LTC1861HMS LTC1861HMS LTWU 10-Lead Plastic MSOP –40°C to 125°C
LTC1861CS8 LTC1861CS8 1861 8-Lead Plastic SO 0°C to 70°C
LTC1861IS8 LTC1861IS8 1861I 8-Lead Plastic SO –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ORDER INFORMATION
LTC1860/LTC1861
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CONVERTER AND MULTIPLEXER CHARACTERISTICS
SYMBOL CONDITIONS MIN TYP MAX UNITS
Resolution l12 Bits
No Missing Codes Resolution l12 Bits
INL (Note 3) l±1 LSB
Transition Noise 0.07 LSBRMS
Gain Error l±20 mV
Offset Error LTC1860 SO-8 and MSOP, LTC1861 MSOP
LTC1861 SO-8
l
l
±2
±3
±5
±7
mV
mV
Input Differential Voltage Range VIN = IN+ – IN–l0V
REF V
Absolute Input Range IN+ Input
IN– Input
–0.05
–0.05
VCC + 0.05
VCC/2
V
V
VREF Input Range LTC1860 SO-8 and MSOP, LTC1861 MSOP 1 VCC V
Analog Input Leakage Current (Note 4) l±1 μA
CIN Input Capacitance In Sample Mode
During Conversion
12
5
pF
pF
The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are TA = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defi ned in Recommended Operating Conditions, unless otherwise noted.
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 72 dB
S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 71 dB
THD Total Hamonic Distortion Up to 5th Harmonic 100kHz Input Signal 77 dB
Full Power Bandwidth 20 MHz
Full Linear Bandwidth S/(N + D) ≥ 68dB 125 kHz
TA = 25°C.
VCC = 5V, fSAMPLE = 250kHz, unless otherwise specifi ed.
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VCC = 5.25V l2.4 V
VIL Low Level Input Voltage VCC = 4.75V l0.8 V
IIH High Level Input Current VIN = VCC l2.5 μA
IIL Low Level Input Current VIN = 0V l–2.5 μA
VOH High Level Output Voltage VCC = 4.75V, IO = 10μA
VCC = 4.75V, IO = 360μA
l
l
4.5
2.4
4.74
4.72
V
V
VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA l0.4 V
The ● denotes specifi cations which apply
over the full operating temperature range, otherwise specifi cations are TA = 25°C.
VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1860/LTC1861
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS
The ● denotes specifi cations which apply
over the full operating temperature range, otherwise specifi cations are TA = 25°C.
VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOZ Hi-Z Output Leakage CONV = VCC l±3 μA
ISOURCE Output Source Current VOUT = 0V –25 mA
ISINK Output Sink Current VOUT = VCC 20 mA
IREF Reference Current (LTC1860 SO-8,
MSOP and LTC1861 MSOP)
CONV = VCC
fSMPL = fSMPL(MAX)
l
l
0.001
0.05
3
0.1
μA
mA
ICC Supply Current CONV = VCC After Conversion
CONV = VCC After Conversion, H-Grade
fSMPL = fSMPL(MAX)
l
l
l
0.001
0.001
0.85
3
5
1.3
μA
μA
mA
PDPower Dissipation fSMPL = fSMPL(MAX) 1.25 mV
RECOMMENDED OPERATING CONDITIONS
The ● denotes specifi cations which apply over
the full operating temperature range, otherwise specifi cations are TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 4.75 5.25 V
fSCK Clock Frequency
H-Grade
l
l
20
16.7
MHz
MHz
tCYC Total Cycle Time 12 • SCK + tCONV μs
tSMPL Analog Input Sampling Time LTC1860 (Note 5)
LTC1861 (Note 5)
12
10
SCK
SCK
tsuCONV Setup Time CONV↓ Before First SCK↑,
(See Figure 1) H-Grade
60
65
30
30
ns
ns
thDI Holdtime SDI After SCK↑LTC1861 15 ns
tsuDI Setup Time SDI Stable Before SCK↑LTC1861 15 ns
tWHCLK SCK High Time fSCK = fSCK(MAX) 40% 1/fSCK
tWLCLK SCK Low Time fSCK = fSCK(MAX) 40% 1/fSCK
tWHCONV CONV High Time Between Data Transfer
Cycles
(Note 5) tCONV μs
tWLCONV CONV Low Time During Data Transfer (Note 5) 12 SCK
thCONV Hold Time CONV Low After Last SCK↑13 ns
LTC1860/LTC1861
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Integral nonlinearity is defi ned as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Guaranteed by design, not subject to test.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONV Conversion Time (See Figure 1)
H-Grade
l
l
2.75
2.75
3.2
3.3
μs
μs
fSMPL(MAX) Maximum Sampling Frequency
H-Grade
l
l
250
248
kHz
kHz
tdDO Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF, H-Grade
l
l
15 20
25
30
ns
ns
ns
tdis Delay Time, CONV↑ to SDO Hi-Z
H-Grade
l
l
30
30
60
65
ns
ns
ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF
CLOAD = 20pF, H-Grade
l
l
30
30
60
65
ns
ns
thDO Time Output Data Remains Valid After
SCK↓
CLOAD = 20pF l510 ns
trSDO Rise Time CLOAD = 20pF 8 ns
tfSDO Fall Time CLOAD = 20pF 4 ns
TIMING CHARACTERISTICS
The ● denotes specifi cations which apply over the full operating temperature
range, otherwise specifi cations are TA = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defi ned in Recommended Operating
Conditions, unless otherwise noted.
LTC1860/LTC1861
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sampling
Frequency Supply Current vs Temperature Sleep Current vs Temperature
Reference Current vs
Sample Rate
Reference Current vs
Temperature
Reference Current vs
Reference Voltage
Typical INL Curve Typical DNL Curve
Analog Input Leakage vs
Temperature
SAMPLING FREQUENCY (kHz)
0.01
SUPPLY CURRENT (MA)
1000
100
10
1
0.1
0.01 100
1860/61 G01
0.1 1.0 10 1000
CONV LOW = 800ns
TA = 25oC
VCC = 5V
TEMPERATURE (oC)
–50
SUPPLY CURRENT (MA)
1000
800
600
400
200
0
050 75
1860/61 G02
–25 25 100 125
CONV HIGH = 3.2MS
fSMPL = 250kHz
VCC = 5V
VREF = 5V
TEMPERATURE (oC)
–50
SLEEP CURRENT (nA)
1000
900
800
700
600
500
400
300
200
100
0050 75
1860/61 G03
–25 25 100 125
CONV = VCC = 5V
SAMPLE RATE (kHz)
0
REFERENCE CURRENT (MA)
60
50
40
30
20
10
050 100 150 200
1860/61 G04
250
CONV IS LOW FOR 800ns
TA = 25oC
VCC = 5V
VREF = 5V
TEMPERATURE (oC)
–50
REFERENCE CURRENT (MA)
55
54
53
52
51
50
49
48
47
46
45 050 75
1860/61 G05
–25 25 100 125
fS = 250kHz
VCC = 5V
VREF = 5V
VREF (V)
0
IREF (MA)
60
50
40
30
20
10
01234
1860/61 G06
5
fS = 250kHz
TA = 25oC
VCC = 5V
CODE
0
INL COC ERROR (LSBs)
4096
1860/61 G07
1024 2048 3072
1.0
0.5
0
–0.5
–1.0 512 1536 2560 3584
TA = 25oC
VCC = 5V
VREF = 5V
CODE
0
DNL EOC ERROR (LSBs)
4096
1860/61 G07
1024 2048 3072
1.0
0.5
0
–0.5
–1.0 512 1536 2560 3584
TA = 25oC
VCC = 5V
VREF = 5V
TEMPERATURE (oC)
–50
ANALOG INPUT LEAKAGE (nA)
100
1860/61 G09
050
100
75
50
25
0
–25 25 75 125
VCC = 5V
VREF = 5V
CONV = 0V
LTC1860/LTC1861
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TYPICAL PERFORMANCE CHARACTERISTICS
Change in Offset Error vs
Reference Voltage Change in Offset vs Temperature
Change in Gain Error vs
Reference Voltage
Change in Gain Error vs
Temperature
Signal-to-(Noise + Distortion)
vs Input Level 4096 Point FFT
Signal-to-(Noise + Distortion)
vs fIN
Total Harmonic Distortion
vs fIN
Spurious Free Dynamic Range
vs fIN
REFERENCE VOLTAGE (V)
0
CHANGE IN OFFSET ERROR (LSB)
5
4
3
2
1
0
–1
–2
–3
–4
–5 4
1860/61 G10
1235
TA = 25oC
VCC = 5V
TEMPERATURE (oC)
–50
CHANGE IN OFFSET (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 050 75
1860/61 G11
–25 25 100 125
VCC = 5V
REFERENCE VOLTAGE(V)
0
CHANGE IN GAIN ERROR (LSB)
5
4
3
2
1
0
–1
–2
–3
–4
–5 245
1860/61 G12
13
VCC = 5V
TA = 25oC
TEMPERATURE (oC)
–50
CHANGE IN GAIN ERROR (LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 050 75
1860/61 G13
–25 25 100 125
VCC = 5V
VREF = 5V
INPUT LEVEL (dB)
–40
SIGNAL-TO-(NOISE + DISTORTION) (dB)
1195 G20
–30–35 –25 –15–20 –5–10 0
80
70
60
50
40
30
20
10
0
fIN = 10kHz
TA = 25oC
VCC = 5V
f (kHz)
0607090
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120 10 20 30 8040
1860/61 G15
10050
fS = 204.1kHz
fIN = 99.5kHz
TA = 25oC
VCC = 5V
fIN (kHz)
SIGNAL-TO-(NOISE + DISTORTION) (dB)
100
90
80
70
60
50
40
30
20
10
01 100 1000 10000
1860/61 G16
10
TA = 25oC
VCC = 5V
VIN = 0dB
SNR
SINAD
fIN (kHz)
1
TOTAL HARMONIC DISTORTION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 10 100 1000
1860/61 G17
TA = 25oC
VCC = 5V
VIN = 0dB
fIN (kHz)
1
SPURIOUS FREE DYNAMIC RANGE (dB)
100
90
80
70
60
50
40
30
20
10
010 100 1000
1860/61 G18
TA = 25oC
VCC = 5V
VIN = 0dB
LTC1860/LTC1861
9
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PIN FUNCTIONS
LTC1860
VREF (Pin 1): Reference Input. The reference input defi nes
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN+, IN– (Pins 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is fi nished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
LTC1861 (MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is fi nished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied directly
to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied directly
to an analog ground plane.
SDI (Pin 6):
Digital Data Input. The A/D confi guration
word is shifted into this input.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 8): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 9):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
VREF (Pin 10): Reference Input. The reference input defi nes
the span of the A/D converter and must be kept free of
noise with respect to AGND.
LTC1861 (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is fi nished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
SDI (Pin 5):
Digital Data Input. The A/D confi guration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8):
Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the analog
ground plane. VREF is tied internally to this pin.
LTC1860/LTC1861
10
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FUNCTIONAL BLOCK DIAGRAM
TEST CIRCUITS
Load Circuit for tdDO, tr
, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr
, tf
Voltage Waveforms for SDO Delay Times, tdDO and thDO
Voltage Waveforms for ten Voltage Waveforms for tdis
1860/61 BD
12-BIT
SAMPLING
ADC
BIAS AND
SHUTDOWN
CONVERT
CLK
SERIAL
PORT
12-BITS
IN+
(CH0)
IN–
(CH1)
VCC
VREF
SDO
GND
CONV (SDI) SCK
PIN NAMES IN
PARENTHESES
REFER TO LTC1861
DATA OUT
DATA IN
+
–
SDO
3k
20pF
TEST POINT
VCC tdis WAVEFORM 2, ten
tdis WAVEFORM 1
1860 TC01
SDO
trtf1860 TC04
VOH
VOL
1860 TC03
CONV
SDO
ten
SCK
SDO
VIL
tdDO
thDO
VOH
VOL
1860 TC02
SDO
WAVEFORM 1
(SEE NOTE 1)
VIH
tdis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONV
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1860 TC05
LTC1860/LTC1861
11
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APPLICATIONS INFORMATION
LTC1860 OPERATION
Operating Sequence
The LTC1860 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV
, the conversion is
fi nished. If CONV is left high after this time, the LTC1860
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1860 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely. See Figure 1.
Analog Inputs
The LTC1860 has a unipolar differential analog input. The
converter will measure the voltage between the “IN+”
and “IN–” inputs. A zero code will occur when IN+ minus
IN– equals zero. Full scale occurs when IN+ minus IN–
equals VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
is grounded and VREF is tied to VCC, a rail-to-rail input
span will result on “IN+” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1860 (and the
LTC1861 MSOP package) defi nes the full-scale range of
the A/D converter. These ADCs can operate with reference
voltages from VCC to 1V.
Figure 1. LTC1860 Operating Sequence
Figure 3. LTC1860 with Rail-to-Rail Input SpanFigure 2. LTC1860 Transfer Curve
CONV
tCONV
SCK
SDO
121110987654321
B11 B10 B8 B6 B4 B2 B0* Hi-Z
Hi-Z
B9 B7 B5 B3 B1
SLEEP MODE
tSMPL
tsuCONV
*AFTER COMPLETING THE DATA TRANSFER
,
IF FURTHER
0V
1LSB
VREF – 2LSB
VREF – 1LSB
VREF
VIN*
*VIN = IN+ – IN–
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1860 F02
1
2
3
4
8
7
6
5
VREF
IN+
IN–
GND
VCC
SCK
SDO
CONV
LTC1860
1860 F03
VIN = 0V TO VCC
VCC
1MF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
LTC1860/LTC1861
12
18601fa
APPLICATIONS INFORMATION
LTC1861 OPERATION
Operating Sequence
The LTC1861 conversion cycle begins with the rising edge
of CONV. After a period equal to tCONV
, the conversion is
fi nished. If CONV is left high after this time, the LTC1861
goes into sleep mode. The LTC1861’s 2-bit data word is
clocked into the SDI input on the rising edge of SCK after
CONV goes low. Additional inputs on the SDI pin are then
ignored until the next CONV cycle. The shift clock (SCK)
synchronizes the data transfer with each bit being trans-
mitted on the falling SCK edge and captured on the rising
SCK edge in both transmitting and receiving systems.
The data is transmitted and received simultaneously (full
duplex). After completing the data transfer, if further SCK
clocks are applied with CONV low, SDO will output zeros
indefi nitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
confi guration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND (or AGND). A zero code will occur when
the “+” input minus the “–” input equals zero. Full scale
occurs when the “+” input minus the “–” input equals
VREF minus 1LSB. See Figure 5. Both the “+” and “–”
inputs are sampled at the same time so common mode
noise is rejected. The input span in the SO-8 package is
fi xed at VREF = VCC. If the “–” input in differential mode
is grounded, a rail-to-rail input span will result on the
“+” input.
Figure 4. LTC1861 Operating Sequence
Figure 5. LTC1861 Transfer Curve
CONV
SDI
SCK
121110987654321
SDO B11 B10 B8 B6 B4 B2 B0* Hi-Z
B9 B7 B5 B3 B1
S/D O/S DON’T CAREDON’T CARE
tCONV
1860 F04
SLEEP MODE
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Hi-Z
tSMPL
0V
1LSB
VCC – 2LSB
VCC – 1LSB
VCC
VIN*
*VIN = (SELECTED “+” CHANNEL) –
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1860 F05
MUX ADDRESS
Table 1. Multiplexer Channel Selection
SGL/DIFF
1
1
0
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
186465 TBL1
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
LTC1860/LTC1861
13
18601fa
APPLICATIONS INFORMATION
Reference Input
The reference input of the LTC1861 SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference input
of the LTC1861 MSOP package defi nes the span of the A/D
converter. The LTC1861 MSOP package can operate with
reference voltages from 1V to VCC.
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1860/LTC1861 should be used with an analog
ground plane and single point grounding techniques. Do not
use wire wrapping techniques to breadboard and evaluate
the device. To achieve the optimum performance, use a
printed circuit board. The ground pins (AGND and DGND
for the LTC1861 MSOP package and GND for the LTC1860
and LTC1861 SO-8 package) should be tied directly to the
analog ground plane with minimum lead length.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with
a minimum of 1μF tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1860/LTC1861
have capacitive switching input current spikes. These cur-
rent spikes settle quickly and do not cause a problem if
source resistances are less than 200Ω or high speed op
amps are used (e.g., the LT
®
1211, LT1469, LT1807, LT1810,
LT1630, LT1226 or LT1215). But if large source resistances
are used, or if slow settling op amps drive the inputs, take
care to ensure the transients caused by the current spikes
settle completely before the conversion begins.
LTC1860/LTC1861
14
18601fa
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
PACKAGE DESCRIPTION
MSOP (MS8) 0307 REV F
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 p 0.0508
(.004 p .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 p 0.152
(.193 p .006)
8765
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
MSOP (MS) 0307 REV E
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12345
4.90 p 0.152
(.193 p .006)
0.497 p 0.076
(.0196 p .003)
REF
8910 76
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
0.50
(.0197)
BSC
0.1016 p 0.0508
(.004 p .002)
LTC1860/LTC1861
15
18601fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)s 45o
0o– 8o TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 p.005
RECOMMENDED SOLDER PAD LAYOUT
.045 p.005
.050 BSC
.030 p.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
LTC1860/LTC1861
16
18601fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 1207 REV A • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION
12-Bit Serial I/o ADCs
LTC1286/LTC1298 12.5ksps/11.1ksps 1.3mW/1.7mW 1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V
LTC1400 400ksps 75mW 1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V
LTC1401 200ksps 15mW SO-8 with Internal Reference, 3V
LTC1402 2.2Msps 90mW Serial I/O, Bipolar or Unipolar, Internal Reference
LTC1404 600ksps 25mW SO-8 with Internal Reference, Bipolar or Unipolar, 5V
14-Bit Serial I/O ADCs
LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V
LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V
16-Bit Serial I/O ADCs
LTC1609 200ksps 65mW Confi gurable Bipolar or Unipolar Input Ranges, 5V
LTC1864/LTC1865 250ksps 4.25mW SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V
References
LT1460 Micropower Precision Series Reference Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23
LT1790 Micropower Low Dropout Reference 60μA Supply Current, 10ppm/°C, SOT-23
Sample Two Channels Simultaneously with a Single Input ADC
–
+
–
+
0.1MF
0.1MF
0.1MF
0.1MF
1MF
1MF
0.1MF1MF
1007
1007
28.7k
10k
4.096V
REF
5V
5V
5k
5k
10k
20k
100pF
100pF
5pF
1/2
LT1492
1/2
LT1492
f1
(0V TO 0.66V)
f2
(0V TO 2V) 8
4
2
81
7
6
5
4
3
4.096V
REF
LTC1860
IN+
IN–
VCC
GND
CONV
SDO
SCK
REF
1860 TA03
