GE28F128W18TD60 - Intel - Product.Network

1.8 Volt Intel® Wirele ss Flash Memor y

(W18)

28F320W18, 28F640W18, 28F128W18

Preliminary Datasheet

Product Features

The 1.8 Volt Intel® Wireless Flash memory with flexible multi-partition dual-operation provides high-

performance asynchronous and synchronous burst reads. It is an ideal memory for low-voltage burst CPUs.

Combining hi gh read perform ance wi th fl ash mem ory’s intrinsic non-volatility, 1.8 Vo lt Intel Wireless Flash

memory eliminates the traditional system-performance paradigm of shadowing redundant code memory from

slow nonvolatil e sto ra ge to faster execution memory. It reduces the total memory requirement that increase s

reliability and reduces overall system power consumption and cost.

The 1.8 Volt I nte l W i reles s F lash me mory’s flexible multi-p artitio n architectu re allows progr amming or erasing to

occur in one partition while reading from another partition. This allows for higher data write throughput

compared to single partition architectures. The dual-operation architecture also allows two processors to

inte rl eave cod e operati ons while progra m and erase operatio n s ta ke place in the backgr ound. The designer can

also choose the size of the code and data partitions via the flexible multi-partition architecture.

The 1.8 Volt Intel W ir eless Flas h memory is manuf acture d on In tel’s 0.18 µm ETOX™ VII process technology . It

is ava il able in µBGA and VF BGA packag es w hi ch are ideal for boar d-constr ained applications.

■Performance

—70 ns Asy nchrono us reads for 32 and 64 Mbit ,

90 ns for 128 M bit

—14 ns Clock to Data Out put (tCHQV)

—20 ns Pa ge Mode Read Speed

—4-Word, 8-Word, and Continuous-Word Burst

Modes

—Burst and Page Modes in Parameter and Main

Partitions

—Programmable WAIT Configuratio n

—Enhanced Factory Programming Mode@

3.50 µs/Word (Typ)

—Glu el ess 12 V in te rface for Fast Fact or y

Progr am ming @ 8 µs/Word (Typ)

—1.8 V Low-Power Programming @ 12 µs/Word

(Typ)

—Program or Er as e during Reads

■Architecture

—Multiple 4-Mbit Partitions

—Dual-Operation: R ead-Whil e-Write or Read-

While-Erase

—Eight, 4-Kword Parameter Code and Data

Blocks

—32-Kword Main Code and Data Blocks

—Top and Bottom Parameter Configurat i ons

■Power Operation

—1.7 V to 1.95 V Read and Write Operations

—1.7 V to 2.24 V VCCQ for I/O Isola tio n

—Standby Current: 5 µA (Typ)

—Read Current: 7 mA (Typ)

■Software

—5 µs (Typ) Program Suspend

—5 µs (Typ) Erase Suspend

—Intel® Flash Data In tegrat or (FD I) Software

Optimized

—Intel Basic Command Set Compatible

—Common Flash Interface (CFI)

■Quality and Reliability

—Extended Temper at ur e: –40 °C to +85 °C

—Minim um 100,00 0 Erase Cycles per Blo ck

—ETOX™ VII Fla sh Techno lo gy (0.18 µm)

■Security

—128-bit Pr ot ection Reg is t er: 64 Unique Devi ce

Identifier Bits; 64 User-Programmable OTP

Bits

—Absolute Write Protection ⇒VPP = GND

—Erase/Program Lockout du ri ng Power

Transitions

—Indivi dual Dynam ic Zer o- L atency Bloc k

Locking

—Indi vi dual Block Lock-Dow n

■Density and Packaging

—32 Mbit and 128 Mbit in a VF BGA Packag e

—64 Mbit in a µBGA*Package

—56 Active Ball Matrix, 0.75 mm Ball-Pitch

µBGA* and VF BGA Packages

—16-bit wide Data Bus

290701-003

Jun e 2001

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any

intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no

liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are

not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to the m.

The 1.8 Volt Intel® Wireless Flash memory may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-8 00-

548-4725 or by visiting Intel's website at http://www.intel.com.

*Other names an d brands may be claimed a s the property of others.

iii

1.8 Volt Intel® Wireless Flash Memory (W18)

Contents

1.0 Introduction..................................................................................................................1

1.1 Document Conventions.........................................................................................1

1.2 Product Overview..................................................................................................2

2.0 Product Description..................................................................................................4

2.1 Package and Ballouts............................................................................................4

2.2 Signal Descriptions................................................................................................4

2.3 Memory Partitioning ..............................................................................................6

3.0 Principles of Operation............................................................................................9

3.1 Bus Operations......................................................................................................9

3.1.1 Read.........................................................................................................9

3.1.2 Standby..................................................................................................10

3.1.3 Write.......................................................................................................10

3.1.4 Reset......................................................................................................10

4.0 Command Definitions.............................................................................................11

4.1 Read-While-Write and Read-While-Erase...........................................................11

4.2 Read Array Command.........................................................................................14

4.3 Read Identifier Command ...................................................................................14

4.4 Read Query Command .......................................................................................15

4.5 Read Status Register Command.........................................................................15

4.6 Clear Status Register Command.........................................................................17

4.7 Word Program Command ...................................................................................17

4.8 Block Erase Command........................................................................................18

4.9 Program Suspend, Program Resume, Erase Suspend,

Erase Resume Commands.................................................................................20

4.10 Enhanced Factory Program Command (EFP) ....................................................23

4.10.1 EFP Requirements and Considerations.................................................23

4.10.2 Setup Phase...........................................................................................24

4.10.3 Program Ph ase ........... ....... ...... ...... ....... ...... .................... ...... ....... ...... ....24

4.10.4 Verify Phase...........................................................................................24

4.10.5 Exit Phase..............................................................................................25

4.11 Security Modes....................................................................................................27

4.12 Block Locking Commands...................................................................................27

4.12.1 Lock Block..............................................................................................28

4.12.2 Unlock Block...........................................................................................28

4.12.3 Lock-Down Block....................................................................................28

4.12.4 Block Lock Status...................................................................................29

4.12.5 Locking Operations During Erase Suspend...........................................29

4.12.6 Status Register Error Checking..............................................................29

4.12.7 WP# Lock-Down Control........................................................................30

4.13 Protection Register..............................................................................................30

4.14 Read Protection Register....................................................................................31

4.15 Program Prote ct ion Register.............................. ...... ....... ...... ....... ................... ....31

4.15.1 Lock Protection Register........................................................................32

4.16 Set Configuration Register..................................................................................34

1.8 Volt Intel® Wireless Flash Memory ( W18)

4.16.1 Read Mode (CR.15)...............................................................................35

4.16.2 First Access Latency Count (CR.13-11).................................................35

4.16.3 WAIT Signal Polarity (CR.10).................................................................37

4.16.4 WAIT Signal Function ............................................................................38

4.16.5 Data Output Configuration (CR.9)..........................................................38

4.16.6 WAIT Delay Configuration (CR.8)..........................................................39

4.16.7 Burst Sequence Configuration (CR.7)....................................................40

4.16.8 Clock Configuration (CR.6) ....................................................................41

4.16.9 Burst Wrap (CR.5)..................................................................................41

4.16.10 Burst Length (CR.2-0)............................................................................42

5.0 Program and Erase Voltages..............................................................................43

5.1 Factory Program Mode .......................................................................................43

5.2 Programming Voltage Protection (VPP)..............................................................43

6.0 P ower Consumption...............................................................................................44

6.1 Active Power.......................................................................................................44

6.2 Automatic Power Savings ...................................................................................44

6.3 Standby Power....................................................................................................44

6.4 Power-Up/Down Operation.................................................................................44

6.4.1 System Reset and RST#........................................................................44

6.4.2 VCC, VPP, and RST# Transitions.................. ....... ...... ....... ...... ....... .......45

6.4.3 Power Supply Decoupling......................................................................45

7.0 Electrical Specifications........................................................................................46

7.1 Absolute Maximum Ratings ................................................................................46

7.2 Extend ed Tempe ratur e Oper ati on...... ...... ...... ....... ...... .................... ...... ....... ...... .47

7.3 Capacitance ........................................................................................................47

7.4 DC Characteristics ..............................................................................................48

7.5 AC I/O Test Conditions .......................................................................................50

7.6 AC Read Characteristics.....................................................................................51

7.7 AC Write Characteristics.....................................................................................61

7.8 Erase and Program Times..................................................................................63

7.9 Reset Specifications............................................................................................63

Appendix A Write State Machine States.............................................................................65

Appendix B Common Flash Interface.................................................................................68

Appendix C Mechanical Specifications..............................................................................76

Appendix D Ordering Information.........................................................................................77

1.8 Volt Intel® Wireless Flash Memory (W18)

Revision History

Date of

Revision Version Description

09/13/00 290701-001 Original Version

01/29/01 290701-002 Deleted 16-Mbit density

Revised ADV#, Section 2.2

Revised Protection Registers, Section 4.16

Revised Program Protection Register, Section 4.18

Revised Example in F irst Acces s Latency Count, Section 5.0.2

Revised Figure 5, Data Output with LC Setting at Code 3

Added WAIT Signal Function, Section 5.0.3

Revised WAIT Signal Polarity, Section 5.0.4

Revised Data Output Configuration, Section 5.0.5

Added Figure 7, Data Output Configuration with WAIT Signal Delay

Revised WAIT Delay Configuration, Section 5.0.6

Changed VCCQ Spec from 1.7 V – 1.95 V to 1.7 V – 2.24 V in Section 8.2,

Extended Temperature Operation

Changed ICCS Spec from 15 µ A to 18 µA in Section 8.4, DC

Characteristics

Changed ICCR Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13

mA (CLK = 52 MHz, burst length = 4) to 13 mA, and 16 mA respectively in

Section 8.4, DC Characteristics

Changed ICCWS Spec from 15 µA to 18 µA in Section 8.4, DC

Characteristics

Changed ICCES Spec from 15 µA to 18 µA in Section 8.4, DC

Characteristics

Changed tCHQX Spec from 5ns to 3ns in Section 8.6, AC Read

Characteristics

Added Figure 25, WAIT Signal in Synchronous Non-Read Array Operation

Waveform

Added Figure 26, WAIT Signal in Asynchronous Page Mode Read

Operation Waveform

Added Figure 27, WAIT Signal in Asynchronou s Single Word Read

Operation Waveform

Revised Appendix E, Ordering Information

06/12/01 290701-003 Revised entire Section 4.10, Enhanced Factory Program Command (EFP)

and Figure 6, Enhanced Factory Program Flowchart

Revised Section 4.13, Protection Register

Revised Section 4.15, Program Protecti on Register

Revised Section 7.3, Capacitance, to include 128-Mbit specs

Revised Section 7.4, DC Characteristics, to include 128-Mbit specs

Revised Section 7.6, AC Read Characteristics, to include 128-Mbit device

specifications

Added tVHGL Spec in Section 7.6, AC Read Characteristics

Revised Section 7.7, AC Write Characteristics, to include 128-Mbit device

specifications

Minor text edits

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 1

1.0 Introduction

This datasheet contains information about the 1.8 Volt Intel® Wireless Flash memory family.

Section 1.0 provides a flash memory overview. Section 2. 0 through Section 6.0 describe the

memory func tionality. Section 7.0 describes the electrical specifications for extended temperature

produc t offerings.

1.1 Document Conventions

Many terms and phrases are used throughout this document as a short-hand version of full, and

more accurate verbiage:

•The term “1.8 V” refers to the full VCC voltage range of 1.7 V – 1.95 V (except where noted)

and “VPP =12V” refers to 12 V ±5%.

•When referring to registers, the term set means the bit is a ‘1’, and clear means the bit is a ‘0’.

•Even though this product supports multiple package typ e s, the term s pin and signal are often

used interchangeably to refer to the external signal connections on the package. (e.g., balls in

the case of µBGA*).

•A word is 2 bytes, or 16 bit s .

•For voltage and ground signals, the signal name is denoted in all CAPS as seen in Sectio n 2.2,

“Sign al Descriptions” on page 4, whereas the voltage applied to the sig nal uses subscripte d

notation. For example VPP r efers to a sig nal, while VPP is a voltage level.

Throughout this document, references are made to top, bottom, parameter, and main partitions. To

clarify these references, the following conventions have been adopted:

•A block is a group of bits (or words) that erase simultaneously with one block erase

instruction.

•A main block contains 32 Kwords.

•A parameter block contains 4 Kwords.

•The Block Base Address (BBA) is the first address of a block.

•A partition is a group of blocks that share erase and program circuitry and a common status

than array data, is available when any address within the same partition is read.

•The Partition Ba se Address (PBA) is the first address of a partition. For example, on a 32-

Mbit top-parameter device, partitio n number 5 has a PBA of 140000h.

•The top partition is located at the highest physical device address. This partition may be a

main partition or a parame ter partition.

•The bo tt o m par tit io n is located at the lowest physical device address. This partition may be a

main partition or a parame ter partition.

•A main partition contains only main blocks.

•A parameter partition contains a mixture of main and parameter blocks.

•A t op parameter device (TPD) has the parameter partition at the top of the memory map with

the parameter blocks at the top of that partiti on. This was formerly referred to as top-boot

device.

1.8 Volt Intel® Wireless Flash Memory (W18)

2Preliminary

•A bottom parameter device (BPD) has the parameter partition at the bottom of th e memory

map with the parameter blocks at the bottom of that partition. This was formerly referred to as

bottom-boot block flash device.

Additionally, many acronyms which describe product features or usage are used throughout the

document. They are defined here:

•EFP: Enhanced Factory Programming

•RWW: Re ad-Whil e-Write

•RWE: Read-While-Erase

•CFI: Common Flash Interface

•CUI: Command User Interface

•WSM: Write State Machine

•OTP: One-Time Programmable

•PBA: Partition Base Address

•BBA: Block Base Address

•APS: Automatic Power Savings

•FDI: Flash Data Integrator

•SRD: Status Register Data

1.2 Product Overview

The 1.8 Volt Intel® Wireless Flash memory provides RWW/RWE capability with high-

performance synchronous and asynchronou s reads on package-compati ble densities with a 16-bit

data bus. In divid ually-era sable memory block s are optimal ly sized fo r code and data st orage. Ei ght

4-Kword parameter blocks are located in the par ameter p art itio n at either the top or bottom of the

memory map. The rest of the memory array is grouped into 32-Kword main blocks.

The memory architecture for the 1.8 V Intel Wi reless Flash memory consists of multiple 4-Mbit

partitions, the exact number depending on device density. By dividing the memory array into

partitions, program or erase operations can take place simu ltaneously during read operations. Burst

reads can traverse partition boundaries, but user application code is responsible for ensuring that

they don’t extend into a partition that is actively programming or erasing. Although each partition

has burst-read, write, and erase capabilities, simultaneous o peration is lim ited to write or erase in

one partition while other partitions are in a read mode.

Augmented erase su spend functionality fur ther en hances the RWW capabilities of this device. An

erase can be suspended to perform a program or read operati on within any block, except that which

is erase-suspended. A program operation nested within a suspended erase can subsequently be

suspended to read yet another memory location.

After device power-up or reset, the 1.8 Volt Intel Wireless Flash memory defaults to asynchronous

read configuration. Writing to the de vice’s configuration register enables synchronous burst-mode

read operation. In synchronous mode, the CLK input increments an internal burst address

generator. CLK also synchronizes the flash memory with the host CPU and outputs data on every,

or on every other, CLK cycle after initial latency. A programmable WAIT output signal provides

easy CPU-to-flas h memory sy nchronization.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 3

In addition to its enhanced architecture and interface, the 1.8 Volt Intel Wireless Flash memory

incorporates technology that enables fast factory programming and low-power designs. The EFP

option renders the fastest available program performance, which can increase a factory’s

manufacturing throughput.

The device supports read op eration s at 1.8 V VCC and erase and program operation s at 1 .8 V or 1 2

V VPP. With the 1.8 V VPP option, VCC and VPP can be tied together for a simple, ultra-lo w-

power design. In additio n to voltage flexibility, th e dedicated VPP input provides complete data

protection when VPP ≤ VPPLK.

A 128-bit protection register enhances the user’s ability to implement new security techniques and

data protection schemes. Unique flash device identification and fraud-, cloning-, or content-

protection schemes are possible via a combination of Intel-programmed and user-OTP data cells.

Zero-latency locking /unlo cking on any memory b lock provides instant and co mplete p rotecti on fo r

critical system code and data. An additional block lock-down capability provides hardware

protection where software commands alone cannot change the block’s protection status.

The device’s C U I is the sy stem processor’s link to internal flash memory operation. A valid

command sequence written to the CUI initiates device WSM operation that automatically executes

the algorithms, timings, and verifications necessary to manage flash memory program and erase.

An internal status register provides ready/busy indication results of the operation (success, fail,

etc.).

Three power-savings features, APS, standby, and RST#, can significantly reduce power

consumption. The device automatically enters APS mode following read cycle completion.

Standby mode begins when the system deselects the flash memory by deasserting CE#. Driving

RST# low produces power savings similar to standby mode. It also resets the part to read array

mode (important for system-level reset), clears internal status registers, and provides an additional

level of flash write protection.

1. 8 Vol t Inte l® Wireless Flash Mem ory (W18)

4Preliminary

2.0 Product Description

2.1 Packa ge and Ballouts

The 1.8 Volt Intel® Wireless Fla sh memory is available in 56 acti ve ball matrix µBGA* and VF

BGA Chip Scal e Packag es with 0. 75 mm ball pitch tha t is idea l for board-c onstra ined app licat ion s.

Fi gure 1, “56 Active Ball Matrix µBGA* an d VF BGA Packages” on page 4 shows devi ce ballout .

NOTES:

1. On lower density devices, upper address balls can be treated as NC. (Example: For 32-Mbit density, A[21]

and A[22] will be NC).

2. See Appendix C, “Mechanical Specifications” on page 76 for package mechanical specifications.

2.2 Signal Descriptions

Tab le 1, “Signal Descriptio ns” on page 5 describes ball us age.

Figure 1. 56 Active Ball Matrix µBG A* and VF BGA Packages

Top View - Ball Side Dow n

Complete In k Mark Not Shown

8 7 6 5 4 3 2 11 2 3 4 5 6 7 8

Bottom View - Ball Side Up

A4 A6 A18 VPP VCC VSS A8 A11

A3 A5 A17 RST# CLK A20 A9 A12

A2 A7 WE# ADV#

A19 A10 A13

A1 A14WP# DQ12 A16 WAIT A15

A0 CE# DQ1 DQ2 DQ4 DQ6 DQ15 VCCQ

OE# DQ0 DQ9 DQ10 DQ11 DQ13 DQ14 VSS

VSSQ DQ8 VCCQ DQ3 VCC DQ5 VSSQ DQ7

A22

A21

A4A6A18VPPVCCVSSA8A11

A3A5A17

RST#

CLKA20A9A12

A2A7

WE#ADV# A19

A10A13

A1A14 WP#DQ12A16WAITA15

A0CE#DQ1DQ2DQ4DQ6DQ15VCCQ

OE#DQ0DQ9DQ10DQ11DQ13DQ14VSS

VSSQDQ8VCCQDQ3VCCDQ5VSSQDQ7

A22

A21

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 5

Table 1. Signal Descriptions

Symbol Type Name and Function

A[22:0] IADDRESS INPUTS: for memory addres ses.

32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]

DQ[15:0] I/O DATA INPUT/ OUTPUTS: Input s data and commands during write cycles, outputs data during memory ,

status register, protection register, and configuration code reads. Data pins float when the chip or

outputs are deselected. Data is internally latched during writes.

ADV# IADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous

read operations, all addresses are latched on ADV#’s rising edge or CLK’s rising (or falling) edge,

whichever occurs first .

CE# ICHIP ENABLE : CE#-low activates internal control logic, I/O buffers, decoders, and sense amps. CE#-

high deselects the device, places it in standby state, and places data and WAIT outputs at High-Z.

CLK ICLOCK: CLK synchronizes the device to the system bus frequency in synchronous-read configuration

and increments an internal burst address generator. During synchronous read operations, addresses

are latched on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.

OE# IOUTPUT ENABLE: Active low OE# enables the device’s output data buf fers during a read cycle. With

OE# at VIH, device data outputs are placed in High-Z state.

RST# IRESET: When low, RST# resets internal automation and inhibits write operations. This provides data

protection during power transitions. RST#-high enables normal operation. Exit from reset places the

device in asynchronous read array mode.

WAIT OWAIT: Indicates data valid in synchronous read modes. Configuration Register bit 10 (CR.10, WT)

determines its polarity when set to ‘1’. With CE# at VIL, WAIT’s active output is VOL or VOH. W A IT is

High-Z if CE# is VIH. WAIT is not gated by OE#.

WE# IWRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the

WE# pulse’s rising edge.

WP# I

WRITE PR OTECT: Disables/enables the lock-down function.

When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot

be unlocked through software.

See Section 4.12, “Block Locking Commands” on page 27 for details on block locking.

VPP Pwr/I

ERASE AND PROGRAM POWER: A valid VPP voltage on this pin allows erase or programming.

Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP

voltages should not be attempted.

Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops

from the system supply, VPP’s VIH level can be as low as VPP1 min. VPP must remain above VPP1 min

to perform in-system flash modification. VPP may be 0 V during read operations.

VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.

VPP can be connected to 12 V for a cumulative total not to exceed 80 hours maximum. Extended use

of this pin at 12 V may reduce block cycling capability.

VCC Pwr DE VICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device operations at invalid VCC

voltages should not be attempted.

VCCQ Pwr OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to

VCC.

VSS Pwr GROUND: Pins for all internal device circuitry must be connected to system ground.

VSSQ Pwr OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied

directly to VSS.

DU DON’T USE: Do not use this pin. This pin should not be connected to any power supplies, signals or

other pins and must be floated.

NC NO CONNECT: No internal connection; can be driven or floated.

1.8 Volt Intel® Wireless Flash Memory (W18)

6Preliminary

2.3 Memory Parti tioning

The 1.8 Volt Intel® Wireless Flash memory is divided into 4-Mbit physical partitions which allows

simultaneous RWW or R WE operation s and allows users to segment code and data areas on 4-Mbit

boundaries. The device’s asymmetrically-blocked architecture enables system code and data

integration within a single flash device. Each block can be erased independently in block erase

mode. Simultaneous pr ogr am and eras e is not allowed. Only o ne p artition at a time can be actively

programming or erasing. See Table 2, “B ott om Param eter Memory Map” on page 7 and Table 3,

“Top Par ameter Memory Ma p” on page 8.

The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit

device has 32 partitions. Each device density contains one parameter partitio n and sev eral main

partitions: the 4-Mbit parameter partition contains eight 4-Kword para meter b locks and seven 32-

Kword main blocks; and each 4-Mbit main partition contains eight 32-Kword blocks each.

The bulk of the array is divided into main blocks that can store code or data, and parameter blocks

allow storage of frequently updated small parameters that would normally be stored in EEPROM.

By using software techniques, the word-rewrite functionality of EEPROMs can be emulated.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 7

Table 2. Bottom Parameter Memory Map

Size

(KW) Blk

#32 Mbit Blk

#64 Mbit Blk

#128 Mbit

Main Partitions Sixteen

Partitions

32 262 7F8000-7FFFFF

...

32 135 400000-407FFF

Eight

Partitions

32 134 3F8000-3FFFFF 134 3F8000-3FFFFF

...

32 71 200000-207FFF 71 200000-207FFF

Four

Partitions

32 70 1F8000-1FFFFF 70 1F8000-1FFFFF 70 1F8000-1FFFFF

...

32 39 100000-107FFF 39 100000-107FFF 39 100000-107FFF

One

Partition

32 38 0F8000-0FFFFF 38 0F8000-0FFFFF 38 0F8000-0FFFFF

...

32 31 0C0000-0C7FFF 31 0C0000-0C7FFF 31 0C0000-0C7FFF

One

Partition

32 30 0B8000-0BFFFF 30 0B8000-0BFFFF 30 0B8000-0BFFFF

...

32 23 080000-087FFF 23 080000-087FFF 23 080000-087FFF

One

Partition

32 22 078000-07FFFF 22 078000-07FFFF 22 078000-07FFFF

...

32 15 040000-047FFF 15 040000-047FFF 15 040000-047FFF

Parameter Par tition

One Partition

32 14 038000-03FFFF 14 038000-03FFFF 14 038000-03FFFF

...

32 8008000-00FFFF 8008000-00FFFF 8008000-00FFFF

4 7 007000-007FFF 7007000-007FFF 7007000-007FFF

...

4 0 000000-000FFF 0000000-000FFF 0000000-000FFF

1.8 Volt Intel® Wireless Flash Memory (W18)

8Preliminary

3.0 Principles of Operation

The 1.8 Volt Intel® Wireless Flash m emory fami ly in clude s an on-chip WSM t o manage bl ock

erase and program algorithms. Its CUI allows minimal processor overhead with RAM-like

interface timings.

Table 3. Top Parameter Memory Map

Size

(KW) Blk

#32 Mbit Blk

#64 Mbit Blk

#128 Mbit

Parameter Partition

One Partition

470 1FF000-1FFFFF 134 3FF000-3FFFFF 262 7FF000-7FFFFF

...

463 1F8000-1F8FFF 127 3F8000-3F8FFF 255 7F8000-7F8FFF

32 62 1F0000-1F7FFF 126 3F0000-3F7FFF 254 7F0000-7F7FFF

...

32 56 1C0000-1C7FFF 120 3C0000-3C7FFF 248 7C0000-7C7FFF

Main Partitions One

Partition

32 55 1B8000-1BFFFF 119 3B8000-3BFFFF 247 7B8000-7BFFFF

...

32 48 18000-187FFF 112 380000-387FFF 240 780000-787FFF

One

Partition

32 47 178000-17FFFF 111 378000-37FFFF 239 778000-77FFFF

...

32 40 140000-147FFF 104 340000-347FFF 232 740000-747FFF

One

Partition

32 39 138000-13FFFF 103 338000-33FFFF 231 738000-73FFFF

...

32 32 100000-107FFF 96 300000-307FFF 224 700000-707FFF

Four

Partitions

32 31 0F8000-0FFFFF 95 2F8000-2FFFFF 223 6F8000-6FFFFF

...

32 0000000-007FFF 64 200000-207FFF 192 600000-607FFF

Eight

Partitions

32 63 1F8000-1FFFFF 191 5F8000-5FFFFF

...

32 0000000-007FFF 128 400000-407FFF

Sixteen

Partitions

32 127 3F8000-3FFFFF

...

32 0000000-007FFF

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 9

3.1 Bus Operations

NOTES:

1. Manufacturer and device codes are accessed in read identifier mode (A[MAX:1]=0).

2. Q uery accesses use only DQ[7:0]. All other accesses use DQ[15:0].

3. X must be VIL or VIH for control pins and addresses.

4. RS T# mu st be at VSS ± 0.2 V to meet the maximum specified power-down current.

5. Ref er to the Table 6, “Bus Cycle Definitions” on page 13 for valid DIN during a write operation.

3.1.1 Read

The 1.8 Volt Intel Wireless Flash memory has several read configurations:

•Asynchronous page mode read.

•Synchronous burst mode read.

—outputs four, eight, or continuous words, from main blocks and parameter blocks.

The device’s partition s have sev e r a l available r ead mo des :

•Read array mode: read accesses return flash array data from the addressed locations.

•Read identifier mode: reads return manufactur er and devic e identifier data, block lock status,

and protection register data. The identification plane occupies the 4-Mbit partition address

locations corresponding to the command’s address; the flash array is not accessible in read

identifier mode.

•Read query mode: reads return device CFI data. The query plane occupies the

4-Mbit partition address locations corresponding to the com mand’s address; the flash array is

not accessible in read query mode.

•Read sta tus r egister mo de: reads return status register data from the addr essed partition. That

partition’s array data is not accessible. A system processor can check the status register to

determine an addressed partition’s state or monitor program and erase progress.

All partitions su pport synchronous burst mode that internally sequences addresses with resp ect to

the input CLK to select and supply data to the outputs.

Identifier codes, query data, and status register read operations execute as single-synchronous or

asynchronous read cycles. WAIT is inactive during these reads.

Access to the modes listed above is independent of VPP. An appropriate CUI command places the

device in a read mode. At initial power-up or after reset, the device defaults to asynchronous read

array mode.

Table 4. Bus Operations

Mode Note RST# CE# OE# WE# ADV# WAIT DQ[15:0]

Read (Array, Status,

Configuration, Identifier, or

Query) 1,2 VIH VIL VIL VIH VIL Valid only in

Synchronous

Mode DOUT

Output Disable 3 VIH VIL VIH VIH XHigh-Z High-Z

Standby 3 VIH VIH X X X High-Z High-Z

Reset 3,4 VIL X X X X High-Z High-Z

Write 5 VIH VIL VIH VIL VIL High-Z DIN

1.8 Volt Intel® Wireless Flash Memory (W18)

10 Preliminary

Asserting CE# enables device read operations. The device internally decodes upper address inputs

to determine which partition is accessed. ADV#-active opens the internal address latches.

Asserting OE# activates the outputs and gates selected data onto the I/O bus. In asynchronous

mode, the address is latched when ADV# is deasserted (when the device is configured to use

ADV#). In synchronous mode, the address is latched by either the rising edge of ADV# or the

rising (or falling) CLK edge while ADV# remains asserted, whichever occurs first. WE# and RST#

must be at deasserted during read operations.

3.1.2 Standby

CE# inactive deselects the device and places it in standby mode, substantially reducing device

power consumptio n. In standby mod e, outputs are placed in a high-imped ance state indepen dent of

OE#. If deselected during a program or erase algorithm, the device will consume active power until

the program or erase operation completes.

3.1.3 Write

A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash control commands

are written to the CUI using standard microp rocess or write timings. The address and data are

latched on the rising edge of WE#. Write operations are asynchronous; CLK is ignored.

The CUI does not occupy an addressab le m emory location within any partition. The system

processor must access it at the correct address range depending on the kind of command executed.

Programming or erasing may occur in only one partition at a time. Other partitions must be in one

of the read modes or erase suspend mode.

Table 5, “Command Codes and Desc riptions ” on page 12 shows the available commands.

Appendix A, “Write State Machine States” on page 65 provides information on moving between

different operating modes using CUI commands.

3.1.4 Reset

The device enters a reset mode when RST# is driven low. In reset mod e, internal circuitry is turned

off and outputs are placed in a high-impedance state.

After returning from r eset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is

required before a write sequence can be initiated. After this wake-u p interval, normal operation is

restored. The device defaults to read array mode, the status register is set to 80h, and the

configuration register defaults to asynchronous page-mode reads.

If RST# is asserted during an erase or program operation, the operation will be aborted and the

memory contents at the aborted block or address are invalid. See Figure 29, “Reset Operations

Waveforms” on page 64 for detailed informatio n regar ding reset timing s.

Like any automated device, it is important to ass ert RST# during system reset. When the system

comes out of reset, the processor expects to read from the flash memory array. Automated flash

memories prov ide status inform ation when read du ring pro gram or er ase operations. If a CPU reset

occurs with no flash memory reset, proper CPU initialization may not occur because the flash

memory may be p rovi d i ng s tat us info rmat ion i n st ead of ar ray d a ta . 1.8 Volt Intel® Flash memories

allow proper CPU initialization following a system reset through the use of the RST# input. In this

application, RST# is controlled by the same CPU reset signal, RESET#.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 11

4.0 Command Definitions

The device’s on-chip WSM manages erase and program algorithms. The local CPU controls the

device’s in-system read, program, and erase operations. Bus cycles to or from the flash memory

conform to standard microprocessor b us cycles. RST#, CE#, OE#, WE#, and ADV# contro l signals

dictate data flow into and out of the device. WAIT informs the CPU of valid data during burst

reads. Table 4, “Bus Operations” on page 9 summarizes bus operations.

Device operations are selected by writing specific commands into the device’s CUI. Table 5,

“Command Codes and Descriptions” on page 12 lists all possible command codes and

descriptions, Table 6, “Bus Cycle Definitions” on page 13 lists command defini tion s. Since

commands are partition-specific, it is important to issue write commands within the target address

range.

Multi-cycle command writes to a flash memory partition mus t be issued sequentially without

intervening command writes. For example, an Erase Setup command to partitio n X must be

immediately followed by the Erase Confirm command in order to be executed properly. The

address given durin g the Erase Co nfirm comman d determines the lo cation of the erase. If the Erase

Confirm command is g iven to partition X, then the command will be executed and a block in

partition X will be erased. Alternatively, if the Erase Confirm command is given to partition Y, the

command will still be execut e d and a block in partition Y will be erased. Any other command

given to any partition prior to the Erase Co nfirm command will result in a command sequence

error, which is posted in the status register. After the erase is successfully started in partition X or

Y, read cycles may occur in any other partition Z (e.g., code or data reads).

4.1 Read-While-Write and Read-While-Erase

The 1.8 Volt Intel® Wireless Flash memor y supports flexible multi- partition dual-operation

architecture. By dividing the flash memory into many sep a rate partitions, the device is capable of

reading from one partition while programing or erasing in another partition; hence the terms, RWW

and RWE. Both of these features greatly enhance data storage performance.

The product does not support simultaneous program and erase operations. Attempting to perform

operations such as these will resu lt in a command sequence error. Only one partition may be

programming or erasing while another partition is reading. However, one partition may be in erase

suspend mode while a second partition is performing a program operation, and yet another partition

may be executing a Read Array command.

Table 5. Command Codes and Descriptions

Mode

Code Device Command Description

Read

FFh Read Array P laces select ed partition in read array mode.

70h Read Status Register Places selected partition in status register read mode. The partition enters this mode after a

Program or Erase command is issued to it.

90h Read Identifier Puts the selected partition in read identifier mode. Device reads from partition addresses

output manufacturer/device codes, configuration register data, block lock status, or

protection register data on DQ[15:0].

98h Read Query Puts the addressed partition in read query mode. Device reads from the partition addresses

output CFI information on DQ[7:0].

50h Clear Status Register The WSM can set the status register’s block lock (SR.1), VPP (SR.3), program (SR.4), and

erase (SR.5) status bits, but it cannot clear them. SR.1,3,4,5 can only be cleared by a devi ce

reset or through the Clear Status Register command.

1.8 Volt Intel® Wireless Flash Memory (W18)

12 Preliminary

NOTE: Do not use unassigned commands. Intel reserves the right to redefine these codes for future functions.

Program

40h Word Program

Setup

This preferred program command’s first cycle prepares the CUI for a program operation. The

second cycle latches address and data and executes the WSM Program algorithm at this

location. S t atus register updates occur when CE# or OE# is toggled. A Read Array command

is required to read array data after programming.

10h Alternate Setup Equivalent to a Program Setup command (40h).

30h EFP Setup This program command activates EFP mode. The first write cycle sets up the command. If

the second cycle is an EFP Confirm command (D0h), subsequent writes provide program

data. All other commands are ignored once EFP mode begins.

D0h EFP Confir m If the first command was EFP Setup (30h), the CUI latches the address and data and

prepares the device for EFP mode.

Erase

20h Erase Setup

Prepares the CUI for Block Erase. The device erases the block addressed by the Erase

Confirm command. If the next command is not Erase Confirm, the CUI:

(a) sets status register bits SR.4 and SR.5,

(b) places the partition in the read status register mode, and

D0h Erase Confirm

If the first command was Erase Setup (20h), the CUI latches address and data and erases

the block indicated by the erase confirm cycle address. During program or erase, the

partition responds only to Read Status Register, Program Suspend, and Erase Suspend

commands. CE# or OE# toggle updates status register data.

Suspend

B0h Program Suspend or

Erase Suspend

This command issued at any device address suspends the currently executing program or

erase operation. The status register , invoked by a Read Status Register command, indicates

successful operation suspension by setting status bits SR.2 (program suspend) or SR.6

(erase suspend) and SR.7. The WSM remains in the suspend mode regardless of control

signal states, except RST# = VIL.

D0h Suspend Resume This command issued at any device address resumes suspended program or erase

operation.

Block Locking

60h Lock Setup Prepares the CUI lock configuration. If the next command is not Block-Lock, Unlock, or Lock-

Down, the CUI sets SR.4 and SR.5 to indicate command sequence error.

01h Lock Block If the previous command was Lock Setup (60h), the CUI locks the addressed block.

D0h Unlock Block If the previous command was Lock Setup (60h) command, the CUI latches the address and

unlocks the addressed block. If previously locked-down, the operation has no effect.

2Fh Lock-Down If the previous command was Lock Setup (60h) command, the CUI latches the address and

locks-down the addressed block.

Protection

C0h Protection Program

Setup

Prepares the CUI for a protection register program operation. The second cycle latches

address and data and starts the WSM’s protection register program or lock algorithm.

Toggling CE# or OE# updates the flash status register data. To read array data after

programming, issue a Read Array command.

Configuration

60h Configuration Setup Prepares the CUI for device configuration. If Set Configuration Register is not the next

command, the CUI sets SR.4 and SR.5 to indicate command sequence error.

03h Set Configuration

If the previous command was Configuration Setup (60h), the CUI latches the address and

writes A[15:0] data into the configuration register. Following a Set Configuration Register

command, subsequent read operations access array data.

Table 5. Command Codes and Descriptions

Mode

Code Device Command Description

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 13

NOTES:

1. First cycle command addresses should be the same as the operation’s target address. Examples: the first-

cycle address for the Read Identifier command should be the same as the Identification code address (IA);

the first cycle address for the Word Program command should be the same as the word address (WA) to be

programmed; the first cycle address for the Erase/Program Suspend comm and should be the same as the

address within the block to be suspended; etc.

XX = Any valid address within the device.

IA = Identification code address.

BA = Block Address. Any address within a specific block.

LPA = Lock Protection Address is obt ained from the CFI (via the Read Query command). The 1.8 Volt Intel

Wireless Flash mem ory fam ily’s LPA is at 0080h.

PA = User programmable 4-word protection address in the device identification plane.

PnA = Any address within a specific partition.

PBA = Partition Base Address. The very first address of a particular partition.

QA = Query code address.

WA = Word address of memory location to be written.

2. S RD = Data read from the status register.

WD = Data to be written at location WA.

IC = Identifier code data.

PD = User programmable 4-word protection data.

QD = Query code data on DQ[7:0].

CD = Configuration register code data presented on device addresses A[15:0]. A[MAX:16] address bits can

se lec t any part itio n. See Table 12, “Conf iguration Register Definitions” on page 34 for configuration register

bits descriptions.

3. Com mands other than those shown above are reserved by Intel for future device implementations and

should not be used.

Table 6. Bus Cycle Definitions

Mode Command Bus

Cycles

First Bus Cycle Second Bus Cycle

Oper Addr(1) Data(2,3) Oper Addr(1) Data(2,3)

Read

Read Array/Reset 1Write PnA FFh

Read Identifier ≥ 2 Write PnA 90h Read PBA+IA IC

Read Query ≥ 2 Write PnA 98h Read PBA+QA QD

Read S tatus Register 2Write PnA 70h Read BA SRD

Clear S tatus Register 1Write XX 50h

Program

Erase

Block Era se 2Write BA 20h Write BA D0h

Word Program 2Write WA 40h/10h Write WA WD

EFP >2 Write WA 30h Write WA D0h

Program/Erase Sus pend 1Write XX B0h

Program/Erase Resum e 1Write XX D0h

Lock

Lock Block 2Write BA 60h Write BA 01h

Unlock Block 2Write BA 60h Write BA D0h

Lock-Down Block 2Write BA 60h Write BA 2Fh

Protec-

tion

Protection Program 2Write PA C0h Write PA PD

Lock Protection Program 2Write LPA C0h Write LPA FFFDh

Config-

uration

Set Configuration Register 2Write CD 60h Write CD 03h

1.8 Volt Intel® Wireless Flash Memory (W18)

14 Preliminary

4.2 Read Array Command

The Read Array command places (or resets) the partition in read array mode. Upon initial device

power-up or after reset (RST# transitions from VIL to VIH), all partitions default to read array mode

and to asynchronous page mode read configuration. A Read Array command written to a partition

that is performing an erase or program operation will present invalid data until the operatio n

completes; it will then display array data when read. If an Erase- or Program-Suspend command

suspends the WSM, a subsequent R ead Array command will place the addressed partition in read

array mode. The Read Array command function s indepen dently of VPP.

4.3 Read Identifier Command

The read identifier mode outputs the manufacturer/device identifier, block lock status, protection

address range supplied by the Read Identifier command (90h) address. Reads from addresses in

Table 7 retrieve ID info rmatio n. Issuing a Read Identifier command to a partition that is

programming or erasing places that partition’s outputs in read ID mode while the partiti on

continues to program or erase in the background.

NOTES:

1. The address is constructed from a base address plus an offset. For example, to read the Block Lock St atus

for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), i.e. 0F8002h.

Then examine bit 0 of the data to determine if the block is locked.

2. See Section 4.12.4, “Block Lock Status” on page 29 fo r valid lock status.

Table 7. Device Identification Codes

Item Address(1)

Data Description

Base Offset

Manufacturer ID Partition 00h 0089h

Device ID Partition 01h

8862h 32-Mbit TPD

8863h 32-Mbit BPD

8864h 64-Mbit TPD

8865h 64-Mbit BPD

8866h 128-Mbit TPD

8867h 128-Mbit BPD

Block Lock Status(2) Block 02h DQ[0] = 0 Block is unlocked

DQ[0] = 1 Block is locked

Block Lock-Down Status(2) Block 02h DQ[1] = 0 Block is not locked-down

DQ[1] = 1 Block is locked down

Configuration Register Partition 05h Register Data

Protection Register Lock Status Partition 80h Lock Data

Protection Register Partition 81h - 88h Register Data Multiple reads required to read

the entire 128-bit Protection

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 15

4.4 Read Query Command

The query plane comes to the foreground and occupies a 4-Mbit add ress r ange at the par titio n

supplied by the Read Query command address. The mode outputs CFI data when partition

addresses are read. Appendix B, “Common Flash Interface” on page 68 shows query mode

information and addresses . Issui ng a Read Query comm a nd to a partition that is programming or

erasing places that partition’s outputs in read query mo de while the partition continue s to program

or erase in the background.

4.5 Read Status Register Command

The device’s status register displays program and erase operation status. A partition’s s t atus can b e

read after writing the Read Status Register command to the partition’s address range. The status

Subsequent single reads from that partition will return its status until another valid command is

written.

The read status mode supports single synchronous and single asynchronous reads only; it doesn’t

support page mode or burst reads. The first OE# or CE# falling edge latches and updates status

data whi l e DQ[ 15:8] outputs 00h. See Table 8, “Status Register Definitions” on page 16.

The status register occupies the 4-Mbit partition to which the Read Status, Program, or Erase

command was issued. Status register bit SR.7 is the DWS (Device WSM Status) bit and provides

program and eras e status of the d evice. The PWS (Partition Write/Erase Status) bit t ells whether the

addressed partition or so m e other par tition is actively programming or erasing. Status register bits

SR.6-1 present information about the WSM’s program, erase, suspend, VPP, and block-lock status.

Table 9, “Stat us Reg ister DW S a nd PWS Descr i pt i on” on page 16 presents descriptions of DWS

(SR.7) and PWS (SR.0) combinations.

1.8 Volt Intel® Wireless Flash Memory (W18)

16 Preliminary

Table 8. Status Register Definitions

DWS ESS ES PS VPPS PSS DPS PWS

76543210

Bit Name State Description

7DWS

Device WSM Status 0 = Device WSM is Busy

1 = Device WSM is Ready

SR.7 indicates erase or program completion in the

device. SR.1–6 are invalid while SR.7 = 0. See Table 9

for valid SR.7 and SR.0 combinations.

6ESS

Erase Suspend Status 0 = Erase in progress/completed

1 = Erase suspended

After issuing an Erase Suspend command, the WSM

halts and sets SR.7 and SR.6. SR.6 remains set until

the device receives an Erase Resume command.

5ES

Erase Status 0 = Erase successful

1 = Erase error

SR.5 is set if an attempt ed erase failed.

A Command Sequence Error is indicated when SR.4,

SR.5 and SR.7 are set.

4PS

Program Status 0 = Program successful

1 = Program error SR.4 is set if the WSM failed to program a word.

3VPPS

VPP Status 0 = VPP OK

1 = VPP low detect, operation aborted

The WSM indicates the VPP level after program or erase

completes. SR.3 does not provide continuous VPP

feedback and isn’t guaranteed when VPP ≠ VPP1/2.

2PSS

Program Suspend

Status

0 = Program in progress/completed

1 = Program suspended

After receiving a Program Suspend command, the

WSM halts execution and sets SR.7 & SR.2. They

remain set until a Resume command is received.

1DPS

Device Protect St atus

0 = Unlocked

1 = Aborted erase/program attempt on

locked block

If an erase or program operation is attempted to a

locked block (if WP# = VIL), the WSM sets SR.1 and

aborts the operation.

0PWS

Partition Write Status

0 = Depending on SR.7’s state, the

addressed partition is busy or no

other partition is busy.

1 = Another partition is busy

Addressed partition or another partition is erasing or

programming. In EFP mo de, SR.0 indicates that a data-

stream word has finished programming or verifying

depending on the p articular EFP phase. See Table 9 for

valid SR.7 and SR.0 combinations.

Table 9. Status Register DWS and PWS Description

DWS

(SR.7) PWS

(SR.0) Description

0 0 The addressed partition is performing a program/erase operation.

EFP: device is finished programming or verifying data or is ready for data.

0 1 A partition other than the one currently addressed is performing a program/erase operation.

EFP: the device is either programming or verifying data.

1 0 No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR.6 and

SR.2) indicate whether other partitions are suspended.

EFP: the device has exited EFP mode.

1 1 Won’t occur in standard program or erase modes.

EFP: this combination will not occur.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 17

4.6 Clear Status Register Command

The Clear Status Register command clears the status register and leaves all partition output states

unchanged. The command functions independently of the applied VPP voltage. The WSM can set

all status register bits and clear bits 0, 2, 6, and 7. Because bits 1, 3, 4 and 5 indicate various error

conditions, they can only be cleared by the Clear Status Register command. By allowing system

software to reset these bits, several operations (such as cumulatively programming several

addresses or erasing multiple blocks in sequence), may be performed before reading the status

another command or sequence. Device reset (RST# = VIL) also clears the status register.

4.7 Word Program Command

Writing a Word Program command to the device initiates internally timed sequences that progr am

the requested word.

Programming can occur in only one parti tio n at a time. Other p art itions must be in one of the read

modes or in erase suspend mode. Note that only one partition at a time can be in erase suspend

mode.

The WSM executes a sequence of internally timed events to program desired bits at the addressed

location and verify that the bits are sufficiently programmed. Programming the memory changes

specifically addressed bits to ‘0.’ ‘1’ bits do not change the memory cell contents.

The status register can be examined for program progress and error s by reading any address within

the partition that’s programming. Issuing a Read Status Register command to other partitions

brings the status register to the foreground in those partition s, allowing program progress to be

monitored or detected at other device addresses. Status register bit SR.7 indicates device program

status while the program seq uence executes. CE# or OE# tog gle (during polling) updates the status

Read Status Register, Program Suspend, Read Identifier, Read Query, and Read Array (which

returns unknown data).

When programming completes, SR.4=1 indicates program failure . If SR.3 is set, the WSM couldn’t

execute the Wo rd Pro gram comman d b ecause V PP was outs ide accep table limits. If SR. 1 is set, the

program operation targeted a locked block and was aborted.

After examining the status register, it should be cleared by the Clear Status Register command

before issuing a new comman d. Th e partitio n remains in status register mode until another

command is written to that partition. Any command can follow once program completes.

1.8 Volt Intel® Wireless Flash Memory (W18)

18 Preliminary

4.8 Block Erase Command

The two-cycle block erase command sequence, consis ting of Erase Setup (20h) and Erase Confirm

(D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode

at a time; other partitions must be in a read mode. The Erase Confirm comm and internally latches

the address of the block to be erased. Erase forces all bits within the block to ‘1’. SR.7 is cleared

while the erase executes.

Figure 2. Word Program Flowchart

Suspend

Program

Loop

Start

Wri te 40h,

Word Address

Write Data

Word Address

Read Status

SR.7 =

Full Program

Status Check

(if desired)

Program

Complete

FULL PROGRAM STATUS CHECK PROCEDURE

Suspend

Program

Read Status

Program

Successful

SR.3 =

SR.1 =

SR.4 =

Yes

Range

Error

Device

Protect Error

Program

Error

WORD PROGRAM PROCEDURE

SR.3 MUST be cleared before the WSM will allow further

program attempts

Only the Clear Staus Register command clears SR.1, 3, 4.

If an error is detected, clear the s tatus register before

attempting a program retry or other error recovery.

Standby

Bus

Operation Command

Check SR.3

1 = V

error

Check SR.4

1 = Data program error

Comments

Repeat for subsequent programming operations.

Full status register check can be done after each program or

after a sequence of program operations.

Comments

Bus

Operation Command

Data = 40h

Addr = Location to program (WA)

Write Program

Setup

Data = Data to program (WD)

Addr = Location to program (WA)

Write Data

Read SRD

Toggle CE# or OE# to update SRD

Read

Check SR.7

1 = WSM ready

0 = WSM busy

Standby

Standby Check SR . 1

1 = Attempted program to locked block

Program aborted

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 19

After writing the Erase Confirm command, the selected partition is placed in read status register

mode and reads performed to that partition will return current status data. The CPU can detect

block erase completion by analyzing SR.7 of that partition. SR.5=1 indicates an erase failure,

SR.3=1 indicates an inv a lid VPP supply voltage, and SR.1=1 indicates an erase operation was

attempted on a locked block.

If an error bit was flagged, the status register can be cleared by issuing the Clear Status Register

command before attemptin g the next operatio n. The partition will remain in read status register

mode until another command is written to its CUI. Any CUI ins tr uction can fol low once erasing

completes. The CUI can be set to read array mode to prevent inadvertent status register reads.

Figure 3. Block Erase Flowchart

SR. 1 and 3 must be cleared before the WSM will allow further

erase attem pts.

Only the Clear Status Register comma nd clears SR.1, 3, 4, 5.

If an error is detected , clear the Status regi ster before

attempting an erase retry or other error recovery.

Start

FULL ER ASE STATUS CHECK PROCED URE

Repeat for subsequent block erasures.

Full status register che ck can be done after each block erase

or after a sequence of block erasures.

Suspend

Erase

0Yes

Suspend

Erase

Loop

Wr ite 20h

Block Address

Write D0h and

Block Address

Read Status

SR.7 =

Full Era s e

Status Check

(if desired)

Block Erase

Complete

Read Status

Block Erase

Successful

SR.1 = Erase of

Lock ed Block

Aborted

BLOCK ERASE PROCEDURE

Bus

Operation Command Comments

Write Block

Erase

Setup

Data = 2 0h

Addr = Block to be erased ( BA)

Write Erase

Confirm Data = D0h

Addr = Block to be erased ( BA)

Read Read SRD

Toggle CE# or OE# to update SRD

Standby Check SR.7

1 = WS M ready

0 = WS M busy

Bus

Operation Command Comments

SR.3 = VPP Range

Error

SR.4,5 = Command

Sequence Error

SR.5 = Block Erase

Error

Standby Check SR.3

1 = VPP error

Standby Check SR.4,5

Both 1 = Command sequence error

Standby Check SR.5

1 = Block erase error

Standby Check SR.1

1 = Attempted erase of locked block

Erase aborted

1.8 Volt Intel® Wireless Flash Memory (W18)

20 Preliminary

4.9 Program Suspend, Program Resume

Erase Suspend, Erase Resume Commands

The Program Suspend and Erase Suspend commands halt an in-progress program or erase

operation. The command can be issued at any device address. The partition corresp ondi ng to the

command’s address remains in its previous state. The Suspend command allows data to be

accessed from memory locations other than the one being programmed or the block being erased.

A program oper ation can be suspend ed to perform read s only. An erase operation can be s uspended

to perform either a program or a read operation within any block, except the block that is erase

suspended. A Program command nested within a suspended erase can subsequently be suspended

to read yet another location. Once a program/erase process starts, the Suspend command requests

that the WSM suspend the program/erase sequence at predetermined points in the algorithm. The

partition that is actually suspended continues to output status register data after the Suspend

command is written. An operat ion is s uspend ed when statu s bits SR.7 and SR.6 and/or SR.2

display ‘1’. tWHRH1/tEHRH1 specifies suspend latency.

To read data from blocks within the partitio n (other than an erase-susp ended block), a Read Array

command can be written. During Erase Suspend, a Program command can be issued to a block

other than the erase-suspended block. Block erase cannot resume until program operations initiated

during erase suspend complete. Read Array, Read Status Register, Read Identifier (ID), Read

Query, and Program Resume are val id comm ands durin g Program or Erase Suspen d. Addi ti onally,

Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and

Lock-Down Block are valid commands during erase suspend.

To read data from a block in a partition that is not programming /erasin g, the oper ation does not

need to be suspended . If the oth er part ition is already in read array, ID, or Query mode, issuing a

valid address will r e turn corresponding data. If the other partition is not in a read mode , one of the

read commands must be issued to the partition before data can be read.

During a suspe nd, CE # = V IH places the dev ice in stan dby st ate, which red uces active curr ent. V PP

must remain at its program level and WP# must remain unchanged while in suspend mode.

A Resume command instructs the WSM to continue programming or erasing and clears status

read at the partition that is progra m ming or erasing, the device outputs data corresponding to the

partition’s last mode. If status register error bits are set, the status register can be cleared before

issuing the next instruction. RST# must r e main at VIH. See Figure 4, “Program Suspend /Resume

Flowchart” on page 21 and Figure 5, “Erase Suspend/Resume Flowchart” on page 22.

If a suspended partition was placed in read array, read status register, read identifier (ID), or read

query mode dur ing the s uspend, the dev ice remains in that mode and output s data co rrespon ding to

that mode after the program or erase operation is resumed. After resuming a suspend operation,

issue the read command appropriate to the read operation. To read status after resuming a

suspended operation, issue a Read Status Register command (70h) to return the suspended partition

to status mode.

A minimum tWHWH time should elapse between an Erase command and a subsequent Erase

Suspend command to ensure that the device achieves sufficient cumulative erase time. Occasional

Erase-to-Suspend interrupts do not cause problems, but Erase-to-Suspend commands issued too

frequently may produce undetermined results.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 21

Figure 4. Program Suspend/Resume Flowchart

Read S tatus

SR.7 =

SR.2 =

Write FFh

Susp Partition

Read Array

Data

Program

Completed

Done

Reading

Wr ite F Fh

Pgm’d Partition

Write D0h

Any Address

Program

Resumed Read Array

Data

Yes

PROGRAM SUSPEND / RESUME PROCEDURE

Write Program

Resume Data = D0h

Addr = an y devic e address

Bus

Operation Command Comments

Write Program

Suspend

Data = B0h

Addr = Any address within programming

partition

Standby Check SR.7

1 = WSM ready

0 = WSM busy

Standby Check SR.2

1 = Pro gram suspended

0 = Program completed

Write Read

Array

Data = FFh

Addr = Any device address (except word

being program med)

Read Read ar ray data from block ot her than

the one being programmed

Read Read SRD

Toggle CE# or OE# to update SRD

Addr = Any address in same partition

Start

Write B0h

Any Address

Wr ite 70h

Same Partition

Write Read

Status Data = 70h

Addr = Any address in same partition

If the suspended partition was placed in Read Array mode:

Write Read

Status

Return partiti on to status mode:

Data = 70h

Addr = address within same partition

Wr ite 70h

Same Partition

1.8 Volt Intel® Wireless Flash Memory (W18)

22 Preliminary

Figure 5. E ra se Su spen d/R esu me Flow c hart

Erase

Completed

Write FFh

Erased Partition

Read Array

Data

Read

Program

Loop

Read Array

Data

Yes

Start

Write B0h

Any Address

Read Status

SR.7 =

SR.6 =

Write D0h

Any Address

Erase Resumed

Read or

Program?

Done?

Write

Standby

Write

Erase

Suspend

Read Array

or Program

Erase

Resume

Data = B0h

Addr = Any address

Data = FFh or 40h

Addr = Any device address (except

block being erased)

Check SR.7

1 = WSM ready

0 = WSM busy

Check SR.6

1 = Erase suspended

0 = Erase completed

Data = D0h

Addr = Any address

Bus

Operation Command Comments

Read Read SRD

Toggle CE# or OE# to update SRD

Addr = Any address in same partition

Read or

Write Read array or program data from/to

block other than the one being erased

ERASE SUSPEND / RESUME PROCEDURE

Write 70h

Same Partit ion

Write Read

Status Data = 70h

Addr = Any address in same partition

Write 70h

Same Partit ion

If the suspended partition was placed in

Read Array mode or a Program Loop:

Write Read

Status

Return partition to status mode:

Data = 70h

Addr = Address within same partition

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 23

4.10 Enhanced Factory Program Command (EFP)

EFP substantially improves device programming performance via a number of enhancements to

the conventional 12-volt word program algorithm. EFP’s more ef ficient WSM algorithm eliminates

the traditi ona l ov erhead del ays of conv ent ional wor d pro gram mo de in both t he ho st pro gram mi ng

system and the flash device. Changes to the conventional word programming flowchart and

internal WSM routine were developed because of today’s beat-rate-sensitive manufacturing

environments; a balance between programming speed and cycling performance was struck.

After a single comman d sequence, host p rogrammer bus cy cles write data words followed by status

checks to determine when th e n ext d ata wo rd is ready to b e accep ted. This mo dification essen tially

cuts write bus cycles in half. Following each internal program pulse, the WSM increments the

device’s address to the next physical location. Now, programming equipment can sequentially

stream program data throughout an entire block without having to setup and present each new

address. In combination, these enhancements reduce much of the host programmer overhead,

enabling more of a data streaming approach to device programming.

Additionally, EFP speeds up programming by performing internal code verificat ion. With this,

PROM program mers can r ely on th e dev ice to verif y t hat it ’s been programmed properly. From the

device side, EFP streamlines internal overhead by eliminating the delays previously associated to

switch voltages between programming and verify levels at each memory-word location.

EFP cons ists of four phas es: s et up, pro gram , ver if y an d exit . Refer to F igure 6, “Enhanced F actory

Program Flowch art ” on page 26 for a detailed graphical representation on how to implement EFP.

4.10.1 EFP Requirements and Considerations

EFP requirements:

•Ambient temperature: TA = 25 °C ±5 °C

•VCC within specified operating range

•VPP within specified VPP2 range

•Target block unlocked

EFP considerations:

•Block cycling below 10 erase cycles (1)

•RWW not s uppor t ed(2)

•EFP programs one block at a time

•EFP cannot be suspende d

1. Recommended for optimum performance. Some degradation in performance may occur if this limit is

exceeded, but the internal algorithm will continue to work properly.

2. Code or data cannot be read from another partition during EFP.

See Figure 6, “Enhanced Factory Program Flowchart” on page 26 for a detailed flowchart on how

to implement an EFP operatio n.

1.8 Volt Intel® Wireless Flash Memory (W18)

24 Preliminary

4.10.2 Setup Ph ase

After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR.7 trans itions

from a ’1’ to a ’0’ indicating that the WSM is busy with EFP algorithm startup. A delay before

checking SR.7 is required to allow the WSM time to perform all of its setups and checks (V PP level

and block lock status). If an erro r is detected, status regist er bits SR.4, SR.3 and/or SR.1 are set and

EFP operation terminates.

NOTE: After the EFP Setup and Confirm command s equence, read s from the device automatically

output status register data. Do not issue the Read S tatus Register command; it will be interpreted as

data to program at WA0.

4.10.3 Program Phase

After setup completion, the host programming system must check SR.0 to determine "data-stream

ready" status (SR.0=0). Each subsequent write after this is a program-data write to the flash array.

Each cell within the memory word to be program m ed to ‘0’ will receive one WSM pulse;

additional pulses , if required, occur in the verify phase. SR.0=1 indicates that the WSM is busy

applying the program pul s e.

The host programmer must poll the device's status register for the "program done" state after each

data-stream write. SR.0=0 indicates that the appropriate cell(s) within the accessed memory

location have received their single WSM program pulse, and that the device is now ready for the

next word. Although the host may check full status for errors at any time, it is only necessary on a

block basis, after EFP exit.

Addresses must remain within the target block. Supplying an address outside the target block

immediately terminates the program phase; the WSM then enters the EFP verify phase.

The address can either hold constant or it can increment. The device compares the incoming

address to that stored from the setup ph ase (WA0); if they match, the WSM programs the new data

word at the next sequential memory location. If they differ, the WSM jumps to the new address

location.

The program phase concludes when the host programming system writes to a different block

address, data su pplied mus t be FFFFh. Upo n prog ram p hase com pletion, the d evice enter s th e EFP

verify phase.

4.10.4 Verify Phase

A high percentage of the flash bits program on the first WSM pulse. However, for those cells that

do not completely program on their first attempt, EFP internal verification identif ies them and

applies add itional pulses as requi red.

The verify phase is identical in flow to that of the program phase, except that instead of

programming incoming data, the WSM compares the verify-stream data to that which was

previously programmed into the block. If the data compares correctly, the host programmer

proceeds to the next word. If not, the host waits while the WSM applies an additional pulse(s).

The host programmer m ust r e set its initial verify-word address to the same starting location

supplied during the program phase. It then reissues each data word in the same order it did during

the program phase. Like pro gramm ing, the h ost may write each subseq uent data wor d to WA0 or it

may increment up through the block addresses.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 25

The verification phase concludes when the interfacing programmer writes to a different block

address; data supplied must be FFFFh. Upon verify phase completion, the device enters the EFP

exit phase.

4.10.5 Exit Phase

SR.7=1 indicates that the device has returned to normal operating conditions. A full status check

should be performed at this time to ensure the entire block programmed successfully. After EFP

exit, any valid CUI command can be issued.

1.8 Volt Intel® Wireless Flash Memory (W18)

26 Preliminary

Figure 6. Enhanced Factory Program Flowchart

EFP Setup EFP Program EFP Verify

EFP Exit

1. WA

= first Word Address to be programmed within the target block. The BBA (Block Base

Address) must remain constant throughout the program phase data stream; WA can be held

constant at the first address location, or it can be written to sequence up through the addresses

within the block. Writing to a BBA not equal to that of the block currently being written to

terminates the EFP program phase, and instructs the device to enter the EFP verify phase.

2. For proper verification to occur, the verify data stream must be presented to the device in the

same sequence as that of the program phase data stream. Writing to a BBA not equal to WA

terminates the EFP verify phase, and instructs the device to exit EFP .

3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive

additional program-pulse attempts during the EFP verify phase. The device will report any

program failure by setting SR.4=1; this check can be performed during the full status check after

EFP has been exited for that block, and will indicate any error within the entire data stream.

Comments

Bus

State

Repeat for subsequent operations.

After EFP exit, a Full Status Check can

determine if any program error occurred.

See the Full Status Check procedure in the

Word Program flowchart.

Write

Standby

Read

Write

(note 2)

Read

Standby

Write

Read

Standby

EFP

Setup

Program

Done?

Exit

Program

Phase

Last

Data?

Exit

Verify

Phase

EFP

Exited?

Write EFP

Confirm

Read

Standby EFP

Setup

Done?

Read

Standby Verify

Stream

Ready?

Write Unlock

Block

Write

(note 1)

Standby Last

Data?

Standby

(note 3) Verify

Done?

SR.0=1=N

Write Data

Address = WA

Last

Data?

Write FFFFh

Address

≠

BBA

Program

Done?

Read

Status Register

SR.0 = 0 = Y

SR.0=1=N

Write Data

Address = WA

Verify

Done?

Last

Data?

Read

Status Register

Write FFFFh

Address

≠

BBA

Verify Stream

Ready?

Read

Status Register

SR.7=0=N

Full Status Check

Procedure

Operation

Complete

Read

Status Register

EFP

Exited?

SR.7 = 1 = Y

SR.0=1=N

Start

Write 30h

Address = WA

= 12V

Unlock Block

Write D0h

Address = WA

EFP Setup

Done?

Read

Status Register

SR.7 = 1 = N

Exit

EFP Program EFP Verify EFP ExitEFP Setup

ENHANCED FACTORY PROGRAMMING PROCEDURE

Comments

Bus

State

Data = 30h

Address = WA

Data = D0h

Address = WA

Status Register

Check SR.7

0 = EFP ready

1 = EFP not ready

= 12V

Unlock block

Check SR.0

0 = Program done

1 = Program not done

Status Register

Data = FFFFh

Address not within same

BBA

Data = Data to program

Address = WA

Device automatically

increments address.

Comments

Bus

State

Data = Word to verify

Address = WA

Status Register

Device automatically

increments address.

Data = FFFFh

Address not within same

BBA

Status Register

Check SR.0

0 = Ready for verify

1 = Not ready for verify

Check SR.0

0 = Verify done

1 = Verify not done

Status Register

Check SR.7

0 = Exit not finished

1 = Exit completed

Check V

& Lock

errors (SR.3, SR.1)

Data Stream

Ready?

Read

Status Register

SR.0 = 0 = Y

SR.7=0=Y

SR.0=1=N

Standby

Read

Data

Stream

Ready?

Check SR.0

0 = Ready for data

1 = Not ready for data

Status Register

SR.0 = 0 = Y

EFP setup time

Standby EFP setup time

Standby Error

Condition

Check

If SR.7 = 1:

Check SR.3, SR.1

SR.3 = 1 = V

error

SR.1 = 1 = locked block

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 27

4.11 Security Modes

The 1.8 Volt Intel® Wireless Flash memory offers both hardware and software security features to

protect the flash data. The softwar e security feature is used by executing the Lock Block command.

The hardware security feature is used by executing the Lock-Down Block command and by

asse rting t he WP # signa l .

Refer to Figure 7, “Block Locking State Diagram” on page 28 for a state diagram of the flash

security features. Also see Figure 8, “Locking Operations Flowchart” on page 30 .

4.12 Block Locking Commands

Individual instant block locking protects code and data by allowing any block to be locked or

unlocked with no latency. This locking scheme offers two levels of protection. The first allows

software-only control of block locking (useful for frequently changed data blocks), while the

second requ ires hardware interaction b efore locking can b e changed (protects infreq uently changed

code blocks).

The following sections discuss the locking system operation. The term “state [XYZ]” specifies

locking states; e.g., “state [001],” where X = WP# value, Y = Block Lock status register bit

DQ1, and Z = Block Lock status register bit DQ0. Fi gure 7, “Blo ck Lockin g S tate Diagram def ines

possible locking states .

The following summarizes the locking functionality.

•All blocks power-up in a locked state. Unlock commands can unlock these blocks.

•The Lock-Down command locks a block and prevents it from being unlocked when

WP# = VIL.

—WP# = VIH overrides lock-down so commands can unlock or lock blocks.

—When WP# returns to VIL, previously locked-down blocks return to lock-down.

—The Lock-Down state is cleared only when the device is reset or powered-down.

Each block’s locking status can be set to locked, unlocked, and lock-down, as described in the

following sections. Figure 7, “Block Locking State Diagram” on page 28 shows the state table for

the locking functions. See also Figure 8, “Locking Operations Flowchart” on page 30.

1.8 Volt Intel® Wireless Flash Memory (W18)

28 Preliminary

NOTES:

1. The notation [X ,Y,Z] denotes the locking state of a block, The current locking st ate of a block is defi ned by the

state of WP# and the two bits of the block-lock status DQ[1:0].

4.12.1 Lock Block

All blocks default to locked (states [001] or [101]) aft er initial p ower-up or reset. Locked blocks

are fully protected from alteration. Attemp ted program or erase operations to a locked block will

return an error in SR.1. Unlocked blocks can be locked by using the Lock Block command

sequence. Similarly, a locked block’s status can be changed to unlocked or lock-down using the

appropriate software commands.

4.12.2 Unlock Block

Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks

return to the locked state when the device is reset or powered-down. An unlocked block’s status

can be changed to the locked or locked-down state using the appropriate software commands. A

locked block can be unlocked by writing the Unlock Block command sequence if the block is not

locked-down.

4.12.3 Lock-Down Block

Locked-down bl ocks (state [0 1 1]) of fer the user an addit ion level of writ e protection beyon d that of

a regular locked block. A block that is locked-down cannot have it’s state changed by software if

WP# is asserted. A locked or unlocked block can be locked-down by writing the Lock-Down Block

Figure 7. Block Locking State Diagram

WP# write protection is enabled in these states while the

lock-down status bit is set. (DQ[1]=1)

Locked

[x01] Unlocked

[x00]

Locked

[111]

Unlocked

[110]

Locked-

Down

[011]

Unloc k cmd

WP#=x

Lock cmd

WP#=x

Unlock cmd

WP#=1

WP#=0

Lock cmd

WP#=1

Lock-down cmd

WP#=x

WP#=0

WP#=1

Lock-down cmd

WP#=x

Device in Reset

or Powered-Down

WP# DQ[1] DQ[0] Block Status

X00Unlocked

X 0 1 Locked

0 1 1 Locked Down

110Unlocked

1 1 1 Locked

(all other combinations are invalid)

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 29

command sequence. If a block was set to locked-down, then later changed to unlocked, asserting

WP# will force that b lock back to the lock ed-d own. When W P# is deas serted, locked-down blo cks

are changed to the locked state and can then be unlocked by Unlock Block command. Locked-

down blocks revert to the locked state at device reset or power-down.

4.12.4 Block Lock Status

Every bl ock’s lock status can be read in read identifier mode. To enter this mode, write 90h to the

device. Subsequent reads at Block Address + 02h will output that block’s lock status. For ex ample,

to read the block lock st atus of block 10, the address sen t to the device sh ould be 5000 2h (for a top-

parameter device). The lowest two data bits, DQ[1] and DQ[0], represent the lock status. DQ[0]

indicates the block lock status. It is set by the Lock Block command and cleared by the Block

Unlock command. It is also set when entering lock-down state. DQ[1] indicates lock-down status

and is set by the Lock-Down command. The lock-down status bit cannot be cleared by software,

only by device reset or power-down. See Table 10.

4.12.5 Locking Operations During Erase Suspend

Block lock configurations can be performed during an erase suspend operation by using the

standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful

when another block requires immediate updating.

To change block locking during an erase operation, first write the Erase Suspend command. After

checking SR.6 to determine the erase operation has suspended, write the desired lock command

sequence to a block; the lock status will be changed. After completing lock, unlock, read, or

program operations, resume the erase operation with the Erase Resume command (D0h).

If a block is locked or locked-down durin g a suspended erase of the same block, the locking status

bits will change immediately. But, when resumed, the erase operation will complete.

Locking operations cannot occur during program suspend. Appendix A, “Write State Machine

States” on page 65 shows valid commands during erase suspend.

4.12.6 Status Register Error Checking

Using nested locking or program command sequences during erase suspend can introduce

ambiguity into statu s regis ter results.

Since locking changes require two-cycle command sequences, e.g., 60h followed by 01h to lock a

block, following the Configuration Setup command (60h) with an invalid command produces a

command sequence error (SR.4=1 and SR.5=1). If a Lock Block command error occurs during

erase suspend, the device sets SR.4 and SR.5 to ‘1’ even after the erase is resumed. When erase is

Table 10. Write Protection Truth Table

VPP WP# RST# Write Protection

X X VIL Device inacces si ble

VIL X VIH Word program and block erase prohibited

X VIL VIH All lock-down blocks locked

X VIH VIH All lock-down blocks can be unlocked

1.8 Volt Intel® Wireless Flash Memory (W18)

30 Preliminary

complete, possible errors during the erase cannot be detected via the status register because of the

previous locking command error. A similar situation occurs if a program operation error is nested

within an erase suspend.

4.12.7 WP# Lock-Down Control

WP# allows block lock-down to be overridden. Table 10, “Write Protection Truth Table” on

page 29 defines the write protecti on met hods.

WP# controls the lock-down function. WP# = VIL protects locked-down blocks [011] from

program, erase, and lock status changes. When WP# = VIH, the block’s lock-down state reverts to

locked [1 1 1]. A so ftware command can then individually unlock a block [110] for erase or program

operations . Thes e bl ock s can then b e re-locked [111 ] whil e WP # rem a ins h i gh. When WP# returns

low, previously locked-down blocks are forced back to the lock-down state [011] regardless of

changes made while WP# was high. Device reset or power-down resets all blocks to the locked

state [101] or [001].

4.13 Protection Register

The 1.8 Volt Intel® Wireless Fla sh Memory i ncludes a 1 28-bit protecti on register. This protection

substitution.

Figure 8. Locking Operations Flowchart

Optional

Start

Write 60h

Block Address

Write 90h

BBA + 02h

Read Block Lock

Status

Locking

Change?

Lock Change

Complete

Write 01, D0, 2Fh

Block Address

Write FFh

Partition Address

Yes

Write

(Optional)

Read

(Optional)

Standby

(Optional)

Write

Lock

Setup

Lock,

Unlock, or

Lockdown

Confirm

Read ID

Plane

Block Lock

Status

Read

Array

Data = 60h

Addr = Block to lock/unlock/lock-down (BA)

Data = 01h (Lock block)

D0h (Unlock block)

2Fh (Lockdown block)

Addr = Block to lock/unlock/lock-down (BA)

Data = 90h

Addr = BBA + 02h

Block Lock status data

Addr = BBA + 02h

Confirm locking change on DQ[1:0].

(See Block Locking State Transitions Table

for valid comb in ations.)

Data = FFh

Addr = Any address in same partition

Bus

Operation Command Comments

LOCKING OPERATIONS P ROCE DURE

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 31

The lower 64 bits within the pro tectio n register are progr ammed by Intel wi th a uniqu e num ber in

each flash device. The upper 64 OTP bits within the protection register are left for the customer to

program. Once pro grammed, the customer segment can be locked to prevent further programm ing.

Note that the individual bits of the user segment of the protection register are OTP, not the register

in total. The user may program each OTP bit individually, one at a time, if desired. Once the

protection regi ster is lock ed, h owever, the entire user segmen t is lock ed and no more u ser bits may

be programmed.

The protection register shares some of the same internal flash resources as the param eter par tition.

Therefore, RWW is only allowed between the protection register and main partitions. Table 11

describes the operat ions allowed in the protection register, parameter partition, and main p arti tion

during RWW and RWE.

4.14 Read Protection Register

W riting the Read Id entifier command allows the pr otection regi ster data to be read 16 bits at a time

from addresses shown in Table 7, “Dev ice Identification Codes” on page 14. The protection

Array command returns the device to read array mode.

4.15 Program Protection Register

The Protection Program comm and should be issued only at the bottom partition followed by the

data to be programed at the specified location. It programs the upper 64 bits of the protection

addresses. See also Figure 9, “Protection Register Programming Flowchart” on page 32. Issuing a

Protection Program command outs ide the regis t er’s address space results in a status register error

(SR.4=1).

Table 11. Simultaneous Operations Allowed with the Protection Register

Protection

Parameter

Partition

Array Data

Main

Partitions Description

Read See

Description Write/Erase

While programming or erasing in a main partition, the protection register may be

read from any other partition. Reading the parameter partition data is not allowed

if the protection register is being read from addresses within the parameter

partition.

See

Description Read Write/Erase While programming or erasing in a main partition, read operations are allowed in

the parameter partition. Accessing the protection registers from parameter

partition addresses is not allowed.

Read Read Write/Erase

While programming or erasing in a main partition, read operations are allowed in

the parameter partition. Accessing the protection registers in a partition that is

different from the one being programed/erased, and also different from the

parameter partition, is allowed.

Write No Access

Allowed Read

While programming the protection register, reads are only allowed in the other

main partitions. Access to the parameter partition is not allowed. This is because

programming of the protection register can only occur in the parameter partition,

so it will exist in status mode.

No Access

Allowed Write/Erase Read While programming or erasing the parameter partition, reads of the protection

registers are not allowed in any partition. Reads in other main partitions are

supported.

1.8 Volt Intel® Wireless Flash Memory (W18)

32 Preliminary

4.15.1 Lock Protection Register

PR-LK.0 is programmed to ‘0’ by Intel to protect the unique device number. PR-LK.1 can be

programmed by the user to lock the user portion (upper 64 bits) of the protection register (see

Figur e 10, “Protection Register Locking). This bit is set using the Protection Program command to

program “FFFDh” into PR-LK.

After PR-LK register bits are programmed (locked), the protection register’s stored values can ’t be

changed. Protection Program commands written to a locked section result in a status register error

(SR.4=1, SR.5=1).

Figure 9. Protection Register Programming Flowchart

FULL STATUS CHECK PROCEDURE

Protec tion Program operat ions addres ses mus t be wi thin the

protection register address space. Addresses outside this

space w i ll re tu rn an er ro r.

Repeat for subsequent programm ing operati ons.

Full status register check can be done after each progr am or

after a sequence of program operations.

SR.3 MUST be cleared before the WSM will allow further

program attempts.

Only the Clear Staus Register command clears S R.1, 3, 4.

If an error is detecte d, clear the status register before

attempting a program retry or other error recov ery.

Yes

1,1

0,1

1,1

PROTECTION R EGISTER PROGRAMMING PROCEDURE

Start

Wr ite C 0h

Addr =Prot addr

Write Protect.

Address / Data

Read S tatus

SR.7 = 1?

Full Status

Check

(if desired )

Program

Complete

Read SRD

Program

Successful

SR.3, SR.4 =

SR.1, SR.4 =

VPP Range Error

Prog r ammin g Er ror

Locked-Register

Program Abor ted

Standby

Bus

Operation Command

SR.1 SR.3 SR.4

011V

PP Error

0 0 1 Protection register

program error

Comments

Write

Standby

Protection

Program

Setup

Protection

Program

Data = C0h

Addr = Protectio n address

Da ta = Data to program

Addr = Protectio n address

Check SR.7

1 = WSM Ready

0 = WSM Busy

Bus

Operation Command Comments

Read Read S RD

Toggle CE# or OE # to update SRD

Standby 1 0 1 Register locked ;

Operation aborted

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 33

Figure 10. Protection Register Locking

Lock Register 0

4 Words (64 bits)

User Programmed

Group 1

4 Words (64 bits)

Intel Factory Programmed

Group 0

84h

88h

85h

81h

80h

PROT_REG.WMF

1.8 Volt Intel® Wireless Flash Memory (W18)

34 Preliminary

4.16 Set Configuratio n Regist er

The Set Configuration Register command sets the burst order, frequency configuration, burst

length, and other parameter s.

A two-bus cycle command sequence initiates this operation. The configuration register data is

placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set

Configuration Register command is written along with the configuration data (on the address bus).

This is followed by a second write that confirms the operation and again pr esents the configur ation

ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the

applied VPP voltage. After executing this command, the device returns to read array mode. The

configuration register ’s contents can be examined by writing the Read Identifier command and

then reading location 05h.

Table 12. Configuration Register Definitions

Read

Mode Res’dFirst Access Latency Count WAIT

Polarity Data

Output

Config WAIT

Config Burst

Seq Clock

Config Res’dRes’dBurst

Wrap Burst Length

RM RLC2 LC1 LC0 WT DOC WC BS CC R R BW BL2 BL1 BL0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit Name Description Notes(1)

15 RM

Read Mode 0 = Synchronous Burs t Reads Enabled

1 = Asynchronous Reads Enabled (Default) 2

14 RReserved

13-11 LC2-0

First Access Latency

Count

000 = Code 0 (Reserved)

001 = Code 1 (Reserved)

010 = Code 2

011 = Code 3

100 = Code 4

101 = Code 5

110 = Code 6 (Reserved)

111 = Code 7 (Reserved) (Default)

10 WT

WAIT Signal Polarity 0 = WAIT signal is active low

1 = WAIT signal is active high (Default) 3

9DOC

Data Output Configuration 0 = Hold Data for One Clock

1 = Hold Data for Two Clock (Default)

8WC

WAIT Configuration 0 = WAIT Asserted During Delay

1 = WAIT Asserted One Data Cycle before Delay (Default)

7BS

Burst Sequence 0 = Intel Burst Order

1 = Linear Burst Order (Default)

6CC

Clock

Configuration

0 = Burst Starts and Data Output on Falling Clock Edge

1 = Burst Starts and Data Output on Rising Clock Edge (Default)

5RReserved

4RReserved

3BW

Burst Wrap 0 = Wrap bursts within burst length set by CR.2–0

1 = Don’t wrap accesses within burst length set by CR.2–0.(Default)

2-0 BL2-0

Burst Length

001 = 4-W ord Burst

010 = 8-W ord Burst

011 = Reserved

111 = Continuous Burst (Default)

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 35

NOTES:

1. Undoc ument ed combinations of bits are reserved by Intel for future implementations.

2. S ynchronous and page read mode configurations affect reads from main blocks and parameter blocks.

Status register and configuration reads support single read cycles. CR.15=1 disables configuration set by

CR.14-1.

3. Data is not ready when WAIT is active.

4. S et the synchronous burst length. In asynchronous page mode, the burst length equals four words.

4.16.1 Rea d Mode (CR.15)

All partitions sup por t two high-performance read configurations: synchronous burst mod e and

asynchronous page mode (default). CR.15 sets the read configuration to one of these modes.

Stat us register , query, and iden tifier modes supp ort only asynchro nous and singl e-synchronous read

operations.

4.16.2 First Access Latency Count (CR.13-11)

The First Access Latency Count (CR.13-11) configuration tells the device how many clocks must

elapse from ADV#-inactive (VIH) before the first data word should be driven onto its d a ta pins.

The input clock frequency determines this value. See Table 12, “Configuration Register

Definitions” on page 34 for latency values. Figure 13, “First Access Latency Configuration” on

page 37 shows data output latency from ADV#-active for different latencies.

Use these equations to calculate First Access Latency Count:

(1) {1/ Frequency} = C LK Peri od

(2) n (CLK Period) ≥ tAVQV (ns) + tADD-DE LAY (ns) + tDATA (ns)

(3) n-2 = First A ccess Latency C ount (LC) *

n: # of C lock pe riods (rounded up t o th e next int eger)

*Must use LC = n - 1 when the starting ad dress is not aligned to a four-wo rd boundary and CR .3=1

(No W rap).

)

Table 13. First Latency Count (LC)

LC Setting Mode Wrap Aligned To 4-word

Boundary Wait Asserted on 16-Word

Boundary Crossing

n-1 4 or 8 disabled no yes, occurs on the every occurrence

n-2 4 or 8 disabled yes no

n-2 4 or 8 enabled no no

n-2 4 or 8 enabled yes no

n-1 continuous XXyes, occurs once

1.8 Volt Intel® Wireless Flash Memory (W18)

36 Preliminary

NOTE:

1. T he 16-word boundary is the end of the device sense word-line.

Parameters defined by CPU:

tADD-DELAY = Clock to CE#, A D V#, or Addr ess Valid whichever occurs last.

tDATA = Data set up to Clock.

Parameters defined by flash:

tAVQV = Address to Out put Delay.

Example:

CPU Clock Speed = 5 2 MHz

tADD-DELAY = 6 ns (typ ical speed fr om C PU) (max)

tDATA = 4 ns (typical speed from CPU) (min)

tAVQV = 70 ns (from AC C haract eristic - Re ad Only Operati ons Table)

From Eq. (1): 1/52 (MHz) = 19.2 ns

From Eq. (2) n(19.2 ns) ≥ 70 ns + 6 ns + 4 ns

n(19.2 ns) ≥ 80 ns

n ≥ 80/19.2 = 4 .17 = 5 (I ntege r)

From Eq. (3) n - 2 = 5 - 2 = 3

First Access Laten cy Cou nt S etting t o th e CR is Code 3.

(Figure 12, “Data Output with LC Setting at Code 3” on page 37 displays

example da ta)

The formula tAVQV (ns) + tADD-DELAY (ns) + tDATA (ns) is also known as initial access time.

Figure 12 shows the data output available and valid after four clocks from ADV# going low in the

first clock period with the LC s etting at 3.

Figure 11. Word Boundary

0123456789ABCDEF

16 Word Boundary

Word 0 - 3 Word 4 - 7 Word 8 - B Word C - F

4 Word Boundary

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 37

4.16.3 WAIT Signal Polarity (CR.10)

The WAIT signal polarity is set by CR.10 (WT).

If the WT bit is cleared (CR.10=0), then WAIT is configured to be active low. This means that a ‘0’

on the WAIT signal indicates that data is not ready and the data bus contains invalid data.

Conversely, if CR.10 is set (CR.10=1), then WAIT is active high. In either case, if WAIT is

deasserted, then data is ready and valid.

Figure 12. Data Output with LC Setting at Code 3

Figure 13. First Access Latency Configuration

Address [A]

DQ[15:0] [Q]

CLK [C]

CE# [E ]

ADV# [V]

R103

Valid

Output Valid

Output

High Z

ADD t

DATA

2nd 1st 3rd 4th 5th

Valid Address

Code 3

Code 1

(Reserved

Code 6 (Reserved)

Code 5

Code 4

Code 3

Code 2

Code 0 (Reserved)

Code 7 (Reserved)

Valid

Address

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output Valid

Output

Valid

Output

Address [A]

ADV# [V]

DQ[15:0] [Q]

CLK [C]

DQ[15:0] [Q]

1.8 Volt Intel® Wireless Flash Memory (W18)

38 Preliminary

WAIT is High-Z until the device is active (CE# = VIL). In synchronous read array mode, when the

device is active (CE# = VIL) and data is valid, CR.10 determines if WAIT goes to VOH or VOL. The

WAIT signal is only “deasserted” once data is valid on the bus. Invalid data drives the WAIT signal

to the asserted state. WAIT is asserted during asynchronous page mode reads.

4.16.4 WAIT Signal Function

The WAIT signal indicates data valid when the device is operating in synchronous burst mode

(CR.15=0), and when addressing a partition that is currently in read array mode. The WAIT signal

is only “deasserted” when data is valid on the bus.

When the device is operating in synchronous non-read array mode, such as read status, read ID, or

read query, WAIT is set to an “asserted” state as determined by CR.10 . Figure 25, “WAIT Signal in

Synchronous Non-Read Array Operat i on Waveform” on page 58 displays WAIT Signal in

Synchronous Non-Read Array Operat i on Waveform.

When the devi ce is op erating in asynchron ous p age mod e o r asyn chro nou s s ingle wo rd read mo de,

WAIT is set to an “asserted” state as determined by CR.10. See Figure 26, “WAIT Sig nal in

Asynchronou s Page-Mode Read Operation W avefor m” on page 59 and Figure 27, “WAIT Signal in

Asynchronous Single-Word Read Operation Waveform” on page 60.

From a system perspective, the WAIT signal will be in the asserted state (based on CR.10) when

the device is operating in synchronous non-read array mode (such as Read ID, Read Query, or

Read Status), or if the device is operating in asynchronous mode (CR.15=1). In these cases, the

system software should ignore (mask) the WAIT signal, as it does not convey any useful

information about the validity of what is appearing on the data bus.

Systems may tie several components’ WAIT signals together.

4.16.5 Dat a Output Configuration (CR.9)

The Data Output Configuratio n bit ( CR . 9) d etermin es whether a data word remains valid on th e

data bus for one or two clock cycles. The processor’s minimum data set-up time and the flash

memory’s clock-to-data output delay determine whether one or two clocks are needed.

If the Data Output Configuration is set at one-clock data hold, this corresponds to a one-clock data

cycle; if the Data Output Con fi gur ation is set at two-clock data hold, this corresponds to a two-

clock data cycle. This configuration bit’s setting depends on the system and CPU characteristics.

Refer to Figure 14, “Data Output Configuration with WAIT Signal Delay” on page 39 for

clarification.

A method for determining what this configuration should be set at is shown below.

To set the device at one clock data hold for subsequent reads, the foll owing condition must be

satisfied:

tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)

As an example, a clock frequency of 52 MHz will be used. The clock period is 19.2 ns. This data is

applied to the formula above for the subsequent reads assuming the data output hold time is one

clock:

14 ns + 4 ns ≤ 19.2 ns

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 39

This equation i s satisfied and data output will be availa ble and valid at every cl ock period. If tDATA

is long, hold for two cycles.

Now assume the clock frequency is 66 MHz. This corresponds to a 15 ns period. The initial access

time is calculated to be 80 ns (Latency Count = Code 4). This conditio n satisf ies tAVQV (ns) +

tADD-DELAY (ns) + tDATA (ns) = 70 ns + 6 ns + 4 n s = 80 ns, as shown ab ove in the Fir st Ac cess

Latency Count equations. However, the data hold time of one clock violates the one-clock data

hold condition:

tCHQV (ns) + tDATA (ns) ≤ One CL K P eri o d

14 ns + 4 ns = 18 ns is not less than one clock period of 15 ns. To satisfy the formula above, the

data output hold time must be set at 2 clock s to correctly allow for data output setup time. This

formula is also satisfied if the CPU has tDATA (ns) ≤ 1 ns, which yields:

14 ns + 1 ns ≤ 15 ns

In page-mode reads, the initial access time can be determined by the formula:

tADD-DELAY (ns) + tDATA (ns) + tAVQV (ns)

and subsequent reads in page mode are defined by:

tAPA (ns) + tDATA (ns) (minimum time)

4.16.6 WAIT Delay Configurati on (CR.8)

The WAIT configuration bit (CR.8) controls WAIT signal delay behavior for all synchronous read

array modes. Its setting depe nds on the system and CPU characte ristics. The WAIT can be asserted

either during or one data cycle before a valid output.

Figure 14. Data Output Configuration with WAIT Signal Delay

DQ[15:0] [Q]

CLK [C]

Valid

Output Valid

Output

DQ[15:0] [Q] Valid

Output

Valid

Output

1 CLK

Data Hold

WAIT (CR.8 = 1)

WAIT (CR.8 = 0) t

CHQV

WAIT (CR.8 = 0)

WAIT (CR.8 = 1)

2 CLK

Data Hold

CHTL/H

Note 1

Note1: WAIT shown active high (CR.10 = 1)

1.8 Volt Intel® Wireless Flash Memory (W18)

40 Preliminary

In synchronous linear read array (no-wrap mode CR.3=1) of 4-, 8-, or continuous-word burst

mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16-

word boundary). If th e burst star t address is four-word boundary aligned, the delay will not occur.

If the start address is misaligned to a four-word boundary, the delay occurs once per burst-mode

read sequence. The WAIT signal informs the system of this delay.

4.16.7 Burst Sequence Configuration (CR.7)

The burst sequence specifies the synchronous burst mode data order (Table 14, “Sequence and

Burst Length” on page 41). Set this bit for linear or Intel burst order. Continuous burst mode

su pports only line ar burst o rder.

When operating in a linear burst mode, either 4-word or 8-word burst length with the burst wrap bit

(CR.3) set, or in continuou s burst mo de, the device may in cur an output delay when the burst

sequence crosses the first 16-word boundary. (See Figure 1 1, “Word Boundary” on page 36 for

word boundary description.) This is dependent on the starting address. If the starting address is

aligned to a four-word boundary, the delay will not occur. If the starting address is the end of a

four-word boundary, the output delay will be one clock cycle less than the First Access Latency

Count; this is the worst-case d e lay. The delay will take place only once and will not happen if the

burst s equence d oes no t cross a 16-w ord bo undary. The WAIT pin informs the sy stem of th is del ay.

See Figure 22, “Single Synchronous Read Operation Waveform” on page 55 through Figure 24,

“WAIT Functionality for EOWL (End of Word Line) Condition Waveform” on page 57 for timing

diagrams of WAI T f unctionality.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 41

4.16.8 Clock Configuration (CR.6)

Clock-edge facilitates easy memory interface to a wide range of burst CPUs. Clock configuration

sets the device to start a burst cycle, output data, and assert WAIT on the clock’s rising or falling

edge.

4.16.9 Burst Wrap (CR.5)

The burst wrap bit determines whether 4-word or 8-word burst accesses wrap within the burst-

length boundary or whether they cross word-length boundaries to perform linear accesses. No-

wrap mode (CR.3=1) enables WAIT to hold off the system processor, as it does in the continuous

burst mode, until v alid data is available. In the no-wra p mode (CR. 3=0), the devi ce operates si milar

to continuous linear burst mode but consumes less power during 4 or 8-word bursts.

For example, if CR.3=0 (wrap mode) and CR.2–0 = 1h (4-word burst), possible linear burst

sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.

Table 14. Sequence and Burst Length

Start Addr.

(Dec) Wrap

CR.3= 0 No Wr ap

CR.3= 1

Burst Addressing Sequence (Dec)

4-Word Burst Length

CR.2–0 = 001 8-Word Burst Length

CR.2–0 = 010 Continuous B urst

CR.2–0 = 111

Linear Intel Linear Intel Linear

0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-...

1 0 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-...

2 0 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-...

3 0 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-...

4 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3- 4-5-6-7-8-9-10...

5 0 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11...

6 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-...

7 0 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13...

...

14 014-15-16-17-18-19-20-...

15 015-16-17-18-19-20-21-...

...

0 1 0-1-2-3 NA 0-1-2-3-4-5-6-7 NA 0-1-2-3-4-5-6-...

1 1 1-2-3-4 NA 1-2-3-4-5-6-7-8 NA 1-2-3-4-5-6-7-...

2 1 2-3-4-5 NA 2-3-4-5-6-7-8-9 NA 2-3-4-5-6-7-8-...

3 1 3-4-5-6 NA 3-4-5-6-7-8-9-10 NA 3-4-5-6-7-8-9-...

4 1 4-5-6-7-8-9-10-11 NA 4-5-6-7-8-9-10...

5 1 5-6-7-8-9-10-11-12 NA 5-6-7-8-9-10-11...

6 1 6-7-8-9-10-11-12-13 NA 6-7-8-9-10-11-12-...

7 1 7-8-9-10-11-12-13-14 NA 7-8-9-10-11-12-13...

...

14 114-15-16-17-18-19-20-...

15 115-16-17-18-19-20-21-...

1.8 Volt Intel® Wireless Flash Memory (W18)

42 Preliminary

If CR.3=1 (no-wrap mode) and CR.2–0 = 1h (4-word burst length), then possible linear burst

sequences are 0-1 -2-3, 1- 2-3-4, 2 -3-4-5, and 3- 4-5-6. CR.3 =1 no t only enab les li mited no n-align ed

sequential bursts, but also reduces power by minimizing the number of internal read operations.

Setting CR.2-0 bits for continuous linear burst mode (7h) also achieves the above 4-word burst

sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for

example, will consume power during the initial access, again during the internal pipeline lookup as

the processor reads word 2, and possibly again, depending on system timing, near the end of the

sequence as the device pipelines the next 4-word sequence. CR.3=1 while in 4-word burst mode

(no wrap mode) reduces this excess power consumption.

4.16.10 Burst Length (CR.2-0)

The burst length is the number of words the device outpu ts in a synchron ous read access. 4-, 8-, and

continuous burst lengths are supported. In 4- or 8-word burst configuration, the burst wrap bit

(CR.3) determines if burst accesses wrap within word-length boundaries or whether they cross

word-length boundaries to perform a linear access. Once an address is given, the device will output

data until it reaches the end of its burstable address space. Continuous burst access are linear only

and do not wrap within word-length boundaries. (see Table 14, “Sequence and Burst Length” on

page 41).

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 43

5.0 Program and Erase Voltages

The 1.8 Volt Intel® Wireless Flash memory provides in-system program and erase at VPP1. For

factory pr ogramming, it also incl udes a low-cost, backw ard-compatible 12 V programming featu re.

The EFP feature can also be used to greatly improve factory program performance.

5.1 Factory Program Mode

The standard factory programming mode uses the same commands and algorithm as the Word

Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through

VCC. Note that if VPP is dr iven by a lo gic signal, VPP1 must remain above the VPP1Min value to

perform i n-syste m flash mo dificati ons. When VPP i s connected t o a 12 V power supply, the devi ce

draws program and erase current directly from VPP. This eliminates the need for an external

switching transistor to control the VPP voltage. Figure 15, “Example VPP Power Supply

Configuration shows examples of flash power supply usage in various configurations.

The 12 V VPP mode enhances programming performance during the short time period typically

found in manufacturing processes; however, it is not intended for extended use. 12 V may be

applied to VPP during program and erase operations as specified in Section 7.2, “Extended

Temperature Operation” on page 47. VPP may be connected to 12 V for a total of tPPH hours

maximum. Stressing the device beyond these limits may cause permanent damage.

5.2 Programming Voltage Protection (VPP)

In addition to the flexible block lockin g, h ol ding the VPP programming voltage low can provide

absolute hardware write protect ion of all flash - device b locks. If VPP is below VPPLK, program or

erase operations will result in an error displayed in SR.3.

NOTE:

1. I f the VCC supply can sink adequate current, an appropriately valued resistor can be used.

Figure 15. Example VPP P ower Supply Configuration

•

12 V fast programming

•

Absolute write protection with V

≤

PPLK

System supply

(Note 1)

12 V supply

•

Low voltage and 12 V fast programming

System supply

12 V supply

•

Low-voltage programming

•

Absolute write protection via logic signal

System supply V

Prot# (logic signal)

•

Low-voltage programming

System supply V

≤

10K

Ω

VPPSUPLY.WMF

(Note 2)

1 2

3 4

1.8 Volt Intel® Wireless Flash Memory (W18)

44 Preliminary

6.0 Power Consumption

1.8 Volt Intel ® Flash memory devices have a layered approach to power savings that can

significantly reduce overall system power consumption. The APS feature reduces power

consumption when the device is selected but idle. If CE# is de-asserted, the memory enters its

standby mo de, where current consumpt ion is even lower. Asserting RST# provi des current s avings

similar to standby mode. The combination of these features can minimize memory power

consumption, and therefore, overall system power consumption.

6.1 Act i ve Po w er

W ith CE# at VIL and RST# at VIH, the device is in the active mode. Refer to the Section 7.4, “DC

Characteristics” on page 48, for ICC value s.

6.2 Automatic Power Savings

APS mode provides low-power operation during read mode. After data is read from the memory

array and the address lines are quiescent, APS circuitry places the device in a mode where typical

current is comparable to ICCS. The flash stays in this static state with outputs valid, OE# low, until

a new location is read.

6.3 Standby Power

W ith CE# at VIH and the dev ice in read mode, t he flash mem ory is in st andby mode , which disa bles

most device circuitry and substantially reduces power consumption. Outputs are placed in a high-

impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or

program operations, the device will continue to perform the operation and consume corresponding

active power until the ope rati on is complete.

6.4 Power-Up/Down Operation

The device is protected against accidental block erasure or programming during power transitions.

It does not matter whether VPP or VCC pow ers-up first. Power supply sequenc i ng is not required.

6.4.1 System Reset and RST#

The use of RST# during system reset is important with automated program/erase devices since the

system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs

without a flash memory reset, proper CPU initialization will n ot occur because the flash memory

may be providing status information instead of array data. Intel recommends connecting RST# to

the system CPU RESET# signal to allow proper CPU/flash initialization at system reset.

System designers must guard against spurious writes when VCC voltages are above VLKO. Since

both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit

writes to the device. The CUI architecture pro vides additional protection since alteratio n of

memory contents can only occur after successful completion of the two-step command sequences.

The device is also disabled until RST# is brought to VIH, regardless of its control input states. By

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 45

holding the device in reset (RST# connected to system PowerGood) during power-up/down,

invalid bus conditions during power-up can be masked, providing yet another level of memory

protection.

6.4.2 VCC, VPP, and RST# Transitions

The CU I latch es comman ds is sued by system software and is not altered by VPP or CE# transitions

or WSM actions. Read array mode is its power-up default state after exit from reset mode or after

VCC transitions above VLKO (Lockout voltage).

After completi ng prog ram or bloc k erase operati ons (even after VPP transi tions below VPPLK), the

Read Array command must reset the CUI to read array mode if flash memory array access is

desired.

6.4.3 Power Supply Decoupling

When the device is accessed, many internal conditions change. Circuits are enabled to charge

pumps and switch voltag es. This int e rnal activ ity produces transient noise. To m ini mi ze the effect

of this transient noise, device decoupling capacitors are required. Transient current magnitudes

depend on the device outputs’ capacitive and inductive loading. Two-line control and proper

decoupling capacitor selection will suppress these transient voltage peaks. Each flash device

should have a 0.1 µF ceramic capacitor connected between each power (VCC, VCCQ, VPP), and

ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as

close as possible to package signals.

1.8 Volt Intel® Wireless Flash Memory (W18)

46 Preliminary

7.0 Electrical Specifications

7.1 Absolute Maximum Ratings

NOTES:

1. A ll specified voltages are with respect to VSS. Minimum DC voltage is –0.5 V on input/output pins and

–0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns

which, during transitions, may overshoot to VCC +2.0 V for periods < 20 ns.

2. M a xim um DC voltage on VPP may overshoot to +14.0 V f or periods < 20 ns.

3. VPP program voltage is normally VPP1. VPP can be 12V ± 0.6 V for 1000 cycles on the main blocks and 2500

cycles on the parameter blocks during program/erase.

4. O utput shor ted for no more than one second. No more than one output shorted at a time.

Warning: Stressing the device beyond the “Absolute Maximu m Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

Parameter Note Maximum Rati ng

Temperature under Bias –40 °C to +85 °C

Storage Temperature –65 °C to +125 °C

Voltage On Any Pin (except VCC, VCCQ, VPP) 1–0.5 V to +2.45 V

VPP Voltage 1,2,3 –0.2 V to +14 V

VCC and VCCQ Voltage 1–0.2 V to +2.45 V

Output Short Circuit Current 4100 mA

Notice: This datasheet contains preliminary information on new products in production. Specifications are

subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet

before finalizing a design.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 47

7.2 Extended Temperature Operation

NOTES:

1. See DC Characteristics tables for voltage-range specific specifications.

2. VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for extended

temperatures and 2500 cycles at extended temperature on parameter blocks.

3. Contact your Intel field representative for enhanced VCC/VCCQ operations down to 1.65 V.

7.3 Capacitance

TA = +25 °C, f = 1 MHz

NOTE: Sampled, not 100% tested.

Symbol Parameter(1) Note Min Nom Max Unit

TAO per ating Temperature –40 25 85 °C

VCC VCC Supply Voltage 31.7 1.80 1.95 V

VCCQ I/O Supply Voltage 31.7 1.80 2.24 V

VPP1 VPP Voltage Supply (Logic Level) 20.90 1.80 1.95 V

VPP2 Factory Programming VPP 211.4 12.0 12.6 V

tPPH Maximum VPP Hours VPP = 12 V 280 Hours

Block

Erase

Cycles

Main and Parameter

blocks VPP ≤ VCC 2100,000 Cycles

Main Blocks VPP = 12 V 21000 Cycles

Parameter Bloc ks VPP = 12 V 22500 Cycles

Sym Parameter(1) 32/64 Mbi t 128 Mb i t Unit Condition

Typ Max Typ Max

CIN Input

Capacitance 6889pF VIN = 0.0 V

COUT Output

Capacitance 812 812 pF VOUT = 0.0 V

CCE CE# Input

Capacitance 10 12 10 12 pF VIN = 0.0 V

1.8 Volt Intel® Wireless Flash Memory (W18)

48 Preliminary

7.4 DC Characteri stics

Sym Parameter (1) Note 32/64 Mbit 128 Mbit Unit Test Co ndition

Typ Max Typ Max

ILI Input Load Current ±1 ±1 µA VCC = VCCMax

VCCQ = VCCQMax

VIN = VCCQ or GND

ILO Output

Leakage

Current DQ[15:0] ±1 ±1 µA VCC = V CCMax

VCCQ = VCCQMax

VIN = VCCQ or GND

ICCS VCC Standby Current 518 525 µA

VCC = VCCMax

VCCQ = VCCQMax

CE# = VCC

RST# =VCC or GND

ICCR Average

VCC Read

Current

Synchronous

CLK = 40 MHz 2, 3

613 613 mA Burst

length = 4

VCC = VCCMax

CE# = VIL

OE# = VIH

Inputs = VIH or VIL

814 814 mA Burst

length = 8

11 20 11 20 mA Burst

length =

Continuous

Synchronous

CLK = 52 MHz 2, 3

716 716 mA Burst

length = 4

10 18 10 18 mA Burst

length = 8

13 25 13 25 mA Burst

length =

Continuous

ICCW VCC Program Current 4, 5 18 40 18 40 mA VPP = VPP1, Program in Progress

815 815 mA VPP = VPP2, Program in Progress

ICCE VCC Block Erase Current 4, 6 18 40 18 40 mA VPP = VPP1, Block Erase in

Progress

815 815 mA VPP = VPP2, Block Erase in

Progress

ICCWS VCC Program Suspend

Current 4, 7 518 525 µA CE# = VCC, Program Suspended

ICCES VCC Erase Suspend Current 4, 7 518 525 µA CE# = VCC, E rase Sus pended

IPPS

(IPPWS,

IPPES)

VPP Standby Current

VPP Progr am Suspend Current

VPP Erase Suspend Current 40.2 50.2 5µA VPP <VCC

IPPR VPP Read Current 215 215 µA VPP ≤ VCC

IPPW VPP Program Current 40.05 0.10 0.05 0.10 mA VPP = VPP1, Program in Progress

822 822 VPP = VPP2, Program in Progress

IPPE VPP Erase Current 40.05 0.10 0.05 0.10 mA VPP = VPP1, Erase in Progress

822 822 VPP = VPP2, Erase in Progress

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 49

DC Characteri st ics, con tinue d

NOTES:

1. All currents are RMS unless noted. Typi cal values at typical VCC, TA = +25 °C.

2. A PS reduces ICCR to approximately standby levels in static operation.

3. CR.3 determines whether 4- or 8-word burst accesses wrap within the burst-length boundary or whether they

cross word-length boundaries to perform linear access es. In the no-wrap mode (CR.3=1), the device

operates similar to continuous linear burst mode but consumes less power.

4. Sampled, not 100% tested.

5. VCC read + program current is the summation of VCC read and VCC program currents.

6. VCC read + erase current is the summation of VCC read and VCC block erase currents.

7. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of

ICCES and ICCR.

8. VIL can undershoot to –0.4 V and VIH can overshoo t to VCCQ+0.4 V for durations of 20 ns or less.

9. E rase and program operations are inhibited when VPP ≤ VPPLK and not guaranteed outside valid VPP1 and

VPP2 ranges.

Sym Parameter Note Min Typ Max Unit Test Condition

VIL Input Low Voltage 8 0 0.4 V

VIH Input High Voltage 8VCCQ

– 0.4 VCCQ V

VOL Output Low V oltage 0.1 VVCC = VCCMin

VCCQ = VCCQMin

IOL = 100 µA

VOH Output High V oltage VCCQ

– 0.1 VVCC = VCCMin

VCCQ = VCCQMin

IOH = –100 µA

VPPLK VPP Lock-Out Voltage 90.4 V

VLKO VCC Lock Voltage 1.0 V

1.8 Volt Intel® Wireless Flash Memory (W18)

50 Preliminary

7.5 AC I/O Test Conditions

NOTE: AC test inputs are driven at VCCQ for a Logic ‘1’ a nd 0.0 V for a Logic ‘0’. Input timing begins, and output

timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are

when VCC = VCCMin.

0672_22

NOTE: See table for component values.

Test configuration component value for worst case speed conditions

NOTE:CL includes jig capacitance.

Figure 16. AC Input/Output Reference Waveform

CCQ

/2 V

CCQ

Test Points

Input Output

Figure 17. Transient Equivalent Testing Load Circuit

Device

Under Test

VCCQ

CLR2

Out

Test Configura t ion CL (pF) R1 (Ω) R2 (Ω)

VCCQMin Standard Test 30 16.7K 16.7K

Figure 18. Clock Input AC Waveform

CLK [C] VIH

VIL

R203R202

R201

1.8 Volt Intel® Wireless Flash Memory (W18)
Preliminary 51
7.6 AC Read Characteristics
#Sym Parameter (1,2) Notes
32/64 Mbit 128 Mbit
Unit–70 –85 -90
Min Max Min Max Min Max
Asynchronous Specifications
R1 tAVAV Read Cycle Time 70 85 90 ns
R2 tAVQV Address to Output Del a y 70 85 90 ns
R3 tELQV CE# Low to Output Delay 70 85 90 ns
R4 tGLQV OE# Low to Output Delay 430 30 30 ns
R5 tPHQV RST# High to Output Delay 150 150 150 ns
R6 tELQX CE# Low to Output in Low-Z 50 0 0 ns
R7 tGLQX OE# Low to Output in Low-Z 4,50 0 0 ns
R8 tEHQZ CE# High to Output in High-Z 520 25 25 ns
R9 tGHQZ OE# High to Output in High-Z 4,520 25 25 ns
R10 tOH CE# (OE#) High to Output in Low-Z 4,50 0 0 ns
Latching Specifica tion s
R101 tAVVH Address Setup to ADV # High 10 10 10 ns
R102 tELVH CE# Low to ADV# High 10 10 10 ns
R103 tVLQV ADV# Low to Output Delay 70 85 90 ns
R104 tVLVH ADV# Pulse W idth Low 10 10 10 ns
R105 tVHVL ADV# Pulse Width High 10 10 10 ns
R106 tVHAX Address Hold from ADV# High 39 9 9 ns
R108 tAPA Page Address Access Time 20 25 30 ns
Clock Specifications
R200 fCLK CLK Frequency 52 40 40 MHz
R201 tCLK CLK Period 19 25 25 ns
R202 tCH/L CLK High or Low Time 5 5 5 ns
R203 tCHCL CLK Fall or Rise Time 3 3 3 ns

1.8 Volt Intel® Wireless Flash Memory (W18)

52 Preliminary

xNOTES:

1. See Figure 16, “AC Input/Output Reference Waveform” on page 50 for timing measurements and maximum

allowable input slew rate.

2. A C specif ications assume the data bus voltage is less than or equal to VCCQ when a read operation is

initiated.

3. A ddress hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is

satisfied fir s t.

4. OE# may be delayed by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV.

5. Sampled, not 100% tested.

6. Applies only to subsequent synchronous reads.

Synchr onous Specifications

R301 tAVCH Address Valid Setup to CLK 9 9 9 ns

R302 tVLCH ADV# Low Setup to CLK 10 10 10 ns

R303 tELCH CE# Low Setup to CLK 9 9 9 ns

R304 tCHQV CLK to Output Valid 14 18 18 ns

R305 tCHQX Output Hold from CLK 3.5 3.5 3.5 ns

R306 tCHAX Address Hold from CLK 310 10 10 ns

R307 tCHTV CLK to WAIT Valid 14 18 18 ns

R308 tELTV CE# Low to W A IT Valid 614 18 18 ns

R309 tEHTZ CE# High to WAIT High-Z 5,620 25 25 ns

R310 tEHEL CE# Pulse Width High 615 20 20 ns

# Sym Parameter (1,2) Notes

32/64 Mbit 128 Mbit

Unit–70 –85 -90

Min Max Min Max Min Max

Figure 19. Asynchronous Read Operation Waveform

Valid

Address

High Z

Valid

Output

R10

Addr ess [ A]

F-CE# [E]

F-OE# [G]

F-WE# [W]

Data [D/Q]

F-RST# [P]

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 53

Figure 20. Latched Asynchronous Read Operation Waveform

High Z Valid

Output

Valid

Address

Data [Q]

WE# [W]

OE# [G ]

CE# [E]

A[MAX:2] [A]

ADV# [V]

RST# [P]

R102

R104

R10

R103

R101

R105 R106

A[1:0] [A]

Valid

Address

Valid

Address

Valid

Address

1.8 Volt Intel® Wireless Flash Memory (W18)

54 Preliminary

Figure 21. Page-Mode Read Operation Wav eform

R105

High Z Valid

Output Valid

Output

Valid

Address

Valid

Address Valid

Address

R102

R104

ADV# [V]

CE# [E]

OE# [G]

WE# [W]

Data [Q]

RST# [P]

A[MAX:2] [A]

A[1:0] [A]

R101

R106

R103

R108

R10R5

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 55

NOTES:

1. Section 4.16.2, “First Access Latenc y Count (CR.13-11)” on page 35 describes how to insert clock cycles

during the initial access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Figure 22. Single Synchronous Read Operation Waveform

Note 1

Valid

Address

High Z Valid

Output

R101

R102

R302

R301 R306

R106R105

R103

R10

R305

High Z

R304

CLK [C ]

RST# [P]

Address [A]

ADV# [V]

OE# [G]

WE# [W]

WAIT [T]

Data [Q]

CE# [E]

R303

R104

High Z

R308

R309

Note 2

1.8 Volt Intel® Wireless Flash Memory (W18)

56 Preliminary

NOTES:

1. Section 4.16.2, “First Ac cess Latency Count (CR.13-11)” on page 35 describes how to insert clock cyc le s

during the initial access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Figure 23. Synchronous Four-Word Burst Read Operation Waveform

Valid

Address

Note 1

Valid

Output Valid

Output

High Z

R105

R102

R301

R302

R306

R101

R106

R103

R304

R305

RST# [P]

WAIT [T]

WE# [W]

OE# [G ]

CE# [E]

ADV# [V]

Address [A]

CLK [C]

Data [Q]

Note 2

R104

R303

R10

R307

High Z

R308 R309

R310

High Z

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 57

NOTES:

1. Section 4.16.2, “First Access Latenc y Count (CR.13-11)” on page 35 describes how to insert clock cycles

during the initial access.

2. WAIT (shown active low) can be configured to assert either during or one data cycle before valid data.

Figure 24. WAIT Functionality for EOWL (End of Word Line) Condition Waveform

Valid

Address

Note 1

Valid

Output Valid

Output

High Z

R105

R102

R301

R302

R306

R101

R106

R103

R304

R305

RST# [P]

WAIT [T]

WE# [W]

OE# [G]

CE# [E]

ADV# [V]

Address [A]

CLK [C]

Data [D/Q]

Note 2

R104

R303

R307

High Z

R308

High Z

1.8 Volt Intel® Wireless Flash Memory (W18)

58 Preliminary

NOTES:

1. Section 4.16.2, “First Ac cess Latency Count (CR.13-11)” on page 35 describes how to insert clock cyc le s

during the initial access.

2. WAIT shown active low.

Figure 25. WAIT Signal in Synchronous Non-Read Array Operation Waveform

Note 1

Valid

Address

High Z Valid

Output

R101

R102

R302

R301 R306

R106R105

R103

R10

R305

High Z

R304

CLK [C]

RST# [P]

Address [A]

ADV# [V]

OE# [G]

WE# [W]

WAIT [T]

Data [Q]

CE# [E]

R303

R104

High Z

R308

R309

Note 2

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 59

NOTES:

1. WAIT shown active low.

Figure 26. WAIT Signal in Asynchronous Page-Mode Read Operation Waveform

R105

High Z Valid

Output Valid

Output

Valid

Address

Valid

Address Valid

Address

R102

R104

ADV# [V]

CE# [E]

OE# [G]

WE# [W]

Data [D/Q]

RST# [P]

A[MAX:2] [A]

A[1:0] [A]

R101

R106

R103

R108

R10R5

High Z

WAIT [T]

High Z

Note 1

1.8 Volt Intel® Wireless Flash Memory (W18)

60 Preliminary

NOTES:

1. WAIT shown active low.

Figure 27. WAIT Signal in Asynchronous Single-Word Read Operation Waveform

Valid

Address

High Z

Valid

Output

R10

Address [A]

CE# [E]

OE# [G]

WE# [W]

Data [D/Q]

RST# [P]

High Z

WAIT [T]

High Z

Not e 1

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 61

7.7 AC Write Characteristics

NOTES:

1. Write timing characteristics during erase suspend are the same as during write-only operations.

2. A write operation can be terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or

WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.

5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE#

low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.

6. tWHQV is tAVQV + 50 ns. System designers should take this into account and may insert a software No-Op

instruction to delay the first read after issuing a command.

7. F or comm and other than resume commands .

8. VPP should be held at VPP1 or VPP2 until block erase or program success is determined.

9. Applicable during asynchronous reads following a write.

10.During synchronous reads, either tWHCV or tWHVH must be met, whichever occurs first.

#Sym Parameter (1,2) Notes

32 Mbit / 64 Mbit 128 Mbit

Unit–70 –85 -90

Min Max Min Max Min Max

W1 tPHWL

(tPHEL)RST# High Recovery to WE# (CE#) Low 3150 150 150 ns

W2 tELWL

(tWLEL)CE# (WE#) Setup to WE# (CE#) Low 0 0 0 ns

W3 tWLWH

(tELEH)WE# (CE#) Write Pulse Width Low 445 60 60 ns

W4 tDVWH

(tDVEH)Data Setup to WE# (CE#) High 45 60 60 ns

W5 tAVWH

(tAVEH)Address Setup to WE# (CE#) High 45 60 60 ns

W6 tWHEH

(tEHWH)CE # (WE#) Hold from WE# (CE#) High 0 0 0 ns

W7 tWHDX

(tEHDX)Data Hold from WE# (CE#) High 0 0 0 ns

W8 tWHAX

(tEHAX)Address Hold from WE# (CE#) High 0 0 0 ns

W9 tWHWL

(tEHEL)WE# (CE#) Pulse Width High 5, 6, 725 25 25 ns

W10 tVPWH

(tVPEH)VPP Setup to WE# (CE#) High 3200 200 200 ns

W11 tQVVL VPP Hold from Valid SRD 3, 80 0 0 ns

W12 tQVBL WP# Hold from Valid SRD 3, 80 0 0 ns

W13 tBHWH

(tBHEH)WP# Setup to WE# (CE#) High 3200 200 200 ns

W14 tWHGL

(tEHGL)Write Recovery before Read 0 0 0 ns

W16 tWHQV WE# High to Valid Data 6tAVQV

+ 40 tAVQV

+ 50 tAVQV

+ 50 ns

W18 tWHAV WE# High to Address Valid 90 0 0 ns

W19 tWHCV WE# High to CLK Valid 10 25 25 25 ns

W20 tWHVH WE# Hi gh to ADV# High 10 25 25 25 ns

1.8 Volt Intel® Wireless Flash Memory (W18)

62 Preliminary

NOTES:

1. VCC power-up and standby.

2. Write Program or Erase Setup command.

3. Write valid address and data (for program) or Erase Confirm command.

4. Automated program/erase delay.

5. Read status register data (SRD) to determine program/erase operation completion.

6. OE# and CE# must be asserted and WE# deasserted for read operations.

Figure 28. Write Operations Waveform

Note 1 Note 2 Note 3 Note 4 Note 5

Address [A]

Valid

Address Valid

Address

CE# (WE#) [E(W)]

Not e 6

OE# [G]

WE# (CE#) [W(E)]

RST# [P]

W11

W12

R105

VPP [V]

PPH

PPLK

WP# [B]

Data [Q]

Data In Valid

SRD

ADV# [V]

W16W1

W10

W13

W14

R101

R106

Data In

Valid

Address

Not e 6

R104

W5 W18

W19

W20

CLK [C]

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 63

7.8 Erase and Program Times

Unless noted otherwise, all above parameters are measured at TA = +25 °C and nominal voltages,

and they are sampled, not 100% tested.

NOTES:

1. E xcludes ext ernal syst em -level overhead.

2. Exact results may vary based on system overhead.

7.9 Reset Specificati ons

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. T he de vice may res et if tPLPH< tPLPHMin, but this is not guaranteed.

3. Not applicable if RST# is tied to VCC.

4. Sampled, but not 100% tested.

5. If RST# is tied to VCC, the device is not ready until tVCCPH after time when VCC ≥ VCCMin.

6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC

until VCC ≥ VCCMin.

Operation Symbol Parameter Description Notes VPP1 VPP2 Unit

Typ Max Typ Max

Erasing and Suspending

Erase Time W500 tERS/PB 4-KW Parameter Block 1,2 0.3 2.5 0.25 2.5 s

W501 tERS/MB 32-KW Main Block 1,2 0.7 40.4 4 s

Suspend

Latency W600 tSUSP/P Program Suspend 1 5 10 510 µs

W601 tSUSP/E Erase Suspend 1 5 20 520 µs

Conventional Word Programming

Program

Time

W200 tPROG/W Single Word 112 150 8130 µs

W201 tPROG/PB 4-KW Paramete r B l ock 1,2 0.05 .23 0.03 0.07 s

W202 tPROG/MB 32-KW Main Block 1,2 0.4 1.8 0.24 0.6 s

Enha nc ed Fa ct or y Pr ogra m m i ng

Program

W400 tEFP/W Single Word 3.5 16 µs

W401 tEFP/PB 4-KW Parameter Block 1,2 15 ms

W402 tEFP/MB 32-KW Main Block 1,2 120 ms

Operation

Latency

W403 tEFP/SETUP EFP Setup 5µs

W404 tEFP/TRAN Program to Verify Transition 2.7 5.6 µs

W405 tEFP/VERIFY Verify 1.7 130 µs

#Symbol Parameter(1) Notes Min Max Unit

P1 tPLPH RST# Low Pulse Width 2, 3, 4 100 ns

P2 tPLRH RST # Low to device reset during Block Erase 3, 4, 5 20 µs

RST# Low to device reset during Program 3, 4, 5 10 µs

P3 tVCCPH V CC Power Va lid to RST# High 1,3,4,5,6 60 µs

1.8 Volt Intel® Wireless Flash Memory (W18)

64 Preliminary

Figure 29. Reset Operations Waveforms

(

A) Reset during

read mode

(B) Reset during

program or block erase

≤

program or block erase

≥

RST# [P]

Abort

Complete

Abort

Complete

VCC

(D) VCC Power-up to

RST# high

P1 R5

P2 R5

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 65

Appendix A Write State Machine States

This table shows the command state transitions based on incoming commands. Only one partition can be

actively p rogrammin g or erasin g at a time. Ea ch pa rtition stays in its la st output sta te (Array, ID/CFI o r S tatus )

until a new command changes it. The next WSM state does not depend on the partition’s output state .

Table A1. Write State Machine - Next State Table

Next State After Command Input

Read

Array(3) Program

Setup

(4,5)

Erase

Setup

(4,5) EFP

Setup(4)

Block Erase

Confirm,

Pgm/Erase

Resume,

ULB Confirm(9)

Program/

Erase

Suspend

Read

Status

Clear

Status

(6)

Read

Identifier/

Query

Current State (FFh) (10h/

40h) (20h) (30h) (D0h) (B0h) (70h) (50h) (90h, 98h)

Ready Ready Program

Setup Erase

Setup EFP

Setup Ready

Lock/CR Setup Ready (Lock Error) Ready Ready (Loc k Er ror )

OTP Setup OTP Busy

Busy OTP Busy

Program

Setup Program Busy

Busy Program Busy Program

Suspend Program Busy

Suspend Program Suspend Program Busy Program Suspend

Erase

Setup Ready (Error) Erase Busy Ready (Error)

Busy Erase Busy Erase

Suspend Er ase Busy

Suspend Erase

Suspend

Program

in Erase

Suspend

Setup Erase Suspend Erase Busy Erase Suspend

Program in Erase

Suspend

Setup Program in Erase Suspend Busy

Busy Program in Erase Suspend Busy Program in

Erase

Suspend Program in Erase Suspend Busy

Suspend Program in Erase Suspend Program in Erase

Suspend Busy Program in Erase Suspend

Lock/CR Setup in Erase Suspend Erase Suspend (Lock Error) Erase Suspend Era se Suspend (Lock Error )

EFP

Setup Ready (Error) EFP Busy Ready (Error)

Busy EFP Busy(7)

Verify Verify Busy(7)

State Output After Command Input

Program Er ase

Erase Setup

OTP Setup

Program in Erase Suspend

EFP Setup, EF P Busy

Verify Busy

Status

Lock/CR Setup

Lock/CR Setup in Erase Suspend Status

OTP Busy Array(3) Status Output doesn’t change Status Output

doesn’t

change Status

Ready

Program Busy

Program Suspend

Erase Busy

Erase Suspend

Program in Erase Suspend

Pgm Susp en d in Eras e Su sp en d

Array Status Output doesn’t change Status Output

doesn’t

change ID/Query

1.8 Volt Intel® Wireless Flash Memory (W18)

66 Preliminary

Table A1. Write State Machine -- Next State Table (continued)

Next State After Command Input

Lock,

Unlock,

Lock-Dwn,

CR Setup(5)

OTP

Setup(5)

Lock

Block

Confirm

(9)

Lock-Dwn

Block

Confirm(9) Write CR

Confirm(9) EFP Ex i t

(BlkAdr≠WAO)

Illegal

Cmds or

EFP Data(2)

WSM

Operation

Completes

Current State (60h) (C0h) (01h) (2Fh) (03h) (XXXXh) (other

codes)

Ready Lock/CR

Setup OTP

Setup Ready N/A

Lock/CR Setup Ready (Lock Error) Ready Ready (Lock Error) N/A

OTP Setup OTP Busy N/A

Busy OTP Busy Ready

Program

Setup Program Busy N/A

Busy Program Busy Ready

Suspend Program Suspend N/A

Erase

Setup Ready (Error) N/A

Busy Erase Busy Ready

Suspend Lock/CR

Setup in

Erase

Suspend Er ase Suspe nd N/A

Program i n

Erase Suspend

Setup Program in Erase Suspend Busy N/A

Busy Program in Erase Suspend Busy Erase

Suspend

Suspend Program in Erase Suspend Busy N/A

Lock/CR Setup in Erase

Suspend

Erase

Suspend

(Lock Error) Erase Suspend Erase Suspend

(Lock Er ro r) N/A

EFP

Setup Ready (Error) N/A

Busy EFP Busy(7) EFP Verify EFP Busy(7) N/A

Verify Verify Busy(7) Ready EFP Verify(7) Ready

State Output Afte r Command Input

Program Erase

Erase Setup

OTP Setup

Program in Erase Suspend

EFP Setup

EFP Busy

Verify Busy

Status Output

doesn’t

change

Lock/CR Setup

Lock/CR Setup in Erase

Suspend Status Array Status Output

doesn’t

change

OTP Busy Status(7) Output doesn’t change Array Status Output

doesn’t

change

Ready

Program Busy

Program Suspend

Erase Busy

Erase Suspend

Program in Erase Suspend

Pgm Suspend in Erase Suspend

Status O utp ut doe sn’t change Array Status Output

doesn’t

change

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 67

NOTES:

1. The output state shows the type of data that appears at the outputs if t he partition address is the same as the

command address. A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the

command issued. Each partition stays in its last output state (Array, ID/CFI or Status) until a new command

changes it. The next WSM state does not depend on the partition’s output state. For example, if partition #1’s

output state is Read Array and partition #4’s output state is Read Status, every read from partition #4 (without

issuing a new command) outputs the status register.

2. I llegal commands are those not defined in the command set.

3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition

results in undermined data when a partition address is read.

4. Both cycles of 2-cycle commands should be issued to the same partition address. If they are issued to

different partitions, the second write determines the active partition. Both partitions will output status

information when read.

5. I f the WSM is active, both cycles of a 2-cycle command are ignored. This differs from previous Intel devices.

6. T he Clear Status command clears status register error bits except when the WSM is running (Pgm Busy,

Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm

Suspend, Pgm Suspend In Erase Suspend).

7. EFP writes are allowed only when status register bit SR.0=0. EFP is busy if Block Address = address at EFP

Confirm command. Any other commands are treated as data.

8. The "current state" is that of the WSM, not the partition.

9. Conf irm com mands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the

operation and then move to the Ready State.

1.8 Volt Intel® Wireless Flash Memory (W18)

68 Preliminary

Appendix B Common Flash Interface

This appendix defines the data structure or “database” returned by the Common Flash Interface

(CFI) Query command. System software should parse this structure to gain critical information

such as block size, density, x8/x16, and electrical specifications. Once this information has been

obtained, the software will know which command sets to use to enable flash writes, block erases,

and otherwise control the flash component. The Query is part of an overall specification for

multiple command set and control interface descriptions called Common Flash Interface, or CFI.

B.1 Query Structure Output

The Query database allows system software to obtain information for controlling the flash device.

This section describ e s the device’s CFI-compliant interface that allows access to Query data.

Query data are presented on the lowest-order data outputs (DQ[7:0]) only. The numerical offset

value is the address r elative to the maximum bus width su pported by the device. On this family of

devices, the Query table device starting address is a 10h, which is a word address for x16 devices.

For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on

the low byte at word addresses 10h and 11h. This CFI-co mpli ant dev i ce outpu ts 00h da ta on upp er

bytes. The device outputs ASCII “Q” in the low byte (DQ[7:0]) and 00h in the high byte

(DQ[15:8]).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word -wi de devi ces is “00h,” the

leading “00” has been dropped from the table notation and only the lower byte value is shown. Any

x16 device outputs can be assumed to have 00h on the upper byte in this mode.

B.2 Query Structure Overview

The Read Query command causes the flash component to display the CFI Query structure or

“database.” The structure subsections and address locations are summarized below.

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 69

NOTES:

1. Ref er to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. B BA = Block Bas e Address beginning location (i.e., 08000h is block 1’s beginning location when the block

size is 32K-word).

3. Offset 15h defines “P” which points to the Primary Intel-specific Extended Query Table.

Table B1. Query Structure

Offset Subsection Description(1)

00h Manufacturer Code

01h Device Code

BBA + 02h(2) Block Status Register Block-specific information

04h to 0Fh Reserved Reserved for vendor-specific information

10h CFI Query identification string Command set ID and vendor data offset

1Bh System interface information Device timing and voltage information

27h Device geometry definition Flash device layout

P(3) Primary Intel-specific Extended Query Table Addit ion vendor-defined information specific

to the Primary Vendor Algorithm

1.8 Volt Intel® Wireless Flash Memory (W18)

70 Preliminary

B.3 CFI Query Identificati on String

The Identification S tring prov ides verification that the component s upports the CFI specification. It

also indicates the specification version and supported vendor-specified command set(s).

Table B2. CFI Identification

Address

Offset Description Data Value

CFI Identification

10h

Query unique ASCII string “QRY”

51h ‘Q’

11h 52h ‘R’

12h 59h ‘Y’

13h Primary vendor command set and control interface ID code. 16-bit ID

code for vendor-specified algorithms 03h

14h 00h

15h Extended Query Table primary algorithm address.

(Denotes the starting offset address for the vendor-specific query table.) 39h

16h 00h

17h Alternate vendor command set and control interface ID code. 0000h

means no second vendor-specified algorithm exists 00h

18h 00h

19h Secondary algorithm Extended Query Table address. 0000h means none

exists. 00h

1Ah 00h

System Interface Information

1Bh Vcc logic supply minimum program/era se voltage

DQ[7:4] = Volt s (BCD)

DQ[3:0] = 100mV (BCD) 17h 1.7 V

1Ch Vcc logic supply maximum program/ erase voltage

DQ[7:4] = Volt s (BCD)

DQ[3:0] = 100mV (BCD) 19h 1.9 V

1Dh Vcc programming supply minimum program/erase voltage

DQ[7:4] = Volt s (BCD)

DQ[3:0] = 100mV (BCD) B4h 11.4 V

1Eh Vcc programming supply minimum program/erase voltage

DQ[7:4] = Volts (HEX)

DQ[3:0] = 100mV (BCD) C6h 12.6 V

1Fh n such that typical single-word program time-out = 2n µs 04h 16 µs

20h n such that typical buffer write time-out = 2n µs 00h

21h n such that typical block erase time-out = 2n ms 0Ah 1 s

22h n such that typical full-chip erase time-out = 2n ms 00h

23h n such that max single-word program time-out = 2n µs 04h 256 µs

24h n such that max buffer write time-out = 2n µs 00h

25h n such that max block erase time-out = 2n ms 03h 8 s

26h n such that max full-chip erase time-out = 2n ms 00h

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 71

Device Geometry Definition

27h Flash density: 2n bytes 16h

17h

18h

32Mbit

64Mbit

128Mbit

28h Data bus width (low byte): 00h=x8, 01h=x16, 02h=x32, 03h=x64 01h x16

29h Data bus width (high byte): not used 00h 0

2Ah Write buffer size: 2n bytes 00h 0

2Bh 00h 0

2Ch

Number of erase block regions (x) within device:

1. x = 0 means no erase blocking; the device erases in bulk

2. x specifies the number of device regions with one or more contiguous

same-size erase blocks.

3. Symmetrically blocked partition

02h 2

2Dh Erase Block Region 1 Information

Bits 0–15 = y, y+1 = number of identical-size erase blocks

Bits 16–31 = z, region erase block(s) size are z x 256 bytes

BPD: 00200007h

TPD: 32Mb = 0100 003Eh, 64Mb = 0100 007Eh, 128Mb = 0100 00FEh

See Description

2Eh

2Fh

30h

31h Erase Block Region 2 Information

Bits 0–15 = y, y+1 = number of identical-size erase blocks

Bits 16–31 = z, region erase block(s) size are z x 256 bytes

BPD: 32Mb = 0100 003Eh, 64Mb = 0100 007Eh, 128Mb = 0100 00FEh

TPD: 0020 0007h

See Description

32h

33h

34h

35h

Reserved for future erase block region information

36h

37h

38h

Primary Vendor-Specific Extended Query

39h(1)

Primary Extended Query Table, Unique ASCII string: “PRI”

50h ‘P’

3Ah 52h ‘R’

3Bh 49h ‘I’

3Ch Major version number, ASCII 31h ‘1’

3Dh Minor version number, ASCII 33h ‘3’

Table B2. CFI Identification (Continued)

Address

Offset Description Data Value

1.8 Volt Intel® Wireless Flash Memory (W18)

72 Preliminary

3Eh Optional feature and command support:

Bit Feature

0 - Full chip erase

1 - Erase suspend

2 - Program Suspend

3 - Legacy lock/unlock

4 - Queued erase

5 - Instant individual block locking

6 - Protection bits

7 - Pagemode read

8 - Synchronous read

9 - Simultaneous operations

bits 10-31 are Reserved.

66h

bit 0=no

bit 1=yes

bit 2=yes

bit 3=no

bit 4=no

bit 5=yes

bit 6=yes

bit 7=no

bit 8=yes

bit 9=yes

3Fh 03h

40h 00h

41h 00h

42h

Supported functions after Program/Erase Suspend (besides Read Array,

Read S tatus, and Read Query):

Bit Feature

0 - Program after Erase Suspend

01h bit 0=yes

43h Block S tatus Register Mask (bits 2-16 are reserved)

Bit Feature

0 - Block Lock status active

1 - Block Lock-down status active

03h bit 0=yes

bit 1=yes

44h 00h

45h Highest VCC Supported:

Bits 0-3 : 100mV (BCD)

Bits 4-7 : Volts (BCD) 18h 1.8 V

46h Highest VPP Supported:

Bits 0-3 : 100mV (BCD)

Bits 4-7 : Volts (HEX) C0h 12.0 V

Protection Register Information

47h Number of protection register fields in JEDEC ID space.

‘00h’ indicates that 256 fields are available 01h 1

48h Protection Field 1: Protection Description

Bits 0-7 : Lower byte of protection register address

Bits 8-15 : Upper byte of protection register address

Bits 16-23 : 2n bytes in factory pre-programmed region

Bits 24-31 : 2n bytes in user-program mable region

80h 0080h

49h 00h

5Ah 03h 8 bytes

5Bh 03h 8 bytes

Burst Read Information

5Ch Page Mode Read Buffer Size

BIts 0-7 : 2n bytes in read page-mode buffer

(00h indicates no page buffer exists for reads) 00h None

5Dh Number of Synchronous Read configurations fields that follow. 00h

indicates no burst capability 03h 3 fields

Table B2. CFI Identification (Continued)

Address

Offset Description Data Value

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 73

5Eh Synchronous Read Field 1

Bits 0-1 : 2n+1 words per synchronous read

Bits 2-7 : Reserved 01h 4-words

5Fh Synchronous Read Field 2

Bits 0-1 : 2n+1 words per synchronous read

Bits 2-7 : Reserved 02h 8-words

60h Synchronous Read Field 3

Bits 0-1 : 2n+1 words per synchronous read

Bits 2-7 : Reserved 07h Continuous

Table B2. CFI Identification (Continued)

Address

Offset Description Data Value

Table B3. Partition and Erase Block Region Information

Feature Description Bottom-Parameter Top-Parameter

Adrs 32 Mbit 62 Mbit 128

Mbit Adrs 32 Mbit 64 Mbit 128

Mbit

Number of device hardware partition regions

n = number of partition regions containing one or more contiguous erase

block regions 51h 02 51h 02

Partition Region 1 Information

Number of identical partitions within partition region 1 52h 01 52h 07 0F 1F

53h 00 53h 00

Number of program or erase operations allowed in partition region 1:

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations 54h 11 54h 11

Number of program or erase operations allowed in other partitions while

a partition in this region is Programming

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations 55h 00 55h 00

Number of program or erase operations allowed in other partitions while

a partition in this region is Erasing

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations 56h 00 56h 00

Types of erase block regions in partition region 1

n = number of erase block regions w/ contiguous same-size erase locks.

Symmetrically blocked partitions have one blocking region. 57h 02 57h 01

Partition Region 1 Erase Block Type 1 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

58h 07 58h 07

59h 00 59h 00

5Ah 20 5Ah 00

5Bh 00 5Bh 01

Partition Region 1 (Erase Block Type 1)

Minimum block erase cycles × 1000 5Ch 64 5Ch 64

5Dh 00 5Dh 00

Partition Region 1 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved 5Eh 01 5Eh 01

1.8 Volt Intel® Wireless Flash Memory (W18)

74 Preliminary

Partition Region 1 (Erase Block Type 1): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchron ous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

5Fh 02 5Fh 02

Partition Region 1 Erase Block Type 2 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

60h 06

61h 00

62h 00

63h 01

Partition Region 1 (Erase Block Type 2)

Minimum block erase cycles × 1000 64h 64

65h 00

Partition Regions 1 (Erase Block Type 2): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved 66h 01

Partition Region 1 (Erase Block Type 2): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchron ous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

67h 02

Partition Region 2 Information

Number of identical partitions within partition region 2 68h 07 0F 1F 60h 01

69h 00 61h 00

Number of program or erase operations allowed in partition region 2:

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations 6Ah 01 62h 11

Number of program or erase operations allowed in other partitions while

a partition in this region is Programming

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations 6Bh 00 63h 00

Number of program or erase operations allowed in other partitions while

a partition in this region is Erasing

Bits 0-3 : Number of simultaneous program operations

Bits 4-7 : Number of simultaneous erase operations 6Ch 00 64h 00

Types of erase block regions in partition region 2

n = number of erase block regions w/ contiguous same-size erase locks.

Symmet rica lly blocked partitions have one blo cking region . 6Dh 01 65h 02

Partition Region 2 Erase Block Type 1 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

6Eh 07 66h 06

6Fh 00 67h 00

70h 00 68h 00

71h 01 69h 00

Partition Region 2 (Erase Block Type 1)

Minimum block erase cycles × 1000 72h 64 6Ah 01

73h 00 6Bh 64

Partition Region 2 (Erase Block Type 1): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved 74h 01 6Ch 01

Table B3. Partitio n and Eras e Block Region Information (Continued)

Feature Description Bottom-Parameter Top-Parameter

Adrs 32 Mbit 62 Mbit 128

Mbit Ad rs 32 Mbit 64 Mbit 128

Mbit

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 75

NOTES:

1. The variable P is a pointer which is defined at CFI offset 15h.

2. For a 16Mb the 1.8 Volt Intel® Wireless Flash memory z1 = 0100h = 256 ⇒ 2562 = 64K, y1 = 17h = 23d ⇒

y1+1 = 24 ⇒

24 * 64K = 1½MB ⇒ Partition 2’s offset is 0018 0000h bytes (000C 0000h words).

3. T PD - Top parameter device; BPD - Bottom parameter device.

4. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains

all the partitions that are made up of main blocks only. B. contains the partition that is made up of the

parameter and the main blocks.

Partition Region 2 (Erase Block Type 1): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchronous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

75h 02 6Dh 02

Partition Region 2 Erase Block Type 2 Information

Bits 0-15 : n+1 = number of identical-sized erase blocks

Bits 16-31 : n×256 = number of bytes in erase block region

6Eh 07

6Fh 00

70h 02

71h 00

Partition Region 2 (Erase Block Type 2)

Minimum block erase cycles × 1000 72h 64

73h 00

Partition Region 2 (Erase Block Type 2): BIts per cell, internal ECC

Bits 0-3 : bits per cell in erase region

Bit 4 : reserved for “internal ECC used”

BIts 5-7 : reserved 74h 01

Partition Region 2 (Erase Block Type 2): Page mode and synchronous

mode capabilities (defined in table 10)

Bit 0 : Page-mode host reads permitted

Bit 1 : Synchronous host reads permitted

Bit 2 : Synchronous host writes permitted

Bits 3-7 : reserved

75h 02

Feature S pace definitions : Reserved 76h 76h

Reserved 77h 77h

Table B3. Partition and Erase Block Region Information (Continued)

Feature Description Bottom-Parameter Top-Parameter

Adrs 32 Mbit 62 Mbit 128

Mbit Adrs 32 Mbit 64 Mbit 128

Mbit

1.8 Volt Intel® Wireless Flash Memory (W18)

76 Preliminary

Appendix C Mechanical Specifications

C.4 The 1.8 Volt Intel® Wireless Flash memory 56 Active Ball

Matrix (7x8) 0.75 mm Bal l Pitch Package Specifications

NOTES:

1. 8 Ball direction of the matrix runs parallel to this dimension

2. 7 Ball direction of the matrix runs parallel to this dimension

3. 4 outrigger support balls on 128-Mbit density only

7 x 8 Ball Matrix

Mecha nical Sp ec ificat ion s

Pkg Type Density D (Widt h)(1)

(± 0.1 mm) E (Length)(2)

(± 0.1 mm) Height

(max)

VF BGA 32 Mbit 7.7 mm 9.0 mm 1.0 mm

µBGA* CSP 64 Mbit 7.7 mm 9.0 mm 1.0 mm

VF BGA 128 Mbit 12.5 mm 12.0 mm 1.0 mm

Note 3

1.8 Volt Intel® Wireless Flash Memory (W18)

Preliminary 77

Appendix D Ordering Informat ion

Component Ordering Information

G T 2 8 6 4 0

1 8 T 7 0

Package Designator

Exten ded Temperatur e

(-25°C to +85°C)

GT = .75mm µBGA*

GE = .75mm VFBGA

56-Bal l 7x8 matr ix

Prod uct line designator

for all Intel

Flash product s

Access S peed (ns)

(70, 85, 90)

Product Family

W18 = 1.8 Volt Intel®

Wireless Flash Memory

= 1.7 V - 1.95 V

CCQ

= 1.7 V - 2.24 V

Device Dens ity

320 = x16 (32-Mbit)

640 = x16 (64-Mbit)

128 = x16 (128-Mbit)

Parameter Parition

T =

Top Parameter

Device

B =

Bottom Parameter

Device