CYW20737
Single-Chip Bluetooth Low Energy-Only
System-On-Chip with Support for Wireless Charging
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-16365 Rev. *C Revised July 5, 2017
The Cypress CYW20737 is an advanced Bluetooth low energy SoC that supports wireless charging profile, includes advanced security
features and introduces new software support for NFC pairing via a tag. The CYW20737 is designed to support the entire spectrum
of Bluetooth Smart use cases for the medical, home automation, accessory, sensor, Internet Of Things, and wearable market
segments.
The CYW20737 radio has been designed to provide low power, low cost, and robust communications for applications operating in the
globally available 2.4 GHz unlicensed Industrial, Scientific, and Medical (ISM) band.
The single-chip Bluetooth low energy SoC is a monolithic component implemented in a standard digital CMOS process and requires
minimal external components to make a fully compliant Bluetooth device. The CYW20737 is available in a 32-pin, 5 mm × 5 mm 32-
QFN package as well as BGA SIP. CYW20737 is supported in WICED SDK 2.x.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Cypress to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Features
■AirFuel wireless charging profile.
■Support for RSA encryption/decryption and key exchange
mechanisms (up to 4 kbit)
■Support for X.509 certificate exchange
■Support for NFC tag-based "tap-to-pair"
■Support for Bluetooth Smart Based Audio via Apple LEA
Spec.
■Bluetooth low energy (BLE)-compliant
■Infrared modulator
■IR learning
■Supports Adaptive Frequency Hopping
■Excellent receiver sensitivity
■10-bit auxiliary ADC with nine analog channels
■On-chip support for serial peripheral interface (master and
slave modes)
■Broadcom Serial Communications interface (compatible with
Philips® I2C slaves)
■Programmable output power control
■Integrated ARM® Cortex™-M3 based microprocessor core
■Automation Profile
■Support for secure OTA
■On-chip power-on reset (POR)
■Support for EEPROM and serial flash interfaces
■Integrated low-dropout regulator (LDO)
■On-chip software controlled power management unit
■Package type:
❐32-pin 32-QFN package (5 mm × 5 mm)
■RoHS compliant
Applications
The following profiles are supported1 in ROM:
■Battery status
■Blood pressure monitor
■Find me
■Heart rate monitor
Broadcom Part Number Cypress Part Number
BCM20737 CYW20737
BCM20737A1KML2G CYW20737A1KML2G
1.Full qualification and use of these profiles may require FW updates from Broadcom. Some of these profiles are under development/approval at the Bluetooth
SIG and conformity with the final approved version is pending. Contact your supplier for updates and the latest list of profiles.
Document Number: 002-16365 Rev. *C Page 2 of 36
CYW20737
■Proximity
■Thermometer
■Weight scale
■Time
Additional profiles that can be supporteda from RAM include:
■Blood glucose monitor
■Temperature alarm
■Location
Figure 1. Functional Block Diagram
Processing
Unit
(ARM -CM3)
System Bus
Bluetooth
Baseband
Core
2.4 GHz
Radio
RF Control
and Data
T/R
Switch
RF I/O
GPIO
Control/
Status
Registers
Frequency
Synthesizer
24 MHz
Ref Xtal
PMU
I/O Ring Bus
I/O Ring
Control
Registers
Peripheral
Interface
Block
1.2V VDD_CORE
Domain
VDD_IO
Domain
WAKE
1.2V
LDO 1.425V to 3.6V
1.62V to 3.6V
1.2V
VDD_CORE
320K
ROM 60K
RAM
BSC/SPI
Master
Interface
(BSC is I
2
C-
compaƟble)
SDA/
MOSI
SCL/
SCK
High Current
Driver Controls
14 GPIOs
32 kHz
LPCLK
9 ADC
Inputs
24
MHz
hclk
(24 MHz to 1 MHz)
AutoCal
MISO
1.2V VDD_RF
Domain PWM
WDT
128 kHz
LPO
÷4
32 kHz
LPCLK
128 kHz
LPCLK
32 kHzyƚĂů;ŽƉƟŽŶĂůͿ
Power
1.62V to 3.6V
VDD_IO
1.2V
POR
1.2V
Test
UART
IR
I/O
IR
Mod.
and
Learning
SPI
M/S
3.6V
MIA POR
28 ADC
Inputs
CT ɇѐ
ADC
VSS,
VDDO,
VDDC
Periph
UART
UART_RXD
UART_TXD Tx
Rx
RTS_N
CTS_N
Muxed on GPIO
Volt. Trans
Document Number: 002-16365 Rev. *C Page 3 of 36
CYW20737
Contents
1. Functional Description ..................................... 4
1.1 Bluetooth Baseband Core ................................... 4
1.1.1 Frequency Hopping Generator ................ 4
1.1.2 E0 Encryption .......................................... 4
1.1.3 Link Control Layer ................................... 4
1.1.4 Adaptive Frequency Hopping .................. 4
1.1.5 Bluetooth Low Energy Profiles ................ 4
1.1.6 Test Mode Support .................................. 5
1.2 Infrared Modulator ............................................... 5
1.3 Infrared Learning ................................................. 6
1.4 Security ............................................................... 6
1.5 Support for NFC Tag Based Pairing ................... 6
1.6 Bluetooth Smart Audio ........................................ 6
1.7 ADC Port ............................................................. 7
1.8 Serial Peripheral Interface ................................... 8
1.9 Microprocessor Unit ............................................ 9
1.9.1 EEPROM Interface .................................. 9
1.9.2 Serial Flash Interface ............................... 9
1.9.3 Internal Reset ........................................ 10
1.9.4 External Reset ....................................... 10
1.10 Integrated Radio Transceiver ............................ 11
1.10.1 Transmitter Path .................................... 11
1.10.2 Receiver Path ........................................ 11
1.10.3 Local Oscillator ...................................... 11
1.10.4 Calibration ............................................. 11
1.10.5 Internal LDO Regulator .......................... 11
1.11 Peripheral Transport Unit .................................. 12
1.11.1 Broadcom Serial Communications
Interface ................................................. 12
1.11.2 UART Interface ...................................... 12
1.12 Clock Frequencies ............................................ 12
1.12.1 Crystal Oscillator ................................... 12
1.13 GPIO Port .......................................................... 14
1.14 PWM ................................................................. 14
1.15 Power Management Unit ....................................16
1.15.1 RF Power Management ..........................16
1.15.2 Host Controller Power Management ......16
1.15.3 BBC Power Management .......................16
2. Pin Assignments............................................. 17
2.1 Pin Descriptions .................................................17
2.2 GPIO Pin Multiplexing ........................................21
2.3 Ball Maps ...........................................................22
3. Specifications ................................................. 23
3.1 Electrical Characteristics ....................................23
3.2 RF Specifications ...............................................26
3.3 Timing and AC Characteristics ...........................27
3.3.1 UART Timing ..........................................27
3.3.2 SPI Timing ..............................................28
3.3.3 BSC Interface Timing .............................29
3.4 ESD Test Models ...............................................30
3.4.1 Human-Body Model (HBM) – ANSI/ESDA
/JEDEC JS-001-2012 .............................30
3.4.2 Machine Model (MM) – JEDEC JESD22-
A115C .....................................................30
3.4.3 Charged-Device Model (CDM) - JEDEC ....
JESD22-C101E 30
3.4.4 Results Summary ...................................30
4. Mechanical Information.................................. 31
4.0.1 Tape Reel and Packaging Specifications 32
5. Ordering Information...................................... 33
6. Additional Information ................................... 33
6.1 Acronyms and Abbreviations .............................33
6.2 IoT Resources ....................................................34
Document History Page................................................. 35
Sales, Solutions, and Legal Information ...................... 36
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CYW20737
1. Functional Description
1.1 Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation.
The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, handles
data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into
baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it
independently handles HCI event types and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and security
before sending over the air:
■Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic
redundancy check (CRC), data decryption, and data dewhitening.
■Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and
data whitening.
1.1.1 Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,
Bluetooth clock, and device address.
1.1.2 E0 Encryption
The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide
minimal processor intervention.
1.1.3 Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit
(LCU). This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or
configured by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state.
STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, and inquiry
scan.
1.1.4 Adaptive Frequency Hopping
The CYW20737 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map
selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency hop
map.
1.1.5 Bluetooth Low Energy Profiles
The CYW20737 supports Bluetooth low energy, including the following profiles that are supported2 in ROM:
■Battery status
■Blood pressure monitor
■Find me
■Heart rate monitor
■Proximity
■Thermometer
■Weight scale
■Time
■AirFuel wireless charging
2. Full qualification and use of these profiles may require FW updates from Broadcom. Some of these profiles are under development/approval at
the Bluetooth SIG and conformity with the final approved version is pending. Contact your supplier for updates and the latest list of profiles.
Document Number: 002-16365 Rev. *C Page 5 of 36
CYW20737
■Automation profile
■Support for secure OTA
The following additional profiles can be supported2 from RAM:
■Blood glucose monitor
■Temperature alarm
■Location
■Custom profile
1.1.6 Test Mode Support
The CYW20737 fully supports Bluetooth Test mode, as described in the Bluetooth low energy specification.
1.2 Infrared Modulator
The CYW20737 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms.
For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from
firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.
If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20737 IR TX firmware driver
inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun (see
Figure 2).
Figure 2. Infrared TX
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CYW20737
1.3 Infrared Learning
The CYW20737 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.
For modulated signals, the CYW20737 can detect carrier frequencies between 10 kHz– 500 kHz and the duration that the signal is
present or absent. The CYW20737 firmware driver supports further analysis and compression of learned signal. The learned signal
can then be played back through the CYW20737 IR TX subsystem (see Figure 3).
Figure 3. Infrared RX
1.4 Security
CYW20737 provides elaborate mechanisms for implementing security and authentication schemes using:
■RSA (Public Key Cryptography)
■X.509 (excluding parsing)
■Hash functions: MD5, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512
■Message authentication code: HMAC MD5, HMAC SHA-1
Note: Details on how to use this functionality via SDK are available in application notes on this topic.
1.5 Support for NFC Tag Based Pairing
CYW20737 provides support for "ease of pairing" and "secure key exchange" use cases using passive tags. Active tags can be used
with the chip for OOB pairing. In a typical use case, the BCM20203 (NFC tag) can be used to provide "tap to pair" functionality for
easy pairing.
Note: Details on how to use this functionality via SDK are available in application notes on this topic.
1.6 Bluetooth Smart Audio
CYW20737 supports using the BLE link for audio streaming. This functionality can be used for audio applications in toys, wearable,
and HID devices, as well as in hearing aids.
Note: Details on how to use this functionality via SDK are available in application notes on this topic.
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CYW20737
1.7 ADC Port
The CYW20737 contains a 16-bit ADC (effective number of bits is 10).
Additionally:
■There are 9 analog input channels in the 32-pin package
■The following GPIOs can be used as ADC inputs:
❐P0
❐P1
❐P8/P33 (select only one)
❐P11
❐P12
❐P13/P28 (select only one)
❐P14/P38 (select only one)
❐P15
❐P32
■The conversion time is 10 s.
■There is a built-in reference with supply- or bandgap-based reference modes.
■The maximum conversion rate is 187 kHz.
■There is a rail-to-rail input swing.
The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes
the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input
multiplexers that select the ADC input signal Vinp and the ADC reference signals Vref.
The ADC input range is selectable by firmware control:
■When an input range of 0–3.6V is used, the input impedance is 3 M.
■When an input range of 0–2.4V is used, the input impedance is 1.84 M.
■When an input range of 0–1.2V is used, the input impedance is 680 k.
ADC modes are defined in Ta b l e 2 .
Table 2. ADC Modes
Mode ENOB (Typical) Maximum Sampling Rate (kHz) Latencya (μs)
a. Settling time after switching channels.
0 13 5.859 171
1 12.6 11.7 85
212 46.875 21
3 11.5 93.75 11
410 187 5
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CYW20737
1.8 Serial Peripheral Interface
The CYW20737 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.
Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the
CYW20737 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Tab l e 3 ,
Tabl e 4 , and Ta b l e 5. The CYW20737 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20737 can also
act as an SPI slave device that supports a 1.8V or 3.3V SPI master.
Table 3. CYW20737 First SPI Set (Master Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISOa
a. SPIFFY1 MISO should always be P32. Boot ROM does not configure any others.
SPI_CSb
b. Any GPIO can be used as SPI_CS when SPI 1 is in master mode, and when the SPI slave is not a serial flash.
Configured Pin Name SCL SDA – –
––––
––P32P33
c
c. P33 is always SPI_CS when a serial flash is used for non-volatile storage.
Table 4. CYW20737 Second SPI Set (Master Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CSa
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Configured Pin Name P3 P0 P1 –
–P4P25–
P24 P27 – –
Table 5. CYW20737 Second SPI Set (Slave Mode)
Pin Name SPI_CLK SPI_MOSI SPI_MISO SPI_CS
Configured Pin Name P3 P0 P1 P2
–P27––
P24 P33 P25 P26
–––P32
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CYW20737
1.9 Microprocessor Unit
The CYW20737 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer components.
The microprocessor is based on an ARM® Cortex™ M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG interface
units. The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code. The
SoC has a total storage of 380 KB, including RAM and ROM.
The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications with
an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is executed
from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
1.9.1 EEPROM Interface
The CYW20737 provides a Broadcom Serial Control (BSC) master interface. BSC is programmed by the CPU to generate four types
of bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and fast mode
devices. BSC is compatible with an NXP® I2C slave device, except that master arbitration (multiple I2C masters contending for the
bus) is not supported.
The EEPROM can contain customer application configuration information including application code, configuration data, patches,
pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.
Native support for the Microchip® 24LC128, Microchip 24AA128, and ST Micro® M24128-BR is included.
1.9.2 Serial Flash Interface
The CYW20737 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Devices natively supported include the following:
■Atmel® AT25BCM512B
■MXIC® MX25V512ZUI-20G
Other (larger) serial flash parts from MXIC, Numonyx, and Adesto with commands identical to these parts here are also supported.
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CYW20737
1.9.3 Internal Reset
Figure 4. Internal Reset Timing
1.9.4 External Reset
The CYW20737 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external
active low reset signal, RESET_N, can be used to put the CYW20737 in the reset state. The RESET_N pin has an internal pull-up
resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the
VDDO supply voltage level has been stabilized.
Figure 5. External Reset Timing
VDDO
VDDOPOR
VDDC
VDDOPORthreshold
VDDOPORdelay
~2ms
VDDCPOR
VDDCPORthreshold
VDDCPORdelay
~2ms
BasebandReset
Crystal
warm‐up
delay:
~5ms
CrystalEnable
StartreadingEEPROMand
firmwareboot
RESET_N
Pulsewidth
>20µs
CrystalEnable
BasebandReset
StartreadingEEPROMand
firmwareboot
Crystal
warm‐up
delay:
~5ms
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CYW20737
1.10 Integrated Radio Transceiver
The CYW20737 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth wireless systems. It has been designed
to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed
ISM band. It is fully compliant with Bluetooth Radio Specification 4.1 and meets or exceeds the requirements to provide the highest
communication link quality of service.
1.10.1 Transmitter Path
The CYW20737 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes
any frequency drift or anomalies in the modulation characteristics of the transmitted signal.
Power Amplifier
The CYW20737 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.
1.10.2 Receiver Path
The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation,
enables the CYW20737 to be used in most applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20737 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller
to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
1.10.3 Local Oscillator
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The
CYW20737 uses an internal loop filter.
1.10.4 Calibration
The CYW20737 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during
normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and
amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and
temperature variations into account, and it takes place transparently during normal operation and hop setting times.
1.10.5 Internal LDO Regulator
The CYW20737 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO regulator
operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.
Note: Always place the decoupling capacitors near the pins as closely together as possible.
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CYW20737
1.11 Peripheral Transport Unit
1.11.1 Broadcom Serial Communications Interface
The CYW20737 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external
EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse
devices. The BSC interface is compatible with I2C slave devices. The BSC does not support multimaster capability or flexible wait-
state insertion by either master or slave devices.
The following transfer clock rates are supported by the BSC:
■100 kHz
■400 kHz
■800 kHz (not a standard I2C-compatible speed.)
■1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
The following transfer types are supported by the BSC:
■Read (Up to 16 bytes can be read.)
■Write (Up to 16 bytes can be written.)
■Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)
■Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20737 are required on
both the SCL and SDA pins for proper operation.
1.11.2 UART Interface
The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 1.5 kbps. The baud rate can
be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth 3.0 UART HCI (H4) specification. The
default baud rate for H4 is 115.2 kbaud.
Both high and low baud rates can be supported by running the UART clock at 24 MHz.
The CYW20737 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.
1.12 Clock Frequencies
The CYW20737 is set with crystal frequency of 24 MHz.
1.12.1 Crystal Oscillator
The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load
capacitors in the range of 5 pF to 30 pF (see Figure 6) are required to work with the crystal oscillator. The selection of the load
capacitors is crystal-dependent. Tabl e 6 shows the recommended crystal specifications.
Figure 6. Recommended Oscillator Configuration—12 pF Load Crystal
Tabl e 6 shows the recommended crystal specifications.
22pF
20pF
Crystal
XIN
XOUT
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CYW20737
Peripheral Block
The peripheral blocks of the CYW20737 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the
request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.
The keyboard scanner is a special case, in that it may drop its clock request line even when enabled, and then reassert the clock
request line if a keypress is detected.
32 kHz Crystal Oscillator
Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Tab le 7 lists the oscillator’s
characteristics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to create a single-
ended digital output. The hysteresis was added to eliminate any chatter when the input is around the threshold of the
comparator and is ~100 mV. This circuit can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with
a clock input at similar frequency. The default component values are: R1 = 10 M, C1 = C2 = ~10 pF. The values of C1
and C2 are used to fine-tune the oscillator.
Figure 7. 32 kHz Oscillator Block Diagram
Table 6. Reference Crystal Electrical Specifications
Parameter Conditions Minimum Typical Maximum Unit
Nominal frequency – – 24.000 – MHz
Oscillation mode – Fundamental –
Frequency tolerance @25°C – ±10 – ppm
Tolerance stability over temp @0°C to +70°C – ±10 – ppm
Equivalent series resistance – – – 50
Load capacitance – – 12 – pF
Operating temperature range – 0 – +70 °C
Storage temperature range – –40 – +125 °C
Drive level – – – 200 W
Aging – – – ±10 ppm/year
Shunt capacitance – ––2pF
C2
C1
R1 32.768kHz
XTAL
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CYW20737
1.13 GPIO Port
The CYW20737 has 14 general-purpose I/Os (GPIOs) in the 32-pin package. All GPIOs support programmable pull-up and pull-down
resistors, and all support a 2 mA drive strength except P26, P27, and P28, which provide a 16 mA drive strength at 3.3V supply.
The following GPIOs are available:
■P0–P4
■P8/P33 (Dual bonded, only one of two is available.)
■P11/P27 (Dual bonded, only one of two is available.)
■P12/P26 (Dual bonded, only one of two is available.)
■P13/P28 (Dual bonded, only one of two is available.)
■P14/P38 (Dual bonded, only one of two is available.)
■P15
■P24
■P25
■P32
For a description of all GPIOs, see Table 9. “GPIO Pin Descriptions”.
1.14 PWM
The CYW20737 has four internal PWM channels. The PWM module is described as follows:
■PWM0–3
■The following GPIOs can be mapped as PWMs:
❐P26
❐P27
❐P14/P28 (Dual bonded, only one of two is available.)
❐P13
■Each of the PWM channels, PWM0–3, contains the following registers:
❐10-bit initial value register (read/write)
❐10-bit toggle register (read/write)
❐10-bit PWM counter value register (read)
■The PWM configuration register is shared among PWM0–3 (read/write). This 12-bit register is used:
❐To configure each PWM channel.
❐To select the clock of each PWM channel.
❐To change the phase of each PWM channel.
Table 7. XTAL Oscillator Characteristics
Parameter Symbol Conditions Minimum Typical Maximum Unit
Output frequency Foscout – – 32.768 – kHz
Frequency
tolerance
– Crystal dependent – 100 – ppm
Start-up time Tstartup – – – 500 ms
XTAL drive level Pdrv For crystal selection 0.5 – – W
XTAL series resis-
tance
Rseries For crystal selection – – 70 k
XTAL shunt capaci-
tance
Cshunt For crystal selection – – 1.3 pF
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Figure 8 shows the structure of one PWM channel.
Figure 8. PWM Channel Block Diagram
pwm_cfg_adrregister pwm#_init_val_adrregister pwm#_togg_val_adrregister
pwm#_cntr_adr
enable
cntrvalueisCM3readable
clk_sel
o_flip
10'H000
10'H3FF
10
10 10
Example:PWMcntrw/pwm#_init_val=0(dashedline)
PWMcntrw/pwm#_init_val=x(solidline)
10'Hx
pwm_out
pwm_togg_val_adr
pwm_out
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1.15 Power Management Unit
The Power Management Unit (PMU) provides power management features that can be invoked by software through power
management registers or packet-handling in the baseband core.
1.15.1 RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-
ceiver, which then processes the power-down functions accordingly.
1.15.2 Host Controller Power Management
Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the
disabling of the on-chip regulator when in deep sleep mode.
1.15.3 BBC Power Management
There are several low-power operations for the BBC:
■Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
■Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYW20737 runs on the Low
Power Oscillator and wakes up after a predefined time period.
The CYW20737 automatically adjusts its power dissipation based on user activity. The following power modes are supported:
■Active mode
■Idle mode
■Sleep mode
■HIDOFF (Deep Sleep) mode
■Timed Deep Sleep mode
The CYW20737 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered
when user activity resumes.
In HIDOFF (Deep Sleep) mode, the CYW20737 baseband and core are powered off by disabling power to LDOOUT. The VDDO
domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power
consumption and is intended for long periods of inactivity.
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2. Pin Assignments
2.1 Pin Descriptions
Table 8. Pin Descriptions
Pin Number Pin Name I/O Power Domain Description
Radio I/O
6 RF I/O VDD_RF RF antenna port
RF Power Supplies
4 VDDIF I VDD_RF IFPLL power supply
5 VDDFE I VDD_RF RF front-end supply
7 VDDVCO I VDD_RF VCO, LOGEN supply
8 VDDPLL I VDD_RF RFPLL and crystal oscillator supply
Power Supplies
11 VDDC I VDDC Baseband core supply
28 VDDO I VDDO I/O pad and core supply
14 VDDM I VDDM I/O pad supply
Clock Generator and Crystal Interface
9 XTALI I VDD_RF Crystal oscillator input. See page 12 for options.
10 XTALO O VDD_RF Crystal oscillator output.
1 XTALI32K I VDDO Low-power oscillator (LPO) input is used.
Alternative Function:
■P11
■P27
32 XTALO32K O VDDO Low-power oscillator (LPO) output.
Alternative Function:
■P12
■P26
Core
18 RESET_N I/O PU VDDO Active-low system reset with open-drain output & internal
pull-up resistor
17 TMC I VDDO Test mode control
High: test mode
Connect to GND if not used.
UART
12 UART_RXD I VDDM UART serial input – Serial data input for the HCI UART
interface. Leave unconnected if not used.
Alternative function:
■GPIO3
13 UART_TXD O, PU VDDM UART serial output – Serial data output for the HCI UART
interface. Leave unconnected if not used.
Alternative Function:
■GPIO2
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BSC
15 SDA I/O, PU VDDM Data signal for an external I2C device.
Alternative function:
■SPI_1: MOSI (master only)
■GPIO0
■CTS
16 SCL I/O, PU VDDM Clock signal for an external I2C device.
Alternative function:
■SPI_1: SPI_CLK (master only)
■GPIO1
■RTS
LDO Regulator Power Supplies
2 LDOIN I N/A Battery input supply for the LDO
3 LDOOUT O N/A LDO output
Table 9. GPIO Pin Descriptionsa
Pin Number Pin Name Default Di-
rection
After POR
State Power Domain Alternate Functions
19 P0 Input Input
floating
VDDO ■GPIO: P0
■PUART_TX (peripheral UART)
■SPI_2: MOSI (master and slave)
■ADC_IN29 (A/D converter input)
■IR_RX/60 Hz_main
■Not available during TMC=1
20 P1 Input Input
floating
VDDO ■GPIO: P1
■IR_TX
■PUART_RTS (peripheral UART)
■SPI_2: MISO (master and slave)
■ADC_IN28 (A/D converter input)
21 P3 Input Input
floating
VDDO ■GPIO: P3
■SPI_2: SPI_CLK (master and slave)
■Quadrature X1
■PUART_CTS (peripheral UART)
22 P2 Input Input
floating
VDDO ■GPIO: P2
■SPI_2: SPI_MOSI (master only)
■Quadrature X0
■PUART_RX (peripheral UART)
■SPI_2: SPI_CS (slave)
Table 8. Pin Descriptions (Cont.)
Pin Number Pin Name I/O Power Domain Description
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CYW20737
23 P4 Input Input
floating
VDDO ■GPIO: P4
■IR_TX
■SPI_2: MOSI (master and slave)
■Quadrature Y0
■PUART_RX (peripheral UART)
24 P8 Input Input
floating
VDDO ■GPIO: P8
■~TX_PD (external T/R switch control)
■ADC_IN27 (A/D converter input)
P33 Input Input
floating
VDDO ■GPIO: P33
■ACLK1 (auxiliary clock output)
■SPI_2: MOSI (slave)
■ADC_IN6 (A/D converter input)
■QDX1 (quadrature X1)
■PUART_RX (peripheral UART)
P9 ■GPIO: P9
■TX_PD
■ADC_IN26
P10 ■GPIO: P10
■PA_RAMP (power amplifier ramp)
■ADC_IN25 (A/D converter input)
1 P11 Input Input
floating
VDDO ■GPIO: P11
■ADC_IN24 (A/D converter input)
■XTALI32K
P27 Input Input
floating
VDDO ■GPIO: P27
■QOC1 (quadrature output control)
■SPI_2: MOSI (master and slave)
■PWM1
■Current: 16 mA
32 P12 Input Input
floating
VDDO ■GPIO: P12
■ADC_IN23 (A/D converter input)
■XTALO32K
P26 Input Input
floating
VDDO ■GPIO: P26
■QOC0 (quadrature output control)
■SPI_2: SPI_CS (slave)
■SPI_1: MISO (master)
■PWM0
■Current: 16 mA
Table 9. GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default Di-
rection
After POR
State Power Domain Alternate Functions
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29 P13 Input Input
floating
VDDO ■GPIO: P13
■PWM3
■ADC_IN22 (A/D converter input)
P28 Input Input
floating
VDDO ■GPIO: P28
■Q0C2 (quadrature output control)
■ADC_IN11 (A/D converter input)
■PWM2
■LED1
■IR_TX
■Current: 16 mA
30 P14 Input Input
floating
VDDO ■GPIO: P14
■PWM2
■ADC_IN21 (A/D converter input)
P38 Input Input
floating
VDDO ■GPIO: P38
■IR_TX
■SPI_2: MOSI (master and slave)
■ADC_IN1 (A/D converter input)
31 P15 Input Input
floating
VDDO ■GPIO: P15
■SWDIO
■IR_RX/60 Hz_main
■ADC_IN20 (A/D converter input)
27 P24 Input Input
floating
VDDO ■GPIO: P24
■PUART_TX (peripheral UART)
■SPI_2: SPI_CLK (master and slave)
■SPI_1: MISO (master)
26 P25 Input Input
floating
VDDO ■GPIO: P25
■SPI_2: MISO (master and slave)
■PUART_RX (peripheral UART)
25 P32 Input Input
floating
VDDO ■GPIO: P32
■ACLK0 (auxiliary clock output)
■PUART_TX (peripheral UART)
■SPI_2: SPI_CS (slave)
■ADC_IN7 (A/D converter input)
■SPI_1: MISO (master)
a. During power-on reset, all inputs are disabled.
Table 9. GPIO Pin Descriptionsa (Cont.)
Pin Number Pin Name Default Di-
rection
After POR
State Power Domain Alternate Functions
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2.3 Ball Maps
Figure 9. 32-pin QFN Ball Map
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32
P11/P27/XIN32
LDO_IN
LDO_OUT
VDDIF
VDDFE
RF
VDDVCO
VDDPLL
XTALI
XTALO
VDDC
UART_RXD
UART_TXD
VDDM
SDA
SCL
TMC
RST_N
P0
P1
P3
P2
P4
P8/P33
P32
P25
P24
VDDO
P13/P28
P14/P38
P15
P12/P26/XO32
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3. Specifications
3.1 Electrical Characteristics
Tabl e 11 shows the maximum electrical rating for voltages referenced to VDD pin.
Tabl e 1 2 shows the power supply characteristics for the range TJ = 0 to 125°C.
Tabl e 1 3 shows the digital level characteristics for (VSS = 0V).
Table 14 shows the specifications for the ADC characteristics.
Table 11. Maximum Electrical Rating
Rating Symbol Value Unit
DC supply voltage for RF domain – 1.4 V
DC supply voltage for core domain – 1.4 V
DC supply voltage for VDDM domain (UART/I2C) – 3.8 V
DC supply voltage for VDDO domain – 3.8 V
DC supply voltage for VR3V – 3.8 V
DC supply voltage for VDDFE – 1.4 V
Voltage on input or output pin – VSS – 0.3 to VDD + 0.3 V
Operating ambient temperature range Topr –30 to +85 °C
Storage temperature range Tstg –40 to +125 °C
Table 12. Power Supply
Parameter Minimuma
a. Overall performance degrades beyond minimum and maximum supply voltages.
Typical MaximumaUnit
DC supply voltage for RF 1.14 1.2 1.26 V
DC supply voltage for Core 1.14 1.2 1.26 V
DC supply voltage for VDDM (UART/I2C) 1.62 – 3.63 V
DC supply voltage for VDDO 1.62 – 3.63 V
DC supply voltage for LDOIN 1.425 – 3.63 V
DC supply voltage for VDDFE 1.14 1.2b
b. 1.2V for Class 2 output with internal VREG.
1.26 V
Table 13. LDO Regulator Electrical Specifications
Parameter Conditions Min Typ Max Unit
Input voltage range – 1.425 – 3.63 V
Default output voltage – – 1.2 – V
Output voltage Range 0.8 – 1.4 V
Step size – 40 or 80 – mV
Accuracy at any step –5 – +5 %
Load current – – – 30 mA
Line regulation Vin from 1.425 to 3.63V, Iload = 30 mA –0.2 – 0.2 %VO/V
Load regulation Iload from 1 µA to 30 mA, Vin = 3.3V, Bonding R = 0.3–0.10.2%V
O/mA
Quiescent current No load @Vin = 3.3V
*Current limit enabled
–6–µA
Power-down current Vin = 3.3V, worst@70°C – 5 200 nA
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Table 15 shows the specifications for the digital voltage levels.
Table 14. ADC Specifications
Parameter Symbol Conditions Min Typ Max Unit
Number of Input channels – – – 9 – –
Channel switching rate fch – – – 133.33 kch/s
Input signal range Vinp –0–3.63V
Reference settling time – Changing refsel 7.5 – – s
Input resistance Rinp Effective, single ended – 500 – k
Input capacitance Cinp –––5pF
Conversion rate fC– 5.859 – 187 kHz
Conversion time TC– 5.35 – 170.7 s
Resolution R – – 16 – bits
Effective number of bits – In specified performance range – See
Tabl e 2
–
Absolute voltage
measurement error
– Using on-chip ADC firmware driver – ±2 – %
Current I Iavdd1p2 + Iavdd3p3 –– 1 mA
Power P – – 1.5 – mW
Leakage current Ileakage T = 25°C – – 100 nA
Power-up time Tpowerup –––200µs
Integral nonlinearity3INL In guaranteed performance range –1 – 1 LSBa
a. LSBs are expressed at the 10-bit level.
Differential nonlinearityaDNL In guaranteed performance range –1 – 1 LSBa
Table 15. Digital Levelsa
a. This table is also applicable to VDDMEM domain.
Characteristics Symbol Min Typ Max Unit
Input low voltage VIL ––0.4V
Input high voltage VIH 0.75 × VDDO––V
Input low voltage (VDDO = 1.62V) VIL ––0.4V
Input high voltage (VDDO = 1.62V) VIH 1.2 ––V
Output low voltageb
b. At the specified drive current for the pad.
VOL ––0.4V
Output high voltagebVOH VDDO – 0.4 – – V
Input capacitance (VDDMEM domain) CIN –0.12–pF
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Table 16 shows the specifications for current consumption.
Table 16. Current Consumption a
a. Currents measured between power terminals (Vdd) using 90% efficient DC-DC converter at 3V.
Operational Mode Conditions Typ Max Unit
Receive Receiver and baseband are both operating, 100% ON. 9.8 10.0 mA
Transmit Transmitter and baseband are both operating, 100% ON. 9.1 9.3 mA
Sleep Internal LPO is in use. 12.0 13.0 A
– 0.65 –
Table 17. Power Supply Current Consumption
Power Supply Advertisement Rates Typ Max Unit
VDDC 20 ms 1.96 mA
100 ms
500 ms
1 s
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3.2 RF Specifications
Table 18. Receiver RF Specifications
Parameter Mode and Conditions Min Typ Max Unit
Receiver Sectiona
a. 30.8% PER.
Frequency range – 2402 – 2480 MHz
RX sensitivity (standard) 0.1%BER, 1 Mbps – –94 – dBm
RX sensitivity (low current) – –91.5 – dBm
Input IP3 – –16 – – dBm
Maximum input – –10 – – dBm
Interference Performancea,b
b. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
C/I cochannel 0.1%BER – – 21 dB
C/I 1 MHz adjacent channel 0.1%BER – – 15 dB
C/I 2 MHz adjacent channel 0.1%BER – – –17 dB
C/I 3 MHz adjacent channel 0.1%BER – – –27 dB
C/I image channel 0.1%BER – – –9.0 dB
C/I 1 MHz adjacent to image channel 0.1%BER – – –15 dB
Out-of-Band Blocking Performance (CW)a,b
30 MHz to 2000 MHz 0.1%BERc
c. Measurement resolution is 10 MHz.
– –30.0 – dBm
2003 MHz to 2399 MHz 0.1%BERd
d. Measurement resolution is 3 MHz.
– –35 – dBm
2484 MHz to 2997 MHz 0.1%BERd– –35 – dBm
3000 MHz to 12.75 GHz 0.1%BERe
e. Measurement resolution is 25 MHz.
– –30.0 – dBm
Spurious Emissions
30 MHz to 1 GHz – – – –57.0 dBm
1 GHz to 12.75 GHz – – – –55.0 dBm
Table 19. Transmitter RF Specifications
Parameter Minimum Typical Maximum Unit
Transmitter Section
Frequency range 2402 – 2480 MHz
Output power adjustment range –20 – 4 dBm
Default output power – 4.0 – dBm
Output power variation – 2.0 – dB
Adjacent Channel Power
|M – N| = 2 – – –20 dBm
|M – N| 3– – –30dBm
Out-of-Band Spurious Emission
30 MHz to 1 GHz – – –36.0 dBm
1 GHz to 12.75 GHz – – –30.0 dBm
1.8 GHz to 1.9 GHz – – –47.0 dBm
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3.3 Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
3.3.1 UART Timing
Figure 10. UART Timing
5.15 GHz to 5.3 GHz – – –47.0 dBm
LO Performance
Initial carrier frequency tolerance – – ±150 kHz
Frequency Drift
Frequency drift – – ±50 kHz
Drift rate – – 20 kHz/50 µs
Frequency Deviation
Average deviation in payload
(sequence used is 00001111)
225 – 275 kHz
Maximum deviation in payload
(sequence used is 10101010)
185 – – kHz
Channel spacing – 2 – MHz
Table 20. UART Timing Specifications
Reference Characteristics Min Max Unit
1 Delay time, UART_CTS_N low to UART_TXD valid – 24 Baud out cycles
2 Setup time, UART_CTS_N high before midpoint of stop bit – 10 ns
3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baud out cycles
Table 19. Transmitter RF Specifications (Cont.)
Parameter Minimum Typical Maximum Unit
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3.3.2 SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO 2.2V. The supported clock speed is 6 MHz when 2.2V > VDDIO
1.62V.
Figure 11 and Figure 12 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively.
Figure 11. SPI Timing – Mode 0 and 2
Figure 12. SPI Timing – Mode 1 and 3
Table 21. SPI Interface Timing Specifications
Reference Characteristics Min Typ Max
1 Time from CSN asserted to first clock edge 1 SCK 100
2 Master setup time – ½ SCK –
3 Master hold time ½ SCK – –
4 Slave setup time – ½ SCK –
5 Slave hold time ½ SCK – –
6 Time from last clock edge to CSN deasserted 1 SCK 10 SCK 100
3
SPI_CSN
SPI_CLK
(Mode0)
SPI_MOSI ‐FirstBit
SPI_MISO NotDriven FirstBit
SecondBit
SecondBit
Lastbit
Lastbit
1
2
6
SPI_CLK
(Mode2)
NotDriven
‐
54
3
SPI_CSN
SPI_CLK
(Mode1)
SPI_MOSI ‐Invalidbit
SPI_MISO NotDriven Invalidbit
Firstbit
Firstbit
Lastbit
Lastbit
1
2
6
‐
NotDriven
SPI_CLK
(Mode3)
54
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3.3.3 BSC Interface Timing
Figure 13. BSC Interface Timing Diagram
Table 22. BSC Interface Timing Specifications
Reference Characteristics Min Max Unit
1 Clock frequency – 100 kHz
400
800
1000
2 START condition setup time 650 – ns
3 START condition hold time 280 – ns
4 Clock low time 650 – ns
5 Clock high time 280 – ns
6 Data input hold timea
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions.
0 – ns
7 Data input setup time 100 – ns
8 STOP condition setup time 280 – ns
9 Output valid from clock – 400 ns
10 Bus free timeb
b. Time that the cbus must be free before a new transaction can start.
650 – ns
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CYW20737
3.4 ESD Test Models
ESD can have serious detrimental effects on all semiconductor ICs and the system that contains them. Standards are developed to
enhance the quality and reliability of ICs by ensuring all devices employed have undergone proper ESD design and testing, thereby
minimizing the detrimental effects of ESD. Three major test methods are widely used in the industry today to describe uniform methods
for assessing ESD immunity at Component level, Human Body Model (HBM), Machine Model (MM), and Charged Device Model
(CDM). The following standards were used to test this device:
3.4.1 Human-Body Model (HBM) – ANSI/ESDA/JEDEC JS-001-2012
The HBM has been developed to simulate the action of a human body discharging an accumulated static charge through a device to
ground, and employs a series RC network consisting of a 100 pF capacitor and a 1500 (Ohm) resistor. Both positive and negative
polarities are used for this test. Although, a 100 ms delay is allowable per specification, the minimum delay used for testing was set
to 300 ms between each pulse.
3.4.2 Machine Model (MM) – JEDEC JESD22-A115C
The MM has been developed to simulate the rapid discharge from a charged conductive object, such as a metallic tool or fixture. The
most common application would be rapid discharge from charged board assembly or the charged cables of automated testers. This
model consists of a 200 pF capacitor discharged directly into a component with no series resistor (0). One positive and one negative
polarity pulses are applied. The minimum delay between pulses is 500 ms.
3.4.3 Charged-Device Model (CDM) - JEDEC JESD22-C101E
CDM simulates charging/discharging events that occur in production equipment and processes. The potential for a CDM ESD events
occurs when there is metal-to-metal contact in manufacturing. CDM addresses the possibility that a charge may reside on the lead
frame or package (e.g., from shipping) and discharge through a pin that subsequently is grounded, causing damage to sensitive
devices in the path. Discharge current is limited only by the parasitic impedance and capacitance of the device. CDM testing consists
of charging package to a specified voltage, then discharging the voltage through relevant package leads. One positive and one
negative polarity pulse is applied. The minimum delay between pulses is 200 ms.
3.4.4 Results Summary
ESD Test Voltage Level Results:
■HBM +/– 2KV PASS
■CDM +/– 500V PASS
■MM +/– 150V PASS
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4. Mechanical Information
Figure 14. 32-pin QFN
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CYW20737
4.0.1 Tape Reel and Packaging Specifications
The top left corner of the CYW20737 package is situated near the sprocket holes, as shown in Figure 15.
Figure 15. Pin 1 Orientation
Table 23. CYW20737 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications
Parameter Value
Quantity per reel 2500 pieces
Reel diameter 13 inches
Hub diameter 7 inches
Tape width 12 mm
Tape pitch 8 mm
Pin 1: Top left corner of package toward sprocket holes
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CYW20737
5. Ordering Information
6. Additional Information
6.1 Acronyms and Abbreviations
The following list of acronyms and abbreviations may appear in this document.
Table 24. Ordering Information
Part Number Package Ambient Operating Temperature
CYW20737A1KML2G 32-pin QFN –30°C to +85°C
Term Description
ADC analog-to-digital converter
AFH adaptive frequency hopping
AHB advanced high-performance bus
APB advanced peripheral bus
APU audio processing unit
ARM7TDMI-S® Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable
BSC Broadcom Serial Control
BTC Bluetooth controller
COEX coexistence
DFU device firmware update
DMA direct memory access
EBI external bus interface
HCI Host Control Interface
HV high voltage
IDC initial digital calibration
IF intermediate frequency
IRQ interrupt request
JTAG Joint Test Action Group
LCU link control unit
LDO low drop-out
LHL lean high land
LPO low power oscillator
LV LogicVision™
MIA multiple interface agent
PCM pulse code modulation
PLL phase locked loop
PMU power management unit
POR power-on reset
PWM pulse width modulation
QD quadrature decoder
RAM random access memory
RF radio frequency
ROM read-only memory
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CYW20737
In most cases, acronyms and abbreviations are defined on first use.
For a comprehensive list of acronyms and other terms used in Cypress documents, go to: http://www.cypress.com/glossary
6.2 IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technica
l documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire
technical documentation and software from the Cypress Support Community website (https://community.cypress.com/)
RX/TX receive, transmit
SPI serial peripheral interface
SW software
UART universal asynchronous receiver/transmitter
UPI µ-processor interface
WD watchdog
Term Description
Document Number: 002-16365 Rev. *C Page 35 of 36
CYW20737
Document History Page
Document Title: CYW20737 Single-Chip Bluetooth Low Energy-Only System-On-Chip with Support for Wireless Charging
Document Number: 002-16365
Revision ECN Orig. of
Change
Submission
Date Description of Change
** - -
05/30/2014 20737-DS100-R
Initial release
02/10/2016 20737-DS101-R
Added:
“ESD Test Models”
08/17/2016 20737-DS102-R
Updated:
•“Ordering Information” on page 45
*A 5525954 UTSV 11/22/2016 Added Cypress Part Numbering Scheme and Mapping Table on Page 1.
Updated to Cypress template.
*B 5738817 NIBK 05/15/2017 Updated Cypress Logo and Copyright.
*C 5792463 SGUP 07/05/2017 Updated the Title.
Replaced Alliance with Wireless Power to Airfuel - “Features” on page 1.
Removed (aka Bluetooth Smart) from Page 1.
Replaced 4.0 with 4.1 in “Integrated Radio Transceiver” on page 11.
Removed Wireless Charging Section from the datasheet.
Document Number: 002-16365 Rev. *C Revised July 5, 2017 Page 36 of 36
CYW20737
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
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