S1R72V27 Data Sheet Rev.1.00 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. (c)SEIKO EPSON CORPORATION 2007, All rights reserved. Scope This document applies to the S1R72V27 USB 2.0 device/host controller LSI. Contents 1. Overview............................................................................................................................................ 1 2. Features............................................................................................................................................. 2 3. Block Diagram................................................................................................................................... 3 4. Explanation of Functions ................................................................................................................. 4 4.1 Power Supply ............................................................................................................................. 4 4.2 Reset .......................................................................................................................................... 5 4.2.1 Hard Reset ........................................................................................................................ 5 4.2.2 Soft Reset.......................................................................................................................... 5 4.3 Clock .......................................................................................................................................... 5 4.4 Power Management ................................................................................................................... 6 4.5 CPU-I/F....................................................................................................................................... 7 4.6 USB Device I/F ........................................................................................................................... 7 4.6.1 Speed Mode and Transfer Type ........................................................................................ 7 4.6.2 Resources ......................................................................................................................... 7 4.6.2.1 Endpoint ......................................................................................................................... 7 4.6.2.2 FIFO ............................................................................................................................... 8 4.6.3 Data Flow .......................................................................................................................... 8 4.6.4 USB Device Port External Circuits .................................................................................... 9 4.7 USB Host I/F............................................................................................................................. 10 4.7.1 Speed Mode and Transfer Type ...................................................................................... 10 4.7.2 Resources ....................................................................................................................... 10 4.7.2.1 Channels ...................................................................................................................... 10 4.7.2.2 FIFO ............................................................................................................................. 10 4.7.3 Data Flow ........................................................................................................................ 10 4.7.4 USB Host Port External Circuits ...................................................................................... 12 4.8 FIFO ......................................................................................................................................... 12 5. Terminal Layout Diagrams ............................................................................................................. 13 6. Terminal Functions ......................................................................................................................... 15 7. Electrical Characteristics ............................................................................................................... 18 7.1 Absolute Maximum Ratings ...................................................................................................... 18 S1R72V27 Data Sheet (Rev. 1.00) EPSON i 7.2 Recommended Operating Conditions....................................................................................... 18 7.3 DC Characteristics.................................................................................................................... 19 7.3.1 Current Consumption ...................................................................................................... 19 7.3.2 Input Characteristics........................................................................................................ 21 7.3.3 Output Characteristics ..................................................................................................... 22 7.3.4 Terminal Capacitance ...................................................................................................... 23 7.4 AC Characteristics.................................................................................................................... 24 7.4.1 Reset Timing ................................................................................................................... 24 7.4.2 Clock Timing.................................................................................................................... 24 7.4.3 CPU/DMA I/F Access Timing ........................................................................................... 26 7.4.3.1 Specifications for CVDD = 1.65 V to 3.6 V ................................................................... 26 7.4.3.2 Specifications when limited to CVDD = 3.0 V to 3.6 V 7.4.4 (relaxed specifications).......... 27 USB I/F Timing ................................................................................................................ 28 8. Connection Examples .................................................................................................................... 29 8.1 CPU I/F Connection Example................................................................................................... 29 8.2 USB I/F Connection Example ................................................................................................... 30 9. Product Codes ................................................................................................................................ 31 10. External Dimension Diagrams ..................................................................................................... 32 ii EPSON S1R72V27 Data Sheet (Rev. 1.00) 1. Overview 1. Overview The S1R72V27 is a USB host/device controller LSI that supports the USB 2.0 high-speed mode. A single USB port can be operated as a USB host or USB device depending on how control is switched. This LSI maintains high compatibility with the S1R72V17 but includes additional functions such as support for USB host isochronous transfers. S1R72V27 Data Sheet (Rev. 1.00) EPSON 1 2. Features 2. Features <<USB 2.0 host functions>> * Supports HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) transfer * Built-in pull-down resistor for downstream ports (no external circuit required) * Built-in HS termination (no external circuit required) * Supports control, bulk, interrupt, and isochronous transfers Proven channel system designed specifically for embedded host Dedicated control transfer channel x1 Dedicated bulk transfer channel x1 Bulk, interrupt, and isochronous transfer channels x4 * USB power switching interface <<USB 2.0 device functions>> * Supports HS (480 Mbps) and FS (12 Mbps) transfer * Built-in FS/HS termination (no external circuit required) * VBUS 5V I/F (requires external protective circuit) * Supports control, bulk, interrupt, and isochronous transfers * Supports five bulk, interrupt, and isochronous transfers and Endpoint 0 <<MCU I/F>> * Supports 16-bit width standard CPU bus I/F * Includes DMA 1ch for each port (multi-word sequence) * Big Endian (Includes bus-swapping function to support Little Endian CPUs) * I/F variable voltage (3.3 V to 1.8 V) <<Miscellaneous>> * Clock input: Supports 12 MHz/24 MHz crystal oscillator. (built-in oscillator circuit and 1 M feedback resistor) * Dedicated terminals for 12/24/48 MHz clock input * Power supply voltage: 3-voltage system including 3.3 V, 1.8 V, and CPU I/F power supply (3.3 V to 1.8 V) * Package type QFP14-80, PFBGA5UX60, PFBGA8UX81 * Guaranteed operating temperature range: -40C to 85C 2 EPSON S1R72V27 Data Sheet (Rev. 1.00) 3. Block Diagram 3. Block Diagram XRESET CLKIN XINT XCS CA[8:1] XRD XBEL XWRH XWRL XDREQ XDACK CD[15:0] CPU I/F Controller DMA Controller VBUSEN VBUSFLG Host SIE DP DM MTM R1 PLL Device SIE VBUS Channel/Endpoint OSC XI XO USB FIFO Controller USB FIFO Test MUX TSTEN BURNIN S1R72V27 Data Sheet (Rev. 1.00) ATPGEN Figure 3-1 Overall block diagram EPSON 3 4. Explanation of Functions 4. Explanation of Functions For details of the register names used in the following discussion, refer to the Technical Manual for this LSI. 4.1 Power Supply This LSI has three power supply systems and a common GND. The power supply systems consist of HVDD (3.3 V) for the USB I/O power supply, CVDD (3.3 V to 1.8 V) for the CPU I/F power supply, and LVDD (1.8 V) for internal circuits and TEST I/O. (See Figure 4-1.) CVDD 1.8V to 3.3V CPU I O CPU -I/F LVDD HVDD 1.8V 3.3V SIE MTM USB FIFO TEST IO Figure 4-1 S1R72V27 power supply circuit diagram The sequence of steps for turning the power supplies on and off are described below. This LSI cannot be operated with only the LVDD or CVDD power supplies turned on or off. The HVDD can be turned off if the LVDD or CVDD power supplies are on. The synchronous register cannot be accessed while HVDD is off, since the PLL does not operate. Also, the following restrictions apply to the sequence for turning the CVDD/HVDD I/O power supplies and LVDD internal power supply on or off. There are no restrictions on the sequence for turning the CVDD and HVDD power supplies on or off. * The LVDD must be turned on before turning on the CVDD and HVDD power supplies. * In the powering off sequence, the CVDD and HVDD must be turned off before turning off the LVDD. If power supply circuit characteristics or the power supply load make this sequence impossible to follow, the CVDD or HVDD must not be on for more than 1 second while the LVDD is off. 4 EPSON S1R72V27 Data Sheet (Rev. 1.00) 4. Explanation of Functions 4.2 Reset This LSI includes a hard reset function using the external XRESET terminal and a soft reset function using register settings. 4.2.1 Hard Reset Start up from reset status when power is turned on, then cancel the reset after confirming power on. 4.2.2 Soft Reset Circuits related to the USB port or individual internal USB analog macros can be reset via software. This LSI can be soft reset using the ChipReset.AllReset bit. The ChipReset.ResetMTM bit is used to reset USB analog macros. Note, however, that analog macros should only be reset in the sleep state. 4.3 Clock This LSI contains an internal oscillator and feedback resistor (1 M) and supports clock generation using an external oscillator. External clock input is supported via the CLKIN terminal. The oscillator frequency supports 12 MHz or 24 MHz using the internal oscillator. Frequencies of 12, 24, or 48 MHz are supported via the external input. Figure 4-2 shows a typical connection arrangement for an oscillation circuit. Contact the oscillator manufacturer to determine circuit constants, as Cd, Cg, and Rd in the oscillator circuit must be matched, based on the oscillator. Cd Cg Rd XO Figure 4-2 XI Clock generation using the internal oscillator and external oscillator S1R72V27 Data Sheet (Rev. 1.00) EPSON 5 4. Explanation of Functions 4.4 Power Management This LSI includes a power management function featuring two power management states, SLEEP and ACTIVE, together with the CPU_Cut power management state. (See Figure 4-3.) All function blocks are active in the ACTIVE state, whereas only the bare minimum circuits necessary for restarting from standby mode are active in SLEEP state. CPU_Cut mode minimizes power consumption attributable to the CPU-I/F input buffer. CPU -I/F ACTIVE SIE UTM SIE UTM SIE UTM FIFO OSC CPU -I/F* SLEEP FIFO OSC CPU -I/F** CPU_Cut FIFO OSC Active Inactive * The CPU-I/F is only partially active in SLEEP state. The asynchronous access register can be accessed. ** CPU-I/F operation is suspended in CPU_Cut to minimize power consumption attributable to the I/O input buffer. Figure 4-3 6 Power management states EPSON S1R72V27 Data Sheet (Rev. 1.00) 4. Explanation of Functions 4.5 CPU-I/F This LSI is connected to the CPU via a 16-bit interface. Endian settings can be set as Big Endian or Little Endian in 16-bit steps. For Big Endian, registers with even addresses can be accessed above the bus (CD[15:8]), while registers with odd addresses can be accessed below the bus (CD[7:0]). For Little Endian, registers with even addresses can be accessed below the bus (CD[7:0]), while registers with odd addresses can be accessed above the bus (CD[15:8]). The bus mode can be set to either Strobe mode for access using high/low strobe (XWRH/XWRL) or Byte Enable mode for access using high/low byte enable (XBEH/XBEL) for writing the first or last 8 bits. Endian and bus mode is set by the CPUIF_MODE register immediately cancelling of hard reset. The CPU-I/F on this LSI includes 1-ch DMA (slave). The registers that can be accessed will depend on the power management state. For details, refer to the LSI Technical Manual. 4.6 USB Device I/F This LSI supports High-Speed specification USB device functions complying with the USB 2.0 (Universal Serial Bus Specification Revision 2.0) standards. 4.6.1 Speed Mode and Transfer Type This LSI's USB device function supports HS (480 Mbps) and FS (12 Mbps) speed modes. The speed mode is set automatically by the speed negotiation performed when resetting the bus. For example, HS transfer mode is selected automatically by speed negotiation if connected to a USB host that supports HS speed mode. In addition, the register can be set so that FS speed mode is always selected in speed negotiations. All transfer types stipulated under the USB 2.0 standard are supported, including control transfers (endpoint 0), bulk transfers, interrupt transfers, and isochronous transfers. 4.6.2 Resources 4.6.2.1 Endpoint This LSI's USB device function includes endpoint 0 and five standard endpoints. Endpoint 0 supports control transfers. The standard endpoints support bulk transfers, interrupt transfers, and isochronous transfers. The standard endpoint numbers, maximum packet size, and transfer direction (in/out) can be set as desired. S1R72V27 Data Sheet (Rev. 1.00) EPSON 7 4. Explanation of Functions 4.6.2.2 FIFO The LSI ports include 4.5 kB of FIFO for use with USB data transfers. This forms the data transfer route with USB. The FIFO capacity of each endpoint can be assigned as desired by the software. For example, performance can be improved by assigning a sufficient size FIFO area to the endpoints for bulk transfers. 4.6.3 Data Flow Endpoints are assigned to USB FIFO areas on a one-to-one basis, and responses are returned to USB transactions automatically, depending on effective USB FIFO free capacity (for OUT transfers) or effective data quantity (for IN transfers). This means the software does not need to be directly involved in individual transactions, allowing USB data transfers to be controlled as data flows at the USB FIFO. CPU USB FIFO Write Read FIFO_Empty Write Endpoint Data quantity < MaxPktSize Data quantity >= MaxPktSize FIFO_Full Transfer sent FIFO_Empty Write Data quantity < MaxPktSize Data quantity >= MaxPktSize FIFO_Full Empty USB Host IN token NAK handshake IN transaction (NAK response) IN token DATA packet IN transaction (Data reply) ACK handshake IN token NAK handshake IN transaction (NAK response) IN token DATA packet IN transaction (Data reply) ACK handshake Data Figure 4-4 8 Typical data flow (with FIFO assigned for MaxPktSize and IN transfer) EPSON S1R72V27 Data Sheet (Rev. 1.00) 4. Explanation of Functions CPU USB FIFO Read Write FIFO_Empty Endpoint Free quantity >= MaxPktSize USB Host PING token ACK handshake OUT token DATA packet FIFO_Full Read d Transfer receive NYET handshak e Free quantity < MaxPktSize PING token Free quantity >= MaxPktSize FIFO_Empty Empty NAK handshake PING transaction (ACK response) OUT transaction (Data receipt) PING transaction (NAK response) PING token ACK handshake PING transaction (ACK response) Data Note: PING transactions are performed only in High Speed mode. Figure 4-5 4.6.4 Typical data flow (with FIFO assigned for MaxPktSize and OUT transfer) USB Device Port External Circuits The LSI USB Port 0 has internal FS and HS device termination resistors, eliminating the need for the components normally used to adjust impedance. This allows a DP/DM line to be connected directly between the LSI terminal and the connector. Note that the appropriate components must be used to ensure static electricity protection and to implement EMI precautions. The VBUS terminal uses a 5 V input and does not require external voltage conversion. A protection circuit is recommended, since certain commercially-available USB host and hub products may apply surge voltages exceeding VBUS ratings. Refer to the separately provided PCB Design Guidelines for S1R72V Series USB 2.0 Hi-Speed. S1R72V27 Data Sheet (Rev. 1.00) EPSON 9 4. Explanation of Functions 4.7 USB Host I/F The LSI USB Port 0 and Port 1 support high-speed specification USB host functions complying with the USB 2.0 (Universal Serial Bus Specification Revision 2.0) standards. 4.7.1 Speed Mode and Transfer Type This LSI's USB host function supports HS (480 Mbps), FS (12 Mbps) and LS (1.5 Mbps) speed modes. The speed mode is automatically set by speed negotiations performed on resetting the bus. All transfer types stipulated in the USB 2.0 standard are supported, including control transfers, bulk transfers, interrupt transfers, and isochronous transfers. 4.7.2 Resources 4.7.2.1 Channels In the LSI USB host functions, sets of register settings for transfers with end points on a one-to-one basis are called channels. The LSI USB host function features one dedicated channel for control transfers, one dedicated channel for bulk transfers, and four general channels that support bulk transfers, interrupt transfers, and isochronous transfers. The endpoint number, maximum packet size, and transfer direction (IN/OUT) can be set as desired for all channels. Transfers are also possible for a number of endpoints exceeding the channel number using software-based time-multiplexing for the channels. 4.7.2.2 FIFO Each port on the LSI includes 4.5 kB of FIFO for use with USB data transfers. This forms the data transfer route with USB. The FIFO capacity for each channel can be assigned as desired by the software. For example, to improve performance, assign a FIFO area of adequate size to the endpoints for bulk transfers. 4.7.3 Data Flow The channels are assigned to FIFO areas on a one-to-one basis. Transactions are sent automatically to USB, depending on the FIFO effective free capacity (for IN transfers) or effective data quantity (for OUT transfers). The software does not need to be directly involved in individual transactions, allowing USB data transfers to be controlled as data flow at the FIFO. 10 EPSON S1R72V27 Data Sheet (Rev. 1.00) 4. Explanation of Functions CPU FIFO Read Channel USB Device Write Free quantity >= MaxPktSize FIFO_Empty IN token NAK handshake IN transaction (NAK response) IN token DATA packet Transfer received FIFO_Full Read IN transaction (Data reply) ACK handshake Free quantity < MaxPktSize Free quantity >= MaxPktSize FIFO_Empty Empty IN token NAK handshake Data Figure 4-6 Typical data flow (with FIFO assigned for MaxPktSize and IN transfer) CPU FIFO Write Channel Read FIFO_Empty Write USB Device Data quantity < MaxPktSize Data quantity >= MaxPktSize FIFO_Full OUT token DATA packet Transfer sent FIFO_Empty Write OUT transaction ACK handshake Data quantity < MaxPktSize Data quantity >= MaxPktSize FIFO_Full OUT token DATA packet Empty Data Figure 4-7 IN transaction (NAK response) Transfer sent OUT transaction ACK handshake Typical data flow (with FIFO assigned for MaxPktSize and OUT transfer) S1R72V27 Data Sheet (Rev. 1.00) EPSON 11 4. Explanation of Functions 4.7.4 USB Host Port External Circuits The LSI ports have internal USB host termination resistors, including an HS termination resistor, eliminating the need for the external components normally used to adjust impedance. This allows a DP/DM line to be connected between the LSI terminal and the connector. Note that the appropriate components must be used to ensure static electricity protection and to implement EMI precautions. An external VBUS control component is required for the VBUS. 4.8 FIFO The LSI includes 4.5 kB of USB FIFO for use with USB data transfers. The USB FIFO capacity for each endpoint or channel can be assigned as desired using the register settings. Transfers are possible between the USB-I/F and CPU-I/F via the USB FIFO. 12 EPSON S1R72V27 Data Sheet (Rev. 1.00) 5. Terminal Layout Diagrams VSS LVDD CD9 CD10 VSS CVDD CD11 CD12 CD13 CD14 CD15 N.C. CVDD CLKIN VSS VSS XO XI LVDD BURNIN 5. Terminal Layout Diagrams 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Figure 5-1 VSS LVDD TESTEN CA8 CA7 CA6 CA5 CVDD VSS CA1 ATPGEN CD8 CD7 CD6 CD5 CD4 CD3 LVDD VSS CVDD CD2 CD1 CD0 XDACK XDREQ XWRL XWRH XRD XCS XINT 9 10 11 12 13 14 15 16 17 18 19 20 CA4 8 CA3 7 CA2 5 6 XBEL 4 XRESET 3 HVDD 2 VBUSEN 1 VBUSFLG 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LVDD N.C. N.C. N.C. N.C. LVDD VSS R1 VSS N.C. HVDD DM VSS DP HVDD VBUS LVDD VSS N.C. N.C. N.C. QFP package terminal layout diagram (QFP14-80) 1 2 3 4 5 6 7 8 A NC LVDD DP DM HVDD R1 LVDD BURNIN A B VBUSFLG VSS HVDD VSS VSS VSS VSS XI B C VBUSEN HVDD VBUS CA1 CA3 CD15 LVDD XO C D XRESET XBEL CA5 CD13 CVDD CLKIN D E CA2 CA4 XINT CD4 CD11 CD14 E F CA7 CA8 XWRH XDACK CD3 CD7 CD10 CD12 F G CA6 LVDD XRD XDREQ CD1 CD6 VSS CD9 G H TESTEN XCS XWRL CD0 CD2 CD5 CD8 ATPGEN H 1 2 3 4 5 6 7 8 Top View Figure 5-2 BGA package terminal layout diagram (PFBGA5UX60) S1R72V27 Data Sheet (Rev. 1.00) EPSON 13 5. Terminal Layout Diagrams 1 2 3 4 5 6 7 8 9 A NC LVDD HVDD DP DM HVDD R1 LVDD NC A B VSS VSS VBUS VSS VSS VSS VSS VSS XI B HVDD LVDD XBEL CA1 CVDD BURNIN LVDD XO C CA3 NC NC NC CD12 CD15 CLKIN D C VBUSFLG D XRESET VBUSEN E CA2 VSS CA4 NC NC NC VSS CD13 CD14 E F CVDD CA5 CA8 NC NC NC CD7 CD9 CD11 F G CA7 CA6 TESTEN XCS XDACK CD0 CD4 CD8 CD10 G H J LVDD NC XINT VSS XWRL XWRH XRD XDREQ CD1 CD2 CVDD CD3 CD6 CD5 ATPGEN VSS LVDD NC H J 1 2 3 4 5 6 7 8 9 Top View Figure 5-3 14 BGA package terminal layout diagram (PFBGA8UX81) EPSON S1R72V27 Data Sheet (Rev. 1.00) 6. Terminal Functions 6. Terminal Functions OSC QFP Pin BGA5 Ball BGA8 Ball 58 B8 B9 57 C8 C9 Name Terminal type I/O RESET Terminal description XI IN - Analog Internal oscillator circuit input (12 MHz, 24 MHz) XO OUT - Analog Internal oscillator circuit output The clock inputs from the crystal oscillator and CLKIN for XI and XO are used exclusively by the register settings. Fix XI at Low when using CLKIN. TEST QFP Pin BGA5 Ball BGA8 Ball 18 H1 G3 40 H8 H8 ATPGEN IN (PD) (PD) Test terminal (Set to Low) 60 A8 C7 BURNIN IN (PD) (PD) Test terminal (Set to Low) BGA5 Ball BGA8 Ball I/O RESET Terminal type Terminal description Analog Internal operation reference current setting terminal Connect 6.2 kW 1% resistance between terminal and VSS Name TESTEN I/O RESET Terminal type IN (PD) (PD) Terminal description Test terminal (Set to Low) USB QFP Pin 67 A6 A7 Name R1 IN - 73 A3 A4 DP BI Hi-Z Analog USB port 0, data line (Data +) 71 A4 A5 DM BI Hi-Z Analog USB port 0, data line (Data -) 3 B1 C1 VBUSFLG IN (PU) Schmitt (PU) USB power switch fault detection signal (1: Normal, 0: Error) 4 C1 D2 VBUSEN OUT Lo 2mA USB power switch control signal 75 C3 B3 VBUS IN (PD) (PD) USB device bus detection signal PD: Pull Down PU: Pull Up S1R72V27 Data Sheet (Rev. 1.00) EPSON 15 6. Terminal Functions CPU I/F QFP Pin BGA5 Ball BGA8 Ball Name I/O RESET Terminal type Bus Mode Terminal description Strobe Mode BE Mode 6 D1 D1 XRESET IN - Schmitt 54 D8 D9 CLKIN IN - - External clock input Reset signal 23 G3 H4 XRD IN - - Read/strobe IN - - Write/strobe (lower) Write/strobe Write/strobe (upper) High-byte enable 25 H3 H3 XWRL (XWR) 24 F3 J3 XWRH (XBEH) IN - - 22 H2 G4 XCS IN - Schmitt 21 E3 H2 XINT OUT High 2mA (Tri-state) 26 G4 J4 XDREQ OUT High 2mA 27 F4 G5 XDACK IN - - DMA acknowledge 7 D2 C4 XBEL IN - - Set to High or Low 8 C4 C5 CA1 IN - - 9 E1 E1 CA2 IN - - 10 C5 D3 CA3 IN - - 11 E2 E3 CA4 IN - - 14 D3 F2 CA5 IN - - 15 G1 G2 CA6 IN - - 16 F1 G1 CA7 IN - - 17 F2 F3 CA8 IN - - 28 H4 G6 CD0 BI Hi-Z 2mA 29 G5 H5 CD1 BI Hi-Z 2mA 30 H5 J5 CD2 BI Hi-Z 2mA 2mA 34 F5 J6 CD3 BI Hi-Z 35 E6 G7 CD4 BI Hi-Z 2mA 36 H6 J7 CD5 BI Hi-Z 2mA 37 G6 H7 CD6 BI Hi-Z 2mA 38 F6 F7 CD7 BI Hi-Z 2mA 39 H7 G8 CD8 BI Hi-Z 2mA 43 G8 F8 CD9 BI Hi-Z 2mA 44 F7 G9 CD10 BI Hi-Z 2mA 47 E7 F9 CD11 BI Hi-Z 2mA 48 F8 D7 CD12 BI Hi-Z 2mA 49 D6 E8 CD13 BI Hi-Z 2mA 50 E8 E9 CD14 BI Hi-Z 2mA 51 C6 D8 CD15 BI Hi-Z 2mA Chip select signal Interrupt output signal DMA request Low-byte enable CPU bus address CPU data bus The XINT terminal can be set to 1/0 or Hi-Z/0 mode, depending on register settings. Note, however, that it cannot be pulled up with a voltage exceeding the rated value even in Hi-Z/0 mode, since it is not an open drain. The clock inputs from the crystal oscillator and CLKIN for XI and XO are used exclusively by the register settings. Fix CLKIN at Low when using XI and XO. PD: Pull Down PU: Pull Up 16 EPSON S1R72V27 Data Sheet (Rev. 1.00) 6. Terminal Functions POWER QFP Pin BGA5 Ball BGA8 Ball Name Voltage Terminal description 5, 70, 74 A5, B3, C2 A3, A6, C2 HVDD 3.3V 13, 31, 46, 53 D7 C6, F1, H6 CVDD 1.8 to 3.3V 1, 19, 33, 42, 59, 65, 76 A2, A7, C7, G2 A2, A8, C3, C8, H1, H9 LVDD 1.8V 2, 12, 20, 32, 41, 45, 55, 56, 66, 68, 72, 77 B2, B4, B5, B6, B7, G7 B1, B2, B4, B5, B6, B7, B8, E2, E7, J2, J8 VSS 0V GND A1 A1, A9, D4, D5, D6, E4, E5, E6, F4, F5, F6, J1, J9 N.C. 0V NC terminal (connect to GND) 52, 61, 62, 63, 64, 69, 78, 79, 80 S1R72V27 Data Sheet (Rev. 1.00) EPSON USB I/O power supply CPU I/F I/O power supply OSC I/O, TEST I/O, and internal power supply 17 7. Electrical Characteristics 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Item Symbol Rating Units Power supply voltage HVDD VSS - 0.3 to 4.0 V Input voltage Output voltage CVDD VSS - 0.3 to 4.0 V LVDD VSS - 0.3 to 2.5 V HVI VSS - 0.3 to HVDD + 0.5 V CVI*1 VSS - 0.3 to CVDD + 0.5 V VVI*2 VSS - 0.3 to 6.0 V LVI*3 VSS - 0.3 to LVDD + 0.5 V HVO VSS - 0.3 to HVDD + 0.5 V CVO*1 VSS - 0.3 to CVDD + 0.5 V Output current/terminal IOUT 10 mA Storage temperature Tstg -65 to 150 C *1 CPU-IF *2 VBUS *3 XI, TESTEN, ATPGEN, BURNIN 7.2 Recommended Operating Conditions Item Symbol MIN TYP MAX Units Power supply voltage HVDD 3.00 3.30 3.60 V CVDD 1.65 - 3.60 V LVDD 1.65 1.80 1.95 V HVI -0.3 - HVDD+0.3 V CVI*1 -0.3 - CVDD+0.3 V Input voltage Ambient temperature VVI*2 -0.3 - 6.0 V LVI*3 -0.3 - LVDD+0.3 V Ta -40 25 85 C *1 CPU-I/F *2 VBUS *3 XI, TESTEN, ATPGEN, BURNIN Turn on power to the IC in the sequence shown below. LVDD (internal) HVDD, CVDD (IO section) Likewise, turn off power to the IC in the sequence shown below. HVDD, CVDD (IO section) LVDD (internal) Note: Avoid leaving the HVDD or CVDD on continuously (for more than 1 second) when the LVDD is off, as doing so may affect chip reliability. 18 EPSON S1R72V27 Data Sheet (Rev. 1.00) 7. Electrical Characteristics 7.3 DC Characteristics 7.3.1 Item Power supply feed current Power supply current Stationary current Power supply current Current Consumption Symbol Condition MIN TYP MAX Units *1 IDDH HVDD = 3.3V(typ) - 7.9 12.0 mA IDDCH CVDD = 3.3V(typ) - 1.6 5.0 mA IDDCL CVDD = 1.8V(typ) - 0.7 2.0 mA IDDL LVDD = 1.8V(typ) - 40.2 62.0 mA VIN = HVDD,CVDD,LVDD or VSS HVDD = 3.6V CVDD = 3.6V LVDD = 1.95V - - 25 A HVDD = 3.6V CVDD = 3.6V LVDD = 1.95V HVIH = HVDD CVIH = CVDD LVIH = LVDD VIL = VSS -5 - 5 A HVDD = 3.0V CVDD = 1.65V LVDD = 1.65V HVOH = 5.5V -10 - 10 A *2 IDDS Input leakage Input leakage current IL Input leakage Input leakage current (5 V tolerant) ILIF *1: TYP is the measured value when transferring data with the USB-HDD connected as the USB host. MAX is the value estimated from this value. *2: Stationary current with Ta = 25C and both terminals in input mode. S1R72V27 Data Sheet (Rev. 1.00) EPSON 19 7. Electrical Characteristics Current consumption measurements for individual power management states using Seiko Epson operating conditions (Ta = 25C) Item CPU_Cut Power supply power SLEEP Power supply power ACTIVE (when operating as USB device) (USB CPU-I/F) Power supply power ACTIVE (when operating as USB host) (USB CPU-I/F) Power supply power Condition TYP Units 4.2 uW 8.8 uW 98 mW 118 mW CPU bus operation *1 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V CPU bus operation *1 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V *2 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V *3 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V *1: Excluding current consumption due to DP pull-up resistance inside S1R72V27 (approx. 200 A). *2: When transferring data connected to a PC as a USB device (actual transfer rate 13.5 MB/s). *3: When transferring data with the USB-HDD connected as the USB host (actual transfer rate 13 MB/s). 20 EPSON S1R72V27 Data Sheet (Rev. 1.00) 7. Electrical Characteristics 7.3.2 Input Characteristics Item Input characteristics (LVCMOS) H level input voltage L level input voltage Input characteristics (LVCMOS) H level input voltage L level input voltage H level input voltage L level input voltage Schmitt input characteristics (USB FS) H level trigger voltage L level trigger voltage Hysteresis voltage Input characteristics (USB FS differential) Differential input sensitivity Symbol Terminal names: VIH1 VIL1 Terminal names: VIH2 VIL2 VIH3 VIL3 Terminal names: VT+ (USB) VT- (USB) V (USB) Terminal names: VDS (USB) Input characteristics (VBUS) Terminal names: VT+(VBUS) VT- (VBUS) V (VBUS) Terminal names: VT1+ VT1V Terminal names: VT1+ VT1V1 VT2+ VT2V2 Terminal names: RPLU2H Terminal names: RPLD3L Terminal names: RPLD1L Terminal names: RPLD2L H level trigger voltage L level trigger voltage Hysteresis voltage Input characteristics (Schmitt) H level trigger voltage L level trigger voltage Hysteresis voltage Input characteristics (Schmitt) H level trigger voltage L level trigger voltage Hysteresis voltage H level trigger voltage L level trigger voltage Hysteresis voltage Input characteristics Pull-up resistor Input characteristics Pull-down resistor Input characteristics Pull-down resistor Input characteristics Pull-down resistor S1R72V27 Data Sheet (Rev. 1.00) Condition MIN TESTEN, ATPGEN, BURNIN LVDD = 1.95V LVDD = 1.65V 1.27 - TYP MAX Units - 0.57 V V CA[8:1], CD[15:0], XRD, XWRL, XWRH, XBEL, XDACK, CLKIN CVDD=3.6V 2.2 CVDD=3.0 0.8 CVDD=1.95V 1.27 CVDD=1.65V 0.57 DP, DM HVDD = 3.6V HVDD = 3.0V HVDD= 3.0V DP, DM pair V V V V 1.1 1.0 0.1 - 1.8 1.5 - V V V - - 0.2 V HVDD = 3.6V HVDD = 3.0V HVDD= 3.0V VBUSFLG 1.86 1.48 0.31 - 2.85 2.23 0.64 V V V HVDD = 3.6V HVDD = 3.0V HVDD= 3.0V XCS, XRESET 1.4 0.6 0.3 - 2.7 1.8 - V V V CVDD=3.6V CVDD=3.0V CVDD=3.0V CVDD=1.95V CVDD=1.65V CVDD=1.65V 1.4 0.6 0.3 0.6 0.3 0.2 - 2.7 1.8 1.4 1.1 - V V V V V V VBUSFLG VI=VSS VBUS 50 100 240 k VI=5.0V ATPGEN, BURNIN 110 125 150 k VI=LVDD TESTEN 24 60 150 k VI=LVDD 48 120 300 k HVDD = 3.0V Differential input voltage 0.8V to 2.5V VBUS EPSON 21 7. Electrical Characteristics 7.3.3 Item Output characteristics Symbol Condition MIN TYP MAX Units Terminal names: CD[15:0], XDREQ, XINT H level output voltage VOH1 CVDD = 3.0V IOH = -2mA CVDD-0.4 - - V L level output voltage VOL1 CVDD = 3.0V IOL = 2mA - - VSS+0.4 V H level output voltage VOH2 CVDD = 1.65V IOH = -1mA CVDD-0.4 - - V L level output voltage VOL2 CVDD = 1.65V IOL = 1mA - - VSS+0.4 V L level output voltage VOL2(2) CVDD = 1.65V IOL = 0.8mA - - VSS+0.3 V Output characteristics Terminal names:VBUSEN H level output voltage VOH4 HVDD = 3.0V IOH = -2mA HVDD-0.4 - - V L level output voltage VOL4 HVDD = 3.0V IOL = 2mA - - VSS+0.4 V 2.8 - - V - - 0.3 V 360 - - mV - - 10.0 mV -5 - 5 A Output characteristics (USB FS) Terminal names: DP, DM H level output voltage VOH(USB) L level output voltage VOL(USB) Output characteristics (USB HS) VHSOH (USB) L level output voltage VHSOL (USB) OFF-STATE leakage current HVDD=3.0V HVDD=3.6V Terminal names: DP, DM H level output voltage Output characteristics 22 Output Characteristics HVDD = 3.0V HVDD = 3.6V Terminal names: CD[15:0], XINT IOZ CVDD = 3.6V CVOH = CVDD VOL = VSS EPSON S1R72V27 Data Sheet (Rev. 1.00) 7. Electrical Characteristics 7.3.4 Item Terminal capacitance Input terminal capacitance Terminal capacitance Output terminal capacitance Terminal capacitance Input/output terminal capacitance 1 Terminal capacitance Input/output terminal capacitance 2 Terminal Capacitance Symbol Condition MIN TYP MAX Units - - 8 pF - - 8 pF - - 8 pF - - 11 pF Terminal name: All input terminals CI f = 10MHz HVDD = CVDD = LVDD = VSS Terminal name: All output terminals CO f = 10MHz HVDD = CVDD = LVDD = VSS Terminal name: All input/output terminals (except DP, DM) CIO1 f = 10MHz HVDD = CVDD = LVDD = VSS Terminal names: DP, DM CIO2 f = 10MHz HVDD = CVDD = LVDD = VSS S1R72V27 Data Sheet (Rev. 1.00) EPSON 23 7. Electrical Characteristics 7.4 AC Characteristics 7.4.1 Reset Timing tRESET XRESET Code tRESET 7.4.2 Description Reset pulse width min typ max Units 40 - - ns min typ max Units Clock Timing <Internal oscillator> tCYC tCYCL tCYCH XI Code tCYC Clock cycle (ClkFreq=0b00) 11.9988 12 12.0012 MHz tCYC Clock cycle (ClkFreq=0b01) 23.9976 24 24.0024 MHz 45 - 55 % tCYCH tCYCL 24 Description Clock duty EPSON S1R72V27 Data Sheet (Rev. 1.00) 7. Electrical Characteristics <External input> tCYI tCYIL tCYIH CLKIN Code Description min typ max Units tCYI Clock cycle (ClkFreq=0b00) 11.9988 12 12.0012 MHz tCYI Clock cycle (ClkFreq=0b01) 23.9976 24 24.0024 MHz tCYI Clock cycle (ClkFreq=0b11) 47.9952 48 48.0048 MHz 45 - 55 % tCYIH tCYIL Clock duty S1R72V27 Data Sheet (Rev. 1.00) EPSON 25 7. Electrical Characteristics 7.4.3 CPU/DMA I/F Access Timing 7.4.3.1 Specifications for CVDD = 1.65 V to 3.6 V tcas tcah CAI tccn tccs tcch XCSI trcy tras XRDI trng trdf Read trbd trbh trdh CDO Valid twcy XWRH/LI XWR Write twas twbs XBEH/L(I) twng twbh twds twdh CDI tdrn tdng XDREQ(O) tdaa tdan XDACK(I) (CL=30pF) Code Item min typ max unit tcas Address setup time 6 - - ns tcah Address hold time 6 - - ns tccs XCS setup time 6 - - ns tcch XCS hold time 6 - - ns tccn XCS negate time (Only when CPUIF mode is set*) 15 - - ns trcy Read cycle 55 - - ns tras Read strobe assert time 35 - - ns trng Read strobe negate time 20 - - ns trbd Read data output start time 1 - - ns trdf Read data confirmation time - - 33 ns trdh Read data hold time 2 - - ns trbh Read data output delay time - - 6 ns twcy Write cycle 55 - - ns twas Write strobe assert time 35 - - ns twng Write strobe negate time 20 - - ns twbs Write byte enable setup time 6 - - ns twbh Write byte enable hold time 6 - - ns twds Write data delay acknowledge time - - 10 ns twdh Write data hold time (after strobe negation) 6 - - ns tdrn XDREQ negate delay time - - 35 ns tdaa XDACK setup time 6 - - ns tdan XDACK hold time 6 - - ns tdng XDREQ minimum negate time Nn *16.6 - - ns *Nn is determined by the DMA_EdgeMode.NegControl[3:0] setting. Nn = (NegControl + 3) 26 EPSON S1R72V27 Data Sheet (Rev. 1.00) 7. Electrical Characteristics 7.4.3.2 Specifications when limited to CVDD = 3.0 V to 3.6 V (relaxed specifications) tcas tcah CAI tccn tccs tcch XCSI trcy tras XRDI trng trdf Read trbd trbh trdh CDO Valid twcy XWRH/LI XWR Write twas twbs XBEH/L(I) twng twbh twds twdh CDI tdrn tdng XDREQ(O) tdaa tdan XDACK(I) (CL=30pF) Code Item min typ max unit tcas Address setup time 6 - - ns tcah Address hold time 6 - - ns tccs XCS setup time 6 - - ns tcch XCS hold time 6 - - ns tccn XCS negate time (Only when CPU IF mode is set*) 15 - - ns trcy Read cycle 55 - - ns tras Read strobe assert time 33 - - ns trng Read strobe negate time 20 - - ns trbd Read data output start time 1 - - ns trdf Read data confirmation time - - 30 ns trdh Read data hold time 2 - - ns trbh Read data output delay time - - 6 ns twcy Write cycle 55 - - ns twas Write strobe assert time 33 - - ns twng Write strobe negate time 20 - - ns twbs Write byte enable setup time 6 - - ns twbh Write byte enable hold time 6 - - ns twds Write data delay acknowledge time - - 10 ns twdh Write data hold time (after strobe negation) 6 - - ns tdrn XDREQ negate delay time - - 30 ns tdaa XDACK setup time 6 - - ns tdan XDACK hold time 6 - - ns tdng XDREQ minimum negate time Nn *16.6 - - ns *Nn is determined by the DMA_EdgeMode.NegControl[3:0] setting. Nn = (NegControl + 3) S1R72V27 Data Sheet (Rev. 1.00) EPSON 27 7. Electrical Characteristics 7.4.4 USB I/F Timing Complies with the USB 2.0 standard (Universal Serial Bus Specification Revision 2.0 Released on April 27, 2000). 28 EPSON S1R72V27 Data Sheet (Rev. 1.00) 8. Connection Examples 8. Connection Examples 8.1 CPU I/F Connection Example Address[8:1] CA[8:1] XBEL DATA[15:0] DATA[15:0] XCS XCS XRD XRD XWRH XWRH/XBEH XWRL XWRL/XWR XDREQ XDREQ *1 *1: Open when DMA is not used XDACK XDACK *2 *2: Set to inactive level when DMA is not used XINT XINT 16-bit CPU (XWRH/XWRL) connection example Address[8:1] XBEL DATA[15:0] CA[8:1] XBEL DATA[15:0] XCS XCS XRD XRD XBEH XWRH/XBEH XWR XWRL/XWR XDREQ XDREQ *1 *1: Open when DMA is not used XDACK XDACK *2 *2: Set to inactive level when DMA is not used XINT XINT 16-bit CPU (XBEH/XBEL) connection example S1R72V27 Data Sheet (Rev. 1.00) EPSON 29 8. Connection Examples 8.2 USB I/F Connection Example Refer to the separately provided S1R72V Series USB 2.0 Hi-Speed PCB Design Guidelines. 30 EPSON S1R72V27 Data Sheet (Rev. 1.00) 9. Product Codes 9. Product Codes Table 9-1 Product codes Product code Product type S1R72V27B05**** PFBGA5UX60 package S1R72V27B08**** PFBGA8UX81 package S1R72V27F14**** QFP14-80 package S1R72V27 Data Sheet (Rev. 1.00) EPSON 31 10. External Dimension Diagrams 10. External Dimension Diagrams Refer to the PFBGA5UX60, PFBGA8UX81 and QFP14-80 package drawings at the end of this document. 32 EPSON S1R72V27 Data Sheet (Rev. 1.00) Revision History Revision History Revision details Date 11/20/2007 Rev. Page (old issue) Type 1.0 All New Details Newly established Top View D Index A1 A E A1 Corner Bottom View Symbol e SD A1 Corner 1 2 3 4 5 6 7 8 e SE H G F E D C B A D E A A1 e b X Y SD SE Min Nom Max 0.26 5 5 0.23 0.5 0.25 0.25 1.2 0.36 0.08 0.1 PTFBGA06005050.50(PFBGA5U60) 2900000201(Rev.1.1) Top View D A1 Corner A1 A E Index Bottom View ZD e Symbol 1 2 3 4 5 6 7 8 9 ZE A1 Corner e J H G F E D C B A D E A A1 e b x y ZD ZE PTFBGA08108080.80(PFBGA8U81) 2900000201(Rev.1.1) Min 0.38 Nom Max 8 8 0.3 0.8 0.8 0.8 1.2 0.48 0.08 0.1 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS EPSON (CHINA) CO., LTD. 2580 Orchard Parkway San Jose , CA 95131,USA Phone: +1-800-228-3964 FAX: +1-408-922-0238 SALES OFFICES Northeast 301 Edgewater Place, Suite 210 Wakefield, MA 01880, U.S.A. Phone: +1-800-922-7667 FAX: +1-781-246-5443 EUROPE EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-89-14005-0 FAX: +49-89-14005-110 23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: +86-10-6410-6655 FAX: +86-10-6410-7320 SHANGHAI BRANCH 7F, High-Tech Bldg., 900, Yishan Road, Shanghai 200233, CHINA Phone: +86-21-5423-5522 FAX: +86-21-5423-5512 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX EPSON Electronic Technology Development (Shenzhen) LTD. 12/F, Dawning Mansion, Keji South 12th Road, Hi- Tech Park, Shenzhen Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 FAX: +65-6271-3182 SEIKO EPSON CORPORATION KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: +82-2-784-6027 FAX: +82-2-767-3677 GUMI OFFICE 2F, Grand B/D, 457-4 Songjeong-dong, Gumi-City, KOREA Phone: +82-54-454-6027 FAX: +82-54-454-6093 SEIKO EPSON CORPORATION SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117 Document Code: 411338400 First Issue December 2007 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Epson: S1R72V27F14H100 S1R72V27B08H100 S1R72V27B05H100