Datasheet Feb 2010
1Order Number: 208043-04
Numonyx™ Axcell™ P33-65nm Flash Memory
512-Mbit , 1-Gbit , 2-Gbit
Datasheet
Product Features
High performance:
— 95ns initial access time for Easy BGA
— 105ns initial access time for TSOP
— 25ns 16-word asynchronous-page read
mode
— 52MHz with zero WAIT states, 17ns clock-
to-data output synchronous-burst read
mode
— 4-, 8-, 16-, and continuous-word options
for burst mode
— Buffered Enhanced Factory Programming at
2.0MByte/s (typ) using 512-word buffer
— 3.0V buffered programming at 1.46MByte/s
(Typ) using 512-word buffer
Architecture:
— Multi-Level Cell Technology: Highest
Density at Lowest Cost
— Symmetrically-blocked architecture (512-
Mbit, 1-Gbit, 2-Gbit)
— Asymmetrically-blocked architecture, Four
32-KByte parameter blocks: Top or Bottom
configuration (512-Mbit, 1-Gbit)
—128-KByte array blocks
— Blank Check to verify an erased block
Voltage and Power:
—V
CC (core) voltage: 2.3V – 3.6V
—V
CCQ (I/O) voltage: 2.3V – 3.6V for Easy
BGA
—V
CCQ (I/O) voltage: 2.3V - 3.0V for TSOP
— Standby current: 70µA(Typ) for 512-Mbit,
75µA (Typ) for 1-Gbit
— Continuous synchronous read current:
21mA (Typ)/24mA (Max) at 52MHz
Enhanced Security:
— Absolute write protection: VPP = VSS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down capability
— Password Access feature
— One-Time Programmable Register:
— 64 OTP bits, programmed with unique
information by Numonyx
— 2112 OTP bits, available for customer
programming
Software:
— 25µs (Typ) program suspend
— 30µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
— Common Flash Interface capable
Density and Packaging
— 56-Lead TSOP(512-Mbit, 1-Gbit)
— 64-Ball Easy BGA(512-Mbit, 1-Gbit, 2-Gbit)
— 16-bit wide data bus
Quality and Reliability
— Operating temperature: –40°C to +85°C
for Easy BGA
— Operating temperature: 0°C to +85°C for
TSOP
— Minimum 100,000 erase cycles
— 65nm process technology
Datasheet Feb 2010
2Order Number: 208043-04
Legal Lines and Dis claimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and Axcell are trademarks or registered trademarks of Numonyx , B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2010, Numonyx, B.V., All Rights Reserved.
Datasheet Feb 2010
3Order Number: 208043-04
P33-65nm
Contents
1.0 Functional Description............................................................................................... 5
1.1 Introduction ....................................................................................................... 5
1.2 Overview ...........................................................................................................5
1.3 Virtual Chip Enable Description (2-Gbit) ................................................................. 6
1.4 Memory Map....................................................................................................... 7
2.0 Package Information .................................................................................................9
2.1 56-Lead TSOP Package (512-Mbit, 1-Gbit) .............................................................. 9
2.2 64-Ball Easy BGA Package (512-Mbit, 1-Gbit, 2-Gbit) ............................................. 10
3.0 Pinouts and Ballouts................................................................................................ 12
4.0 Signals .................................................................................................................... 14
4.1 Dual-Die Configurations ..................................................................................... 15
5.0 Bus Operations ........................................................................................................ 16
5.1 Read - Asynchronous Mode................................................................................. 16
5.2 Read - Synchronous Mode .................................................................................. 16
5.3 Write ............................................................................................................... 17
5.4 Output Disable.................................................................................................. 17
5.5 Standby ........................................................................................................... 17
5.6 Reset............................................................................................................... 18
6.0 Command Set .......................................................................................................... 19
6.1 Device Command Codes ..................................................................................... 19
6.2 Device Command Bus Cycles .............................................................................. 20
7.0 Read Operation........................................................................................................ 22
7.1 Read Array ....................................................................................................... 22
7.2 Read Device Identifier........................................................................................ 22
7.3 Read CFI.......................................................................................................... 23
7.4 Read Status Register ......................................................................................... 23
7.5 Clear Status Register ......................................................................................... 23
8.0 Program Operation .................................................................................................. 24
8.1 Word Programming ........................................................................................... 24
8.2 Buffered Programming ....................................................................................... 24
8.3 Buffered Enhanced Factory Programming.............................................................. 25
8.3.1 BEFP Requirements and Considerations ..................................................... 26
8.3.2 BEFP Setup Phase .................................................................................. 26
8.3.3 BEFP Program/Verify Phase ..................................................................... 27
8.3.4 BEFP Exit Phase ..................................................................................... 27
8.4 Program Suspend .............................................................................................. 27
8.5 Program Resume............................................................................................... 28
8.6 Program Protection............................................................................................ 28
9.0 Erase Operation....................................................................................................... 29
9.1 Block Erase ...................................................................................................... 29
9.2 Blank Check ..................................................................................................... 29
9.3 Erase Suspend .................................................................................................. 30
9.4 Erase Resume................................................................................................... 30
9.5 Erase Protection ................................................................................................ 30
10.0 Security................................................................................................................... 31
10.1 Block Locking.................................................................................................... 31
10.1.1 Lock Block............................................................................................. 31
P33-65nm
Datasheet Feb 2010
4Order Number: 208043-04
10.1.2 Unlock Block ..........................................................................................31
10.1.3 Lock-Down Block ....................................................................................31
10.1.4 Block Lock Status ...................................................................................31
10.1.5 Block Locking During Suspend ..................................................................32
10.2 Selectable OTP Blocks ........................................................................................33
10.3 Password Access................................................................................................33
11.0 Register ...................................................................................................................34
11.1 Status Register (SR) ..........................................................................................34
11.2 Read Configuration Register (RCR) .......................................................................35
11.2.1 Read Mode (RCR.15) ...............................................................................36
11.2.2 Latency Count (RCR[14:11]) ....................................................................36
11.2.3 End of Word Line (EOWL) Considerations ...................................................38
11.2.4 WAIT Polarity (RCR.10) ...........................................................................39
11.2.5 WAIT Delay (RCR.8)................................................................................39
11.2.6 Burst Sequence (RCR.7) ..........................................................................39
11.2.7 Clock Edge (RCR.6).................................................................................40
11.2.8 Burst Wrap (RCR.3) ................................................................................40
11.2.9 Burst Length (RCR[2:0])..........................................................................41
11.3 One-Time Programmable (OTP) Registers .............................................................41
11.3.1 Reading the OTP Registers .......................................................................42
11.3.2 Programming the OTP Registers................................................................42
11.3.3 Locking the OTP Registers........................................................................43
12.0 Power and Reset Specifications ...............................................................................44
12.1 Power-Up and Power-Down .................................................................................44
12.2 Reset Specifications ...........................................................................................44
12.3 Power Supply Decoupling ....................................................................................45
13.0 Maximum Ratings and Operating Conditions ............................................................46
13.1 Absolute Maximum Ratings .................................................................................46
13.2 Operating Conditions..........................................................................................47
14.0 Electrical Specifications ...........................................................................................48
14.1 DC Current Characteristics ..................................................................................48
14.2 DC Voltage Characteristics ..................................................................................49
15.0 AC Characteristics....................................................................................................50
15.1 AC Test Conditions.............................................................................................50
15.2 Capacitance ......................................................................................................51
15.3 AC Read Specifications ......................................................................................52
15.4 AC Write Specifications .......................................................................................56
15.5 Program and Erase Characteristics .......................................................................60
16.0 Ordering Information...............................................................................................61
A Supplemental Reference Information.......................................................................62
A.1 Common Flash Interface .....................................................................................62
A.2 Flowcharts ........................................................................................................73
A.3 Write State Machine ...........................................................................................82
B Conventions - Additional Documentation .................................................................86
B.1 Acronyms .........................................................................................................86
B.2 Definitions and Terms ........................................................................................86
C Revision History.......................................................................................................87
Datasheet Feb 2010
5Order Number:208043-04
P33-65nm
1.0 Functional Description
1.1 Introduction
This document provides information about the NumonyxTM AxcellTM P33-65nm Flash
memory and describes its features, operations, and specifications.
P33-65nm is the latest generation of NumonyxTM AxcellTM P33 Flash memory to the
embedded flash market segment, offered in 64-Mbit up through 2-Gbit. This document
covers specifically 512-Mbit, 1-Gbit, 2-Gbit product information. Benefits include more
density in less space, high-speed interface NOR device, and support for code and data
storage. Features include high-performance synchronous-burst read mode, dramatical
improvement in buffer program time through larger buffer size, fast asynchronous
access times, low power, flexible security options, and two industry-standard package
choices.
P33-65nm is manufactured using Numonyx™ 65nm process technology.
1.2 Overview
The P33-65nm device provides high performance on a 16-bit data bus. Individually
erasable memory blocks are sized for optimum code and data storage. Upon initial
power-up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the RCR(Read Configuration Register) enables synchronous burst-mode
reads. In synchronous burst mode, output data is synchronized with a user-supplied
clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast buffer program and erase operations. The device features
a 512-word buffer to enable optimum programming performance, which can improve
system programming throughput time significantly to 1.46MByte/s.
Designed for low-voltage systems, P33-65nm device supports read operations with VCC
at 3.0V, and erase and program operations with VPP at 3.0V or 9.0V. Buffered
Enhanced Factory Programming provides the fastest flash array programming
performance with VPP at 9.0V, which increases factory throughput. With VPP at 3.0V,
VCC and VPP can be tied together for a simple, ultra low power design. In addition to
voltage flexibility, a dedicated VPP connection provides complete data protection when
VPP ≤ VPPLK.
The Command User Interface is the interface between the system processor and all
internal operations of the device. An internal Write State Machine automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
A device command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations.
The P33-65nm OTP register allows unique flash device identification that can be used to
increase system security. The individual Block Lock feature provides zero-latency block
locking and unlocking. The P33-65nm device adds enhanced protection via Password
Access; this new feature allows write and/or read access protection of user-defined
blocks. In addition, the P33-65nm device also has backward compatible One-Time
Programmable (OTP) permanent block locking security feature.
P33-65nm
Datasheet Feb 2010
6Order Number: 208043-04
1.3 Virtual Chip Enable Description (2-Gbit)
The P33-65nm device employs a Virtual Chip Enable which combines two 1-Gbit dies
with a common chip enable, CE# for Easy BGA and TSOP packages. Address A27 is
then used to select between the die pair with CE# asserted, depending upon the
package option used. When chip enable is asserted and A27 is low (VIL), the bottom die
is selected; when chip enable is asserted and A27 is high (VIH), the top die is selected.
Table 1: Flash Die Virtual Chip Enable Truth Table for 2-Gbit (1-Gbit/1-Gbit) Devices
Die Selected CE# A27
Bottom Die L L
To p D i e L H
Datasheet Feb 2010
7Order Number:208043-04
P33-65nm
1.4 Memory Map
Figure 1: P33-65nm Memory Map (512-Mbit and 1-Gbit Densities)
16- Kword Bloc k
16- Kword Bloc k
64- Kword Bloc k
1024
1023
A[26:1]1-Gbit
16- Kword Bloc k
16- Kword Bloc k
64- Kword Bloc k
64- Kword Bloc k
1025
1026
0
1
1022
3FFC000-3FFFFFF
3FF8000-3FFBFFF
3FF4000-3FF7FFF
3FF0000-3FF3FFF
3FE0000-3FEFFFF
010000-01FFFF
000000-00FFFF
16- K w ord Block
16- K w ord Block
Top Boot
512-Mbit
Word Wi de (x16) M ode
64- K w ord Block
512
511
A[25:1 ] 512Mbit
16- K w ord Block
16- K w ord Block
64- K w ord Block
64- K w ord Block
513
514
0
1
510
512-Mbit
1FFC000-1FFFFFF
1FF8000-1FFBFFF
1FF4000-1FF7FFF
1FF0000-1FF3FFF
1FE0000-1FEFFFF
010000-01FFFF
000000-00FFFF
-Gbit1
16- Kw o rd B lock
64- Kw o rd B lock
16- Kw o rd B lock
Bottom B oot
512-Mbit and 1-Gbit
Word Wide (x16) Mo de
000000-003FFF
64- Kw o rd B lock
1
0
514
512-Mbit
64- Kw o rd B lock
1026
16- Kw o rd B lock
16- Kw o rd B lock
64- Kw o rd B lock
64- Kw o rd B lock
2
3
4
5
258
004000-007FFF
008000 -00BFFF
00C000-00FFFF
010000-01FFFF
020000-02FFFF
FF0000-FFFFFF
1FF0000-1FFFFFF
3FF0000-3FFFFFF
-Gbit1
000000-00FFFF
512-Mbit
010000-01FFFF
020000-02FFFF
FF0000-FFFFFF
1FF0000-1FFFFFF
3FF0000-3FFFFFF
-Gbit1
Word Wide (x 16) Mode
Sy mmetrically-Blocked
512-Mbit and 1-Gbit
64- Kword Block
64- Kword Block
0
1
64- Kword Block
64- Kword Block
2
3
64- Kword Block
255
030000-03FFFF
64- Kword Block
511
64- Kword Block
1023
Top B oot
1-Gbit
Word Wi de (x16) Mode
P33-65nm
Datasheet Feb 2010
8Order Number: 208043-04
Figure 2: P33-65nm Memory Map (2-Gbit)
64- Kword Bl ock
000000-00FFFF
64- Kword Bl ock
511
512-Mbit
64- Kword Bl ock
1023
64- Kword Bl ock
64- Kword Bl ock
1
2
255
010000-01FFFF
020000-02FFFF
FF0000-FFFFFF
1
FF0000-1FFFFFF
3
FF0000-3FFFFFF
-Gbit1
64- Kword Bl ock
0
Word W i de (x16) Mode
A[27:1 ] 2-Gbit (1-Gbit/1-Gbit)
64- Kword Bl ock
1024
4000000 -400FFFF
64- Kword Bl ock
1025
4010000 -401FFFF
64- Kword Bl oc k
2047
7
FF0000-7FFFFFF
1-Gbit/1-Gbit
Datasheet Feb 2010
9Order Number:208043-04
P33-65nm
2.0 Package Information
2.1 56-Lead TSOP Package (512-Mbit, 1-Gbit)
Figure 3: TSOP Mechanical Specifications
Table 2: TSOP Package Dimensions (Sheet 1 of 2)
Product Information Symbol
Millimeters Inches
Min Nom Max Min Nom Max
Package Height A - - 1.200 - - 0.047
Standoff A10.050 - - 0.002 - -
Package Body Thickness A20.965 0.995 1.025 0.038 0.039 0.040
Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008
Lead Thickness C 0.100 0.150 0.200 0.004 0.006 0.008
Package Body Length D118.200 18.400 18.600 0.717 0.724 0.732
Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559
Lead Pitch e - 0.500 - - 0.0197 -
Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795
Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028
A
0
L
Detail A
Y
D
C
Z
Pin 1
E
D
1
b
Detail B
See Detail A
e
See Detail B
A
1
Seating
Plane
A
2
See Note 2
See Notes 1 and 3
P33-65nm
Datasheet Feb 2010
10 Order Number: 208043-04
2.2 64-Ball Easy BGA Package (512-Mbit, 1-Gbit, 2-Gbit)
Lead Count N - 56 - - 56 -
Lead Tip Angle θ0° 3° 5° 0° 3° 5°
Seating Plane Coplanarity Y - - 0.100 - - 0.004
Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014
Notes:
1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Figure 4: Easy BGA Mechanical Specifications (8x10x1.2 mm)
Table 2: TSOP Package Dimensions (Sheet 2 of 2)
Product Information Symbol
Millimeters Inches
Min Nom Max Min Nom Max
E
Seating
Plane
S1
S2
e
Top View - Ball side down Bottom View - Ball Side Up
Y
A
A1
D
Ball A1
Corner
A2
Note: Drawing not to scale
A
B
C
D
E
F
G
H
876543 2 1
87654321
A
B
C
D
E
F
G
H
b
Ball A
1
Corne
r
Table 3: Easy BGA Package Dimensions for 8x10x1.2 mm (Sheet 1 of 2)
Product Information Symbol
Millimeters Inches
Min Nom Max Min Nom Max
Package Height A - - 1.200 - - 0.0472
Ball Height A1 0.250 - - 0.0098 - -
Package Body Thickness A2 - 0.780 - - 0.0307 -
Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209
Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976
Datasheet Feb 2010
11 Order Number:208043-04
P33-65nm
Package Body Length E 7.900 8.000 8.100 0.3110 0.3149 0.3189
Pitch e - 1.000 - - 0.0394 -
Ball (Lead) Count N - 64 - - 64 -
Seating Plane Coplanarity Y - - 0.100 - - 0.0039
Corner to Ball A1 Distance Along D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630
Corner to Ball A1 Distance Along E S2 0.400 0.500 0.600 0.0157 0.0197 0.0236
Note: One dimple on package denotes Pin 1, which will always be in the upper left corner of the package, in
reference to the product mark.
Table 3: Easy BGA Package Dimensions for 8x10x1.2 mm (Sheet 2 of 2)
Product Information Symbol
Millimeters Inches
Min Nom Max Min Nom Max
P33-65nm
Datasheet Feb 2010
12 Order Number: 208043-04
3.0 Pinouts and Ballouts
Notes:
1. A1 is the least significant address bit.
2. A25 is valid for 512-Mbit densities and above; otherwise, it is a no connect (NC).
3. A26 is valid for 1-Gbit density and above; otherwise, it is a no connect (NC).
4. One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the
product mark.
Figure 5: 56-Lead TSOP Pinout (512-Mbit and 1-Gbit Densities)
Numonyx
TM
™
Axcell
TM
P33 Flash Memory
56-Lead TSOP P inout
14 mm x 20 mm
Top View
1
3
4
2
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
25
27
28
26
56
54
53
55
52
50
49
51
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
30
29
31
A14
A13
A12
A10
A9
A11
A23
A21
VSS
A22
A27
WP#
A20
WE#
A19
A8
A7
A18
A6
A4
A3
A5
A2
A25
A26
A24
WAIT
DQ1
5
DQ7
A17
DQ1
4
DQ1
3
DQ5
DQ6
DQ1
2
ADV
#
CLK
DQ4
RST
#
A16
DQ3
VPP
DQ1
0
VCC
Q
DQ9
DQ2
DQ1
DQ0
VCC
DQ8
OE#
CE#
A1
VSS
A15
DQ1
1
Datasheet Feb 2010
13 Order Number:208043-04
P33-65nm
Notes:
1. One dimple on package denotes A1 Pin which will always be in the upper left corner of the package, in reference to the
product mark.
2. A1 is the least significant address bit.
3. A25 is valid for 512-Mbit densities and above; otherwise, it is a no connect.
4. A26 is valid for 1-Gbit densities and above; otherwise, it is a no connect.
5. A27 is valid for 2-Gbit densities; otherwise, it is a no connect.
Figure 6: 64-Ball Easy BGA Ballout (512-Mbit, 1-Gbit, 2-Gbit)
18
234567
E asy BGA
To p Vi ew- Bal l si de do w n Easy BGA
Bottom V i ew- B al l si d e up
1
8234
5
67
H
G
F
E
D
C
B
A
H
G
F
E
D
C
A
A2 VSS A9 A14CE# A19 A26A25
A27 VSS VCC DQ13VSS DQ7 A24VSS
A3 A7 A10 A15A12 A20 A21WP#
A4 A5 A11 VCCQRST# A16 A17VCCQ
RFUDQ8 DQ1 DQ9 DQ4DQ3 DQ15CLK
RFU OE#DQ0 DQ10 DQ12DQ11 WAITADV#
WE#A23 RFU DQ2 DQ5VCCQ DQ14DQ6
A1 A6 A8 A13VPP A18 A22VCC
A23
A4A5A11VCCQ RST#A16A17 VCCQ
A1A6A8A13 VPPA18A22 VCC
A3A7A10A15 A12A20A21 WP#
RFU DQ8DQ1DQ9DQ4 DQ3DQ15 CLK
RFUOE# DQ0DQ10DQ12 DQ11WAIT ADV#
WE# RFUDQ2DQ5 VCCQDQ14 DQ6
A2VSSA9A14 CE#A19A26 A25
A27VSSVCCDQ13 VSSDQ7A24 VSS
B
P33-65nm
Datasheet Feb 2010
14 Order Number: 208043-04
4.0 Signals
Table 4: TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Symbol Type Name and Function
A[MAX:1] Input
ADDRESS INPUTS: Device address inputs. 512-Mbit: A[25:1], 1-Gbit: A[26:1], 2-Gbit: A[27:1].
Note: The virtual selection of the Top 1-Gbit die in the dual-die 2-Gbit configuration is accomplished
by setting A27 high (VIH).
DQ[15:0] Input/
Output
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
reads of memory, status register, OTP register, and read configuration register. Data balls/pins float
when the CE# or OE# are deasserted. Data is internally latched during writes.
ADV# Input
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CE# Input
CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted,
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip Enable must be high when device is not in use.
CLK Input
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OE# Input OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RST# Input
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT Output
WAIT: Indicates data valid in synchronous array or non-array burst reads. RCR.10, (WT) determines
its polarity when asserted. WAIT’s active output is VOL or VOH when CE# and OE# are VIL. WAIT is
high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WE# Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WP# Input
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
VPP Power/
Input
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP
voltages should not be attempted.
Set VPP = VPPL for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to array blocks for 1000 cycles maximum. VPP can be connected to 9 V for a
cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling
capability.
VCC Power DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ Power OUTPUT POWER SUPPLY: Output-driver source voltage.
VSS Power GROUND: Connect to system ground. Do not float any VSS connection.
Datasheet Feb 2010
15 Order Number:208043-04
P33-65nm
4.1 Dual-Die Configurations
Note: Amax = VIH selects the Top Die; Amax = VIL selects the Bottom Die.
RFU — RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Don’t Use (DU) signal.
DU — DON’T USE: Do not connect to any other signal, or power supply; must be left floating.
NC — NO CONNECT: No internal connection; can be driven or floated.
Table 4: TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)
Symbol Type Name and Function
Figure 7: 2-Gbit Dual-Die Block Diagram
Top Die
(1-Gbit)
Bottom Die
(1-Gbit)
WP#
CLK
CE#
ADV#
OE#
WAIT
WE#
RST#
VCC
VPP
DQ[15:
0]
A
[MAX:1]
VCCQ
VSS
2-Gbit ( Dual-D ie) Configurati on
P33-65nm
Datasheet Feb 2010
16 Order Number: 208043-04
5.0 Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
Bus cycles to/from the P33-65nm device conform to standard microprocessor bus
operations. Table 5, “Bus Operations Summary” summarizes the bus operations and
the logic levels that must be applied to the device control signal inputs.
5.1 Read - Asynchronous Mode
To perform an asynchronous page or single word read, an address is driven onto the
address bus, and CE# is asserted. ADV# can be driven high to latch the address, or it
must be held low throughout the read cycle. WE# and RST# must already have been
deasserted. WAIT is set to a deasserted state during asynchronous page mode and
single word mode as determined by RCR.10. CLK is not used for asynchronous page-
mode reads, and is ignored. After OE# is asserted, the data is driven onto DQ[15:0]
after an initial access time tAVQV or tGLQV delay. (See Table 25, “AC Read Specifications
-” on page 52).
If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level,
WAIT signal can be floated and ADV# must be tied to ground.
In asynchronous page mode, sixteen data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest four address bits determine which word of the
16-word page is output from the data buffer at any given time.
Refer to the following waveforms for more detailed information:Figure 18,
“Asynchronous Single-Word Read (ADV# Low)” on page 53, and Figure 19,
“Asynchronous Single-Word Read (ADV# Latch)” on page 54, and Figure 20,
“Asynchronous Page-Mode Read Timing” on page 54.
5.2 Read - Synchronous Mode
To perform a synchronous burst read on array or non-array, an initial address is driven
onto the address bus, and CE# is asserted. WE# and RST# must already have been
deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately,
Table 5: Bus Operations Summary
Bus Operation RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0] Notes
Read
Asynchronous VIH XL L L H
Deasserted Output
Synchronous VIH Running L L L H Driven Output
Write VIH X L L H L High-Z Input 1
Output Disable VIH X X L H H High-Z High-Z 2
Standby VIH X X H X X High-Z High-Z 2
Reset VIL X X X X X High-Z High-Z 2,3
Notes:
1. Refer to the Table 7, “Command Bus Cycles” on page 21 for valid DQ[15:0] during a write
operation.
2. X = Don’t Care (H or L).
3. RST# must be at VSS ± 0.2V to meet the maximum specified power-down current.
Datasheet Feb 2010
17 Order Number:208043-04
P33-65nm
ADV# can remain asserted throughout the burst access, in which case the address is
latched on the next valid CLK edge while ADV# is asserted. Once OE# is asserted, the
the first word is driven onto DQ[15:0] on the next valid CLK edge after initial access
latency delay (see Section 11.2.2, “Latency Count (RCR[14:11])” on page 36).
Subsequent data is output on valid CLK edges following a minimum delay Tchqv (see
Table 25, “AC Read Specifications -” on page 52).
However, for a synchronous non-array read, the same word of data will be output on
successive clock edges until the burst length requirements are satisfied.
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus. When
the device is operating in synchronous non-array read mode, such as read status, read
ID, or read query, the WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
Refer to the following waveforms for more detailed information: Figure 21,
“Synchronous Single-Word Array or Non-array Read Timing” on page 55, and
Figure 22, “Continuous Burst Read, showing an Output Delay Timing” on page 55, and
Figure 23, “Synchronous Burst-Mode Four-Word Read Timing” on page 56.
5.3 Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 7, “Command Bus Cycles” on page 21
shows the bus cycle sequence for each of the supported device commands, while
Table 6, “Command Codes and Definitions” on page 19 describes each command. See
Table 26, “AC Write Specifications” on page 56 for signal-timing details.
When the device is operating in write operations, WAIT is set to a deasserted state as
determined by RCR.10.
Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and
should not be attempted.
5.4 Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
5.5 Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
P33-65nm
Datasheet Feb 2010
18 Order Number: 208043-04
5.6 Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
NumonyxTM allow proper CPU initialization following a system reset through the use of
the RST# input.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80.
When RST# is driven low (RST# asserted), the flash device enters reset mode. Then all
internal circuits are de-energized, and the output drivers are placed in High-Z. If RST#
is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no
longer valid. A device reset also clears the Status Register. See Table 18, “Power and
Reset” on page 44 for RST# timing detail.
When RST# is driven high (RST# deasserted), a minimum wait is required before the
flash device is able to perform normal operations. Please consider Tphqv (R5) and
Tphwl (W1) during system design. see Table 25, “AC Read Specifications -” on page 52.
and Section 26, “AC Write Specifications” on page 56. After this wake-up interval
passes, normal operation is ready for execution.
Datasheet Feb 2010
19 Order Number:208043-04
P33-65nm
6.0 Command Set
6.1 Device Command Codes
The flash Command User Interface (CUI) provides control of all read, write, and erase
operations. The on-chip WSM manages all block-erase and word-program algorithms.
Device commands are written to the CUI to control all flash memory device operations.
The CUI does not occupy an addressable memory location; it is the mechanism through
which the flash device is controlled. Ta b l e 6 shows valid device command codes and
descriptions.
Table 6: Command Codes and Definitions (Sheet 1 of 2)
Mode Code Device Mode Description
Read
0xFF Read Array Places the device in Read Array mode. Array data is output on DQ[15:0].
0x70 Read Status
Register
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. SR data is output on DQ[7:0].
0x90
Read Device ID
or Read
Configuration
Register(RCR)
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or OTP register data on DQ[15:0].
0x98 Read CFI Places the device in Read Query mode. Subsequent reads output Common
Flash Interface information on DQ[7:0].
0x50 Clear Status
Register
The WSM can only set SR error bits. The Clear Status Register command is
used to clear the SR error bits.
Write
0x40 Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the SR Data for synchronous Non-array reads. The Read Array
command must be issued to read array data after programming has finished.
0xE8 Buffered Program This command loads a variable number of words up to the buffer size of 512
words onto the program buffer.
0xD0 Buffered Program
Confirm
The confirm command is issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
0x80 BEFP Setup
First cycle of a 2-cycle command; initiates the BEFP mode. The CUI then
waits for the BEFP Confirm command, 0xD0, that initiates the BEFP
algorithm. All other commands are ignored when BEFP mode begins.
0xD0 BEFP Confirm If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
Erase
0x20 Block Erase Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR[5,4], and places the
device in Read Status Register mode.
0xD0 Block Erase Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
SR Data for synchronous Non-array reads.
P33-65nm
Datasheet Feb 2010
20 Order Number: 208043-04
6.2 Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. See
Table 7, “Command Bus Cycles” on page 21. Several commands are used to modify
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RST# or by issuing an appropriate suspend command.
Suspend
0xB0 Program or Erase
Suspend
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR.2 (program
suspended) or SR.6 (erase suspended), along with SR.7 (ready). The WSM
remains in the suspend mode regardless of control signal states (except for
RST# asserted).
0xD0 Suspend Resume This command issued to any device address resumes the suspended program
or block-erase operation.
Protection
0x60 Block lock Setup
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets SR[5,4], indicating a
command sequence error.
0x01 Block lock If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
0xD0 Block Unlock
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
0x2F Block Lock-Down If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
0xC0
OTP Register or
Lock Register
program setup
First cycle of a 2-cycle command; prepares the device for a OTP register or
Lock Register program operation. The second cycle latches the register
address and data, and starts the programming algorithm to program data the
the OTP array.
Configuration
0x60 Read Configuration
Register Setup
First cycle of a 2-cycle command; prepares the CUI for device read
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR[5,4], indicating a
command sequence error.
0x03 Read Configuration
Register
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[16:1] to the Read Configuration
Register. Following a Configure RCR command, subsequent read operations
access array data.
Blank check
0xBC Block Blank Check First cycle of a 2-cycle command; initiates the Blank Check operation on a
array block.
0xD0 Block Blank Check
Confirm
Second cycle of blank check command sequence; it latches the block address
and executes blank check on the main array block.
EFI 0xEB Extended Function
Interface command
This command is used in extended function interface. first cycle of a multiple-
cycle command second cycle is a Sub-Op-Code, the data written on third
cycle is one less than the word count; the allowable value on this cycle are 0
through 511. The subsequent cycles load data words into the program buffer
at a specified address until word count is achieved.
Table 6: Command Codes and Definitions (Sheet 2 of 2)
Mode Code Device Mode Description
Datasheet Feb 2010
21 Order Number:208043-04
P33-65nm
Table 7: Command Bus Cycles
Mode Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr(1) Data(2) Oper Addr(1) Data(2)
Read
Read Array 1 Write DnA 0xFF - - -
Read Device Identifier ≥ 2WriteDnA0x90ReadDBA + IA ID
Read CFI ≥ 2WriteDnA0x98ReadDBA + CFI-ACFI-D
Read Status Register 2 Write DnA 0x70 Read DnA SRD
Clear Status Register 1 Write DnA 0x50 - - -
Program
Word Program 2 Write WA 0x40 Write WA WD
Buffered Program(3) > 2 Write WA 0xE8 Write WA N - 1
Buffered Enhanced
Factory Program
(BEFP)(4) > 2 Write WA 0x80 Write WA 0xD0
Erase Block Erase 2 Write BA 0x20 Write BA 0xD0
Suspend
Program/Erase
Suspend 1WriteDnA0xB0- - -
Program/Erase
Resume 1WriteDnA0xD0- - -
Protection
Block Lock 2 Write BA 0x60 Write BA 0x01
Block Unlock 2 Write BA 0x60 Write BA 0xD0
Block Lock-down 2 Write BA 0x60 Write BA 0x2F
Program OTP register 2 Write OTP-RA 0xC0 Write OTP-RA OTP-Data
Program Lock Register 2 Write LRA 0xC0 Write LRA LRD
Configuration Configure Read
Configuration Register 2 Write RCD 0x60 Write RCD 0x03
Blank Check Block Blank Check 2 Write BA 0xBC Write BA D0
EFI Extended Function
Interface command(5) >2 Write WA 0xEB Write WA Sub-Op
code
Notes:
1. First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address.(Note: needed for dual-die 2-Gbit device.)
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = OTP register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[16:1].
2. ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = OTP register data.
LRD = Lock Register data.
3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 512 words of data. Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4. The confirm command (0xD0) is followed by the buffer data.
5. The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1 ≤ N ≤ 512. The subsequent cycles load data
words into the program buffer at a specified address until word count is achieved, after the data words are loaded, the
final cycle is the confirm cycle 0xD0)
P33-65nm
Datasheet Feb 2010
22 Order Number: 208043-04
7.0 Read Operation
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read Query. Upon power-up or after a reset, the device defaults to Read Array
mode. To change the read state, the appropriate read command must be written to the
device (see Section 6.2, “Device Command Bus Cycles” on page 20). The following
sections describe read-mode operations in detail.
In order to enable synchronous burst reads, the RCR must be configured. Please see
Section 11.2, “Read Configuration Register (RCR)” on page 35 for RCR detail. Please
refer to Section 5.1, “Read - Asynchronous Mode” on page 16 and Section 5.2, “Read -
Synchronous Mode” on page 16 for bus operation detail. See Section 25, “AC Read
Specifications -” on page 52 for timing specification.
7.1 Read Array
Following a device power-up or reset, the device is set to Read Array mode. However,
to perform array reads after any other device operation (e.g. write operation), the Read
Array command must be issued in order to read from the flash memory array. Please
refer to Section 5.1, “Read - Asynchronous Mode” on page 16 and Section 5.2, “Read -
Synchronous Mode” on page 16 for bus operation detail. See Section 25, “AC Read
Specifications -” on page 52 for timing specification.
7.2 Read Device Identifier
The Read Device Identifier command instructs the device to output manufacturer code,
device identifier code, block-lock status, OTP register data, or configuration register
data (see Section 6.2, “Device Command Bus Cycles” on page 20 for details on issuing
the Read Device Identifier command). Table 8, “Device Identifier Information” on
page 22 and Table 9, “Device ID codes” on page 23 show the address offsets and data
values for this device.
Table 8: Device Identifier Information (Sheet 1 of 2)
Item Address(1,2) Data(x16)
Manufacturer Code 0x00 0x89h
Device ID Code 0x01 ID (See Ta b l e 9 )
Block Lock Configuration:
BBA(1) + 0x02
Lock Bit:
• Block Is Unlocked DQ0 = 0b0
• Block Is Locked DQ0 = 0b1
• Block Is not Locked-Down DQ1 = 0b0
• Block Is Locked-Down DQ1 = 0b1
Read Configuration Register 0x05 RCR Contents
General Purpose Register(3) DBA(2) + 0x07 GPR data
Lock Register 0 0x80 PR-LK0
64-bit Factory-Programmed OTP register 0x81–0x84 Numonyx Factory OTP register data
64-bit User-Programmable OTP Register 0x85–0x88 User OTP register data
Datasheet Feb 2010
23 Order Number:208043-04
P33-65nm
7.3 Read CFI
The Read CFI command instructs the device to output Common Flash Interface data
when read. See Section A.1, “Common Flash Interface” on page 62 for detailed
information.
7.4 Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Write Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
See Table 12, “Status Register Description” on page 34 for the description of the status
register.
7.5 Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of VPP. The WSM sets and clears SR.7, but it sets bits SR[5:3,1] without clearing them.
The Status Register should be cleared before starting a command sequence to avoid
any ambiguity. A device reset also clears the Status Register.
Lock Register 1 0x89 OTP register lock data
128-bit User-Programmable OTP registers 0x8A–0x109 User OTP register data
Notes:
1. BBA = Block Base Address.
2. DBA = Device base Address, Numonyx reserves other configuration address locations.
3. In P33-65nm, the GPR is used as read out register for Extended Function interface command.
Table 9: Device ID codes
ID Code Type Device Density
Device Identifier Codes
-T
(Top Parameter)
-B
(Bottom Parameter) Symmetrical Blocks
Device Code
512-Mbit 8964 8965 899E
1-Gbit 8966 8967 899F
Note: The 2-Gbit devices do not have a unique Device ID associated with them. Each die within the stack can be identified by
the ID codes.
Table 8: Device Identifier Information (Sheet 2 of 2)
Item Address(1,2) Data(x16)
P33-65nm
Datasheet Feb 2010
24 Order Number: 208043-04
8.0 Program Operation
The device supports three programming methods: Word Programming (40h or 10h),
Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,
D0h). The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block must be unlocked before
attempting to program the block. Attempting to program a locked block causes a
program error (SR[4,1] set) and termination of the operation. See Section 10.0,
“Security” on page 31 for details on locking and unlocking blocks.
8.1 Word Programming
Word programming operations are initiated by writing the Word Program Setup
command to the device. This is followed by a second write to the device with the
address and data to be programmed. The device outputs Status Register data when
read. See Figure 30, “Word Program Flowchart” on page 73. VPP must be above VPPLK,
and within the specified VPPL min/max values.
During programming, the WSM executes a sequence of internally-timed events that
program the desired data bits at the addressed location, and verifies that the bits are
sufficiently programmed. Programming the flash memory array changes “ones” to
“zeros”. Memory array bits that are zeros can be changed to ones only by erasing the
block.
The Status Register can be examined for programming progress and errors by reading
at any address. The device remains in the Read Status Register state until another
command is written to the device.
Status Register bit SR.7 indicates the programming status while the sequence
executes. Commands that can be issued to the device during programming are Read
Status Register, Read Device Identifier, Read CFI, and Read Array (this returns
unknown data).
When programming has finished, Status Register bit SR.4 (when set) indicates a
programming failure. If SR.3 is set, the WSM could not perform the word programming
operation because VPP was outside of its acceptable limits. If SR.1 is set, the word
programming operation attempted to program a locked block, causing the operation to
abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
8.2 Buffered Programming
The device features a 512-word buffer to enable optimum programming performance.
For Buffered Programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming. (see Figure 32, “Buffer Program Flowchart” on page 75).
When the Buffered Programming Setup command is issued, Status Register information
is updated and reflects the availability of the buffer. SR.7 indicates buffer availability: if
set, the buffer is available; if cleared, the buffer is not available.
Note: The device default state is to output SR data after the Buffer Programming Setup
Command. CE# and OE# low drive device to update Status Register. It is not allowed
Datasheet Feb 2010
25 Order Number:208043-04
P33-65nm
to issue 70h to read SR data after E8h command otherwise 70h would be counted as
Word Count.
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 512-word boundary (A[9:1] = 0x000). The
maximum buffer size would be 256-word if the misaligned address range is crossing a
512-word boundary during programming.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer
contents to the flash memory array. If a command other than the Buffered
Programming Confirm command is written to the device, a command sequence error
occurs and SR[7,5,4] are set. If an error occurs while writing to the array, the device
stops programming, and SR[7,4] are set, indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with VPP = VPPL or VPPH
(see Section 13.2, “Operating Conditions” on page 47 for limitations when operating
the device with VPP = VPPH).
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and SR[5,4] are set.
If Buffered programming is attempted while VPP is at or below VPPLK, SR[4,3] are set.
If any errors are detected that have set Status Register bits, the Status Register should
be cleared using the Clear Status Register command.
8.3 Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates
traditional programming elements that drive up overhead in device programmer
systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 33, “BEFP
Flowchart” on page 76). It uses a write buffer to spread MLC program performance
across 512 data words. Verification occurs in the same phase as programming to
accurately program the flash memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 512 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR.0 indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 512-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
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Datasheet Feb 2010
26 Order Number: 208043-04
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
8.3.1 BEFP Requirements and Considerations
Note: Word buffer boundaries in the array are determined by A[9:1] (0x000 through 0x1FF). The alignment start point is A[9:1]
= 0x000.
Notes:
1. Some degradation in performance may occur is this limit is exceeded, but the internal algorithm continues to work
properly.
2. If the internal address counter increments beyond the block’s maximum address, addressing wraps around to the
beginning of the block.
3. If the number of words is less than 512, remaining locations must be filled with 0xFFFF.
8.3.2 BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4
is set and BEFP operation terminates. If the block was found to be locked, SR.1 is also
set. SR.3 is set if the error occurred due to an incorrect VPP level.
Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
Table 10: BEFP Requirements
Parameter/Issue Requirement Notes
Case Temperature TC = 30°C ± 10°C
VCC Nominal Vcc
VPP Driven to VPPH
Setup and Confirm Target block must be unlocked before issuing the BEFP Setup and Confirm commands.
Programming
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired.
Buffer Alignment WA0 must align with the start of an array buffer boundary. 1
Table 11: BEFP Considerations
Parameter/Issue Requirement Notes
Cycling For optimum performance, cycling must be limited below 50 erase cycles per block. 1
Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block. 2
Suspend BEFP cannot be suspended.
Programming the flash
memory array Programming to the flash memory array can occur only when the buffer is full. 3
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P33-65nm
8.3.3 BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7
cleared indicates the device is busy and the BEFP program/verify phase is activated.
SR.0 indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 512 words. During the buffer-loading sequence, data is
stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the buffer is full. If the
number of words is less than 512, the remaining buffer locations must be filled with
0xFFFF.
Caution: The buffer must be completely filled for programming to occur. Supplying an
address outside of the current block's range during a buffer-fill sequence
causes the algorithm to exit immediately. Any data previously loaded into the
buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the BEFP
algorithm will be aborted and the program fails and (SR.4) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR.0 to determine when the buffer
program sequence completes. SR.0 cleared indicates that all buffer data has been
transferred to the flash array; SR.0 set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write
cycles should be issued to the device until SR.0 = 0 and the device is ready for the next
buffer fill.
Note: Any spurious writes are ignored after a buffer fill operation and when internal program
is proceeding.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
8.3.4 BEFP Exit Phase
When SR.7 is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any valid command can be issued to the device.
8.4 Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
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Datasheet Feb 2010
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program operation that is running during an erase suspend can be suspended to
perform a read operation (see Figure 31, “Program Suspend/Resume Flowchart” on
page 74).
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in Section 15.5, “Program and Erase Characteristics” on page 60.
To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.5 Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see Figure 31, “Program Suspend/
Resume Flowchart” on page 74).
8.6 Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If
VPP is at or below VPPLK, programming operations halt and SR.3 is set indicating a VPP-
level error. Block lock registers are not affected by the voltage level on VPP; they may
still be programmed and read, even if VPP is less than VPPLK.
Figure 8: Example VPP Supply Connections
• Factory Programming with VPP = VPPH
• Complete write/Era se Protecti on when VPP ≤ VPPLK
VCC
VPP
VCC
VPP
• Low Voltage and Factory Programming
• Low-volta ge Pr ogramming only
• Logic Contr ol of Device Protec tion
VCC
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
VCC
VPP
≤ 10K Ω
VPP
VCC VCC
PROT #
VCC
VPP=VPPH
VCC
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P33-65nm
9.0 Erase Operation
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
9.1 Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the
address of the block to be erased (see Section 6.2, “Device Command Bus Cycles” on
page 20). Next, the Block Erase Confirm command is written to the address of the
block to be erased. If the device is placed in standby (CE# deasserted) during an erase
operation, the device completes the erase operation before entering standby. VPP must
be above VPPLK and the block must be unlocked (see Figure 34, “Block Erase Flowchart”
on page 77).
During a block erase, the WSM executes a sequence of internally-timed events that
conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones”. Memory array block that are ones can be changed to zeros
only by programming the block.
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR.0 indicates whether the addressed block is erasing. Status
Register bit SR.7 is set upon erase completion.
Status Register bit SR.7 indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR.5 indicates an erase
failure if set. SR.3 set would indicate that the WSM could not perform the erase
operation because VPP was outside of its acceptable limits. SR.1 set indicates that the
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
9.2 Blank Check
The Blank Check operation determines whether a specified main block is blank (i.e.
completely erased). Without Blank Check, Block Erase would be the only other way to
ensure a block is completely erased. Blank Check is especially useful in the case of
erase operation interrupted by power loss event.
Blank check can apply to only one block at a time, and no operations other than Status
Register Reads are allowed during Blank Check (e.g. reading array data, program,
erase etc). Suspend and resume operations are not supported during Blank Check, nor
is Blank Check supported during any suspended operations.
Blank Check operations are initiated by writing the Blank Check Setup command to the
block address. Next, the Check Confirm command is issued along with the same block
address. When a successful command sequence is entered, the device automatically
enters the Read Status State. The WSM then reads the entire specified block, and
determines whether any bit in the block is programmed or over-erased.
The status register can be examined for Blank Check progress and errors by reading
any address within the block being accessed. During a blank check operation, the
Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status
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30 Order Number: 208043-04
Register indicates a ready status (SR.7 = 1). The Status Register should be checked for
any errors, and then cleared. If the Blank Check operation fails, which means the block
is not completely erased, the Status Register bit SR.5 will be set (“1”). CE# or OE#
toggle (during polling) updates the Status Register.
After examining the Status Register, it should be cleared by the Clear Status Register
command before issuing a new command. The device remains in Status Register Mode
until another command is written to the device. Any command can follow once the
Blank Check command is complete.
9.3 Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 36, “Erase Suspend/Resume Flowchart” on page 79).
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Section 15.5, “Program and Erase Characteristics” on page 60.
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at a valid level, and WP# must remain unchanged
while in erase suspend. If RST# is asserted, the device is reset.
9.4 Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears SR[7,6]. This command can be written to any address. If status
register error bits are set, the Status Register should be cleared before issuing the next
instruction. RST# must remain deasserted.
9.5 Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP is at or below VPPLK, erase operations halt and SR.3 is set indicating a VPP-level
error.
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P33-65nm
10.0 Security
The device features security modes used to protect the information stored in the flash
memory array. The following sections describe each security mode in detail.
10.1 Block Locking
Individual instant block locking is used to protect user code and/or data within the flash
memory array. All blocks power up in a locked state to protect array data from being
altered during power transitions. Any block can be locked or unlocked with no latency.
Locked blocks cannot be programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock
commands. Hardware-controlled security can be implemented using the Block Lock-
Down command along with asserting WP#. Also, VPP data security can be used to
inhibit program and erase operations (see Section 8.6, “Program Protection” on
page 28 and Section 9.5, “Erase Protection” on page 30).
10.1.1 Lock Block
To lock a block, issue the Block Lock Setup command. The next command must be the
Block Lock command issued to the desired block’s address (see Section 6.2, “Device
Command Bus Cycles” on page 20 and Figure 35, “Block Lock Operations Flowchart” on
page 78). If the Configure Read Configuration Register command is issued after the
Block Lock Setup command, the device configures the RCR instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block
lock bits may be modified and/or read even if VPP is at or below VPPLK.
10.1.2 Unlock Block
The Block Unlock command is used to unlock blocks (see Section 6.2, “Device
Command Bus Cycles” on page 20). Unlocked blocks can be read, programmed, and
erased. Unlocked blocks return to a locked state when the device is reset or powered
down. If a block is in a lock-down state, WP# must be deasserted before it can be
unlocked (see Figure 9, “Block Locking State Diagram” on page 32).
10.1.3 Lock-Down Block
A locked or unlocked block can be locked-down by writing the Block Lock-Down
command sequence (see Section 6.2, “Device Command Bus Cycles” on page 20).
Blocks in a lock-down state cannot be programmed or erased; they can only be read.
However, unlike locked blocks, their locked state cannot be changed by software
commands alone. A locked-down block can only be unlocked by issuing the Block
Unlock command with WP# deasserted. To return an unlocked block to locked-down
state, a Block Lock-Down command must be issued prior to changing WP# to VIL.
Locked-down blocks revert to the locked state upon reset or power up the device (see
Figure 9, “Block Locking State Diagram” on page 32).
10.1.4 Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 7.2, “Read Device Identifier” on page 22). Data bits DQ[1:0] display the
addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the
addressed block’s lock-down bit.
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Note: LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; LK/01h: Lock Command; LK/2Fh: Lock-Down Command.
10.1.5 Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR[7,6] are set, indicating the device is suspended
and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock
Block, or Lock-Down Block produces a command sequence error and set Status
Register bits SR[4,5]. If a command sequence error occurs during an erase suspend,
SR[4,5] remains set, even after the erase operation is resumed. Unless the Status
Register is cleared using the Clear Status Register command before resuming the erase
operation, possible erase errors may be masked by the command sequence error.
If a block is locked or locked-down during an erase suspend of the same block, the lock
status bits change immediately. However, the erase operation completes when it is
resumed. Block lock operations cannot occur during a program suspend. See Appendix
A, “Write State Machine” on page 82, which shows valid commands during an erase
suspend.
Figure 9: Block Locking State Diagram
[000] [001]
[011]
[111]
[101]
[110]
[100]
LK/
D0h LK/
01h
LK/
2Fh
LK/2Fh
LK/
D0h LK/
01h or 2Fh
LK/
D0h LK/
01h
LK/
2Fh LK/
2Fh
PGM/ERASE
ALLOWED PGM/ERASE
PREVENTED
WP# = VIL = 0
WP# = VIH = 1
Power-Up/
Re s e t De fa u l
t
Power-Up/
R e se t D e fau lt
Locked-down
Locked-down
is disabled by
WP# = VIH
V ir tu a l lo c k-
down
Any Lock
commands W P # toggle
WP# toggle
[010]
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P33-65nm
10.2 Selectable OTP Blocks
P33-65nm provides the backward compatible One Time Programming permanent block
lock security feature. Blocks from the main array can be optionally configured as OTP.
Ask your local Numonyx Sales representative for details about these selectable OTP
implementations.
10.3 Password Access
The Password Access is a security enhancement offered on P33-65nm device. This
feature protects information stored in array blocks by preventing content alteration or
reads until a valid 64-bit password is received. The Password Access may be combined
with Flexible block blocking to create a multi-tiered solution.
Please contact your Numonyx Sales for further details concerning the Password Access.
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11.0 Register
When non-array reads are performed in asynchronous page mode only the first data is
valid and all subsequent data are undefined. When a non-array read operation occurs
as synchronous burst mode, the same word of data requested will be output on
successive clock edges until the burst length requirements are satisfied.
11.1 Status Register (SR)
The Status Register provides the ready/busy information of the device, as well as the
error information about the program, erase, VPP and block-locked operations.
Please refer to Section 7.4, “Read Status Register” on page 23.
Please refer to Section 7.5, “Clear Status Register” on page 23.
Notes:
1. Always clear the Status Register prior to resuming erase operations. It avoids Status Register ambiguity when issuing
commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register
contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible
errors during the erase operation cannot be detected via the Status Register because it contains the previous error status
2. BEFP mode is only valid in array blocks.
Table 12: Status Register Description
Status Register (SR) Default Value = 0x80
Device Write
Status
Erase
Suspend
Status
Erase Status Program
Status VPP Status
Program
Suspend
Status
Block-Locked
Status
BEFP
Write
Status
DWS ESS ES PS VPPS PSS BLS BWS
76543210
Bit Name Description
7 Device Write Status (DWS) 0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
6 Erase Suspend Status (ESS) 0 = Erase suspend not in effect.
1 = Erase suspend in effect.
5Erase Status
(ES)
Command
Sequence
Error
SR.5 SR.4 Description
4Program
Status (PS)
0
0
1
1
0
1
0
1
Program or Erase operation successful.
Program error - operation aborted.
Erase error - operation aborted.
Command sequence error - command aborted.
3 VPP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation.
1 = VPP ≤ VPPLK during program or erase operation.
2Program Suspend Status
(PSS)
0 = Program suspend not in effect.
1 = Program suspend in effect.
1Block-Locked Status (BLS)
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
0BEFP Write Status (BWS)
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.
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P33-65nm
11.2 Read Configuration Register (RCR)
The RCR is a 16-bit read/write register used to select the read mode (synchronous or
asynchronous), and to configure synchronous burst characteristics of the device. To
modify RCR settings, use the Configure Read Configuration Register command (see
Section 6.2, “Device Command Bus Cycles” on page 20).
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 7.2, “Read Device Identifier” on page 22).
Upon power-up or exit from reset, the RCR defaults to asynchronous mode.
The RCR is shown in Ta b l e 1 3 . The following sections describe each RCR bit function.
Table 13: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode Latency Count WAIT
Polarity RES WAIT
Delay
Burst
Seq
CLK
Edge RES RES Burst
Wrap Burst Length
RM LC[3:0] WP RWD BS CE R R BW BL[2:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name Description
15 Read Mode (RM) 0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
14:11 Latency Count (LC[3:0])
0010 =Code 2
0011 =Code 3
0100 =Code 4
0101 =Code 5
0110 =Code 6
0111 =Code 7
1000 =Code 8
1001 =Code 9
1010 =Code 10
1011 =Code 11
1100 =Code 12
1101 =Code 13
1110 =Code 14
1111 =Code 15 (default)
(Other bit settings are reserved)
10 WAIT Polarity (WP) 0 =WAIT signal is active low (default)
1 =WAIT signal is active high
9 Reserved (R) Default “0”, Non-changeable
8 WAIT Delay (WD) 0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
7Burst Sequence (BS) Default “0”, Non-changeable
6Clock Edge (CE) 0 = Falling edge
1 = Rising edge (default)
5:4 Reserved (R) Reserved bits should be cleared (0)
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11.2.1 Read Mode (RCR.15)
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
11.2.2 Latency Count (RCR[14:11])
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 10 shows the data output latency for the different
settings of LC. The maximum Latency Count for P33 would be Code 4 based on the Max
clock frequency specification of 52 MHz, and there will be zero WAIT States when
bursting within the word line. Please also refer to Section 11.2.3, “End of Word Line
(EOWL) Considerations” on page 38 for more information on EOWL.
Refer to Table 14, “LC and Frequency Support” on page 37 for Latency Code Settings.
3Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0 Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Table 13: Read Configuration Register Description (Sheet 2 of 2)
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P33-65nm
Figure 10: First-Access Latency Count
Table 14: LC and Frequency Support
Latency Count Settings Frequency Support (MHz)
3≤ 40
4≤ 52
Code 1
(Reserved
Code 6
Code 5
Code 4
Code 3
Code 2
C ode 0 (Reserved)
Code 7
Valid
Address
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output
Valid
Output
Address [A]
ADV# [V]
D
Q15-0 [D /Q]
CLK [C]
D
Q15-0 [D /Q]
D
Q15-0 [D /Q]
D
Q15-0 [D /Q]
D
Q15-0 [D /Q]
D
Q15-0 [D /Q]
D
Q15-0 [D /Q]
D
Q15-0 [D /Q]
P33-65nm
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11.2.3 End of Word Line (EOWL) Considerations
The delay may occur when a burst sequence access crosses a 16-word boundary. That
is, A[4:1] of start address does not equal 0x0. Figure 12, “End of Wordline Timing
Diagram” on page 38 illustrates the end of wordline WAIT state(s), which occur after
the first 16-word boundary is reached. The number of data words and the number of
WAIT states is summarized in Table 15, “End of Wordline Data and WAIT state
Comparison” on page 39 for both P33-130nm and P33-65nm devices.
Figure 11: Example Latency Count Setting Using Code 3
CLK
CE#
ADV#
A[MAX:0]
D[15:0]
tData
Code 3
Address
Data
012
34
R103
High-Z
A[MAX:1]
Figure 12: End of Wordline Timing Diagram
A
[Max:1]
ADV#
OE#
WAIT
D
Q[15:0] Data Data Data
EOWL
CLK
Latency C ount
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P33-65nm
Table 15: End of Wordline Data and WAIT state Comparison
11.2.4 WAIT Polarity (RCR.10)
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low
(default). WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted, RST# deasserted).
11.2.5 WAIT Delay (RCR.8)
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
11.2.6 Burst Sequence (RCR.7)
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Ta ble 1 7 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Latency Count P33-130nm P33-65nm
Data States WAIT States Data States WAIT States
1 Not Supported Not Supported Not Supported Not Supported
2 4 0 to 1 Not Supported Not Supported
3 4 0 to 2 16 0 to 2
4 4 0 to 3 16 0 to 3
5 4 0 to 4 16 0 to 4
6 4 0 to 5 16 0 to 5
7 4 0 to 6 16 0 to 6
8
Not Supported Not Supported
16 0 to 7
916 0 to 8
10 16 0 to 9
11 16 0 to 10
12 16 0 to 11
13 16 0 to 12
14 16 0 to 13
15 16 0 to 14
Table 16: WAIT Functionality Table
Condition WAIT Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ High-Z 1
CE# =’0’, OE# = ‘0’ Active 1
Synchronous Array Reads Active 1
Synchronous Non-Array Reads Active 1
All Asynchronous Reads Deasserted 1
All Writes High-Z 1,2
Notes:
1. Active: WAIT is asserted until data becomes valid, then deasserts.
2. When OE# = VIH during writes, WAIT = High-Z.
P33-65nm
Datasheet Feb 2010
40 Order Number: 208043-04
11.2.7 Clock Edge (RCR.6)
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
11.2.8 Burst Wrap (RCR.3)
The Burst Wrap (BW) bit determines whether 4, 8, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries.
When BW is set, burst wrapping does not occur (default). When BW is cleared, burst
wrapping occurs.
Table 17: Burst Sequence Word Ordering
Start
Addr.
(DEC)
Burst
Wrap
(RCR.3)
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] = 0b001)
8-Word Burst
(BL[2:0] = 0b010)
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-…
2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-…
3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-…
40 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10…
50 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3-
45-6-7-8-9-10-11…
60 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2-
3-4-5 6-7-8-9-10-11-12-…
70 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3-
4-5-6 7-8-9-10-11-12-13…
…
…
…
…
…
…
14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-
…
15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-
…
…
…
…
…
…
…
0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-…
2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-…
3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-…
41 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10…
51 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11…
61 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-…
71 7-8-9-10-11-12-13-14 7-8-9-10-11…21-22 7-8-9-10-11-12-13…
…
…
…
…
…
…
14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-
…
15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-
…
Datasheet Feb 2010
41 Order Number:208043-04
P33-65nm
11.2.9 Burst Length (RCR[2:0])
The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or
continuous word.
Continuous burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 17, “Burst Sequence Word Ordering” on page 40). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
11.3 One-Time Programmable (OTP) Registers
The device contains 17 one-time programmable (OTP) registers that can be used to
implement system security measures and/or device identification. Each OTP register
can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. Once programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see Figure 13,
“OTP Register Map” on page 42).
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated OTP Register can only be read; it can no longer be
programmed. Each OTP Register can be accessed multiple times to program individual
bits, as long as the register remains unlocked. Additionally, because the Lock Register
bits themselves are OTP, when programmed, Lock Register bits cannot be erased.
Therefore, when a OTP Register is locked, it cannot be unlocked.
P33-65nm
Datasheet Feb 2010
42 Order Number: 208043-04
.
11.3.1 Reading the OTP Registers
The OTP Registers can be read from OTP-RA address. To read the OTP Register, first
issue the Read Device Identifier command at OTP-RA address to place the device in the
Read Device Identifier state (see Section 6.2, “Device Command Bus Cycles” on
page 20). Next, perform a read operation using the address offset corresponding to the
register to be read. Table 8, “Device Identifier Information” on page 22 shows the
address offsets of the OTP Registers and Lock Registers. OTP register and Lock Register
data is read 16 bits at a time.
11.3.2 Programming the OTP Registers
To program an OTP Registers, first issue the Program OTP Register command at the
device base address plus the offset of the desired OTP Register location (See Figure 13,
“OTP Register Map” on page 42). Next, write the desired OTP Register data to the same
OTP Register address. See Section 6.2, “Device Command Bus Cycles” on page 20.
Figure 13: OTP Register Map
0x89 Lo ck Register 1
15 14 13 12 11 10 9876543210
0x102
0x109
0x8A
0x91
128-bit OTP Register 16
(User-Programmable)
128-bit OTP Register 1
(User-Programmable)
0x88
0x85
64-bit Segment
(User-Programmable)
0x84
0x81
0x80 Lock Register 0
64-bit Segment
(Factory-Programmed)
15 14 13 12 11 10 9876543210
128-Bit OTP Register 0
Datasheet Feb 2010
43 Order Number:208043-04
P33-65nm
The device programs the 64-bit and Sixteen 128-bit user-programmable Protection
Registers data 16 bits at a time (see Figure 37, “OTP Register Programming Flowchart”
on page 80). Issuing the Program OTP Register command outside of the OTP Register’s
address space causes a program error (SR.4 set). Attempting to program a locked OTP
Register causes a program error (SR.4 set) and a lock error (SR.1 set).
Note: When programming the OTP bits in the OTP registers for a Top Parameter Device, the
upper address A[Max:17] must also be driven high (VIH) for TSOP and Easy BGA
packages.
11.3.3 Locking the OTP Registers
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock a OTP Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register
data (see Section 6.2, “Device Command Bus Cycles” on page 20). The physical
addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These
addresses are used when programming the lock registers (see Ta bl e 8, “ De v i ce
Identifier Information” on page 22).
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at
Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1
of Lock Register 0 can be programmed by the user to lock the upper half of the first
128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to
be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each
bit of Lock Register 1 corresponds to a specific 128-bit OTP Registers; e.g.,
programming a bit in LR1.0 locks the corresponding OTP Register 1.
Caution: After being locked, the OTP Registers cannot be unlocked.
P33-65nm
Datasheet Feb 2010
44 Order Number: 208043-04
12.0 Power and Reset Specifications
12.1 Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2 Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 18: Power and Reset
Num Symbol Parameter Min Max Unit Notes
P1 tPLPH RST# pulse width low 100 - ns 1,2,3,4
P2 tPLRH
RST# low to device reset during erase - 25
µs
1,3,4,7
RST# low to device reset during program - 25 1,3,4,7
P3 tVCCPH VCC Power valid to RST# de-assertion (high) 300 - 1,4,5,6
Notes:
1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if tPLPH is < tPLPH Min, but this is not guaranteed.
3. Not applicable if RST# is tied to VCC.
4. Sampled, but not 100% tested.
5. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
6. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
7. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
Datasheet Feb 2010
45 Order Number:208043-04
P33-65nm
12.3 Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are: 1) standby current levels; 2) active current levels;
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
de-coupling capacitor selection suppress transient voltage peaks.
Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power
connection should have a 0.1 µF ceramic capacitor to ground. High-frequency,
inherently low-inductance capacitors should be placed as close as possible to package
leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
Figure 14: Reset Operation Waveforms
(
A) Reset during
read mode
(B) Reset during
program or block erase
P1
≤
P2
(C) Reset during
program or block erase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-up to
RST# high
P1 R5
P2
P3
P2 R5
R5
P33-65nm
Datasheet Feb 2010
46 Order Number: 208043-04
13.0 Maximum Ratings and Operating Conditions
13.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the Absolute Maximum Ratings may cause permanent
damage. These are stress ratings only.
Table 19: Absolute Maximum Ratings
Parameter Maximum Rating Notes
Temperature under bias
Easy BGA –40°C to +85°C -
TSOP 0°C to +85°C 5
Storage temperature –65°C to +125°C -
Voltage on any signal (except VCC, VPP and VCCQ) –0.5V to +4.1V 1
VPP voltage –0.2V to +10.0V 1,2,3
VCC voltage –0.2V to +4.1V 1
VCCQ voltage –0.2V to +4.1V 1
Output short circuit current 100mA 4
Notes:
1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5V on input/output signals and –0.2V on
VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0V for periods less than 20ns. Maximum DC
voltage on VCC is VCC + 0.5V, which, during transitions, may overshoot to VCC + 2.0V for periods less than 20ns.
Maximum DC voltage on input/output signals and VCCQ is VCCQ + 0.5V, which, during transitions, may overshoot to
VCCQ + 2.0V for periods less than 20ns.
2. Maximum DC voltage on VPP may overshoot to +11.5V for periods less than 20ns.
3. Program/erase voltage is typically 2.3V – 3.6V. 9.0V can be applied for 80 hours maximum total, to any blocks for
1000 cycles maximum. 9.0V program/erase voltage may reduce block cycling capability.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. The full temperature range of -40°C to +85°C will be applied if customer doesn’t use synchronous mode read and page
mode read in the real application.
Datasheet Feb 2010
47 Order Number:208043-04
P33-65nm
13.2 Operating Conditions
Note: Operation beyond the Operating Conditions is not recommended and extended
exposure beyond the Operating Conditions may affect device reliability.
Table 20: Operating Conditions
Symbol Parameter Min Max Unit Notes
TCOperating Temperature
Easy BGA –40 +85
°C 1, 3
TSOP 0 +85
VCC VCC Supply Voltage 2.3 3.6
V
-
VCCQ I/O Supply Voltage
CMOS inputs
Easy BGA 2.3 3.6 -
TSOP 2.3 3.0 3
TTL inputs
Easy BGA 2.4 3.6 -
TSOP 2.4 3.0 3
VPPL VPP Voltage Supply (Logic Level) 1.5 3.6
2
VPPH Buffered Enhanced Factory Programming VPP 8.5 9.5
tPPH Maximum VPP Hours VPP = VPPH -80Hours
Block
Erase
Cycles
Array Blocks
VPP = VPPL 100,000 -
Cycles
VPP = VPPH - 1,000
Notes:
1. TC = Case Temperature.
2. In typical operation VPP program voltage is VPPL.
3. The full temperature range of -40°C to +85°C, full VCCQ range of 2.3V to 3.6V with CMOS inputs or full VCCQ range of
2.4V to 3.6V with TTL inputs will be applied if customer doesn’t use synchronous mode read and page mode read in the
real application.
P33-65nm
Datasheet Feb 2010
48 Order Number: 208043-04
14.0 Electrical Specifications
14.1 DC Current Characteristics
Table 21: DC Current Characteristics (Sheet 1 of 2)
Sym
Parameter
Easy BGA
CMOS
Inputs
(VCCQ =
2.3 V - 3.6
V)
TTL Inputs
(VCCQ =
2.4 V - 3.6
V)
Unit Test Conditions Notes
TSOP
CMOS
Inputs
(VCCQ =
2.3 V - 3.0
V)
TTL Inputs
(VCCQ =
2.4 V - 3.0
V)
-Typ Max Typ Max
ILI
Input Load Current - ±1 - ±2
µA
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VCCQ or VSS 1,6
2-Gbit - ±2 - ±4
ILO
Output Leakage Current - ±1 - ±10
µA
VCC = VCC Max
VCCQ = VCCQ Max
VIN = VCCQ or VSS
DQ[15:0], WAIT 2-Gbit - ±2 - ±20
ICCS,
ICCD
VCC Standby,
Power-Down
512-Mbit 70 225 70 225
µA
VCC = VCC Max
VCCQ = VCC Max
CE# =VCCQ
RST# = VCCQ (for ICCS)
RST# = VSS (for ICCD)
WP# = VIH
1,2
1-Gbit 75 240 75 240
2-Gbit 150 480 150 480
ICCR
Average
VCC
Read
Current
Asynchronous Single-
Word f = 5 MHz (1 CLK) 26 31 26 31 mA 16-Word
Read
VCC = VCCMax
CE# = VIL
OE# = VIH
Inputs: VIL or
VIH
1
Page-Mode Read
f = 13 MHz (17 CLK) 12 16 12 16 mA 16-Word
Read
Synchronous Burst
f = 52 MHz, LC=4
19 22 19 22 mA 8-Word Read
16 18 16 18 mA 16-Word
Read
21 24 21 24 mA Continuous
Read
ICCW,
ICCE
VCC Program Current,
VCC Erase Current
35 50 35 50
mA
VPP = VPPL, Pgm/Ers in progress 1,3,5
35 50 35 50 VPP = VPPH, Pgm/Ers in progress 1,3,5
ICCWS,
ICCES
VCC Program
Suspend Current,
VCC Erase
Suspend Current
512-Mbit 70 225 70 225
µA CE# = VCCQ; suspend in
progress 1,3,41-Gbit 75 240 75 240
2-Gbit 75 240 75 240
Ipps VPP Standby Current
512-Mbit 0.2 5 0.2 5
µA VPP = VPPL in Stanby mode 1,3,7 1-Gbit 0.2 5 0.2 5
2-Gbit 0.4 10 0.4 10
IPPWS,
IPPES
VPP Program Suspend Current,
VPP Erase Suspend Current 0.2 5 0.2 5 µA VPP = VPPL, suspend in progress 1,3,7
IPPR VPP Read 2 15 2 15 µA VPP = VPPL 1,3
IPPW VPP Program Current
0.05 0.10 0.05 0.10
mA
VPP = VPPL, program in progress
3
0.05 0.10 0.05 0.10 VPP = VPPH, program in progress
Datasheet Feb 2010
49 Order Number:208043-04
P33-65nm
14.2 DC Voltage Characteristics
IPPE VPP Erase Current
0.05 0.10 0.05 0.10
mA
VPP = VPPL, erase in progress
3
0.05 0.10 0.05 0.10 VPP = VPPH, erase in progress
IPPBC VPP Blank Check
0.05 0.10 0.05 0.10
mA
VPP = VPPL, erase in progress
3
0.05 0.10 0.05 0.10 VPP = VPPH, erase in progress
Notes:
1. All currents are RMS unless noted. Typical values at typical VCC, TC = +25 °C.
2. ICCS is the average current measured over any 5ms time interval 5µs after CE# is deasserted.
3. Sampled, not 100% tested.
4. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.
5. ICCW
, ICCE measured over typical or max times specified in Section 15.5, “Program and Erase
Characteristics” on page 60.
6. if VIN > VCC the input load current increases to 10µA max.
7. the IPPS,IPPWS,IPPES Will increase to 200µA when VPP/WP# is at VPPH.
Table 22: DC Voltage Characteristics
Sym Paramet
er
Easy BGA CMOS Inputs
(VCCQ = 2.3 V – 3.6 V)
TTL Inputs (1)
(VCCQ = 2.4 V – 3.6 V)
Unit Test Conditions Notes
TSOP CMOS Inputs
(VCCQ = 2.3 V – 3.0 V)
TTL Inputs (1)
(VCCQ = 2.4 V – 3.0 V)
-MinMaxMinMax
VIL Input Low Voltage -0.5 0.4 -0.5 0.6 V
2
VIH Input High Voltage VCCQ – 0.4 VCCQ + 0.5 2.0 VCCQ + 0.5 V
VOL Output Low Voltage - 0.2 - 0.2 V
VCC = VCC Min
VCCQ = VCCQ Min
IOL = 100 µA
-
VOH Output High Voltage VCCQ – 0.2 - VCCQ – 0.2 - V
VCC = VCC Min
VCCQ = VCCQ Min
IOH = –100 µA
-
VPPLK VPP Lock-Out Voltage - 0.4 - 0.4 V 3
VLKO VCC Lock Voltage 1.5 - 1.5 - V -
VLKO
Q
VCCQ Lock Voltage 0.9 - 0.9 - V -
Notes:
1. Synchronous read mode is not supported with TTL inputs.
2. VIL can undershoot to –1.0 V for duration of 2ns or less , overshoot to VCCQ + 1.0 V for durations of 2ns or less.
3. VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
Table 21: DC Current Characteristics (Sheet 2 of 2)
Sym
Parameter
Easy BGA
CMOS
Inputs
(VCCQ =
2.3 V - 3.6
V)
TTL Inputs
(VCCQ =
2.4 V - 3.6
V)
Unit Test Conditions Notes
TSOP
CMOS
Inputs
(VCCQ =
2.3 V - 3.0
V)
TTL Inputs
(VCCQ =
2.4 V - 3.0
V)
-Typ Max Ty p Max
P33-65nm
Datasheet Feb 2010
50 Order Number: 208043-04
15.0 AC Characteristics
15.1 AC Test Conditions
Note: AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input
rise and fall times (10% to 90%) < 5ns. Worst-case speed occurs at VCC = VCCMin.
Notes:
1. See the following table for component values.
2. Test configuration component value for worst-case speed conditions.
3. CL includes jig capacitance.
.
Figure 15: AC Input/Output Reference Waveform
Figure 16: Transient Equivalent Testing Load Circuit
IO_REF.WMF
Input V
CCQ
/2 V
CCQ
/2 Output
V
CCQ
0V
Test Points
Device
Under Test Ou
t
CL
Table 23: Test Configuration Component Value for Worst-Case Speed Conditions
Test Configuration CL (pF)
VCCQ Min Standard Test 30
Datasheet Feb 2010
51 Order Number:208043-04
P33-65nm
15.2 Capacitance
Figure 17: Clock Input AC Waveform
Table 24: Capacitance
Sym Parameter Signals Min Typ Max Unit Condition
CIN Input Capacitance
Address, Data, CE#,
WE#, OE#, RST#,
CLK, ADV#, WP#
512-Mbit 3 7 8
pF
Typ temp = 25 °C,
Max temp = 85 °C,
VCC = (0 V - 3.6 V),
VCCQ = (0 V - 3.6 V)
1-Gbit 4 8 9
2-Gbit 6 16 18
COUT Output Capacitance Data, WAIT
512-Mbit 3 5 6
1-Gbit 3 5 6
2-Gbit 6 10 12
Note: Sampled, not 100% tested.
CLK [C]
V
IH
V
IL
R203R202
R201
CLKINPUT.WMF
P33-65nm
Datasheet Feb 2010
52 Order Number: 208043-04
15.3 AC Read Specifications
Table 25: AC Read Specifications - (Sheet 1 of 2)
Num Symbol Parameter Min Max Unit Notes
Asynchronous Specifications
R1 tAVAV Read cycle time
Easy BGA 95 - ns -
TSOP 105 ns -
R2 tAVQV Address to output valid
Easy BGA - 95 ns -
TSOP 105 ns -
R3 tELQV CE# low to output valid
Easy BGA - 95 ns -
TSOP 105 ns -
R4 tGLQV OE# low to output valid - 25 ns 1,2
R5 tPHQV RST# high to output valid - 150 ns 1
R6 tELQX CE# low to output in low-Z 0 - ns 1,3
R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# high to output in high-Z - 20 ns
1,3R9 tGHQZ OE# high to output in high-Z - 15 ns
R10 tOH Output hold from first occurring address, CE# or OE# change 0 - ns
R11 tEHEL CE# pulse width high 17 - ns
1
R12 tELTV CE# low to WAIT valid - 17 ns
R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3
R15 tGLTV OE# low to WAIT valid - 17 ns 1
R16 tGLTX OE# low to WAIT in low-Z 0 - ns
1,3
R17 tGHTZ OE# high to WAIT in high-Z - 20 ns
Latching Specifications
R101 tAVVH Address setup to ADV# high 10 - ns
1
R102 tELVH CE# low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid
Easy BGA - 95 ns
TSOP 105 ns
R104 tVLVH ADV# pulse width low 10 - ns
R105 tVHVL ADV# pulse width high 10 - ns
R106 tVHAX Address hold from ADV# high 9 - ns 1,4
R108 tAPA Page address access - 25 ns
1
R111 tphvh RST# high to ADV# high 30 - ns
Clock Specifications
R200 fCLK CLK frequency
Easy BGA - 52
MHz
1,3,5,6
TSOP - 40
R201 tCLK CLK period
Easy BGA 19.2 - ns
TSOP 25 - ns
R202 tCH/CL CLK high/low time 5 - ns
R203 tFCLK/RCLK CLK fall/rise time 0.3 3 ns
Datasheet Feb 2010
53 Order Number:208043-04
P33-65nm
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Synchronous Specifications(5)
R301 tAVCH/L Address setup to CLK 9 - ns
1,6
R302 tVLCH/L ADV# low setup to CLK 9 - ns
R303 tELCH/L CE# low setup to CLK 9 - ns
R304 tCHQV /
tCLQV
CLK to output valid
Easy BGA - 22 ns
TSOP - 17 ns
R305 tCHQX Output hold from CLK 3 - ns 1,6
R306 tCHAX Address hold from CLK 10 - ns 1,4,6
R307 tCHTV CLK to WAIT valid
Easy BGA - 17 ns
TSOP - 22 ns 1,6
R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1
R312 tCHTX WAIT Hold from CLK 3 - ns 1,6
Notes:
1. See Figure 15, “AC Input/Output Reference Waveform” on page 50 for timing measurements and max
allowable input slew rate.
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst read mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. Synchronous burst read mode is not supported with TTL level inputs.
6. Applies only to subsequent synchronous reads.
Figure 18: Asynchronous Single-Word Read (ADV# Low)
Table 25: AC Read Specifications - (Sheet 2 of 2)
Num Symbol Parameter Min Max Unit Notes
R5
R7
R6
R17R15
R9R4
R8R3
R1
R2 R1
Address [A]
ADV#
CE # [E}
OE# [G]
WA IT [T]
Data [D/Q]
RST# [ P]
P33-65nm
Datasheet Feb 2010
54 Order Number: 208043-04
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Figure 19: Asynchronous Single-Word Read (ADV# Latch)
R10
R7
R6
R17R15
R9R4
R8R3
R106
R101
R105R105
R2 R1
A
ddress [A]
A[4:1][A]
ADV#
CE# [ E}
OE# [G]
WAI T [T]
Da ta [D /Q ]
Figure 20: Asynchronous Page-Mode Read Timing
Valid Addr es s
0 1 2 F
Q1 Q2 Q3 Q16
R108R108R108 R13R6
R9R4
R8R3
R106
R101
R105R105
R10R10R10R10
R2
A
[M ax: 5 ] [A ]
A[4:1]
ADV#
CE# [ E ]
OE# [G]
WAIT [T]
DATA [D/Q]
Datasheet Feb 2010
55 Order Number:208043-04
P33-65nm
.
Notes:
1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Notes:
1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See Section 11.2.3, “End of Word Line (EOWL) Considerations” on
page 38 for more information.
Figure 21: Synchronous Single-Word Array or Non-array Read Timing
Figure 22: Continuous Burst Read, showing an Output Delay Timing
R312
R305R304
R4
R17R307R15
R9R7
R8
R303
R102 R3
R104
R106R101
R104
R105R105
R2
R306R301
CL K [C]
A
ddress [A]
ADV# [V]
CE# [ E]
OE# [G]
WA IT [T]
Data [D/Q ]
R305R305R305R305
R304
R4
R7
R312R307R15
R303
R102 R3
R106
R105R105
R101 R2
R304R304R304R306
R302
R301
CLK [C ]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Da ta [D/Q]
P33-65nm
Datasheet Feb 2010
56 Order Number: 208043-04
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10=0, WAIT asserted low).
15.4 AC Write Specifications
Figure 23: Synchronous Burst-Mode Four-Word Read Timing
Table 26: AC Write Specifications (Sheet 1 of 2)
Num Symbol Parameter Min Max Unit Notes
W1 tPHWL RST# high recovery to WE# low 150 - ns 1,2,3
W2 tELWL CE# setup to WE# low 0 - ns 1,2,3
W3 tWLWH WE# write pulse width low 50 - ns 1,2,4
W4 tDVWH Data setup to WE# high 50 - ns
1,2
W5 tAVWH Address setup to WE# high 50 - ns
W6 tWHEH CE# hold from WE# high 0 - ns
W7 tWHDX Data hold from WE# high 0 - ns
W8 tWHAX Address hold from WE# high 0 - ns
W9 tWHWL WE# pulse width high 20 - ns 1,2,5
W10 tVPWH VPP setup to WE# high 200 - ns
1,2,3,7
W11 tQVVL VPP hold from Status read 0 - ns
W12 tQVBL WP# hold from Status read 0 - ns
1,2,3,7
W13 tBHWH WP# setup to WE# high 200 - ns
W14 tWHGL WE# high to OE# low 0 - ns 1,2,9
W16 tWHQV WE# high to read valid tAVQV + 35 - ns 1,2,3,6,10
Write to Asynchronous Read Specifications
W18 tWHAV WE# high to Address valid 0 - ns 1,2,3,6,8
Latency Count
A
Q0 Q1 Q2 Q3
R307
R10
R304
R305R304
R4
R7
R17R15
R9
R8
R303
R3
R106
R102
R105R105
R101 R2
R306
R302
R301
CLK [C]
A
ddress [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
Datasheet Feb 2010
57 Order Number:208043-04
P33-65nm
Write to Synchronous Read Specifications
W19 tWHCH/L WE# high to Clock valid 19 - ns
1,2,3,6,10W20 tWHVH WE# high to ADV# high 19 - ns
W28 tWHVL WE# high to ADV# low 7 - ns
Write Specifications with Clock Active
W21 tVHWL ADV# high to WE# low - 20 ns
1,2,3,11
W22 tCHWL Clock high to WE# low - 20 ns
Notes:
1. Write timing characteristics during erase suspend are the same as write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
6. tWHVH or tWHCH/L must be met when transiting from a write cycle to a synchronous burst read.
7. VPP and WP# should be at a valid level until erase or program success is determined.
8. This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
9. When doing a Read Status operation following any command that alters the Status Register, W14 is 20ns.
10. Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
11. These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
Figure 24: Write-to-Write Timing
Table 26: AC Write Specifications (Sheet 2 of 2)
Num Symbol Parameter Min Max Unit Notes
W1
W7W4W7W4
W3W9 W3W9W3W3
W6W2W6W2
W8W8 W5W5
A
ddress [A]
CE # [ E }
WE# [W]
OE# [G]
Data [ D/Q]
RS T# [P]
P33-65nm
Datasheet Feb 2010
58 Order Number: 208043-04
Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted.
Figure 25: Asynchronous Read-to-Write Timing
Figure 26: Write-to-Asynchronous Read Timing
Q D
R5
W7
W4R10
R7
R6
R17R15
W6W3W3W2
R9R4
R8R3
W8W5
R1
R2 R1
A
ddress [A]
CE # [E}
OE# [G]
WE# [W]
WAIT [T]
Data [D/Q]
RS T# [P]
D Q
W1
R9 R8
R4
R3
R2
W7W4
R17R15
W14
W18W3W3
R10W6W2
R1R1W8W5
A
ddress [A]
ADV# [V]
CE# [ E}
WE# [W]
OE# [G]
WAIT [T ]
Data [ D/Q]
RST# [ P]
Datasheet Feb 2010
59 Order Number:208043-04
P33-65nm
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low). Clock is
ignored during write operation.
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low).
Figure 27: Synchronous Read-to-Write Timing
Figure 28: Write-to-Synchronous Read Timing
Latency C ount
Q D D
W7R305
R304
R7
R312R307R16
W15
W22
W21
W9
W8 W9W3
W22 W21
W3W2
R8
R4
W6
R11R13
R11
R303
R3
R104R104
R106
R102
R105R105
W18
W5
R101 R2
R306
R302
R301
CLK [C ]
Address [ A]
ADV# [ V]
CE# [ E]
OE# [ G ]
WE#
WAIT [T]
Data [D/Q]
D Q Q
W1
R304
R305R304
R3
W7
W4
R307R15
R4
W20
W19
W18
W3W3
R11 R303
R11
W6
W2
R104 R106
R104
R306W8W5
R302 R301 R2
CLK
A
dd ress [A ]
ADV#
CE# [E}
WE# [W]
OE# [ G]
WAIT [T]
D
ata [D/Q]
RST# [P]
P33-65nm
Datasheet Feb 2010
60 Order Number: 208043-04
15.5 Program and Erase Characteristics
Table 27: Program and Erase Specifications
Num Symbol Parameter
VPPL VPPH
Unit Note
Min Typ Max Min Typ Max
Conventional Word Programming
W200 tPROG/W
Program
Time Single word - 270 456 - 270 456 µs 1
Buffered Programming
W250 tPROG
Program
Time
Aligned 32-Wd, BP time
(32 Words) - 310 716 - 310 716
µs 1
Aligned 64-Wd, BP time
(64 Word) - 310 900 - 310 900
Aligned 128-Wd, BP time
(128 Words) - 375 1140 - 375 1140
Aligned 256-Wd, BP time
(256 Words) - 505 1690 - 505 1690
one full buffer (512
Words) - 900 3016 - 900 3016
Buffered Enhanced Factory Programming
W451 tBEFP/B Program
Single byte n/a n/a n/a - 0.5 -
µs
1,2
W452 tBEFP/Setup BEFP Setup n/a n/a n/a 5 - - 1
Erase and Suspend
W500 tERS/PB Erase Time
32-KByte Parameter - 0.8 4.0 - 0.8 4.0
s
1
W501 tERS/AB 128-KByte Array Block - 0.8 4.0 - 0.8 4.0
W600 tSUSP/P
Suspend
Latency
Program suspend - 25 30 - 25 30
µsW601 tSUSP/E Erase suspend - 25 30 - 25 30
W602 tERS/SUSP Erase to Suspend - 500 - - 500 - 1,3
Blank check
W702 tBC/AB Blank check Array Block - 3.2 - - 3.2 - ms
Notes:
1. Typical values measured at TC = +25°C and nominal voltages. Performance numbers are valid for all speed versions.
Excludes system overhead. Sampled, but not 100% tested.
2. Averaged over entire device.
3. W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
Datasheet Feb 2010
61 Order Number:208043-04
P33-65nm
16.0 Ordering Information
Note: The last random digit is used to cover a combination of packing media, features an specific configuration if necessary.
Note: For leaded package option, please contact your Numonyx sales representative for detail.
Figure 29: Decoder for P33-65nm Products
Table 28: Valid Combinations for P33 Products
512-Mbit 1-Gbit 2-Gbit
PC28F512P33EF* PC28F00AP33EF* PC28F00BP33EF*
PC28F512P33BF* PC28F00AP33BF* -
PC28F512P33TF* PC28F00AP33TF* -
JS28F512P33EF* JS28F00AP33EF* -
JS28F512P33BF* JS28F00AP33BF* -
JS28F512P33TF* JS28F00AP33TF* -
F 5 1 P 3 38S 2J 2
P
roduct Line Designator
28F = Numonyx™ Flash Memory
Package Designator
JS = 56- Lead TSOP, lead -free
PC = 64- Ball Easy BGA, lead-free
D
evic e Density Product Family
P33 = Numonyx™ Axcell™ P33 Flash Memor
y
V
CC
= 2. 3– 3. 6V
V
CCQ
= 2.3– 3.6 V
Pa ramet er Lo cat ion
E = Symmetrical Blocks
T = Top Parameter
B = Bottom Parameter
E
512 = 512-Mbit
00A= 1 -Gbit
F
Device lithography
F = 65nm
00B= 2 -Gbit
for Easy BGA
*
Device Features*
V
CCQ
= 2.3–3.0V for TSOP
P33-65nm
Datasheet Feb 2010
62 Order Number: 208043-04
Appendix A Supplemental Reference Information
A.1 Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple
command-set and control-interface descriptions. This appendix describes the database
structure containing the data returned by a read operation after issuing the Read CFI
command (see Section 6.2, “Device Command Bus Cycles” on page 20). System
software can parse this database structure to obtain information about the flash device,
such as block size, density, bus width, and electrical specifications. The system
software will then know which command set(s) to use to properly perform flash writes,
block erases, reads and otherwise control the flash device.
A.1.1 Query Structure Output
The Query database allows system software to obtain information for controlling the
flash device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical
offset value is the address relative to the maximum bus width supported by the device.
On this family of devices, the Query table device starting address is a 10h, which is a
word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0)
and 00h in the high byte (DQ15-8).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs have 00h on
the upper byte in this mode.
Table 29: Summary of Query Structure Output as a Function of Device and Mode
Device
Hex
Offset
Hex
Code
ASCII
Value
00010: 51 "Q"
Device Addres s es 00011: 52 "R"
00012: 59 "Y"
Datasheet Feb 2010
63 Order Number:208043-04
P33-65nm
A.1.2 Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or database. Ta b l e 3 1 summarizes the structure sub-sections and address
locations.
Table 31: Query Structure
Note:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord).
3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.
A.1.3 Read CFI Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Table 30: Example of Query Structure Output of x16 Devices
Offset Hex Code Value
AX-A1D15-D0
00010h 0051 “Q”
00011h 0052 “R”
00012h 0059 “Y”
00013h P_IDLO PrVendor ID#
00014h P_IDHI
00015h PLO PrVendor TblAdr
00016h PHI
00017h A_IDLO AltVendor ID#
00018h A_IDHI
... ... ...
00001-F h Res e rved Res e rved for vendor- specific information
00010h CF I query i dentifi cati on stri ng Comm and set ID and vendor data offs et
0001B h S ystem interface i nformation Device tim ing & voltage information
00027h Device geom e try definition Flash device layout
P(3)
Prim ary Numonyx- speci fic Extended Query
NOTES:
V endor- defined additional i nform ati on speci fic
to the Pri m ary Vend or Al gorithm
P33-65nm
Datasheet Feb 2010
64 Order Number: 208043-04
Table 32: CFI Identification
Offset Length Description Add. Hex
Code Value
10h 3Query-unique ASCII string “QRY”.
10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
13h 2Primary Vendor command set and control interface ID code.
16-bit ID code for Vendor-specified algorithms.
13:
14:
--01
--00
15h 2Extended Query Table primary algorithm address. 15:
16:
--0A
--01
17h 2Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists.
17:
18:
--00
--00
19h 2Secondary algorithm Extended Query Table address.
0000h means none exists.
19:
1A:
--00
--00
Table 33: System Interface Information
Offset Length Description Add Hex
Code Value
1Bh 1
VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1B: --23 2.3V
1Ch 1
VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
1C: --36 3.6V
1Dh 1
VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1D: --85 8.5V
1Eh 1
VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1E: --95 9.5V
1Fh 1 “n” such that typical single word program time-out = 2n µ-sec 1F: --09 512µs
20h 1 “n” such that typical full buffer write time-out = 2n µ-sec 20: --0A 1024µs
21h 1 “n” such that typical block erase time-out = 2n m-sec 21: --0A 1s
22h 1 “n” such that typical full chip erase time-out = 2n m-sec 22: --00 NA
23h 1 “n” such that maximum word program time-out = 2n times typical 23: --01 1024µs
24h 1 “n” such that maximum buffer write time-out = 2n times typical 24: --02 4096µs
25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --02 4s
26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA
Datasheet Feb 2010
65 Order Number:208043-04
P33-65nm
A.1.4 Numonyx-Specific Extended Query Table
Table 34: Device Geometry Definition
Offset Length Description Add Hex
Code Value
27h 1 “n” such that device size = 2n in number of bytes 27: See Table Below
28h 2
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash device width
capabilities as described in the table:
76543210
_ _ _ _ x64 x32 x16 x8 28: --01 x16
15 14 13 12 11 10 9 8
________29:--00
2Ah 2 “n” such that maximum number of bytes in write buffer = 2n2A: --0A 1024
2B: --00
2Ch 1
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or more contiguous
same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
2C: See Table Below
2D 4
Erase Block Region 1 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
2D: ~30: See Table Below
31h 4
Erase Block Region 2 Information
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
31: ~34: See Table Below
35h 4 Reserved for future erase block region information 35: ~38: See Table Below
Address
512-Mbit 1-Gbit 2-Gbit
Top Bottom Symmetrical Top Bottom Symmetrica Symmetrical
27: --1A --1A --1A --1B --1B --1B --1B
28: --01 --01 --01 --01 --01 --01 --01
29: --00 --00 --00 --00 --00 --00 --00
2A: --0A --0A --0A --0A --0A --0A --0A
2B: --00 --00 --00 --00 --00 --00 --00
2C: --02 --02 --01 --02 --02 --01 --01
2D: --FE --03 --FF --FE --03 --FF --FF
2E: --01 --00 --01 --03 --00 --03 --03
2F: --00 --80 -00 --00 --80 -00 -00
30: --02 --00 --02 --02 --00 --02 --02
31: --03 --FE --00 --03 --FE --00 --00
32: --00 --01 --00 --00 --03 --00 --00
33: --80 --00 --00 --80 --00 --00
34: --00 --02 --00 --00 --02 --00
35:~38: --00 --00 --00 --00 --00 --00
P33-65nm
Datasheet Feb 2010
66 Order Number: 208043-04
A.1.5 Numonyx-Specific Extended Query Table
Table 35: Primary Vendor-Specific Extended Query
Offset
P=10Ah Length Description
(Optional flash features and commands) Add. Hex
Code Value
(P+0)h
3Primary extended query table
Unique ASCII string “PRI”
10A: --50 “P”
(P+1)h 10B: --52 “R”
(P+2)h 10C: --49 “I”
(P+3)h 1 Major version number, ASCII 10D: --31 “1”
(P+4)h 1 Minor version number, ASCII 10E: --35 “5”
(P+5)h 4 Optional feature and command support (1=yes, 0=no) 10F: --E6 -
(P+6)h bits 10-31 are reserved; undefined bits are “0”. If bit 31 110: --01 -
(P+7)h “1”then another 31 bit field of Optional features follows at 111: --00 -
(P+8)h the end of the bit-30 field. - -
512-Mbit, 1-Gbit: 112: --00 -
2-Gbit Bottom Die: 112: --40 -
2-Gbit Top Die: 112: --00 -
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Pagemode read supported bit 7 = 1 Yes
bit 8 Synchronous read supported bit 8 = 1 Yes
bit 9 Simultaneous operations supported bit 9 = 0 No
bit 10 Extended Flash Array Blocks supported bit 10 = 0 No
bit 11 Permanent Block Locking of up to Full Main Array supported bit 11 = 0 Yes
bit 12 Permanent Block Locking of up to Partial Main Array supported bit 12 = 0 No
bit 30 CFI Link(s) to follow - -
512-Mbit, 1-Gbit: bit 30 = 0 No
2-Gbit Bottom Die: bit 30 = 1 Yes
2-Gbit Top Die: bit 30 = 0 No
bit 31 Another "Optional Features" field to follow bit 31 = 0 No
(P+9)h 1
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1-7 reserved; undefined bits are “0”
113: --01 -
bit 0 Program supported after erase suspend bit 0 = 1 Yes
(P+A)h 2 Block status register mask 114: --03 -
(P+B)h bits 2-15 are Reserved; undefined bits are “0” 115: --00 -
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes
bit 4 EFA Block Lock-Bit Status register active bit 4 = 0 No
bit 5 EFA Block Lock-Down Bit Status active bit 5 = 0 No
(P+C)h 1
VCC logic supply highest performance program/erase voltage
bits 0-3 BCD value in 100 mV
bits 4-7 BCD value in volts
116: --30 3.0V
(P+D)h 1
VPP optimum program/erase supply voltage
bits 0-3 BCD value in 100 mV
bits 4-7 HEX value in volts
117: --90 9.0V
Datasheet Feb 2010
67 Order Number:208043-04
P33-65nm
Table 36: OTP Register Information
Offset(1) Length Description Hex
P = 10Ah (Optional flash features and commands) Add. Code Value
(P+E)h 1 118: --02 2
(P+ F)h 4 Protection Field 1: Protection Descripti on 119: --80 80h
(P+10)h This field describes user-available One Time Programmable 11A: --00 00h
(P+11)h (OTP) Protection register bytes. Some are pre-programmed 11B: --03 8 byte
(P+12)h 11C: --03 8 byte
(P+13)h 10 Protection Field 2: Protecti on Description 11D: --89 89h
(P+14)h 11E: --00 00h
(P+15)h 11F: --00 00h
(P+16)h 120: --00 00h
(P+17)h 121: --00 0
(P+18)h bits 40–47 = “n” such that n = factory pgm'd groups (high byte) 122: --00 0
(P+19)h 123: --00 0
(P+1A)h 124: --10 16
(P+1B)h 125: --00 0
(P+1C)h 126: --04 16
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n”
such that
n = user pgm'd groups (low byte)
bi ts 64–71 = “n” such that n = user pgm'd groups (hig h byte)
bi ts 72–79 = “n” such that 2n = user programmable bytes/group
with device-unique serial numbers. Others are user
programmable. B i ts 0–15 point to the Protection register Lock
byte, the section’s first byte. The foll owing bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes J edec-plane physical l ow address
bits 8–15 = Lock/bytes Jedec-plane physical hi gh address
bi ts 16–23 = “n” such that 2n = factory pre-programmed bytes
bi ts 24–31 = “n” such that 2n = user programmable bytes
B i ts 0–31 point to the Protection register physi cal Lock -word
address in the Jed ec-plane.
Follo wing bytes are factory or user-programmable.
bits 32–39 = “n”
such that n
= factory pgm'd groups (low byte)
Number of Protection register fields in JEDEC ID space.
“00h,” i ndicates that 256 protection fields are avail ab l e
P33-65nm
Datasheet Feb 2010
68 Order Number: 208043-04
Table 38: Partition and Erase Block Region Information
Table 37: Burst Read Information
Offset(1) Length Description Hex
P = 10 Ah (Optional flash features and comma nd s) Add. Code Va l ue
(P+1D)h 1 127: --05 32 byte
(P+1E)h 1 128: --04 4
(P+1F)h 1 129: --01 4
(P+20)h 1 Synchronous mode read capabili ty configuration 2 12A: --02 8
(P+21)h 1 Synchronous mode read capabili ty configuration 3 12B : --03 16
(P+22)h 1 Synchronous mode read capabili ty configuration 4 12C: --07 Con t
Page Mode R ead capability
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h ind i cates no
read page buffer.
Synchronous mode read capabili ty configuration 1
Bi ts 3–7 = Reserved
Bi ts 0–2 “n” such that 2n+1 HEX value represents the maximum number of
continuous synchronous reads when the devi ce is configured for its maxi mum
word width. A value of 07h indi cates that the device is capable o f continuo us
linear bursts that will output data until the internal burst counter reaches the end
of the device’s burstable address space. Thi s field’ s 3-bit value can be written
directly to the Read Configuration Register bits 0–2 i f the device is configured
for its ma ximum word width. See offset 28h for word width to determine the
burst data output width.
Number of synchronous mode read configuration fields that follow. 00h
indicates no burst capability.
Offset(1) See tab le belo w
P = 10Ah Description Address
Bottom Top (Optional flash fea tures an d c ommand s) Len Bot Top
(P+23)h (P+23)h
112D:12D:Number of device hardware-partitio n regi ons w ithi n the de vice.
x = 0: a singl e ha rdware partiti on de vice (no fiel ds fol lo w).
x specifies the number of device partiti on regions containin g
one or more contiguou s erase bl ock regio ns.
Datasheet Feb 2010
69 Order Number:208043-04
P33-65nm
Table 39: Partition Region 1 Information (Sheet 1 of 2)
Offset(1) See table below
P = 10Ah Descriptio n Address
Bottom Top (Optiona l flash fea tures and c ommands) Len Bot Top
(P+24)h (P+24)h
Data size of this Parition Region Information field
212E:12E
(P+25)h (P+25)h (# addressable locations, including this field) 12F 12F
(P+26)h (P+26)h Number of identical partitions within the partition region 2 130: 130:
(P+27)h (P+27)h 131: 131:
(P+28)h (P+28)h 1 132: 132:
(P+29)h (P+29)h 1 133: 133:
(P+2A)h (P+2A)h 1 134: 134:
(P+2B)h (P+2B)h 1 135: 135:Types of erase block regions in this Partition Region.
x = 0 = no erase blocki ng; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
block i ng region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (T ype 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations all owed in other partitions while a
partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations all owed in other partitions while a
partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
P33-65nm
Datasheet Feb 2010
70 Order Number: 208043-04
Table 40: Partition Region 1 Information (Sheet 2 of 2)
Offset(1) See table below
P = 10Ah Description Address
Bottom Top (Optional flash features a nd commands) Len Bot Top
(P+2C)h (P+2C)h Partition Region 1 Erase Bl ock Type 1 Information 4 136: 136:
(P+2D)h (P+2D)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition 137: 137:
(P+2E)h (P+2E)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 138: 138:
(P+2F)h (P+2F)h 139: 139:
(P+30)h (P+30)h Partiti on 1 (Erase Block Type 1) 2 13A: 13A:
(P+31)h (P+31)h Block erase cycles x 1000 13B: 13B:
(P+32)h (P+32)h 1 13C: 13C:
(P+33)h (P+33)h 1 13D: 13D:
Partition Region 1 (Erase Block Type 1) Programming Reg ion Information 6
(P+34)h (P+34)h bits 0–7 = x, 2^x = Programming Region aligned size (bytes) 13E: 13E:
(P+35)h (P+35)h bits 8–14 = Reserved; bit 15 = Legacy fl ash operation (ignore 0:7) 13F: 13F:
(P+36)h (P+36)h bits 16–23 = y = Control Mode valid size in bytes 140: 140:
(P+37)h (P+37)h bits 24-31 = Reserved 141: 141:
(P+38)h (P+38)h bits 32-39 = z = Control Mode invalid
size in bytes
142: 142:
(P+39)h (P+39)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) 143: 143:
(P+3A)h (P+3A)h Partit i on Region 1 Erase Block Type 2 Informati on 4 144: 144:
(P+3B)h (P+3B)h bits 0–15 = y, y+1 = # identic al-siz e erase blks in a partition 145: 145:
(P+3C)h (P+3C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 146: 146:
(P+3D)h (P+3D)h 147: 147:
(P+3E)h (P+3E)h Partition 1 (Erase Bl ock Type 2) 2 148: 148:
(P+3F)h (P+3F)h Block erase cycles x 1000 149: 149:
(P+40)h (P+40)h 1 14A: 14A:
(P+41)h (P+41)h 1 14B: 14B:
Partition Region 1 (Erase Block Type 2) Programming Reg ion Information 6
(P+42)h (P+42)h bits 0–7 = x, 2^x = Programming Region aligned size (bytes) 14C: 14C:
(P+43)h (P+43)h bits 8–14 = Reserved; bit 15 = Legacy fl ash operation (ignore 0:7) 14D: 14D:
(P+44)h (P+44)h bits 16–23 = y = Control Mode valid size in bytes 14E: 14E:
(P+45)h (P+45)h bits 24-31 = Reserved 14F: 14F:
(P+46)h (P+46)h bits 32-39 = z = Control Mode invalid
size in bytes
150: 150:
(P+47)h (P+47)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) 151: 151:
Partiti on 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
Partiti on 1 (erase block Type 2) page mode and synchronous mode capabil iti es
defined in Tabl e 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
Partiti on 1 (erase block Type 1) page mode and synchronous mode capabil iti es
defined in Tabl e 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partiti on 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
Datasheet Feb 2010
71 Order Number:208043-04
P33-65nm
Table 41: Partition and Erase Block Region Information
Add.
512-Mbit 1-Gbit 2-Gbit
Top
Parameter
Bottom
Parameter Symm. Top
Parameter
Bottom
Parameter Symm. Symm.
Top Die
Symm.
Bottom Die
12D: --01 --01 --01 --01 --01 --01 --01 --01
12E: --24 --24 --14 --24 --24 --14 --14 --14
12F: --00 --00 --00 --00 --00 --00 --00 --00
130: --01 --01 --01 --01 --01 --01 --01 --01
131: --00 --00 --00 --00 --00 --00 --00 --00
132: --11 --11 --11 --11 --11 --11 --11 --11
133: --00 --00 --00 --00 --00 --00 --00 --00
134: --00 --00 --00 --00 --00 --00 --00 --00
135: --02 --02 --01 --02 --02 --01 --01 --01
136: --FE --03 --FF --FE --03 --FF --FF --FF
137: --01 --00 --01 --03 --00 --03 --03 --03
138: --00 --80 --00 --00 --80 --00 --00 --00
139: --02 --00 --02 --02 --00 --02 --02 --02
13A: --64 --64 --64 --64 --64 --64 --64 --64
13B: --00 --00 --00 --00 --00 --00 --00 --00
13C: --02 --02 --02 --02 --02 --02 --02 --02
13D: --03 --03 --03 --03 --03 --03 --03 --03
13E: --00 --00 --00 --00 --00 --00 --00 --00
13F: --80 --80 --80 --80 --80 --80 --80 --80
140: --00 --00 --00 --00 --00 --00 --00 --00
141: --00 --00 --00 --00 --00 --00 --00 --00
142: --00 --00 --00 --00 --00 --00 --00 --00
143: --80 --80 --80 --80 --80 --80 --80 --80
144: --03 --FE --FF --03 --FE --FF --FF --10
145: --00 --01 --FF --00 --03 --FF --FF --C8
146: --80 --00 --FF --80 --00 --FF --FF --00
147: --00 --02 --FF --00 --02 --FF --FF --00
148: --64 --64 --FF --64 --64 --FF --FF --10
149: --00 --00 --FF --00 --00 --FF --FF --FF
14A: --02 --02 --FF --02 --02 --FF --FF --FF
14B: --03 --03 --FF --03 --03 --FF --FF --FF
14C: --00 --00 --FF --00 --00 --FF --FF --FF
14D: --80 --80 --FF --80 --80 --FF --FF --FF
14E: --00 --00 --FF --00 --00 --FF --FF --FF
14F: --00 --00 --FF --00 --00 --FF --FF --FF
150: --00 --00 --FF --00 --00 --FF --FF --FF
151: --80 --80 --FF --80 --80 --FF --FF --FF
P33-65nm
Datasheet Feb 2010
72 Order Number: 208043-04
Table 42: CFI Link Information (2-Gbit )
Length Description
(Optional Flash features and commands Add. Hex
Code Value
4 CFI Link Field bit definitions
See
Ta b l e 41 ,
“Partition
and Erase
Block
Region
Informatio
n” on
page 71.
Bits 0:9 = Address offset (within 32Mbit segment) of referenced CFI table 144:
Bits 10:27 = nth 32Mbit segment of referenced CFI table 145:
Bits 28:30 = Memory Type 146:
Bit 31 = Another CFI Link field immediately follows 147:
1 CFI Link Field Quantity Subfield definitions 148:
Bits 3:0 = Quantity field (n such that n+1 equals quantity)
Bit 4 = Table & die relative location
Bit 5 = Link Field & Table relative location
Bits 6:7 = Reserved
Datasheet Feb 2010
73 Order Number:208043-04
P33-65nm
A.2 Flowcharts
Figure 30: Word Program Flowchart
Start
Data C ycle
- Address = location to program
- Data = Data to program
Yes
D7 = '1'
?
End
No Suspend
?
No
Yes Errors
?
Yes
No
Error-Handler
User Defined Routine
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
Program Su spend
See Suspend/
Resum e Flowchart
Comm and Cy cle
-Issue Program Com m and
- Addres s = loc atio n to p r o g ram
- Data = 0x40
Che ck Read y Sta tus
- Read Status Register Comm and not req u ire d
- Perform read operation
- Read Ready Status on signal D7
P33-65nm
Datasheet Feb 2010
74 Order Number: 208043-04
Start
Get Next
Target Address
Issue Write to Bu ffe r
Command E8h and
Block Ad dress
Read Status Register
Block Addres s
(not e 7)
Is W SM Ready?
SR. 7 =
1 = Yes
Device
Supports Buffer
Writes?
Set Timeout or
Loop Counter
Timeout
or Count
Expired?
Write Confirm D0h
and Block Addr ess
Another Buffered
Programming?
Yes
No
No
Write Bu ffe r Data
St art Address
X = 0
Yes
0=No
No
Yes
Use Single Word
Programming
Abort Bufferred
Program?
No
X = N?
Write Buffer Data
Block Addres s
X = X + 1
Write to another
Block Addres s
Buffered Program
Aborted
No
YesYes
Write Word Count
Block Ad dress
Notes:
1. Word count values on DQ
0
-DQ
15
are loaded into the Count
register. Count ranges for this device are N=0000h to 01FFh.
2. The device outputs the status register when read.
3. Write Buffer contents will be programmed at the device start
address or destination flas h address.
4. Ali gn the s tart address on a Write Buffer boundary for maximum
programming performance (i.e., A
9
-A
1
of the start address =0).
5. The device aborts the Buffered Program command if the
current address is outside the original block address .
6. The Status register indicates an “improper command
Sequence” if the Buffered Program command is aborted. Follow
this with a Clear Status Register command.
7. The device default state is to output SR data afte r the Buffered
Programming Setup Command (E8h). CE # and OE low drive the
devi ce to update Status Register . It is not allowed to issue 70h to
read SR data after E8h command otherwise 70h would be
counted as Word count.
8. Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to reset
the device to read array mode.
.
.
.
Bus
Operation
Standby
Read
Command
Write Write to
Buffer
Read
(Note 7)
Standby
Comments
Check SR.7
1 = WSM Ready
0 = WSM Busy
Status register Data
CE# and OE# low updates SR
Addr = Block Address
Dat a = E 8H
Addr = Block Address
SR. 7 = Valid
Addr = Block Address
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Write Program
Confirm Data = D0H
Addr = Block Address
Write
(Notes 1, 2 )
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Block Address
Write
(Notes 3, 4 ) Data = Write Bu ffe r Data
Addr = Start Address
Write
(Notes 5, 6 ) Data = Write Bu ffe r Data
Addr = Block Address
Sus pend
Program
Loop
Read Status Register
SR.7 =?
Fu ll Status
Check if Desired
Program Complete
Suspend
Program
1
0
No
Yes
Figure 31: Program Suspend/Resume Flowchart
Read S t at us
Register
SR .7 =
SR.2 =
Read A rray
Data
Program
Completed
Done
Reading
Program
Resumed Rea d Array
Data
0
No
0
Yes
1
1
PROGRAM SUSPEND / RESUME PROCEDURE
Write Program
Resume Data = D0h
Addr = Suspended block (BA)
Bus
Operation Command Comments
Write Program
Suspend Data = B0h
Addr = X
Standby Ch e ck SR.7
1 = WSM ready
0 = WSM busy
Standby Ch e ck SR.2
1 = Program suspended
0 = Program completed
Write Read
Array Data = FFh
A d dr = B lock address t o rea d (B A)
Read Read array data f rom block ot her than
t he one being programmed
Read
Status regi ster data
In itia te a r ea d cycl e to up d a te Status
register
Addr = Suspended block (BA)
PGM_SUS.WM
F
Start
Wri t e B0h
Any Address
Program Suspend
Read Status
Write 70h
Writ e FFh
Any Address
Read Array
Wri t e D0h
Any Address
Program Resume
Write FFh
Read Array
Write Read
Status Data = 70h
Addr = Bl o ck to su sp en d ( BA)
Write 70h
Any Address
Read Status
Any Address
Datasheet Feb 2010
75 Order Number:208043-04
P33-65nm
Figure 32: Buffer Program Flowchart
Start
Get Next
Target Address
Issue Write to Buffer
Command E8h and
Block Address
Read Status Register
Block Address
(note 7)
Is WSM Ready?
SR.7 =
1 = Yes
Device
Supports Buffer
Writes?
Set Timeout or
Loop Counter
Timeout
or C ount
Expired?
Write Confirm D0h
and Block Address
Another Buffered
Programming?
Yes
No
No
Write Buffer Data
Start Address
X = 0
Yes
0=No
No
Yes
Use S ingle Word
Programming
Abort Bufferred
Program?
No
X = N?
Write Buffer Data
Block Address
X = X + 1
Write to another
Block Address
Buffered Program
Aborted
No
YesYes
Write Word Count
Block Address
Notes:
1. Word count values on DQ
0
-DQ
15
are loaded into the Count
register. Count ranges for this devi ce are N=0000h to 01FFh .
2. The devic e outputs the status register when read.
3. Write Buffer contents will be programmed at the device start
addres s or desti nation flash address.
4. Align the start addres s on a Write Buffer boundary for maximum
programming performance (i.e., A
9
-A
1
of the start address =0).
5. The devic e aborts the Buffered Program command if the
current address is outside the original block address .
6. The Status register indicates an “improper command
Sequence” if th e Buffered Program command is aborted. Follow
this with a Cl ear Status Register co m mand.
7. The device defaul t state is to output SR data after the Buffered
Programming Setup Command (E8h).CE# and OE low drive the
device to update Status Register . It is not allowed to issue 70h to
read SR data after E8h command otherwise 70h would be
counted as Word count.
8. Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to reset
the device to read array mode.
.
.
.
Bus
Operation
Standby
Read
Command
Write Write to
Buffer
Read
(Note 7)
Standby
Comments
Ch eck SR.7
1 = WSM Ready
0 = WSM Busy
Status regis ter Data
CE# and OE# low updates SR
Addr = Block Address
Data = E 8H
Addr = Block Address
SR. 7 = Valid
Addr = Block Address
Ch eck SR.7
1 = Device WSM is Busy
0 = Devi ce WS M i s Ready
Write Program
Confirm Data = D0H
Addr = Block Address
Write
(Notes 1, 2 )
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Block Address
Write
(Notes 3, 4 ) Data = Write Buffer Data
Addr = Start Address
Write
(Notes 5, 6 ) Data = Write Buffer Data
Addr = Block Address
Suspend
Program
Loop
Read Status Register
SR.7 =?
Full Status
Check if Des ired
Program Complete
Suspend
Program
1
0
No
Yes
P33-65nm
Datasheet Feb 2010
76 Order Number: 208043-04
Figure 33: BEFP Flowchart
SR Error Handler
(User-Defined)
BEFP
Setup
Delay
Yes (SR.7=0) A
Is sue BEFP Setup Cmd
(Data = 0x80)
Is sue BEFP Confirm Cmd
(Data = 00D0h)
Read Status
Register
No (SR.7=1)
Exit
Start
Yes (SR.0=0)
No (SR.0=1)
Write 0xFFFFh outside Block
No (SR.0=1)
Yes (SR.0=0)
No
Yes
Yes (SR.7=1)
No (SR.7=0)
Finish
No
Yes
BEFP Setup
Do ne ?
Full Status
Register check for
errors
Rea d Status
Register
Buffer Ready ?
Write Data Word to Buffer
Buffer Full ?
Rea d Status
Register
Program
Done ?
Program
More Data ?
Program/Ve rify PhaseSetup Phase Exit Phase
A B
B
BEFP Exited ?
Rea d Status
Register
Datasheet Feb 2010
77 Order Number:208043-04
P33-65nm
Figure 34: Block Erase Flowchart
Start
Confirm Cycle
- Issue Confirm command
- Address = B lock to be erased
- Data = E rase confirm (0xD0)
Errors
?
Yes
No
Error-Handler
U ser Defined Rou tine
Chec k Ready St a t us
- Read Status Register Command not req u ire d
- P e rform rea d op eration
- Rea d R eady S tatus on signal SR.7
Comma nd Cyc l e
- Issue Erase comm and
- Address = B lock to be erased
- Data = 0 x20
Yes
S R .7 = '1'
?
End
No Suspend
?
No
Yes
Re ad Status Register
- Toggle CE # or OE# to update Status Register
- See Status Re gister Flowch art
Erase S uspen d
See S uspend/
Re sume F low ch art
P33-65nm
Datasheet Feb 2010
78 Order Number: 208043-04
Figure 35: Block Lock Operations Flowchart
No
Optional
Start
Write 60h
Bloc k Addres s
Write 90h
R ead Block Lock
Status
Locking
Change?
Loc k C hange
Complete
Write 01, D0,2Fh
Bloc k Addres s
Write FFh
Any Addre ss
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Standby
(Optional)
Write
Lock
Setup
Lock,
Unlock, or
Lockdown
Confirm
Read ID
Plane
Bloc k Loc k
Status
Read
Array
Da ta = 6 0 h
Addr = Block to lock/unlock/lock-down (BA)
D ata = 01h (L oc k bl oc k)
D0h (Unloc k bloc k)
2Fh (Lock down block)
Addr = Block to lock/unlock/lock-down (BA)
Da ta = 9 0 h
Addr = Bloc k addres s of f s et +2 (B A + 2)
Bloc k Loc k s tat us dat a
Addr = Bloc k addres s of f s et +2 (B A + 2)
C onf irm l oc k ing c h ange on D Q
1
, DQ
0
.
(See Bloc k Loc k ing St at e T ransit ions T able
f or v ali d c om binations. )
Da ta = FFh
Addr = Block ad dress (BA )
Bus
Operation Command Comments
LOCKING OPE R ATIONS PROCE DUR E
LOCK_OP.WM
F
Lock Confirm
L o ck Se tu p
Read ID Plane
Read Array
Datasheet Feb 2010
79 Order Number:208043-04
P33-65nm
Figure 36: Erase Suspend/Resume Flowchart
Erase
Completed
Read Array
Data
0
0
No
Read
1
Program
Program
Loop
Read Array
Data
1
Start
R ead St atus
Register
SR [7] =
SR [6] =
Erase
Resumed
Read or
Program?
Done
Write
Write
Idle
Idle
Write
Erase
Suspend
R ead Array
or Pro gram
None
None
Program
Resume
Data =0xB0
Addr = Sam e part ition addres s as
above
D ata = 0xF F or 0x40
Addr = Any addres s w it hin t he
s uspended partit ion
Check SR[7]:
1 = W SM rea dy
0 = W SM busy
Check SR[6]:
1 = Erase suspended
0 = Erase completed
Data =0xD0
Addr = Any address
Bus
Operation Command Comments
Read None Stat us Regis t er dat a.
Addr =Same partition
R ead or
Write None Read array or program dat a f rom /t o
bloc k ot h er t han t he on e being er as ed
ERASE SUSPEND / RESUME PROCEDURE
If the suspended par tition was placed in
Read Array mode or a Program Loop:
Wr i te 0x B 0 ,
Any Addres s
(Erase Suspend )
Wr i te 0x70,
Sam e Partit ion
(Read Status )
W rit e 0xD0,
Any Addres s
(Erase Resume )
Wr i te 0x70,
Sam e Partit ion
(Read Status )
Write 0xFF ,
Erased P artition
(Read Array )
Write Read
Status Data =0x70
Addr =Any partition address
Write Read
Status
Register
R eturn partit ion to St atus m ode:
Data =0x70
Addr =Same partition
Yes
P33-65nm
Datasheet Feb 2010
80 Order Number: 208043-04
Figure 37: OTP Register Programming Flowchart
Start
Confirm Da ta
- Write OTP A ddres s and D ata
Yes
SR.7 = '1'
?
End
No
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
OTP Program Setup
- Write 0x C 0
- OTP Address
Check Ready Status
- Rea d Status Register C ommand not required
- Perform read operation
- Rea d Read y Status on signal SR. 7
Datasheet Feb 2010
81 Order Number:208043-04
P33-65nm
Figure 38: Status Register Flowchart
Start
SR7 = '1'
SR2 = '1'
SR4 = '1'
SR3 = '1'
SR1 = '1'
Yes
Yes
No
Yes
No
No
No
SR6 = '1' Yes
No
SR5 = '1'
No
No
Program Suspend
See Suspend/Resum e F lowchart
Erase Su spen d
See Suspend/Resum e F lowchart
Error
C omm and Sequenc e
Yes
Yes
Yes
Error
E ras e Failure
Error
Program F ailure
Error
V
PEN/PP
< V
PENLK/PPLK
Error
B l ock Locked
-Set by WSM
- R eset by user
- See Clear Status
Register Command
- Set/Reset
by WSM
SR4 = '1' Yes
No
End
Command Cycle
-Iss ue S tatus R egi ster Com m and
- Addres s = any devic e address
- D ata = 0x70
D ata Cycle
-R ead St at us Regis t er SR [7:0]
P33-65nm
Datasheet Feb 2010
82 Order Number: 208043-04
A.3 Write State Machine
Show here are the command state transitions (Next State Table) based on incoming
commands. Only one partition can be actively programming or erasing at a time. Each
partition stays in its last read state (Read Array, Read Device ID, Read CFI or Read
Status Register) until a new command changes it. The next WSM state does not depend
on the partition’s output state.
Note: IS refers to Illegal State in the Next State Tables.
Table 43: Next State Table for P3x-65nm (Sheet 1 of 3)
Command Input and Resulting Chip Next State(1)
Current Chip State
Array Read (3)
Word Pgm Setup (4,9)
BP Setup (8)
EFI Command Setup
Erase Setup (4,9)
BEFP Setup (6)
Confirm (7)
Pgm/Ers Suspend
Read Status
Clear SR (5)
Read ID/Query
Lock/RCR/ECR Setup
Blank Check
OTP Setup
Lock Blk Confirm (7)
Lock-down Blk Confirm (7)
Write ECR/RCR Confirm (7)
Block Address Change
Other Commands (2)
WSM Operation Completes
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) (90h,
98h) (60h) (BCh) (C0h) (01h) (2Fh) (03h,
04h) other
Ready
Ready
Program
Setup
BP Setup
EFI
Setup
Erase
Setup
BEFP
Setup
Ready
Lock/RCR
/ECR Setup
BC
Setup
OTP
Setup
Ready N/A
Ready
N/A
Lock/RCR/ECR Setup Ready (Lock
Error [Botch])
Ready (Unlock
Block)
Ready (Lock Error [Botch])
Ready
(Lock
Error
[Botc
h])
Ready
(Lock
Block
)
Ready
(Lock
down
Block
)
Ready
(Set
CR)
N/A Ready (Lock Error
[Botch]) N/A
OTP
Setup OTP Busy OTP Busy N/A OTP Busy N/A
Busy OTP
Busy
IS in
OTP
Busy
OTP Busy IS in OTP
Busy OTP Busy Illegal State in OTP
Busy OTP Busy N/A OTP Busy Ready
IS in OTP Busy OTP Busy OTP Busy
Word
Program
Setup Word Program Busy N/A Pgm Busy N/A
Busy Pgm
Busy
IS in
Pgm
Busy
Pgm Busy IS in Pgm
Busy
Pgm
Busy
Pgm
Susp Word Pgm Busy IS in Word Pgm
Busy Word Pgm Busy N/A Pgm Busy Ready
IS in Pgm Busy Word Pgm Busy
Suspend Pgm
Susp
IS in
Pgm
Susp
Pgm
Suspend
IS in Pgm
Susp
Pgm
Busy Pgm Susp
Pgm
Susp
(Er
bits
clear)
Word
Pgm
Susp
Illegal State in Pgm
Suspend
Word Program
Suspend N/A Word Pgm Susp
N/A
IS in Pgm
Suspend Word Program Suspend
EFI
EFI Setup Sub-function Setup
N/A
Sub-function
Setup Sub-op-code Load 1
Sub-op-code
Load 1 Sub-function Load 2 if word count >0, else Sub-function confirm
Sub-function
Load 2 Sub-function Confirm if data load in program buffer is complete, ELSE Sub-function Load 2
Sub-function
Confirm Ready (Error [Botch]) S-fn
Busy Ready (Error [Botch])
Sub-function
Busy
S-fn
Busy
IS in
S-fn
Busy
S-fn Busy Illegal State
in S-fn Busy
S-fn
Busy
S-fn
Susp S-fn Busy IS in S-fn Busy S-fn Busy S-fn Busy
Ready
IS in Sub-
function Busy Sub-function Busy
Sub-function
Susp
S-fn
Susp
IS in
S-fn
Susp
Sub-function Illegal State
in S-fn Busy
S-fn
Busy
S-fn
Suspend
S-fn
Susp
(Er
bits
clear)
S-fn
Susp IS in S-fn Susp S-fn Suspend N/A S-fn Susp N/A
IS in S-fn Susp Sub-function Suspend
Datasheet Feb 2010
83 Order Number:208043-04
P33-65nm
Buffer
Pgm
(BP)
Setup BP Load 1
N/A
BP Load 1 (8) BP Load 2 if word count >0, else BP confirm
BP Load 2 (8) BP Confirm if data load in program buffer is complete, ELSE BP load 2
Ready
(Error
[Botc
h])
BP Confirm if data
load in program
buffer is
complete, else BP
load 2
BP Confirm Ready (Error [Botch]) BP
Busy Ready (Error [Botch])
BP Busy BP
Busy
IS in
BP
Busy
BP Busy Illegal State
in BP Busy
BP
Busy
BP
Susp BP Busy IS in BP Busy BP Busy BP Busy Ready
IS in BP Busy BP Busy
BP Susp BP
Susp
IS in
BP
Susp
BP Suspend Illegal State
in BP Busy
BP
Busy BP Suspend
BP
Susp
(Er
bits
clear)
BP
Susp IS in BP Susp BP Suspend N/A BP Susp N/A
IS in BP Susp BP Suspend
Erase
Setup Ready (Error [Botch]) Erase
Busy Ready (Error [Botch]) N/A Ready (Err
Botch0])
N/A
Busy Erase
Busy
IS in
Erase
Busy
Erase Busy IS in Erase
Busy
Erase
Busy
Erase
Susp Erase Busy IS in Erase Busy Erase Busy N/A Ers Busy
IS in Erase Busy Erase Busy Ready
Suspend Erase
Susp
Word
Pgm
Setup
in
Erase
Susp
BP
Setup
in
Erase
Susp
EFI
Setup
in
Erase
Susp
IS in Erase
Suspend
Erase
Busy
Erase
Suspend
Erase
Susp
(Er
bits
clear)
Erase
Susp
Lock/
RCR/
ECR
Setup
in
Erase
Susp
Erase
Susp
IS in
Erase
Susp
Erase Suspend N/A Erase Susp N/A
IS in Erase Susp Erase Suspend
Word
Pgm in
Erase
Suspend
Setup Word Pgm busy in Erase Suspend
N/A
Word Pgm Busy in
Ers Suspend
N/A
Busy
Word
Pgm
busy
in
Erase
Susp
IS in
Pgm
busy
in Ers
Susp
Word Pgm
busy in
Erase Susp
IS in Word
Pgm busy in
Ers Susp
Word
Pgm
busy
in
Erase
Susp
Word
Pgm
Susp
in Ers
Susp
Word Pgm busy in
Erase Susp
IS in Word Pgm
busy in Ers Susp
Word Pgm busy in
Erase Susp
Erase
Susp
Illegal state(IS)
in Pgm busy in
Erase Suspend
Word Pgm busy in Erase Suspend
IS in
Ers
Susp
Suspend
Word
Pgm
susp
in Ers
susp
iS in
pgm
susp
in Ers
Susp
Word Pgm
susp in Ers
susp
iS in pgm
susp in Ers
Susp
Word
Pgm
busy
in
Erase
Susp
Word
Pgm
susp
in Ers
susp
Word
Pgm
susp
in Ers
susp
Word
Pgm
Susp
in Ers
Susp
(Er
bits
clear)
Word
Pgm
susp
in Ers
susp
iS in Word Pgm
susp in Ers Susp
Word Pgm susp in
Ers susp N/A
N/A
Illegal State in
Word Program
Suspend in Erase
Suspend
Word Pgm busy in Erase Suspend
BP in
Erase
Suspend
Setup BP Load 1 in Erase Suspend
N/A
BP Load 1 (8) BP Load 2 in Erase Suspend if word count >0, else BP confirm
BP Load 2 (8) BP Confirming Erase Suspend if data load in program buffer is complete, ELSE BP load 2 in Erase Suspend
Ers
Susp
(Error
[Botc
h])
BP Confirm in
Erase Suspend
when count=0,
ELSE BP load 2
BP Confirm Erase Suspend (Error [BotchBP])
BP
Busy
in Ers
Susp
Erase Susp (Error [Botch BP])
BP Busy
BP
Busy
in Ers
Susp
IS in
BP
Busy
in Ers
Susp
BP Busy in
Erase Susp
Illegal State
in BP Busy in
Ers Susp
BP
Susp
in Ers
Susp
BP Busy in Ers Susp IS in BP Busy in
Erase Suspend BP Busy in Ers Susp N/A BP Busy in Ers
Susp
Erase
Susp
IS in BP Busy BP Busy in Erase Suspend
IS in
Ers
Susp
BP Susp
BP
Susp
in Ers
Susp
IS in
BP
Susp
in Ers
Susp
BP Suspend
in Erase
Suspend
Illegal State
in BP Busy in
Ers Susp
BP
Busy
in Ers
Susp
BP Susp in
Ers Susp
BP
Susp
in Ers
Susp
(Er
bits
clear)
BP
Susp
in Ers
Susp
IS in BP Busy in
Erase Suspend BP Susp in Ers Susp N/A BP Susp in Ers
Susp N/A
IS in BP Suspend BP Suspend in Erase Suspend
Table 43: Next State Table for P3x-65nm (Sheet 2 of 3)
Command Input and Resulting Chip Next State(1)
Current Chip State
Array Read (3)
Word Pgm Setup (4,9)
BP Setup (8)
EFI Command Setup
Erase Setup (4,9)
BEFP Setup (6)
Confirm (7)
Pgm/Ers Suspend
Read Status
Clear SR (5)
Read ID/Query
Lock/RCR/ECR Setup
Blank Check
OTP Setup
Lock Blk Confirm (7)
Lock-down Blk Confirm (7)
Write ECR/RCR Confirm (7)
Block Address Change
Other Commands (2)
WSM Operation Completes
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) (90h,
98h) (60h) (BCh) (C0h) (01h) (2Fh) (03h,
04h) other
P33-65nm
Datasheet Feb 2010
84 Order Number: 208043-04
EFI in
Erase
Suspend
EFI Setup Sub-function Setup in Erase Suspend
N/A
Sub-function
Setup Sub-op-code Load 1 in Erase Suspend
Sub-op-code
Load 1 Sub-function Load 2 in Erase Suspend if word count >0, else Sub-function confirm in Erase Suspend
Sub-function
Load 2 Sub-function Confirm in Erase Suspend if data load in program buffer is complete, ELSE Sub-function Load 2
Ers
Susp
(Error
[Botc
h])
Sub-function
Confirm if data
load in program
buffer is
complete, ELSE
Sub-function
Load 2
Sub-function
Confirm Erase Suspend (Error [Botch])
S-fn
Busy
in Ers
Susp
Erase Suspend (Error [Botch])
Sub-function
Busy
S-fn
Busy
in Ers
Susp
IS in
S-fn
Busy
in Ers
Susp
S-fn Busy in
Ers Suspend
Illegal State
in S-fn Busy
in Ers Susp
S-fn
Susp
in Ers
Susp
S-fn Busy in Ers
Susp
IS in S-fn Busy in
Ers Susp
S-fn Busy in Ers
Susp N/A S-fn Busy in Ers
Susp
Erase
Susp
IS in Sub-
function Busy Sub-function Busy in Ers Susp
IS in
Ers
Susp
Sub-function
Susp
S-fn
Susp
in Ers
Susp
IS in
S-fn
Susp
in Ers
Susp
S-fn
Suspend in
Ers Susp
Illegal State
in S-fn Busy
in Ers Susp
S-fn
Busy
in Ers
Susp
S-fn
Suspend in
Ers Susp
S-fn
Susp
in Ers
Susp
(Er
bits
clear)
S-fn
Susp
in Ers
Susp
IS in S-fn Susp in
Ers Susp
S-fn Suspend in Ers
Susp N/A S-fn Susp in Ers
Susp N/A
IS in Phase-1
Susp Sub-Function Suspend in Erase Suspend
Lock/RCR/ECR/Lock
EFA Block Setup in
Erase Suspend
Erase Suspend (Lock Error
[Botch])
Ers
Susp
(Un-
lock
Block
)
Ers Susp (Lock Error [Botch])
Ers
Susp
(Error
[Botc
h])
Ers
Susp
Blk
Lock
Ers
Susp
Blk
Lk-
Down
Ers
Susp
CR
Set
N/A Ers Susp (Error
[Botch]) N/A
Blank
Check
Setup Ready (Error [Botch]) BC
Busy Ready (Error [Botch])
N/A
Ready (Error
[Botch]) N/A
Blank Check Busy BC
Busy
IS in
BC
Busy
BC Busy IS in BC
Busy Blank Check Busy IS in BC Busy BC Busy
BC Busy Ready
IS in Blank Check
Busy BP Busy
BEFP
Setup Ready (Error [Botch])
BEFP
Load
Data
Ready (Error [Botch]) N/A
BEFP Busy BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands
treated as data. (7) Ready BEFP Busy Ready
Table 43: Next State Table for P3x-65nm (Sheet 3 of 3)
Command Input and Resulting Chip Next State(1)
Current Chip State
Array Read (3)
Word Pgm Setup (4,9)
BP Setup (8)
EFI Command Setup
Erase Setup (4,9)
BEFP Setup (6)
Confirm (7)
Pgm/Ers Suspend
Read Status
Clear SR (5)
Read ID/Query
Lock/RCR/ECR Setup
Blank Check
OTP Setup
Lock Blk Confirm (7)
Lock-down Blk Confirm (7)
Write ECR/RCR Confirm (7)
Block Address Change
Other Commands (2)
WSM Operation Completes
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) (90h,
98h) (60h) (BCh) (C0h) (01h) (2Fh) (03h,
04h) other
Datasheet Feb 2010
85 Order Number:208043-04
P33-65nm
Notes:
1. IS refers to Illegal State in the Next State Table.
2. “Illegal commands” include commands outside of the allowed command set.
3. The device defaults to "Read Array" on powerup.
4. If a “Read Array” is attempted when the device is busy, the result will be “garbage” data (we should not tell the user that
it will actually be Status Register data). The key point is that the output mux will be pointing to the “array”, but garbage
data will be output. “Read ID” and "Read Query" commands do the exact same thing in the device. The ID and Query data
are located at different locations in the address map.
5. The Clear Status command only clears the error bits in the status register if the device is not in the following modes:1.
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2. Suspend states (Erase
Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend).
6. BEFP writes are only allowed when the status register bit #0 = 0 or else the data is ignored.
7. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the
operation and then move to the Ready State.
8. Buffered programming will botch when a different block address (as compared to the address given on the first data write
cycle) is written during the BP Load1 and BP Load2 states.
9. All two cycle commands will be considered as a contiguous whole during device suspend states. Individual commands will
not be parsed separately. (I.e. If an erase set-up command is issued followed by a D0h command, the D0h command will
not resume the program operation. Issuing the erase set-up places the CUI in an “illegal state”. A subsequent command
will clear the “illegal state”, but the command will be otherwise ignored.
Table 44: Output Next State Table for P3x-65nm
Command Input to Chip and Resulting Output MUX Next State(1)
Current Chip State
Array Read (3)
Word Pgm Setup (4,9)
BP Setup (8)
EFI Command Setup
Erase Setup (4,9)
BEFP Setup (6)
Confirm (7)
Pgm/Ers Suspend
Read Status
Clear SR (5)
Read ID/Query
Lock/RCR/ECR Setup
Blank Check
OTP Setup
Lock Blk Confirm (7)
Lock-down Blk Confirm (7)
Write ECR/RCR Confirm (7)
Block Address Change
Other Commands (2)
WSM Operation Completes
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) (90h,
98h) (60h) (BCh) (C0h) (01h) (2Fh) (03h,
04h) other
BEFP Setup,
BEFP Pgm & Verify Busy,
Erase Setup,
OTP Setup,
BP Setup, Load 1, Load 2
BP Setup, Load1, Load 2 - in
Erase Susp.
BP Confirm
EFI Sub-function Confirm
Word Pgm Setup,
Word Pgm Setup in Erase
Susp,
BP Confirm in Erase Suspend,
EFI S-fn Confirm in Ers Susp,
Blank Check Setup,
Blank Check Busy
Status Read
Output MUX does not Change
Lock/RCR/ECR Setup,
Lock/RCR/ECR Setup in Erase
Susp Status Read
Array
Read
EFI S-fn Setup, Ld 1, Ld 2
EFI S-fn Setup, Ld1, Ld 2 - in
Erase Susp. Output MUX will not change
BP Busy
BP Busy in Erase Suspend
EFI Sub-function Busy
EFI Sub-fn Busy in Ers Susp
Word Program Busy,
Word Pgm Busy in Erase
Suspend,
OTP Busy
Erase Busy
Status Read
Status
Read
Status Read
Status
Read
Output MUX
Does not Change
Status Read
Array Read
Status Read
Status Read Output MUX does
not Change
Ready,
Word Pgm Suspend,
BP Suspend,
Phase-1 BP Suspend,
Erase Suspend,
BP Suspend in Erase Suspend
Phase-1 BP Susp in Ers Susp
Array Read
Output MUX
doesn’t Change
ID/Query Read
P33-65nm
Datasheet Feb 2010
86 Order Number: 208043-04
Appendix B Conventions - Additional Documentation
B.1 Acronyms
B.2 Definitions and Terms
BEFP : Buffer Enhanced Factory Programming
CUI : Command User Interface
MLC : Multi-Level Cell
OTP : One-Time Programmable
PLR : one-time programmable Lock Register
PR : one-time programmable Register
RCR : Read Configuration Register
RFU : Reserved for Future Use
SR : Status Register
SRD : Status Register Data
WSM : Write State Machine
VCC : Signal or voltage connection
VCC : Signal or voltage level
h : Hexadecimal number suffix
0b : Binary number prefix
0x : exadecimal number prefix
SR.4 : Denotes an individual register bit.
A[15:0] : Denotes a group of similarly named signals, such as address or data bus.
A5 : Denotes one element of a signal group membership, such as an individual address
bit.
Bit : Single Binary unit
Byte : Eight bits
Word : Two bytes, or sixteen bits
Kbit : 1024 bits
KByte : 1024 bytes
KWord : 1024 words
Mbit : 1,048,576 bits
MByte : 1,048,576 bytes
MWord : 1,048,576 words
K : 1,000
M : 1,000,000
Block : A group of bits, bytes, or words within the flash memory array that erase
simultaneously.
Array block : An array block that is usually used to store code and/or data.
Datasheet Feb 2010
87 Order Number:208043-04
P33-65nm
Appendix C Revision History
Date Revision Description
Jan 2008 01 Initial release
Aug 2009 02
Add Top/Bottom device information such as memory map, device ID, CFI, ordering information etc.
Add 40Mhz specification for TSOP package.
Add a Note to clarify the SR output after E8 command in Section 8.2, “Buffered
Programming” on page 24.
Align flowchart of Program/Erase Suspend as same as 130nm.
Align flowchart of block locking operation as same as 130nm.
Add note 7 to flowchart of Buffer program.
Updated Ordering Information.
Update RCR.7 in Section 13, “Read Configuration Register Description” on
page 35.
Nov 2009 03
Add 2-Gbit density related information such as memory map, CFI, ordering information, 2G DC
current spec, capacitance, dual-die configuration and Device ID note etc.
Update suspend latency spec.
Feb 2010 04
Update on TSOP package with VCCQ and Temp .
Update the erase and program performance.
Ordering information with Device feature digit.
CFI update aligned with performance update.
P33-65nm
Datasheet Feb 2010
88 Order Number: 208043-04
