1
HV220/HV20220/HV20320
A011705
D
LE
CL
LE CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
8 BIT
SHIFT
REGISTER
LEVEL
SHIFTERS
OUTPUT
SWITCHES
LATCHES
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
V PP
V NN
VDD
DOUT
DIN
CLK
Low Charge Injection
8-Channel High Voltage Analog Switches
Features
❏HVCMOS® technology for high performance
❏V ery low quiescent power dissipation – 10µA
❏Output on-resistance typically 22 ohms
❏Low parasitic capacitances
❏DC to 10MHz analog signal frequency
❏-60dB typical output of f isolation at 5MHz
❏CMOS logic circuitry for low power
❏Excellent noise immunity
❏On-chip shif t register, latch and clear logic circuitry
❏Flexible high voltage supplies
Block Diagram
HV220/HV20220/HV20320
Applications
❏Medical ultrasound imaging
❏Piezoelectric transducer drivers
General Description
These devices are low charge injection 8-channel high-voltage
analog switch integrated circuits (ICs) intended for use in
applications requiring high voltage switching controlled by low
voltage control signals, such as ultrasound imaging and print-
ers. Input data is shifted into an 8-bit shift register which can
then be retained in an 8-bit latch. To reduce any possible clock
feed-through noise, Latch Enable Bar (LE) should be left high
until all bits are clocked in. Using HVCMOS technology, these
switches combine high voltage bilateral DMOS switches and
low power CMOS logic to provide efficient control of high voltage
analog signals.
These ICs are suitable for various combinations of high voltage
supplies, e.g., VPP/VNN : +50V/–150V , or +100V/–100V.B
B021706
2
HV220/HV20220/HV20320
B021706
Symbol Parameter Value
VDD Logic power supply voltage1, 3 4.5V to 13.2V
VPP Positive high voltage supply 1, 3 40V to VNN+ 200V
VNN Negative high voltage supply1, 3 -40V to -160V
VIH High-level input voltage V DD -1.5V to VDD
VIL Low-level input voltage 0V to 1.5V
VSIG Analog signal voltage peak to peak VNN +10V to VPP -10V2
TAOperating free air-temperature 0°C to 70°C
Notes:
1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2V
SIG must be VNN ≤ VSIG≤ VPP or floating during power up/down transition.
3 Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
Operating Conditions
Ordering Information
Absolute Maximum Ratings*
VDD Logic power supply voltage -0.5V to +15V
VPP - VNN Supply voltage 220V
VPP Positive high voltage supply -0.5V to VNN +200V
VNN Negative high voltage supply +0.5V to -200V
Logic input voltages -0.5V to VDD +0.3V
Analog Signal Range VNN to VPP
Peak analog signal current/channel 3.0A
S torage temperature -65°C to +150°C
Power dissipation:
28-Lead PLCC 1.2W
48-Lead TQFP 1.0W
26-Lead BCC 1.0W
25-Lead FPBGA 1.0W
*Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability . All volt ages are referenced to device ground.
Package Options
Device 28-Lead PLCC 48-Lead TQFP 26-Lead BCC 25-Lead FPBGA
HV20220 HV20220PJ HV20220FG - -
HV20220PJ-G HV20220FG-G
HV20320 HV20320PJ - - -
HV20320PJ-G
HV220 - - -HV220GA
HV220B1-G HV220GA-G
-G indicates the part is RoHS compliant (Green)
3
HV220/HV20220/HV20320
B021706
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register
data flows through the latch.
4. DOUT is high when data in shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L L L OFF
HLLON
L L L OFF
HLLON
L L L OFF
HLLON
L L L OFF
HLLON
L L L OFF
HLL ON
L L L OFF
HLL ON
L L L OFF
HLL ON
L L L OFF
HLL ON
X X X X X X X X H L HOLD PREVIOUS STATE
X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF
T ruth Table
4
HV220/HV20220/HV20320
B021706
Electrical Characteristics
DC Characteristics (over recommended operating conditions unless otherwise noted)
30 26 38 48 ISIG = 5mA VPP = 40V,
25 22 27 32 ISIG = 200mA VNN = -160V
Small Signal Switch (ON) RONS 25 22 27 30 ohms ISIG = 5mA VPP = 100V,
Resistance 18 18 24 27 ISIG = 200mA VNN = -100V
23 20 25 30 ISIG = 5mA VPP = 160V,
22 16 25 27 ISIG = 200mA VNN = -40V
Small Signal Switch (ON) ∆RONS 20 5.0 20 20 % ISW = 5mA, VPP = 100V,
Resistance Matching VNN = -100V
Large Signal Switch (ON) R ONL 15 ohms VSIG = VPP - 10V, ISIG = 1A
Resistance
Switch Off Leakage I SOL 5.0 1.0 10 15 µA VSIG = VPP - 10V
Per Switch and VNN +10V
DC Offset Switch Off 300 100 300 300 mV RL = 100Ω
DC Offset Switch On 500 100 500 500 mV RL = 100KΩ
Pos. HV Supply Current I PPQ 10 50 µA ALL SWs OFF
Neg. HV Supply Current I NNQ - 10 -50 µA ALL SWs OFF
Pos. HV Supply Current I PPQ 10 50 µA ALL SWs ON ISW = 5mA
Neg. HV Supply Current I NNQ - 10 -5 0 µA ALL SWs ON I SW = 5mA
Switch Output 3.0 3.0 2.0 2.0 A VSIG duty cycle ≤ 0.1%
Peak Current
Output Switch Frequency fSW 5 0 KH z Duty Cycle = 50%
6.5 7.0 8.0 VPP = 40V,
VNN = -160V
IPP Supply Current IPP 4.0 5.0 5.5 mA VPP = 100V,
VNN = -100V
4.0 5.0 5.5 VPP = 160V,
VNN = -40V
6.5 7.0 8.0 VPP = 40V,
VNN = -160V
INN Supply Current I NN 4.0 5.0 5.5 mA VPP = 100V,
VNN = -100V
4.0 5.0 5.5 VPP = 160V,
VNN = -40V
Logic Supply IDD 4.0 4.0 4.0 mA fCLK = 5MHz, VDD = 5.0V
Average Current
Logic Supply I DDQ 10 10 10 µA
Quiescent Current
Data Out Source Current ISOR 0.45 0.45 0.70 0.40 mA VOUT = VDD - 0.7V
Data Out Sink Current I SINK 0.45 0.45 0.70 0.40 mA VOUT = 0.7V
Logic Input Capacitance CIN 10 10 10 pF
0°C +25°C +70°C
Characteristics Sym Units Test Conditions
min max min typ* max min max
50KHz
Output
Switching
Frequency
with no
load
* Typical values are only for HV202/HV203
5
HV220/HV20220/HV20320
B021706
AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted)
+25°C Units
Characteristics Sym Test Conditions
min typ* max
Electrical Characteristics
Electrical Characteristics
AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted)
0°C +25°C +70°C
Characteristics Sym min max min typ* max min max Units Test Conditions
Set Up Time Before LE Rises t SD 150 150 150 ns
Time Width of LE tWLE 150 150 150 ns
Clock Delay Time to Data Out t DO 150 150 150 ns
Time Width of CL tWCL 150 150 150 ns
Set Up Time Data to Clock t SU 15 15 8.0 20 ns
Hold Time Data from Clock t h35 35 35 ns
Clock Freq fCLK 5.0 5.0 5.0 MHz 50% duty cycle
fDATA = fCLK/2
Clock Rise and Fall Times tr, tf50 50 50 ns
Turn On Time t ON 5.0 5.0 5.0 µs VSIG = VPP -10V,
RL = 10KΩ
Turn Off Time t OFF 5.0 5.0 5.0 µs VSIG = VPP -10V,
RL = 10KΩ
20 20 20 VPP = 160V,
VNN = -40V
Maximum VSIG Slew Rate dv/dt 20 20 20 V/ns VPP = 100V,
VNN = -100V
20 20 20 VPP = 40V,
VNN = -160V
Off Isolation K O -3 0 -30 - 33 -3 0 dB f = 5MHz,
1KΩ//15pF load
-5 8 -58 -5 8 dB f = 5MHz,
50Ω load
Switch Crosstalk KCR -6 0 -60 - 70 -6 0 dB f = 5MHz,
50Ω load
Output Switch Isolation IID 300 300 300 mA
300ns pulse width,
Diode Current 2.0% duty cycle
Off Capacitance SW to GND C SG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz
On Capacitance SW to GND C SG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz
Output V oltage Spike + VSPK 150 VPP = 40V, VNN = -160V, RL = 50 Ω
– VSPK 150
+VSPK 150 VPP = 100V , VNN = -100V, RL = 50 Ω
– VSPK 150 mV
+VSPK 150 VPP = 160V , VNN = -40V, RL = 50Ω
– VSPK 150
Charge Injection 820 VPP = 40V , VNN = -160V, VSIG = 0V
Q 600 pC VPP = 100V , VNN = -100V , VSIG = 0V
350 VPP = 160V, VNN = -40V, VSIG = 0V
* Typical values are only for HV202/HV203
6
HV220/HV20220/HV20320
B021706
Test Circuit s
Switch OFF Leakage
I
SOL
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
NN
+10V
V
PP
-10V
DC Of
fset ON/OFF
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
VOUT
100KΩR
L
T
ON
/T
OFF
T
est Circuit
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
PP
-10V
R
L10KΩ
VOUT
Isolation Diode Current
I
ID
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
NN
V
SIG
Crosstalk
K
CR
= 20Log V
OUT
V
IN
V
IN
= 10 V
P-P
@5MHz
NC 50Ω
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
50Ω
Charge Injection
VPP 5V
VNN
VPP
VNN
VDD
GND
V
SIG
V
OUT
1000pF
Q = 1000pF x V
OUT
V
OUT
Output V
oltage Spike
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
OUT
1KΩRL
50Ω
+V
SPK
-V
SPK
OFF Isolation
KO = 20Log VOUT
V
IN
V
IN
= 10 V
P-P
@5MHz
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
R
L
V
OUT
7
HV220/HV20220/HV20320
B021706
Logic Timing W aveforms
Block Diagram
D
LE
CL
LE CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
8 BIT
SHIFT
REGISTER
LEVEL
SHIFTERS
OUTPUT
SWITCHES
LATCHES
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
V
PP
V
NN
V
DD
D
OUT
D
IN
CLK
DATA
IN
CLOCK
DATA
OUT
D
N - 1 N N + 1
DD
50%
50%
50%
50%
50%
50%
50%
50%
50%
OUT
(TYP)
V OFF
ON
CLR t
WCL
90%
10%
tOFF
DD
SD
ON
t
tt
t
t
h
WLE
SU
t
LE
8
HV220/HV20220/HV20320
B021706
Typical Performance Curves for HV20220 & HV20320
CLK Frequency (KHz)
TDO vs. Ambient Temperature TA
Ambient Temp TA (°C)
T
DO
(ns) R
ON
(ohms)
Ambient Temperature (
o
C)
R
ON
(ohms) @5mA
Off-Isolation vs. Signal Voltage Frequency
V
DD
= 5.0V, V
PP
/V
NN
= ±100V
Off-Isolation (dB)
-80.0
-75.0
-70.0
-65.0
-60.0
-55.0
-50.0
1.0 10.0
RON vs. Ambient Temperature TA
V
DD
= 5.0V, V
PP
/V
NN
= ±100V
RON vs. VPP/VNN
V
PP
/V
NN
= ±100V
IPP/INN vs. Output Switching Frequency
I
PP
/I
NN
Average Current (mA)
Output Switching Frequency (KHz)
V
DD
= 5.0V
V
DD
= 5.0V, V
PP
/V
NN
= ±100V
I
DD
Current (mA)
IDD vs Clock Frequency
V
DD
= 5.0V, V
PP
/V
NN
= ±100V, T
A
= 0°C to 70°C
3.0
2.0
1.0
0.0
10 1000 10000
100
Signal Voltage Frequency (MHz)
V
PP
V
NN
T
A
= 0
o
C
T
A
= 25
o
C
T
A
= 70
o
C
T
A
= 125
o
C
T
A
= 70°C
T
A
= 0°C
-50 -25 0 25 50 75 100 125 150
0
10.0
20.0
30.0
40.0
I
SW
= 5mA
I
SW
= 200mA
40V 60V 80V 100V 120V 140V 160V
0
10.0
20.0
30.0
40.0
50.0
-160V -140V -120V -100V -80V -60V -40V
T
A
= 125°C
T
A
= 85°C
T
A
= 25°C
T
A
= 0°C
-50 -25 0 25 50 75 100 125
0
20
40
60
80
100
V
DD
= 5.0V
V
DD
= 13.5V
0255075100
125 150
0
1
2
3
4
5
9B021706
10
HV220/HV20220/HV20320
B021706
Pin Configuration
Dimensions in Inches
(Dimensions in Millimeters)
Measurement Legend =
HV203 28 Pin J-Lead
Pin Function Pin Function
1 SW3 15 N/C
2 SW3 16 D
IN
3 SW2 17 CLK
4 SW2 18 LE
5 SW1 19 CL
6 SW1 20 D
OUT
7 SW0 21 SW7
8 SW0 22 SW7
9V
PP
23 SW6
10 V
NN
24 SW6
11 N/C 25 SW5
12 GND 26 SW5
13 V
DD
27 SW4
14 N/C 28 SW4
HV202 28 Pin J-Lead
Pin Function Pin Function
1 SW3 15 N/C
2 SW3 16 D
IN
3 SW2 17 CLK
4 SW2 18 LE
5 SW1 19 CL
6 SW1 20 D
OUT
7 SW0 21 SW7
8 SW0 22 SW7
9 N/C 23 SW6
10 V
PP
24 SW6
11 N/C 25 SW5
12 V
NN
26 SW5
13 GND 27 SW4
14 V
DD
28 SW4
Pin #1
B.C. of Bend Radii
0.480 ± 0.010
(12.192 ± 0.254)
D
e
0.050 ± 0.010
(1.270 ± 0.254)
0.450 ± 0.005
(11.430 ± 0.127)
D1
B
0.027 ± 0.003
(0.6858 ± 0.0762)
0.1725 ± 0.0075
(4.3815 ± 0.1905)
A
A2
min.
0.020
(0.508)
0.410 ± 0.010
(10.414 ± 0.254)
0.110 ± 0.010
(2.794 ± 0.254)
Q
Top View
28-Pin J-Lead Package
1
2
3
4
567891011
12
13
14
15
16
17
18
19202122232425
26
27
28
HV202/HV203 28-Pin J-lead
Package Outline
48-Pin TQFP Pin Configuration
1# niP
0° - 7°
BSC
0.354 ± 0.010
(8.992 ± 0.254)
0.275 ± 0.004
(6.985 ± 0.102)
0.354 ± 0.010
(8.992 ± 0.254)
D
1
, E
1
D, E
0.275 ± 0.004
(6.985 ± 0.1016)
A2
0.055 ± 0.004
(1.397 ± 0.102)
0.020
(0.508)
TYP.
0.039
(0.991)
A
0.059 ± 0.004
(1.4986 ± 0.102)
0.024 ± 0.008
(0.610 ± 0.2032)
L
1#
niP
Pin 1
top view
48-pin TQFP
Pin 12
48-Pin TQFP
Pin Function
1SW5
2N/C
3SW4
4N/C
5SW4
6N/C
7N/C
8SW3
9N/C
10 SW3
11 N/C
12 SW2
13 N/C
14 SW2
15 N/C
16 SW1
17 N/C
18 SW1
19 N/C
20 SW0
21 N/C
22 SW0
23 N/C
24 V
PP
Pin Function
25 V
NN
26 N/C
27 N/C
28 GND
29 V
DD
30 N/C
31 N/C
32 N/C
33 D
IN
34 CLK
35 LE
36 CLR
37 D
OUT
38 N/C
39 SW7
40 N/C
41 SW7
42 N/C
43 SW6
44 N/C
45 SW6
46 N/C
47 SW5
48 N/C
Dimensions in Inches
(Dimensions in Millimeters)
Measurement Legend =
11 B020906
B021706
