Enhanced near infrared sensitivity: QE=40% (λ=1000 nm)
CCD image sensors
IR-enhanced
S11510 series
www.hamamatsu.com 1
The S11510 series is a family of FFT-CCD image sensors for photometric applications that offer improved sensitivity in
the near infrared region at wavelengths longer than 800 nm. Our unique technology in laser processing was used to
form a MEMS structure on the back side of the CCD. This allows the S11510 series to have much higher sensitivity than
our previous products (S10420-01 series).
In addition to having high infrared sensitivity, the S11510 series can be used as an image sensor with a long active area
in the direction of the sensor height by binning operation, making it suitable for detectors in Raman spectroscopy. Bin-
ning operation also ensures even higher S/N and signal processing speed compared to methods that use an external
circuit to add signals digitally.
The S11510 series has a pixel size of 14 × 14 μm and is available in two image areas of 14.336 (H) × 0.896 (V) mm (1024
× 64 pixels) and 28.672 (H) × 0.896 (V) mm (2048 × 64 pixels). The S11510 series is pin compatible with the S10420-
01 series, and so operates under the same drive conditions.
Features Applications
Enhanced near infrared sensitivity: QE=40%
(λ=1000 nm)
High full well capacity and wide dynamic range
(with anti-blooming function)
High CCD node sensitivity: 6.5 μV/e-
Pixel size: 14 × 14 μm
MPP operation
Raman spectrometers, etc.
Spectral response (without window)*1
*1:
Spectral response with quartz glass is decreased
according to the spectral transmittance characteristic
of window material.
Quantum efficiency (%)
Wavelength (nm)
(Typ. Ta=25 °C)
0
200 400 600 800 1000 1200
10
20
30
40
50
60
70
80
100
90 S11510 series
Previous type
(S10420-01 series)
Front-illuminated CCD
KMPDB0324EC
CCD image sensors S11510 series
2
Structure
Absolute maximum ratings (Ta=25 °C)
Parameter S11510-1006 S11510-1106
Pixel size (H × V) 14 × 14 μm
Number of total pixels (H × V) 1044 × 70 2068 × 70
Number of effective pixels (H × V) 1024 × 64 2048 × 64
Image size (H × V) 14.336 × 0.896 mm 28.672 × 0.896 mm
Vertical clock phase 2-phase
Horizontal clock phase 4-phase
Output circuit One-stage MOSFET source follower
Package 24-pin ceramic DIP (refer to dimensional outline)
Window Quartz glass*2
Coooling Non-cooled
*2: Resin sealing
Parameter Symbol Min. Typ. Max. Unit
Operating temperature*3Topr -50 - +50 °C
Storage temperature Tstg -50 - +70 °C
Output transistor drain voltage
V
OD -0.5 - +30 V
Reset drain voltage
V
RD -0.5 - +18 V
Over fl ow drain voltage
V
OFD -0.5 - +18 V
Vertical input source voltage
V
ISV -0.5 - +18 V
Horizontal input source voltage
V
ISH -0.5 - +18 V
Over fl ow gate voltage
V
OFG -10 - +15 V
Vertical input gate voltage
V
IG1V,
V
IG2V -10 - +15 V
Horizontal input gate voltage
V
IG1H,
V
IG2H -10 - +15 V
Summing gate voltage
V
SG -10 - +15 V
Output gate voltage
V
OG -10 - +15 V
Reset gate voltage
V
RG -10 - +15 V
Transfer gate voltage
V
TG -10 - +15 V
Vertical shift register clock voltage
V
P1V,
V
P2V -10 - +15 V
Horizontal shift register clock voltage
V
P1H,
V
P2H
V
P3H,
V
P4H -10 - +15 V
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
*3: Package temperature
Operating conditions (MPP mode, Ta=25 °C)
Parameter Symbol Min. Typ. Max. Unit
Output transistor drain voltage VOD 23 24 25 V
Reset drain voltage VRD 11 12 13 V
Over fl ow drain voltage VOFD 11 12 13 V
Over fl ow gate voltage VOFG 01213V
Output gate voltage VOG 456V
Substrate voltage VSS -0-V
Test point
Input source VISV, VISH -VRD -V
Vertical input gate VIG1V, VIG2V -9 -8 - V
Horizontal input gate VIG1H, VIG2H -9 -8 - V
Vertical shift register clock voltage High VP1VH,VP2VH 468
V
Low VP1VL, VP2VL -9 -8 -7
Horizontal shift register clock voltage
High VP1HH, VP2HH
VP3HH, VP4HH 468
V
Low VP1HL, VP2HL
VP3HL, VP4HL -6 -5 -4
Summing gate voltage High VSGH 468
V
Low VSGL -6 -5 -4
Reset gate voltage High VRGH 468
V
Low VRGL -6 -5 -4
Transfer gate voltage High VTGH 468
V
Low VTGL -9 -8 -7
External load resistance RL90 100 110 k
Ω
CCD image sensors S11510 series
3
Electrical characteristics (Ta=25 °C)
Electrical and optical characteristics (Ta=25 °C, unless otherwise noted)
Parameter Symbol Min. Typ. Max. Unit
Signal output frequency fc - 0.25 0.5 MHz
Vertical shift register
capacitance
-1006 CP1V, CP2V - 600 - pF
-1106 - 1200 -
Horizontal shift register
capacitance
-1006 CP1H, CP2H
CP3H, CP4H
-80-
pF
-1106 - 160 -
Summing gate capacitance CSG -10-pF
Reset gate capacitance CRG -10-pF
Transfer gate capacitance
-1006 CTG -30-
pF
-1106 - 60 -
Charge transfer effi ciency*4CTE 0.99995 0.99999 - -
DC output level Vout 17 18 19 V
Output impedance Zo - 10 - kΩ
Power consumption*5P-4-mW
*4: Charge transfer effi ciency per pixel, measured at half of the full well capacity
*5: Power consumption of the on-chip amplifi er plus load resistance
Parameter Symbol Min. Typ. Max. Unit
Saturation output voltage Vsat - Fw × Sv - V
Full well capacity Vertical Fw 50 60 - ke-
Horizontal 250 300 -
CCD node sensitivity Sv 5.5 6.5 7.5 μV/e-
Dark current*6DS - 50 200
e
-
/pixel/s
Readout noise*7Nr - 6 15 e- rms
Dynamic range*8Line binning DR 41700 50000 - -
Spectral response range λ- 200 to 1100 - nm
Photoresponse nonuniformity*9PRNU - ±3 ±10 %
*6: Dark current nearly doubles for every 5 to 7 °C increase in temperature.
*7: Temperature: -40 °C, readout frequency: 20 kHz
*8: Dynamic range = Full well capacity / Readout noise
*9: Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 660 nm)
Fixed pattern noise (peak to peak)
Signal × 100
[%Photoresponse nonuniformity =
CCD image sensors S11510 series
Dark current vs. temperature
Spectral transmittance characteristic of window material
KMPDB0304EA KMPDB0303EA
4
Temperature (°C)
Dark current (e-/pixel/s)
0.01
100 (Typ.)
10
1
0.1
3020-50 -30-40 -20 -10 100
Wavelength (nm)
(Typ. Ta=25 °C)
Transmittance (%)
0
100
80
90
70
50
30
10
60
40
20
1200
100 300 400200 500 600 700 800 900
1000 1100
Device structure (conceptual drawing of top view in dimensional outline)
Effective pixels
Effective pixels
Horizontal
shift register
Thinning
Thinning
23 22 21 20 19 18 17 16
1
2
6 7 8 9 11 12
14
15
5
64
4
3
2
12345
1024
24
2n signal output
4-bevel 2-bevel
13
4 blank pixels
2n signal output
4 blank pixels
6-bevel 6-bevel
3 4 5 10
V=64
H=1024, 2048
Horizontal
shift register
Note: When viewed from the direction of the incident light, the horizontal shift register is
covered with a thick silicon layer (dead layer). However, long-wavelength light
passes through the silicon dead layer and may possibly be detected by the horizontal
shift register. To prevent this, provide light shield on that area as needed.
KMPDC0365EB
CCD image sensors S11510 series
Timing chart (line binning)
KMPDC0355EA
Integration time
(shutter has to be open)
(shutter has to be closed) (shutter has to be closed)
P1V
P2H
P3H
Readout periodVertical binning period
Tpwv
Tovr
Tovr
P2V, TG
P4H, SG
P1H
RG
OS
TovrhTpwh, Tpws
Tpwr
4...1043 1044: S11510-1006
4...2067 2068: S11510-1106
D3...D10, S1...S1024, D11...D20: S11510-1006
S1...S2048 : S11510-1106
D1 D2 D19 D20
12
123
3...69 70←64 + 6 (bevel)
Parameter Symbol Min. Typ. Max. Unit
P1V, P2V, TG Pulse width*10 Tpwv 6 8 - μs
Rise and fall times*10 Tprv, Tpfv 20 - - ns
P1H, P2H, P3H, P4H
Pulse width*10 Tpwh 1000 2000 - ns
Rise and fall times*10 Tprh, Tpfh 10 - - ns
Pulse overlap time Tovrh 500 1000 - ns
Duty ratio*10 -405060%
SG
Pulse width*10 Tpws 1000 2000 - ns
Rise and fall times*10 Tprs, Tpfs 10 - - ns
Pulse overlap time Tovrh 500 1000 - ns
Duty ratio*10 -405060%
RG Pulse width Tpwr 100 1000 - ns
Rise and fall times Tprr, Tpfr 5 - - ns
TG-P1H Overlap time Tovr 1 2 - μs
*10: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude.
5
CCD image sensors S11510 series
6
Pin connections
Pin no. Symbol Function Remark
(standard operation)
1 OS Output transistor source RL=100 kΩ
2 OD Output transistor drain +24 V
3 OG Output gate +5 V
4 SG Summing gate Same pulse as P4H
5 SS Substrate GND
6 RD Reset drain +12 V
7 P4H CCD horizontal register clock-4
8 P3H CCD horizontal register clock-3
9 P2H CCD horizontal register clock-2
10 P1H CCD horizontal register clock-1
11 IG2H Test point (horizontal input gate-2) -8 V
12 IG1H Test point (horizontal input gate-1) -8 V
13 OFG Over fl ow gate +12 V
14 OFD Over fl ow drain +12 V
15 ISH Test point (horizontal input source) Connect to RD
16 ISV Test point (vertical input source) Connect to RD
17 SS Substrate GND
18 RD Reset drain +12 V
19 IG2V Test point (vertical input gate-2) -8 V
20 IG1V Test point (vertical input gate-1) -8 V
21 P2V CCD vertical register clock-2
22 P1V CCD vertical register clock-1
23 TG Transfer gate Same pulse as P2V
24 RG Reset gate
KMPDA0265EA
Dimensional outline (unit: mm)
Index mark
38.10 ± 0.4
24
112
13
27.94 ± 0.3
A3.3 ± 0.35
0.25-0.03
+0.05
10.41 ± 0.25
10.03 ± 0.3
B
2.54 ± 0.13
0.46 ± 0.05
1.27 ± 0.2
1.27 ± 0.253.0 ± 0.5
Photosensitive surface
Photosensitive area
Type no.
1.72 ± 0.17
1.47
14.336 (H)
28.672 (H)
AB
0.896 (V)
0.896 (V)
S11510-1006
S11510-1106
Index mark
Cat. No. KMPD1126E04 Aug. 2012 DN
www.hamamatsu.com
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184
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China: Hamamatsu Photonics (China) Co., Ltd.: 1201 Tower B, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866
Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the
information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always
contact us for the delivery specification sheet to check the latest specifications.
Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or
a suffix "(Z)" which means developmental specifications.
The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that
one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product
use.
Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
Information described in this material is current as of August, 2012.
CCD image sensors S11510 series
7
Precautions (electrostatic countermeasures)
・
When handling CCD sensors, always wear a wrist strap and also anti-static clothing, gloves, and shoes, etc. The wrist strap should
have a protective resistor (about 1 MΩ) on the side closer to the body and be grounded properly. Using a wrist strap having no
protective resistor is hazardous because you may receive an electrical shock if electric leakage occurs.
・
Avoid directly placing these sensors on a work bench that may carry an electrostatic charge.
・
Provide ground lines with the work bench and work fl oor to allow static electricity to discharge.
・
Ground the tools used to handle these sensors, such as tweezers and soldering irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the
amount of damage that occurs.
Driver circuit for CCD image sensor (S11510 series) C11287 [sold separately]
The C11287 is a driver circuit designed for HAMAMATSU CCD image sensors S11510 series. The C11287 can be used in spectrometers,
etc. when combined with the CCD image sensor.
Features
Built-in 14-bit A/D converter
Interface to computer: USB 2.0
Power supply: USB bus power operation
Related information
Precautions
∙ Notice
∙ Image sensors/Precautions
Technical information
∙ FFT-CCD area image sensor/Technical information
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