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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
1
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Functional Diagram
Features
• 14-bit Resolution
• 50 to 500MSPS Sampling Rate Range
• 83dBc SFDR at 500MSPS,
Fin 187 MHz, BW = 100 MHz
• 71.1dBFS SNR at 500 MSPS, Fin 70MHz, 2.0 Vpp
• Adjustable Full Scale Range: 2.0 Vpp and 1.4 Vpp
• Dynamic Power Scaling vs. Sample Rate
• 2-bit Fast Amplitude Detect (FAD) outputs
• 9x9mm Package: QFN64 – 64 Lead Single Row
Typical Applications
• Cellular and Microwave Infrastructure Receivers
• Communication Test Equipment
• Phased Array Radars
• Magnetic Resonance Imaging
• Spectrum Analyzers
• Precision Digitizers
General Description
The HMCAD1063 is a dual 14-bit wideband ADC, and
achieves excellent linearity performance at high IF
frequencies.
The HMCAD1063 is based on a proprietary structure,
and employs internal reference circuitry, a serial
control interface, and parallel LVDS output data. Data
synchronization clock is supplied for data capture
at the receiver. Internal digital ne gain can be set
separately for the ADC channels to calibrate for gain
errors.
HMCAD1063 provides a multiplexer inserted for each
ADC output bit and the LVDS interface. This allows
reducing the number of active LVDS pairs, as each
LVDS pair will handle even and odd output bits.
2-bit Fast Amplitude Detect (FAD) outputs provide the
amplitude of the input signal linear-in-dB at very low
latency.
Various modes and conguration settings can
be applied to the ADCs through the serial control
interface (SPI). Each channel can be powered down
independently and output data format can be selected
through this interface. A full chip power down mode
can be set by a single external pin. Register settings
determine the exact function of this pin.
HMCAD1063 is designed to interface easily with Field
Programmable Gate Arrays (FPGAs) from several
vendors.
The HMCAD1063LP9 is pin compatible with
HMCAD1073LP9 (QFN64 package).
Pin Compatibility
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
2
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Table of Contents
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features ............................................................................ 1
General Description ..................................................................... 1
Specications .......................................................................... 3
DC Electrical Specications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Digital and Switching Specications ................................................... 3
AC Electrical Specications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC Electrical Specications – 250 and 400 MSPS ................................. 5
AC Electrical Specications – 500 MSPS ........................................ 7
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information ................................................................ 9
Outline Drawings ................................................................. 10
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LVDS Timing Diagram ............................................................. 13
Serial Port Interface (SPI) ............................................................14
Register Overview ...................................................................... 15
Startup Sequence ...................................................................... 16
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Register 0x00 – Software Reset ..................................................... 17
Register 0x01 – Device Conguration ................................................. 17
Register 0x04 – Idle Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register 0x05 – Recalibration by SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register 0x10 – Full Scale Range .................................................... 19
Register 0x11 – Programmable Fine Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register 0x20 – LVDS Control ....................................................... 20
Register 0x21 – Full Scale Range Tuning ..............................................22
Register 0x35 – Offset Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register 0x70 – Test Patterns ....................................................... 23
Registers 0x71, 0x72 – Custom Patterns ............................................... 24
Register 0x73 – Custom Patterns for FAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Registers 0x7E and 0x7F – Vendor and Chip ID ......................................... 24
Theory of Operation .................................................................... 29
Recommended Usage .................................................................. 29
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC-Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Input and Jitter Considerations ................................................. 31
Fast Amplitude Detect (FAD) Output .................................................. 31
Denition of Terms ..................................................................... 32
Evaluation Order Information ............................................................ 33
Document Changes .................................................................... 33
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
3
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Specications
DC Electrical Specications
AVDD = DVDD = VDDIO = 1.8 V, FS = 250 MSPS, Fin = 70 MHz, Ain = –1 dBFS, RSDS output data level, unless otherwise noted
Parameter Description Min. Typ. Max. Units
DC accuracy
No missing codes guaranteed
Offset Offset error after internal digital offset correction 2LSB
GABS Gain error ±6 %FS
Grel Gain matching between channels ±0.5 %FS
DNL Differential nonlinearity 250 / 400 / 500 MSPS ±0.6 / ±0.5 / ±0.5 LSB
INL Integral nonlinearity (endpoint) 250 / 400 / 500 MSPS ±1.6 / ±1.3 / ±2.4 LSB
Vcm,out Common mode voltage output on VCM pin 5/9  Vavdd
Analog Input
Vcm,in Analog input common mode voltage Vcm,out – 0.1 Vcm,out + 0.1 V
FSRHI Differential input voltage full scale range, high setting 2.0 Vpp
FSRLO Differential input voltage full scale range, low setting 1.4 Vpp
Cin Differential input capacitance 6.5 pF
Rin Differential input resistance at 250 / 400 / 500 MSPS 2.5 / 1.4 / 1.26 k
Noise BW –3 dB bandwidth for the ADC input 900 MHz
Gain Flatness ±0.5 dB Bandwidth
±1.0 dB Bandwidth
DC to 250
DC to 500 MHz
AIBW The maximum analog input frequency where proper
ADC performance is achieved for FSRHI / FSRLO 375 / 500 MHz
Nin Input referred noise 1.4 LSBrms
Temperature
TaOperating free-air temperature –40 +85 °C
Digital and Switching Specications
Parameter Description Min Typ Max Unit
Clock Inputs
DCclk Duty Cycle 45 55 %
FSmax Maximum sample rate 250/400/500 MSPS
FSmin Minimum sample rate 50 MSPS
Fclkmax Maximum input clock frequency 2000 MHz
Compliance LVDS, LVPECL, Sinewave
VCK,diff Differential input voltage swing, Fclk ≤ 500 MHz ±200 mVpp
Vck,diff Differential input voltage swing, Fclk > 500 MHz ±300 mVpp
VCK,sine Differential input voltage swing, sine wave clock input ±500 mVpp
VCM,CK Input common mode voltage.
Keep voltages within ground and voltage of VAVDD 0.3 VAVDD – 0.3 V
CCK Differential input capacitance 3pF
RCK Differential input resistance 100
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
4
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Parameter Description Min Typ Max Unit
Logic Inputs (CMOS)
VHI High level input voltage. VVDDIO ≥ 3.0 V 2 V
VHI High level input voltage. VVDDIO = 1.7 V – 3.0 V 0.8 · VVDDIO V
VLI Low level input voltage. VVDDIO ≥ 3.0 V 0 0.8 V
VLI Low level input voltage. VVDDIO = 1.7 V – 3.0 V 0 0.2 · VVDDIO V
IHI High level input leakage current ±10 µA
ILI Low level input leakage current ±10 µA
CIInput Capacitance 3pF
Logic Outputs (CMOS)
VHO High level output voltage (IHO < 1 mA) 0.8 · VVDDIO V
VLO High level output voltage (ILO < 1 mA) 0.2 · VVDDIO V
LVDS Data Outputs
Compliance LVDS / RSDS
VOUT Differential output voltage, LVDS 350 mV
VOUT Differential output voltage, RSDS 175 mV
VCM Output common mode voltage 1.2 V
Output coding Data output format 2’s complement
Timing Characteristics
tAD Aperture delay 0.79 0.95 1.58 ns
Tjrms Aperture jitter 75 fs rms
TPDACT Startup time from Chip Power Down Mode to Active Mode 8000 clock cycles
TSLACT Startup time from Chip Sleep Mode to Active Mode 1200 clock cycles
TCAL Calibration time from ADC Enable to Active Mode 6.35106clock cycles
TOVR Out of range recovery time 1 clock cycles
TL AT,DATA Data output latency 56 clock cycles
TL AT,FAD Fast Amplitude Detect output latency 14 clock cycles
LVDS Output Timing Characteristics
Tod CLK input to data output delay (in addition to the pipeline delay) 1.8 2.4 3.2 ns
Tsk LCLK to Data output skew - 0.15 ±0.1 +0.15 ns
DClclk LVDS LCLCK Duty-Cycle 45 55 %
TEDGE Data rise- and fall time 20% to 80% 0.12 0.2 ns
TCLKEDGE Clock rise- and fall time 20% to 80% 0.12 0.2 ns
“clock cycles” refers to ADC sample clock cycles.
Digital and Switching Specications, continued
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
5
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
AC Electrical Specications – 250 and 400 MSPS
AVDD = DVDD = VDDIO = 1.8 V, FS = 250 MSPS, Fin = 70 MHz, Ain = –1 dBFS, RSDS output data level multiplexed, unless otherwise noted.
Parameter Description 250 MSPS 400 MSPS Units
Min. Typ. Max. Min. Typ. Max.
Performance Parameters
SNR Signal to noise ratio
FSRHI = 2.0 Vpp, Fin = 70 MHz 71.9 70.5 dBFS
FSRLO = 1.4 Vpp, Fin = 70 MHz 69.1 68.4 dBFS
FSRLO = 1.4 Vpp, Fin = 150 MHz 68.9 67. 9 dBFS
FSRHI = 2.0 Vpp, Fin = 350 MHz 70.1 67 dBFS
FSRLO = 1.4 Vpp, Fin = 350 MHz 6 7. 9 66 dBFS
FSRLO = 1.4 Vpp, Fin = 440 MHz 66.3 65 dBFS
Sndr Signal to noise and distortion ratio
FSRHI = 2.0 Vpp, Fin = 70 MHz 71 69 dBFS
FSRLO = 1.4 Vpp, Fin = 70 MHz 69 68.2 dBFS
FSRLO = 1.4 Vpp, Fin = 150 MHz 68.6 67.8 dBFS
FSRHI = 2.0 Vpp, Fin = 350 MHz 67.7 64.5 dBFS
FSRLO = 1.4 Vpp, Fin = 350 MHz 67.7 66 dBFS
FSRLO = 1.4 Vpp, Fin = 440 MHz 65.6 64.5 dBFS
SFdr Spurious free dynamic range
FSRHI = 2.0 Vpp, Fin = 70 MHz 79 75 dBc
FSRLO = 1.4 Vpp, Fin = 70 MHz 85 78 dBc
FSRLO = 1.4 Vpp, Fin = 150 MHz 81 75 dBc
FSRHI = 2.0 Vpp, Fin = 350 MHz 69 70 dBc
FSRLO = 1.4 Vpp, Fin = 350 MHz 77 70 dBc
FSRLO = 1.4 Vpp, Fin = 440 MHz 72 68 dBc
Hd2 Second order harmonic spur
FSRHI = 2.0 Vpp, Fin = 70 MHz 88 86 dBc
FSRLO = 1.4 Vpp, Fin = 70 MHz 85 90 dBc
FSRLO = 1.4 Vpp, Fin = 150 MHz 85 75 dBc
FSRHI = 2.0 Vpp, Fin = 350 MHz 72 90 dBc
FSRLO = 1.4 Vpp, Fin = 350 MHz 77 80 dBc
FSRLO = 1.4 Vpp, Fin = 440 MHz 77 77 dBc
Hd3 Third order harmonic spur
FSRHI = 2.0 Vpp, Fin = 70 MHz 79 75 dBc
FSRLO = 1.4 Vpp, Fin = 70 MHz 86 81 dBc
FSRLO = 1.4 Vpp, Fin = 150 MHz 81 84 dBc
FSRHI = 2.0 Vpp, Fin = 350 MHz 69 70 dBc
FSRLO = 1.4 Vpp, Fin = 350 MHz 78 80 dBc
FSRLO = 1.4 Vpp, Fin = 440 MHz 78 80 dBc
AC Electrical Specications
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
6
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Parameter Description 250 MSPS 400 MSPS Units
Min. Typ. Max. Min. Typ. Max.
ENOB Effective number of bits
FSRHI = 2.0 Vpp, Fin = 70 MHz 11.7 11.3 bit
FSRLO = 1.4 Vpp, Fin = 70 MHz 11. 2 11.0 bit
FSRLO = 1.4 Vpp, Fin = 150 MHz 11.1 11.0 bit
FSRHI = 2.0 Vpp, Fin = 350 MHz 11.0 10.6 bit
FSRLO = 1.4 Vpp, Fin = 350 MHz 11.0 10.7 bit
FSRLO = 1.4 Vpp, Fin = 440 MHz 10.6 10.4 bit
Xtlk Crosstalk
FSRHI = 2.0 Vpp, Fin0 = 70 MHz, Fin1 = 71 MHz 90 80 dBc
IMD2 Second order intermodulation product
FSRHI = 2.0 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 91 88 dBFS
FSRLO = 1.4 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 89 88 dBFS
FSRLO = 1.4 Vpp, Fin = 440, 441 MHz, Ain = -7 dBFS 90 88 dBFS
IMD3 Third order intermodulation product
FSRHI = 2.0 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 89 82 dBFS
FSRLO = 1.4 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 95 89 dBFS
FSRLO = 1.4 Vpp, Fin = 440, 441 MHz, Ain = -7 dBFS 91 88 dBFS
In-Band IMD3 In-Band Third order intermodulation product
FSRHI = 2.0 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 97 86 dBFS
FSRLO = 1.4 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 100 97 dBFS
FSRLO = 1.4 Vpp, Fin = 440, 441 MHz, Ain = -7 dBFS 95 94 dBFS
Power Supply
Iavdd Analog supply current 320 505 mA
Idvdd Digital output driver supply current 170 235 mA
Pavdd Analog power 575 910 mW
Pdvdd Digital power 300 420 mW
Ptot Total power dissipation 875 1330 mW
Ppd Chip Power down Mode power dissipation <0.2 <0.35 mW
PSlp Chip Sleep Mode power dissipation 320 475 mW
PpdcH _Sav Power saving per channel in channel-wise power down
mode 365 535 mW
PSlpcH _Sav Power saving per channel in channel-wise sleep mode 290 380 mW
AC Electrical Specications – 250 and 400 MSPS, continued
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
7
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Parameter Description Min. Typ. Max. Units
Performance Parameters
SNR Signal to noise ratio
FSRHI = 2.0 Vpp, Fin = 70 MHz 71.1 dBFS
FSRLO = 1.4 Vpp, Fin = 70 MHz 68.3 dBFS
FSRLO = 1.4 Vpp, Fin = 70 MHz, BW = 100 MHz 72 dBFS
FSRLO = 1.4 Vpp, Fin = 187 MHz, BW = 100 MHz 72 dBFS
FSRLO = 1.4 Vpp, Fin = 150 MHz 65.6 dBFS
FSRLO = 1.4 Vpp, Fin = 320 MHz 66.2 dBFS
Sndr Signal to noise and distortion ratio
FSRHI = 2.0 Vpp, Fin = 70 MHz 70.2 dBFS
FSRLO = 1.4 Vpp, Fin = 70 MHz 68.1 dBFS
FSRLO = 1.4 Vpp, Fin = 150 MHz 65.6 dBFS
FSRLO = 1.4 Vpp, Fin = 320 MHz 67. 5 dBFS
SFdr Spurious free dynamic range
FSRHI = 2.0 Vpp, Fin = 70 MHz 79 dBc
FSRLO = 1.4 Vpp, Fin = 70 MHz 83 dBc
FSRLO = 1.4 Vpp, Fin = 70 MHz, BW = 100 MHz 83 dBc
FSRLO = 1.4 Vpp, Fin = 187 MHz, BW = 100 MHz 83 dBc
FSRLO = 1.4 Vpp, Fin = 150 MHz 76 dBc
FSRLO = 1.4 Vpp, Fin = 320 MHz 71 dBc
Hd2 Second order harmonic spur
FSRHI = 2.0 Vpp, Fin = 70 MHz 87 dBc
FSRLO = 1.4 Vpp, Fin = 70 MHz 92 dBc
FSRLO = 1.4 Vpp, Fin = 150 MHz 87 dBc
FSRLO = 1.4 Vpp, Fin = 187 MHz, BW = 100 MHz 90 dBc
Hd3 Third order harmonic spur
FSRHI = 2.0 Vpp, Fin = 70 MHz 79 dBc
FSRLO = 1.4 Vpp, Fin = 70 MHz 83 dBc
FSRLO = 1.4 Vpp, Fin = 150 MHz 85 dBc
FSRLO = 1.4 Vpp, Fin = 187 MHz, BW = 100 MHz 83 dBc
ENOB Effective number of bits
FSRHI = 2.0 Vpp, Fin = 70 MHz 11. 5 bit
FSRLO = 1.4 Vpp, Fin = 70 MHz 11.0 bit
FSRLO = 1.4 Vpp, Fin = 150 MHz 10.6 bit
FSRLO = 1.4 Vpp, Fin = 187 MHz, BW = 100 MHz 10.7 bit
Xtlk Crosstalk
FSRHI = 2.0 Vpp, Fin0 = 70 MHz, Fin1 = 71 MHz 80 dBc
IMD2 Second order intermodulation product
FSRHI = 2.0 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 89 dBFS
FSRLO = 1.4 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 86 dBFS
FSRLO = 1.4 Vpp, Fin = 370, 371 MHz, Ain = -7 dBFS 86 dBFS
AC Electrical Specications – 500 MSPS
AVDD = DVDD = VDDIO = 1.9 V, FS = 500 MSPS, Fin = 70 MHz, Ain = –1 dBFS, RSDS output data level unless otherwise noted.
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
8
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Parameter Description Min. Typ. Max. Units
IMD3 Third order intermodulation product
FSRHI = 2.0 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 85 dBFS
FSRLO = 1.4 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 91 dBFS
FSRLO = 1.4 Vpp, Fin = 370, 371 MHz, Ain = -7 dBFS 87 dBFS
In-Band IMD3 In-Band Third order intermodulation product
FSRHI = 2.0 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 85 dBFS
FSRLO = 1.4 Vpp, Fin = 70, 71 MHz, Ain = -7 dBFS 94 dBFS
FSRLO = 1.4 Vpp, Fin = 370, 371 MHz, Ain = -7 dBFS 87 dBFS
Power Supply
Iavdd Analog supply current 630 mA
Idvdd Digital output driver supply current 270 mA
Pavdd Analog power 1130 mW
Pdvdd Digital power 490 mW
Ptot Total power dissipation 1620 mW
Ppd Chip Power down Mode power dissipation <0.5 mW
PSlp Chip Sleep Mode power dissipation 575 mW
PpdcH _Sav Power saving per channel in channel-wise power down mode 635 mW
PSlpcH _Sav Power saving per channel in channel-wise sleep mode 435 mW
AC Electrical Specications – 500 MSPS, continued
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
9
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Operating Conditions
Parameter Description 250 MSPS 400 MSPS 500 MSPS Unit
Min Typ Max Min Typ Max Min Typ Max
VAVDD Analog supply voltage range 1.7 1.8 2.0 1.7 1.8 2.0 1.8 1.9 2.0 V
VDVDD Digital and output driver voltage range 1.7 1.8 2.0 1.7 1.8 2.0 1.8 1.9 2.0 V
VOVDD Digital CMOS Inputs supply voltage range 1.7 1.8 3.6 1.7 1.8 3.6 1.7 1.9 3.6 V
TAAmbient temperature -40 +85 -40 +85 -40 +85 °C
Note: The conditions listed in this table must be observed for the device to be functional as specied in this document.
These conditions do not guarantee specic performance levels – which are listed in the DC Electrical Specications,
AC Electrical Specications, and Digital and Switching Specications, and apply under the test conditions specied
therein.
Absolute Maximum Ratings
Parameter Description Min Typ Max Unit
TjJunction temperature +125 °C
Tstorage Storage temperature -65 +125 °C
AVDD Analog supply voltage in reference to AVSS -0.3 +2.3 V
DVDD Digital supply voltage in reference to DVSS -0.3 +2.3 V
OVDD Digital CMOS Inputs supply voltage in reference to AVSS -0.3 +3.9 V
AVSS-DVSS Supply difference AVSS, DVSS are connected internally V
Vanalog Analog inputs and outputs in reference to AVSS -0.3 AVDD+0.3
or +2.3 V
Vclock Clock input pins voltage in reference to AVSS -0.3 OVDD+0.3
or 3.9 V
VLVDS LVDS output pins voltage in reference to DVSS -0.3 DVDD+0.2
or +2.3 V
Vdigital-in Digital input pins voltage in reference to DVSS -0.3 OVDD+0.3
or 3.9 V
ESD Rating Human body model (JEDEC JS-001-2012) passed 1000 V (class 1C)
Charged device model (JESD-22-C101E) passed 1.5 kV (class IV)
–Soldering prole characteristics J-STD-020
Note: Operating the device beyond the limits specied in this table may cause immediate damage to the device.
Functional operation of the device is further limited by the Operating Conditions. Device functionality is not implied by
the Absolute Maximum Ratings.
Thermal Information
Parameter Description Standard1Min Typ Max Unit
θJA0 Thermal resistance – junction-to-ambient, still air2JESD51-2 19.1 °C/W
θJA1 Thermal resistance – junction-to-ambient, 1 m/s air ow JESD51-6 13 .1 °C/W
θJA2.5 Thermal resistance – junction-to-ambient, 2.5 m/s air ow JESD51-6 11.1 °C/W
θJC Thermal resistance – junction-to-case, still air2MIL-STD883, 1012.1 0.6 °C/W
θJB Thermal resistance – junction-to-board, still air2JESD51-8 3.35 °C/W
1 Simulated environment according to JEDEC standards JESD51, JESD51-5 and JESD51-7.
2 “Still air” signies natural convection in an enclosure according to JESD51-2.
Note: The thermal pad at the bottom of the device package (pin 0) must be attached to the PCB ground plane. It is also
recommended that the thermal pad should be connected to a metal pad on the underside of the PCB through multiple
vias for heat conduction purposes as this is the most optimal path for heat dissipation of this device.
P r e l i m i n a r y
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HMCAD1063
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DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Outline Drawings, Top and Side View
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HMCAD1063
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DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Outline Drawings, Bottom View
NOTES QFN64:
1. PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED.
2. LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY.
3. LEAD AND GROUND PADDLE PLATING: NiPdAu.
4. DIMENSIONS ARE IN INCHES [MILLIMETERS].
5. LEAD SPACING TOLERANCE IS NON-CUMULATIVE.
6. CHARACTERS TO BE HELVETICA MEDIUM, .025 HIGH, WHITE INK, OR LASER MARK LOCATED APPROX. AS SHOWN.
7. PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.25mm MAX.
8. PACKAGE WARP SHALL NOT EXCEED 0.05mm
9. ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND.
10. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN.
11. JEDEC STANDARD MO-220 APPLIES.
Table 1. Package Information
Part Number Package Package Body Material Lead Finish MSL Rating [2] Package Marking [1]
HMCAD1063LP9DE 9x9 mm
QFN64
RoHS-compliant Low Stress
Injection Molded Plastic Silica and
silicon impregnated
NiPdAu MSL3 HAD6502
XXXX
[1] Lot number XXXX
[2] Max peak reow temperature of 260 °C
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HMCAD1063
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Pin Descriptions
Pin Number Function Description Interface Schematic
4, 7, 10, 13 AVDD
Analog power supply, 1.8 V
—
8, 61 AVDDCK
15 AVDDREF
60 VDDCK Digital and LVDS power supply, 1.8 V
32, 41, 42, 49 DVDD
14 VDDIO Digital CMOS I/O supply voltage, 1.8 to 3.3 V
0GND Thermal pad and main ground connection
16, 21, 64 GND Ground connections in addition to thermal pad (pin 0)
2RN
Resets SPI interface when low. After power is applied, a reset must be
executed either by RN pin or SPI command reset to achieve proper ADC
initialization. See also “Startup Sequence” on page 16
3PD Sets chip Power Down when ‘high’
1CAL Initiates Calibration when ‘high’
17 CSN Chip select enable. Active low
18 SCLK Serial clock input
19 SDI Serial data input
20 SDO Serial data output
See Table 2
DP1 LVDS channel 0, positive output
DN1 LVDS channel 0, negative output
DP2 LVDS channel 1, positive output
DN2 LVDS channel 1, negative output
–
FADP0 LVDS FAD channel 0, positive output
FADN0 LVDS FAD channel 0, negative output
FADP1 LVDS FAD channel 1, positive output
FADN1 LVDS FAD channel 1, negative output
39 LCLKP LVDS bit clock, positive output
40 LCLKN LVDS bit clock, negative output
62 CLKP Positive differential input clock
63 CLKN Negative differential input clock
5IN1 Negative differential input signal, channel 1
6 IP1 Positive differential input signal, channel 1
11 IN0 Negative differential input signal, channel 0
12 IP0 Positive differential input signal, channel 0
9VCM Common mode output voltage
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HMCAD1063
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DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
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LVDS Timing Diagram
Figure 1. LVDS timing
Table 2. Pins of LVDS Channels
LVDS channel bit# DXn<0> DXn<1> DXn<2> DXn<3> DXn<4> DXn<5> DXn<6> DXn<7>
n = 0
positive pin 37 35 33 30 28 26 24 22
negative pin 38 36 34 31 29 27 25 23
n = 1
positive pin 58 56 54 52 50 47 45 43
negative pin 59 57 55 53 51 48 46 44
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HMCAD1063
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DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Table 3. SPI Timing Denitions
Parameter Description Minimum value Maximum value Unit
tcs Setup time between CSN and SCLK 8 ns
tch Hold time between CSN and SCLK 8 ns
thi SCLK high time 20 ns
tlo SCLK low time 20 ns
tck SCLK period 50 ns
tsSDI setup time 5 ns
thSDI hold time 5 ns
tchi CSN high time 100 ns
tdSDO delay 5ns
Figure 2. Serial Port Interface Timing during Write Operation
See Table 3 for timing denitions.
Figure 3. Serial Port Interface Timing during Read Operation
Serial Port Interface (SPI)
The HMCAD1063 conguration registers can be
accessed through SPI an interface formed by the pins
• CSN:ChipSelectenabledwhenlow
• SDI:SerialDataInput
• SDO:SerialDataOutput
• SCLK:SerialClock
When CSN is set low, the SDI pin is awaiting input on
the rising edge of SCLK:
• First bit is a R/W bit (‘0’: Write to SPI on SDI,
‘1’: Read from SDO)
• The next 7 bits are the register address to be
written/read.
• ForSPIinput(R/W=‘0’)thelast16bitsaredata,
see Figure 2. Data are clocked in on the rising
edge of SCLK and loaded into the register at the
24th rising SCLK edge.
• For Serial Data Output (R/W=‘1’), 16 bits are
output on SDO during the last 16 SCLK periods, in
sync with the falling edge of SCLK, see Figure 3.
Acceptable SCLK frequencies are from a few Hertz to
20 MHz. Duty cycle is not considered critical.
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HMCAD1063
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DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Register Overview
Hex Address bit Type Name Default Description
0x00
0AUTOCLR reset 0Self clearing software reset
1R/W adc_enable 1Enable ADC
5:4 R/W clock_div 00
division by 1 Congures Input clock division factor
0x01
2R/W fgain_en 0Enables the ne gain function
5:4 R/W vcm_drive_cfg 11
4 mA Congures VCM output driving strength
8R/W pd_pin_cfg 0
Congures the PD pin functionality.
‘0’: PD pin invokes Chip Power Down Mode.
‘1’: PD pin invokes Chip Sleep Mode
0x04
0R/W pd 0 Sets Chip power down Mode
5:4 R/W pd_ch 00 Sets Channel-wise power down Modes
8R/W sleep 0Sets Chip sleep Mode
13:12 R/W sleep_ch 00 Sets Channel-wise sleep Modes
0x05 0AUTOCLR recal_by_spi 0Initiates re-calibration
0x10 3:0 R/W fsr_ch0 0001
FSR = 2.0 Vpp
Congures Full Scale Range for channel 0
11:8 R/W fsr_ch1 Congures Full Scale Range for channel 1
0x11 7:0 R/W fgain_ch0 0x00
factor 1x
Sets ne gain value for channel 0
15:8 R/W fgain_ch1 Sets ne gain value for channel 1
0x20
1:0 R/W lvdsterm_ctrl 00
not terminated Sets LVDS output (data and clock) termination resistance
4R/W lvdscurr_ctrl 0 Selects RSDS (‘0’) or LVDS (‘1’) Mode
5R/W scramble_en 0 Enables scrambling of LVDS outputs by channel’s LSB
8R/W fad_en 0 Enables the Fast Amplitude Detect (FAD) output
0x21 13:8 R/W fsrtune* 0x00
no tuning Selects Full Scale Range Tuning factor
0x35
2:0 R/W offcomp_time_ch0 000 Sets number of samples used for offset compensation for
channel 0
5AUTOCLR offcomp_start_ch0 0 Invokes offset compensation for channel 0
10:8 R/W offcomp_time_ch1 000 Sets number of samples used for offset compensation for
channel 1
13 AUTOCLR offcomp_start_ch1 0 Invokes offset compensation for channel 1
0x59
7:0 Rtemp_val 0x000 Temperature value
14 Rtemp_valid 0Set when temperature measurement completed
15 R/W activate_tempm 0Enables temperature measurement
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250/400/500 MSPS
Hex Address bit Type Name Default Description
0x70
0R/W ramp_en 0 Enables a repeated full scale ramp data output pattern
1R/W single_cust_pat_en 0Enables custom_pattern0 on channel 0 and
custom_pattern1 on channel 1
2R/W dual_cust_pat_en 0Enables toggling custom_pattern0 and custom_pattern1
on both channel 0 and channel 1
3R/W prbs_en 0Enables a pseudo random bit sequences on
each LVDS output pair
0x71 15:0 R/W custom_pattern0 0x5555 Custom pattern 0
0x72 15:0 R/W custom_pattern1 0xAAAA Custom pattern 1
0x713 3:0 R/W custom_fad_pattern0 0x5 Custom pattern 0 for FAD outputs
7:4 R/W custom_fad_pattern1 0xA Custom pattern 1 for FAD outputs
0x7E 15:0 Rvendor_id 0xADC Vendor ID
0x7F 15:0 Rchip_id
250 MSPS: 0x01
Product ID400 MSPS: 0x03
500 MSPS: 0x04
*When modifying registers marked with an asterisk, the ADC operation must be disabled rst by setting adc_enable in register 0x00 to ‘0’. After-
wards, set adc_enable back to ‘1’. See also next section “Startup Sequence”.
Startup Sequence
The recommended startup sequence is:
Step Purpose SPI Write
register value
1. Power up chip –
2. In register 0x00, set clock_div = ‘mn’, adc_enable= ‘0’ and reset = ‘1’ 0x00 ‘00mn 0001’
3. Optional (if non-default values are desired): set fsrtune = ‘abcdef’ in register 0x21 0x21 ‘00ab cdef 0000 0000’
4. Optional: write additional parameters
5. Set adc_enable = ‘1’ while maintaining clock_div = ‘mn’0x00 ‘00mn 0010’
6. Optional: re-estimate Offset Compensation 0x35 see register description
7. Wait for Start-up (see also “Digital and Switching Specications” on page 3) –
Once the ADC is running, registers marked with an asterisk (*) in the Register Overview can be modied by
1. set adc_enable = 0 while maintaining the value of clock_div (register 0x00 = ‘00mn 0000’)
2. follow steps 3. to 7.
Register Overview, continued
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HMCAD1063
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DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Register Description
Register 0x00 – Software Reset
bit Type Name Default Description
0AUTO-
CLEAR reset 0Self clearing software reset
1R/W adc_enable 1Enable ADC
5:4 R/W clock_div 00 Input clock division factor
Setting the reset register bit to ‘1’, restores the default
value of all the internal registers including the reset
register bit itself, but continues using the values of
both clock_div and adc_enable that are being written
to register 0x00 in the same SPI write command as
reset. Using the reset register is equivalent to setting
the RN pin low and then high, but RN always resets
clock_div and adc_enable to their default values.
Setting adc_enable to ‘0’ and later, back to ‘1’ allows
both to change register settings without generating
data in an undesired intermediate state, and to initiate
the ADC at a well-dened time.
The register bits clock_div allow the user to apply an
input clock frequency higher than the sampling rate.
The clock divider will divide the input clock frequency
by a factor of 1, 2, 4, or 8, as in the following table. The
maximum input clock frequency is 2000 MHz.
When changes are written to clock_div it is mandatory
to invoke reset. See also section “Startup Sequence”.
clock_div<1:0> Clock Divider Factor Sampling rate (Fs)
00 (default) 1 Input clock frequency / 1
01 2 Input clock frequency / 2
10 4 Input clock frequency / 4
11 8 Input clock frequency / 8
Register 0x01 – Device Conguration
bit Type Name Default Description
2R/W fgain_en 0Enables the ne gain
function
5:4 R/W vcm_drive_cfg 11 Congures VCM output
driving strength
8R/W pd_pin_cfg 0Congures the PD pin
functionality
The HMCAD1063 has several conguration settings,
controlling Digital Gain, Fast Amplitude Detect (FAD)
Output, Common Mode output drive strength, PD pin
functionality, and ADC resolution:
The register bit fgain_en enables the ne gain setting
given by register 0x11, channel ne gain. If fgain_en is
‘0’ the gain is set to 1.
The vcm_drive_cfg register congures the Common
Mode Voltage Output (VCM pin) driving strength. The
driving strengths, as listed below, are the maximum
currents from/to the VCM pin without exceeding
±50 mV error voltage on the pin.
vcm_drive_cfg<1:0> VCM output driving strength
00 OFF
01 0.1 mA
10 2 mA
11 (de f ault) 4 mA
The register bit pd_pin_cfg sets the function of the PD
pin to either Power Down (‘0’ - default) or Sleep (‘1’).
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Register 0x04 – Idle Mode Control
bit Type Name Default Description
0R/W pd 0Sets Chip to
Power Down Mode
5:4 R/W pd_ch 00 Set Channel-wise Power
Down Modes
8R/W sleep 0 Invokes Chip Sleep Mode
13:12 R/W sleep_ch 00 Set Channel-wise Sleep
Modes
The HMCAD1063 includes power down and sleep idle
modes for power management. The sleep modes offer
short start up times while the power down modes offer
extremely low power dissipation.
The register bit pd sets the Chip Power Down Mode,
powering down the entire chip. All register values are
maintained during Chip Power Down Mode, as long
as reset in register 0x00 is not activated. All internal
circuitry is turned off during Chip Power Down Mode,
but SPI registers may still be written to and read from.
The register bits pd_ch set the Channel-wise Power
Down Modes according to the table below. Setting
both channels in power down (‘11’) is not equal to
using Chip Power Down Mode, as LCLK and VCM
outputs will be active.
pd _ch<1:0> Channel 1 Channel 0
00 (default) Active Active
01 Active Power Down
10 Power Down Active
11 Power Down Power Down
The register bit sleep sets the Chip Sleep Mode, with
short start up time. The LCLK and VCM outputs are
active in sleep mode.
The register bits sleep_ch set Channel-wise Sleep
Modes according to the following table. The Channel-
wise Sleep Modes are similar to the Channel-
wise Power Down Modes, but has higher power
consumption and shorter start up time.
sleep_ch<1:0> Channel 1 Channel 0
00 (default) Active Active
01 Active Sleep
10 Sleep Active
11 Sleep Sleep
Register 0x05 – Recalibration by SPI
bit Type Name Default Description
0AUTO-
CLEAR recal_by_spi 0Initiates
re-calibration
Setting the recal_by_spi register bit to ‘1’, starts the
calibration of HMCAD1063. ADC output data will be
invalid during the calibration sequence. The register
will be reset when the calibration is nished.
During the calibration sequence the ADC input clock
must be operated continuously at the frequency that
will be used during operation. Analog input signals will
not impact the calibration. The SPI interface must not
be used during calibration.
Recalibration by SPI is equivalent to using the CAL
pin.
This calibration is invoked during the Startup
Sequence when setting adc_en = ‘1’. A re-calibration
is recommended when external conditions changed
considerably, such as sampling rate, supply voltage,
or ambient temperature.
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250/400/500 MSPS
Register 0x10 – Full Scale Range
bit Type Name Default Description
3:0 R/W fsr_ch0 0001 Congures Full Scale
Range for channel 0
11:8 R/W fsr_ch1 0001 Congures Full Scale
Range for channel 1
Full Scale Range can be set for each channel
separately. The conguration is described in this table:
Table 4. Conguration of
Full Scale Range (FSR)
fsr_ ch0<3:0>
fsr_c h1<11:8> Name Full Scale
Range [Vpp]
0001 (default) FSRHI 2.0
0100 FSRLO 1.4
In addition, the Full Scale Range of HMCAD1063 can
be ne-tuned, see “Register 0x21 – Full Scale Range
Tuning” on page 22.
Register 0x11 – Programmable Fine Gain
bit Type Name Default Description
7:0 R/W fgain_ch0 0000 0000
factor 1x
Programmable ne gain,
channel 0
15:8 R/W fgain_ch1 0000 0000
factor 1x
Programmable ne gain,
channel 1
Digital ne gain can be set for each channel separately.
ne_gain_en must be set to ‘1’, see also “Register
0x01 – Device Conguration”, and Table 5.
Table 5. Fine Gain Factors
fgain_ch0<7:0>
fgain_ch1<7:0> Arithmetic function Fine gain
factor [x]
0111 1111 out =
in  (1+2-4+2-5+2-6+2-7+2-8+2-9+2-10)1.124 0
0111 1110 out = in  (1+2-4+2-5+2-6+2-7+2-8+2-9)1.1230
0111 1101 out = in  (1+2-4+2-5+2-6+2-7+2-8+2-10)1.1221
… … …
0000 0010 out = in  (1+2-9)1.0020
0000 0001 out = in  (1+2-10)1.0010
0000 0000 out = in 1
1111 1111 out = in 1
1111 1110 out = in  (1-2-10)0.9990
1111 1101 out = in  (1-2-9)0.9980
… … …
1000 0010 out = in  (1-2-4-2-5-2-6-2-7-2-8-2-10)0.8779
1000 0001 out = in  (1-2-4-2-5-2-6-2-7-2-8-2-9)0.8770
1000 0000 out =
in  (1-2-4-2-5-2-6-2-7-2-8-2-9-2-10)0.8760
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250/400/500 MSPS
Register 0x20 – LVDS Control
bit Type Name Default Description
1:0 R/W lvdsterm_ctrl 00
Sets LVDS output
(data and clock) ter-
mination resistance
4R/W lvdscurr_ctrl 0Selects RSDS ('0') or
LVDS ('1') Mode
5R/W scramble_en 0
Enable scrambling
of LVDS output with
each channel’s LSB
8R/W fad_en 0Enable FAD output
lvdsterm_ctrl sets the termination resistance of the
LVDS outputs according to the following table:
lvdsterm_ctrl Nominal termination value
00 (default) Not terminated
01 200 
10 200 
11 100
lvdscurr_ctrl sets the LVDS signalling level. The LVDS
output currents can be set to the RSDS (Reduced
Swing Differential Signaling) or LVDS (Low Voltage
Differential Signaling) currents:
lvdscurr_ctrl LVDS output Mode LVDS output current
0 (default) RSDS 1.75 mA
1LVDS 3.5 mA
scramble_en, if set to ‘1’, scrambles the data of both
LVDS outputs by multiplication by each individual
LSB. This can assist noise reduction within the LVDS
part of the signal chain.
When fad_en is set to ‘1’, 2-bit Fast Amplitude Detect
(FAD) Outputs are available, see Table 6.
LCLK runs at the same frequency as the sampling rate
(Fs).
Channel 0 is output on the positive edge of LCLK and
channel 1 on the negative edge of LCLK, as shown in
the timing diagram in Figure 1.
The output pairs not used are powered down. The
modes dened by fad_en are listed in Table 6. The
corresponding LVDS pin-mappings are given in Table
7.
Table 6. Data Output Modes
fad_en # Data bits per channel FAD output Mode LVDS data update rate
0 (default) 14 <15:2> Disabled 2  Fs
114 <15:2> 2-bit <1:0> 2  Fs
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DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Table 7. LVDS Pin Mapping
FAD disabled FAD enabled
LVDS pair rst slice
phi 0
second slice
phi 1
rst slice
phi 0
second slice
phi 1
DX0<7> DATA0<13> DATA0<12> DATA0<13> DATA0<12>
DX0<6> DATA0 <11> DATA0<10> DATA0<11> DATA0<10>
DX0<5> DATA0<9> DATA0<8> DATA0<9> DATA0<8>
DX0<4> DATA0<7> DATA0<6> DATA0<7> DATA0<6>
DX0<3> DATA0<5> DATA0<4> DATA0<5> DATA0<4>
DX0<2> DATA0<3> DATA0<2> DATA0<3> DATA0<2>
DX0<1> DATA0<1> DATA0<0> DATA0<1> DATA0<0>
DX0<0> - - FAD0<1> FAD0<0>
DX1<7> DATA1<13> DATA1<12> DATA1<13> DATA1<12>
DX1<6> DATA0<11> DATA0<10> DATA1<11> DATA1<10>
DX1<5> DATA0<9> DATA0<8> DATA1<9> DATA1<8>
DX1<4> DATA0<7> DATA0<6> DATA1<7> DATA1<6>
DX1<3> DATA0<5> DATA0<4> DATA1<5> DATA1<4>
DX1<2> DATA0<3> DATA0<2> DATA1<3> DATA1<2>
DX1<1> DATA0<1> DATA0<0> DATA1<1> DATA1<0>
DX1<0> - - FAD1<1> FAD1<0>
Table 8 describes the Fast Amplitude Detect (FAD)
outputs. The FAD will serve as a 2-bit low latency
ADC, converting the analog input amplitude to a digital
value. This allows the FAD outputs to be utilized as
an Received Signal Strength Indicator, providing the
signal strength at a lower latency compared to the
Data output. The Input Amplitude column in the table
shows the Amplitude in V peak-to-peak.
When 2-bit FAD is activated, the FAD0<1:0> and
FAD1<1:0> outputs will provide a low latency 2-bit
signal proportional with the Input Amplitude for
channel 0 and channel 1, respectively.
Table 6 lists the combinations of the data output
modes and accompanying FAD modes. The usage of
LVDS pin pairs in different data output modes is listed
in Table 7.
Table 8. FAD Output Pin Function
Input Amplitude Vpp 2-bit FAD output
Value FADx<1:0>
> 0.94 3 11
0.44 to 0.94 2 10
0.19 to 0.44 1 01
< 0.19 000
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PRODUCT PREVIEW - ADC
22
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Register 0x21 – Full Scale Range Tuning
bit Type Name Default Description
13:8 R/W fsrtune 00 0000 Selects Full Scale Range
tuning factor
HMCAD1063 Full Scale Range can be either
FSRLO = 1.4 Vpp or FSRHI = 2.0 Vpp, see “Register
0x10 – Full Scale Range” on page 19.
In addition, the Full Scale Range can be ne tuned
by ca. ±7%, by multiplying the Full Scale Range in
Table 4 with the Full Scale Range tuning factor fsrtune
according to this table:
fsrtune Full Scale Range Tuning factor
01 1111 +7.0%
01 1110 +6.8%
… …
00 0001 +0.225%
00 0000 (default) +0%
11 1111 -0.225%
… …
10 0001 -7. 0%
10 0000 -7. 2 %
The Full Scale Range tuning will apply equally to
channel 0 and channel 1.
It’s mandatory to set adc_enable = ‘0’ before writing to
fsrtune, see also section “Startup Sequence” on page
16.
Table 9. Offset Compensation Times
offcomp_time_chx # of samples Compensation Time vs. Fs
125 MSPS 500 MSPS
000 (default) 212 0.016 ms 0.004 ms
001 214 0.066 ms 0.017 ms
010 217 0.524 ms 0.131 ms
011 220 4 ms 1 ms
100 222 17 ms 4 ms
101 225 134 ms 34 ms
110 228 1074 ms 269 ms
111 231 8600 ms 2150 ms
Register 0x35 – Offset Compensation
bit Type Name Default Description
2:0 R/W offcomp_
time_ch0 000
Sets number of samples used
for offset compensation for
channel 0
5AUTO-
CLR
offcomp_
start_ch0 0Invokes offset compensation
for channel 0
10:8 R/W offcomp_
time_ch1 000
Sets number of samples used
for offset compensation for
channel 1
13 AUTO-
CLR
offcomp_
start_ch1 0Invokes offset compensation
for channel 1
HMCAD1063 offset voltage may generate a non-zero
DC value. Due to the HMCAD1063 architecture, Offset
mismatch may give a tone in the Nyquist frequency
Fs/2.
For Time Domain applications the Offset Compensation
procedure described below is highly recommended to
minimize unwanted signal energy in DC and Fs/2.
1. Set adc_enable in register 0x00 to ‘1’ (if applicable –
see also “Startup Sequence” on page 16).
2. Disable the analog input signal or reduce the input
amplitude level as much as possible.
3. Set offcomp_start_chx to ‘1’. This triggers an
estimation of the offsets during a time periode
determined by offcomp_time_chx, and adjusts the
compensation accordingly.
The bits offcomp_start_chx are auto-clearing:
once the calibration is done, the bits D5 and D13 in
register 0x35 will read out as ‘0’ again.
The default compensation time (offcomp_time_
chx = 000) is appropriate when the ADC analog
input signal is shorted while offcomp_start_chx = 1.
If there is a residual signal at the ADC input, longer
compensation times may be necessary, see Table
9.
In applications where DC and FS/2 are critical it is
recommended to use offcomp_time_chx = ‘011’ or
higher, see Table 9.
4. When offcomp_start_chx is ‘0’ again, the ADC will
output data with compensated Offsets.
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PRODUCT PREVIEW - ADC
23
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Register 0x59 – Temperature Sensors
bit Type Name Default Description
8:0 Rtemp_val 0x00 Temperature value
14 Rtemp_valid 0‘1’ after temperature mea-
surement is completed
15 R/W activate_tempm 0Triggers a temperature
measurement
HMCAD1063 includes a built-in temperature sensor.
To perform a temperature measurement, the register
activate_tempm must be set to ‘1’. The register
bit temp_valid is set to ‘1’ when the temperature
measurement is completed, and subsequently, the
temperature can be read from the register temp_val.
Based on the value of the signed integer temp_val, the
corresponding temperature T can be calculated in °C:
T = temp_val 1.21°C
temp_val
bit value
temp_val
signed integer Temperature in °C
0 1111 1111 + 255 + 309 °C
0 1111 1110 + 254 + 307 °C
………
0 0000 0001 + 1 + 1.2 °C
0 0000 0000 0 0 °C
1 1111 1111 –1 – 1.2 °C
………
1 0000 0001 – 255 – 309 °C
1 0000 0000 – 256 – 310 °C
Note: The theoretical range of temp_val exceeds
the Absolute Maximum Ratings. Be aware that the
Absolute Maximum Ratings refer to enviromental
conditions, whereas temp_val is rather the core
temperature.
Register 0x70 – Test Patterns
bit Type Name Default Description
0R/W ramp_en 0Enable a repeating full scale ramp
pattern out
1R/W single_cust_
pat_en 0 Enable pattern 0 on ch0 and ch1
2R/W dual_cust_
pat_en 0Enable toggling patterns 0 and 1
on both ch0 and ch1
3R/W prbs_en 0Enables a pseudo random bit se-
quence on each LVDS output pair
For LVDS data output debug purposes, a set of test
patterns is available.
Setting ramp_en to ‘1’, outputs a ramp signal on both
data channels. The ramp on channel 0 starts at code
0x0000 and steps up by one per clock cycle. When the
ramp reaches value 0x3FFF it wraps to code 0x0000.
The ramp on channel 1 starts at 0x3FFF and steps
down by one per clock cycle and wraps around from
0x0000 to 0x3FFF.
Setting single_cust_pat_en to ‘1’ outputs custom_
pattern0 (given by register 0x71) on both channel 0
and channel 1.
Setting dual_cust_pat_en to ‘1’ toggles between
custom_pattern0 on both channels simultaneously,
and custom_pattern1 (content of register 0x72).
Setting prbs_en to ‘1’ outputs a pseudo random bit
sequence on each of the LVDS output pairs.
If the FAD output is activated (fad_en = ‘1’ in Register
0x20 – LVDS Control), the content of register 0x73 will
be output according to single_cust_pat_en and dual_
cust_pat_en.
If both fad_en and ramp_en are activated, the
concatenations of FAD and data on the LVDS channels
will result in 16-bit counters.
Note that only one test pattern must be enabled at a
single time.
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PRODUCT PREVIEW - ADC
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HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Registers 0x71, 0x72 – Custom Patterns
Register bit Type Name Default Description
0x71 15:0 R/W custom_pattern0 0x5555 Custom pattern 0
0x72 15:0 R/W custom_pattern1 0xAAAA Custom pattern 1
The content of these registers is used if either single_
cust_pat_en or dual_cust_pat in register 0x70 is set
to ‘1’.
Register 0x73 – Custom Patterns for FAD
bit Type Name Default Description
3:0 R/W custom_fad_pattern0 0x5 Custom pattern 0
7:4 R/W custom_fad_pattern1 0xA Custom pattern 1
The content of this register is used if either single_
cust_pat or dual_cust_pat in register 0x70 is set to ‘1’,
and FAD output is enabled according to Table 6.
If 2-bit FAD is activated, only the two LSB of custom_
fad_patternx are used.
Registers 0x7E and 0x7F –
Vendor and Chip ID
Register bit Type Name Default Description
0x7E 15:0 Rvendor_id 0xADC Vendor ID
0x7F 15:0 Rchip_id
250 MSPS: 0x1
Chip ID400 MSPS: 0x3
500 MSPS: 0x4
Register vendor_ id can be read to verify the vendor
ID of the chip.
Register chip_id can be read to verify the product
variant identication code for the chip.
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Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
25
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Figure 1. Performance vs. Fin, 250 MSPS
Ain = -1 dBFS, Fs = 250 MSPS, FSRLO = 1.4 Vpp
Figure 3. Performance vs. Fin, 400 MSPS
Ain = -1 dBFS, Fs = 400 MSPS, FSRLO = 1.4 Vpp
Figure 5. Performance vs. Fin, 500 MSPS
Ain = -1 dBFS, Fs = 500 MSPS, FSRLO = 1.4 Vpp
Figure 2. Performance vs. Fin, 250 MSPS
Ain = -1 dBFS, Fs = 250 MSPS, FSRHI = 2.0 Vpp
Figure 4. Performance vs. Fin, 400 MSPS
Ain = -1 dBFS, Fs = 400 MSPS, FSRHI = 2.0 Vpp
Figure 6. Performance vs. Fin, 500 MSPS
Ain = -1 dBFS, Fs = 500 MSPS, FSRHI = 2.0 Vpp
65
70
75
80
85
90
95
0 100 200 300 400 500
SNR (dBFS)
SNDR (dBFS)
SFDR (dBc)
HD2 (dBc)
HD3 (dBc)
PERFORMANCE (dB)
FREQUENCY (MHz)
65
70
75
80
85
90
95
0 50 100 150 200 250 300 350 400
SNR (dBFS)
SNDR (dBFS)
SFDR (dBc)
HD2 (dBc)
HD3 (dBc)
PERFORMANCE (dB)
FREQUENCY (MHz)
60
65
70
75
80
85
90
95
100
0 100 200 300 400 500
SNR (dBFS)
SNDR (dBFS)
SFDR (dBc)
HD2 (dBc)
HD3 (dBc)
PERFORMANCE (dB)
FREQUENCY (MHz)
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400
SNR (dBFS)
SNDR (dBFS)
SFDR (dBc)
HD2 (dBc)
HD3 (dBc)
PERFORMANCE (dB)
FREQUENCY (MHz)
65
70
75
80
85
90
95
100
105
0 100 200 300 400 500
SNR (dBFS)
SNDR (dBFS)
SFDR (dBc)
HD2 (dBc)
HD3 (dBc)
PERFORMANCE (dB)
FREQUENCY (MHz)
65
70
75
80
85
90
95
0 50 100 150 200 250 300 350 400
SNR (dBFS)
SNDR (dBFS)
SFDR (dBc)
HD2 (dBc)
HD3 (dBc)
PERFORMANCE (dB)
FREQUENCY (MHz)
P r e l i m i n a r y
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Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
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HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Figure 7. Performance vs. Input Amplitude
Fs = 250 MSPS, Fin = 141 MHz, FSRLO = 1.4 V
Figure 9. Performance vs. Input Amplitude
Fs = 400 MSPS, Fin = 141 MHz, FSRLO = 1.4 V
Figure 11. Performance vs. Input Amplitude
Fs = 500 MSPS, Fin = 141 MHz, FSRLO = 1.4 V
Figure 8. Performance vs. Input Amplitude
Fs = 250 MSPS, Fin = 141 MHz, FSRHI = 2.0 V
Figure 10. Performance vs. Input Amplitude
Fs = 400 MSPS, Fin = 141 MHz, FSRHI = 2.0 V
Figure 12. Performance vs. Input Amplitude
Fs = 500 MSPS, Fin = 141 MHz, FSRHI = 2.0 V
50
60
70
80
90
100
-35 -30 -25 -20 -15 -10 -5 0
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
PERFORMANCE (dB)
INPUT SIGNAL LEVEL (dBFS)
50
60
70
80
90
100
-35 -30 -25 -20 -15 -10 -5 0
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
PERFORMANCE (dB)
INPUT SIGNAL LEVEL (dBFS)
50
60
70
80
90
100
-35 -30 -25 -20 -15 -10 -5 0
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
PERFORMANCE (dB)
INPUT SIGNAL LEVEL (dBFS)
50
60
70
80
90
100
-35 -30 -25 -20 -15 -10 -5 0
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
PERFORMANCE (dB)
INPUT SIGNAL LEVEL (dBFS)
50
60
70
80
90
100
-35 -30 -25 -20 -15 -10 -5 0
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
PERFORMANCE (dB)
INPUT SIGNAL LEVEL (dBFS)
50
60
70
80
90
100
-35 -30 -25 -20 -15 -10 -5 0
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
PERFORMANCE (dB)
INPUT SIGNAL LEVEL (dBFS)
P r e l i m i n a r y
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Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
27
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Figure 13. Differential Nonlinearity – DNL
250 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0 V
Figure 15. Differential Nonlinearity – DNL
400 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0 V
Figure 17. Differential Nonlinearity – DNL
500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, FSRHI = 2.0 V
-1
-0.5
0
0.5
1
DNL (LSB)
CODE (bit)
-1
-0.5
0
0.5
1
DNL (LSB)
CODE (bit)
-1
-0.5
0
0.5
1
DNL (LSB)
CODE (bit)
Figure 14. Integral Nonlinearity – INL
250 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0 V
Figure 16. Integral Nonlinearity – INL
400 MSPS, Fin = 71 MHz, Ain = -1 dBFS, FSRHI = 2.0 V
Figure 18. Integral Nonlinearity – INL
500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, FSRHI = 2.0 V
-3
-2
-1
0
1
2
3
INL (LSB)
CODE (bit)
-3
-2
-1
0
1
2
3
INL (LSB)
CODE (bit)
-3
-2
-1
0
1
2
3
INL (LSB)
CODE (bit)
P r e l i m i n a r y
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Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
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HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Figure 19. Single Tone FFT – 250 MSPS
Fin = 80 MHz, Ain = -3 dBFS, FSRHI = 2.0 V
Figure 20. Single Tone FFT – 400 MSPS
Fin = 80 MHz, Ain = -3 dBFS, FSRHI = 2.0 V
Figure 21. Single Tone FFT – 500 MSPS
Fin = 80 MHz, Ain = -3 dBFS, FSRHI = 2.0 V
-120
-100
-80
-60
-40
-20
0
0 20 40 60 80 100 120
AMPLITUDE (dBFS)
FREQUENCY (MHz)
-120
-100
-80
-60
-40
-20
0
0 50 100 150 200
AMPLITUDE (dBFS)
FREQUENCY (MHz)
-120
-100
-80
-60
-40
-20
0
0 50 100 150 200 250
AMPLITUDE (dBFS)
FREQUENCY (MHz)
P r e l i m i n a r y
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PRODUCT PREVIEW - ADC
29
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Theory of Operation
HMCAD1063 is a Dual channel 14-bit A-to-D Converter
(ADC). The ADC employs a Pipeline Converter archi-
tecture. Each Pipeline Stage feeds its output data into
the digital error correction and calibration logic, ensur-
ing excellent differential linearity and no missing codes.
HMCAD1063 utilizes a parallel LVDS output. 2:1 muxes
are inserted between the ADC output and LVDS inter-
face, so that even numbered bits are muxed with the
according odd numbered bits of each channel before
being applied to the LVDS interface.
The timing of the LVDS interface is provided in the
LVDS timing diagram on page 13.
Reduced Swing Differential Signalling (RSDS) is se-
lected by default. The I/O current is set to 1.75 mA
compared to 3.5 mA for LVDS. This will result in the
best power dissipation and data integrity for most ap-
plications. Standard LVDS I/O current can be selected
through the SPI interface if desired.
HMCAD1063 uses internally generated references. The
default differential reference value is 1 V. This results in
a differential input of −1 V to correspond to the mini-
mum code of the ADC, and a differential input of +1 V
to correspond to the max code This gives a default Full
Scale Range of 2 Vpp. Section “Register 0x21 – Full
Scale Range Tuning” on page 22 describes how to
adjust the Full Scale Range.
HMCAD1063 operates from two sets of supplies and
grounds. The analog supply and ground set is identied
as AVDD and AVSS, while the digital set is identied by
DVDD and DVSS.
Recommended Usage
Analog Input
The analog input to the HMCAD1063 is a switched ca-
pacitor sample-and-hold circuit optimized for differen-
tial operation.
Operation at common mode voltages of 5/9 of the
analog supply voltage (1 V for 1.8 V supply voltage)
is recommended even if performance will be good for
the ranges specied. The VCM pin provides a voltage
suitable as common mode voltage reference. The inter-
nal buffer for the VCM voltage can be switched off, and
driving capabilities can be changed programming the
vcm_drive_cfg register.
Figure 4. HMCAD1063 switched capacitor input
Figure 4 shows a simplied drawing of the switched ca-
pacitor input of HMCAD1073. During the Sample phase
(S) the analog input signal is sampled on the sampling
capacitors (CS). During the Hold Phase (H) the sam-
pled signal is held to the succeeding pipeline stage. CS
contributes to the total ADC input capacitance (CIN).
The charge sampled to CS at the Sampling rate will
represent a resistive load (RIN) to the ADC driver. The
total ADC input capacitance (CIN) value can be found
in “Digital and Switching Specications” on page 3.
Figure 5 shows a model of the ADC input including RC
shunt and RIN. The CIN parameter is equivalent to the
total capacitance between the ADC analog inputs. Val-
ues for RIN can be found in the section “DC Electrical
Specications” on page 3.
A small external resistor (e.g. 22 ) in series with each
input is recommended as it helps reducing transient
currents and dampens ringing behavior. A small differ-
ential shunt capacitor at the chip side of the resistors
may be used to provide dynamic charging currents and
may improve performance. The resistors form a low
pass lter with the capacitor, and values must therefore
be determined by requirements for the application.
P r e l i m i n a r y
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PRODUCT PREVIEW - ADC
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HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Figure 5. Double Balun based input network
DC-Coupling
For DC coupling the common mode input voltage from
the ADC driver must match the VCM,IN specication giv-
en in “DC Electrical Specications” on page 3. Pref-
erably, the ADC common mode output voltage (VCM
pin) should be used as reference to set the common
mode input voltage.
AC-Coupling
A double balun conguration is recommended for high
performance AC-coupled input network. Figure 5 shows
a recommended conguration utilizing a double balun
conguration. The balun termination resistors (R1) de-
ne the impedance of the input network. A shunt RC
(R2 and C3) to ground from each of the input signals
eliminates both differential and single ended large sig-
nal effects from the ADC kick-back charges.
Recommended Analog Input component values:
Component Value
C1 1 nF
C2 1 nF
R1 28 
C3 10 pF
R2 20 
Make sure that a transformer with sufficient linearity is
selected, and that the bandwidth of the transformer is
appropriate. It is important to minimize second order
distortion. This type of transformer coupled input is the
preferred conguration to optimize Signal to Noise Ra-
tio. A differential amplier or differential Variable Gain
Amplier may result in higher linearity since they most
often are less dependent on a pure resistive load. Mag-
netic coupling between the transformers and PCB trac-
es may impact channel crosstalk, and must hence be
taken into account during PCB layout.
Due to the switched nature of the ADC input stage,
there will be some kick-back going from the ADC input
and back into the driver. If these kick-backs are not ter-
minated properly at the source side, they are reected
and will add to the input signal at the ADC input. This
could reduce the ADC performance. To avoid this ef-
fect, the source must effectively terminate the ADC
kick-backs, or the traveling distance should be very
short.
Differential ampliers are often suited to terminate the
kick-back efficiently. It is of utmost importance that the
amplier is placed close to the ADC input to minimize
any transmission line effects on the trace from the am-
plier to the ADC input. The bandwidth in this node
should also be maximized to allow the kick-back to
settle within the available time. In Figure 5 the ADC
common mode setup for AC-Coupling is shown. By
connecting the termination resistors (R1) to the ADC
VCM output, the ADC Common mode voltage will be
set up correctly given an AC-coupling capacitor (C1) to
control the lower passband frequency.
The value of C1 must be dened based on the
requirement to the high-pass cut-off frequency.
Note that Start Up Time from Sleep Mode and Power
Down Mode will be affected by this lter as the time
required to charge the series capacitors is dependent
on the lter cut-off frequency.
P r e l i m i n a r y
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PRODUCT PREVIEW - ADC
31
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Clock Input and Jitter Considerations
In HMCAD1063 only the rising edge of the clock is
used.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, hence a wide
common mode voltage range is accepted. Differential
clock sources such as LVDS, LVPECL or differential
sine wave can be utilized. The clock input has 100
differential termination. Additional termination, if re-
quired by the clock driver, must be placed as close to
the ADC clock pins as possible. The quality of the input
clock is extremely important for high-speed, high-res-
olution ADCs. The contribution to SNR from clock jitter
with a full scale signal at a given frequency is shown in
equation 1.
SNRjitter = – 20 · log(2 · π · ƒIN · Tjrms) (1)
where ƒIN is the signal frequency, and Tjrms is the root-
mean-square (rms) ADC clock jitter measured in sec-
onds.
It is of utmost importance to limit the clock jitter for ap-
plications where jitter may limit the obtainable perfor-
mance. This can be obtained by using precise and sta-
ble clock references (e.g. crystal oscillators with good
jitter specications) and make sure the clock distribu-
tion is well controlled. It might be advantageous to use
analog power and ground planes to ensure low noise
on the supplies to all circuitry in the clock distribution. It
is of utmost importance to avoid crosstalk between the
ADC output bits and the clock and between the analog
input signal and the clock since such crosstalk often
results in harmonic distortion.
The jitter performance is improved with reduced edge
times of the input clock. Hence, optimum jitter perfor-
mance is obtained with LVDS or LVPECL clock with low
edge times. For sine wave clock inputs, the amplitude
should be as high as possible to minimize the edge
time. To avoid exceeding the clock input maximum lev-
els, a clamping diode can be utilized.
Using PLL/VCOs as Clock Generator
When the direct ADC clock generation is not available,
a high performance PLL/VCO should be utilized to gen-
erate a low jitter master clock. This should be applied to
the ADC either directly or through a fan out buffer.
The recommended PLL/VCOs for HMCAD1063 are
HMC1032LP6GE for excellent clock jitter, and HMC
1033LP6GE for an excellent combination of low clock
jitter and low power consumption. The recommended
fan out buffer is HMC987LP5E.
Fast Amplitude Detect (FAD) Output
Fast Amplitude Detect (FAD) output bits are indicating
the amplitude of the input signal with a very low
latency, see “Digital and Switching Specications” on
page 3.
Depending on the LVDS output mode settings, Table
6, either 0, 2 or 4 FAD bits are available.
The FAD will serve as a 2- or 4-bit low latency ADC,
converting the analog input amplitude to a digital
value. This allows the FAD outputs to be utilized as
an Received Signal Strength Indicator, providing the
signal strength at a lower latency compared to the
Data output. See “Register 0x20 – LVDS Control” on
page 20 for a detailed description.
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
32
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
Denition of Terms
Analog Input Bandwidth (AIBW) The maximum
analog input frequency where proper ADC performance
is achieved. Above this frequency missing codes will
be expected.
Aperture delay (tAD) The delay difference between
Analog and Clock inputs to sampling.
tAD = Tsd – Tid, where
Tsd delay from Clock input to sampling, and
Tid delay from Analog input to sampling.
Aperture jitter (tjrms) The sample-to-sample variation
in Aperture delay.
Cross Talk (Xtlk) Crosstalk is the signal coupling
between the ADC channels, and is measured by
applying full scale signals to both an adjacent channel
and to the channel of interest. The crosstalk is the ratio
of power in between the signal applied to the adjacent
channel and the signal power at the channel of interest
that origin from the adjacent channel.
Decibel – carrier (dBc) A unit where the parameter
is measured by comparing to the applied fundamental
(or carrier) power in the given test.
Decibel – Full Scale (dBFS) A unit where the
parameter is measured by comparing to the theoretical
maximum fundamental power based on Full Scale
Range.
Differential Non-Linearity (DNL) The DNL is the
deviation from the ideal voltage that causes a change
of one single code (1 LSB). The DNL plot is a diagram
showing this deviation for all the codes in the ADC.
The DNL parameter is the worst case value on this
diagram.
Effective Number of Bits (ENOB) Measures the
converter performance in terms of number of bit
resolution, based on a perfect ADC with quantization
noise.
ENOB = (SNDR – 1.76)/6.02.
Full Scale Range (FSR) The voltage difference at the
analog input of the ADC between the voltage that will
generate the maximum digital output code, and the
voltage that will generate the minimum digital output
code.
When referring to deviation in Full Scale Range this
means that the analog voltages giving max/min output
code are different from the theoretical values. A Full
Scale Range fundamental is a sine wave where the
lowest value gives minimum output code and the
highest value gives maximum output code.
Noise Power Bandwidth (NoiseBW) The analog
input frequency where the power of the fundamental
is reduced by 3 dB compared to the low-frequency
value.
Gain error (Gabs) The deviation from ideal Full Scale
Range. This parameter is independent from Grel.
Gain atness The input frequency range where the
Gain variation is within the specied number of dB.
Gain matching (Grel) The mismatch in Full Scale
Range between the ADC channels. This parameter is
independent from Gabs.
Integral Non-Linearity (INL) The INL is the deviation
of the ADC transfer function from an ideal straight
line. The INL plot is this deviation generated with the
best t method for the ADC Full Scale range. The INL
parameter is the worst case value on this line.
Intermodulation Distortion (IMD) IMDs are spectral
spurs due to nonlinearities that occur when two
frequencies f1 and f2 are processed simultaneously.
IMD2 is the worst 2nd order spur, i.e. f1+f2 or f1-f2.
In-Band IMD3 is the worst 3rd order spur close to the
original frequencies, i.e. 2f1-f2 or 2f2-f1.
IMD3 is the worst of all 3rd order spurs: 2f1-f2, 2f2-f1,
2f1+f2, and 2f1+f1.
Signal to Noise Ratio (SNR) The ratio of the power of
the fundamental to the power of the noise measured
in dB. SNR excludes DC, harmonics and interleaving
spurs.
Signal to Noise and Distortion Ratio (SNDR) The
ratio of the power of the fundamental to the power
of the noise and distortion measured in dB. SNDR
excludes DC.
Spurious Free Dynamic Range (SFDR) The ratio
of the power of the fundamental to the power of the
highest harmonic or spurious component.
P r e l i m i n a r y
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343 Fax: +1 978-250-3373 Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
PRODUCT PREVIEW - ADC
33
HMCAD1063
Product Preview - 2.0214
DUAL CHANNEL 14-BIT A-TO-D CONVERTER (ADC)
250/400/500 MSPS
The circuit board used in the application should use RF
circuit design techniques. Signal lines should have 50 Ohm
impedance while the package ground leads and exposed
paddle should be connected directly to the ground plane
similar to that shown. A sufficient number of via holes should
be used to connect the top and bottom ground planes. The
evaluation circuit board shown is available from Hittite upon
request.
Evaluation Order Information
Item Contents Part Number
Evaluation PCB Only HMCAD1063 Evaluation PCB EV1HMCAD1063LP9DE [1]
Evaluation Kit
HMCAD1063 Evaluation PCB
Zynq 7020 evaluation board – Zedboard,
USB memory stick containing users manual and software,
Ethernet cable, attenuators.
EK1HMCAD1063LP9DE [2]
[1] Reference this number when ordering Evaluation PCB Only
[2] Reference this number when ordering an HMCAD1063 Evaluation KIt
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in
the operational section of this specication is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Document Changes
Version Comment
v0.0114 Initial release
Product Preview - 2.0214 Specications completed, performance plots added, FSR adjusted
P r e l i m i n a r y