M29F040B70N1 - STMicroelectronics

1/21April 2002

M29F040B

4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Me mory

■SINGLE 5V ± 10% SUPPLY VOLTAGE for

PROGRAM, ERASE and R EAD O PER AT IONS

■ACCESS TIME: 4 5ns

■PRO GRAMMIN G TIME

– 8 µs per Byte typical

■8 UNIFORM 64 Kbytes MEMORY BLOCKS

■PROGRAM/ERASE CON TROLLER

– Embedded Byte Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Pol ling and Toggle Bits

■ERASE SUSPEND and RESUM E MOD ES

– Read and Program another Block during

Erase Su spend

■UNLOCK BYPASS PROGRAM COMM AND

– Faster Produc tion/Batc h Prog ramming

■LOW POWER CONSUM PTION

– Standby and Automat ic Standby

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■20 YEAR S DATA RETENTION

– Defect ivity below 1 ppm/ye ar

■ELECTRONIC SIG NATURE

– Manufacturer Code: 20h

– Device Code : E2h

TSOP32 (N)

8 x 20mm

PLCC32 (K)

PDIP32 (P)

Figure 1. Logic Diagram

AI02900

A0-A18

DQ0-DQ7

VCC

M29F040B

VSS

M29F040B

2/21

Figure 2 . PLCC Connection s

AI02901

A17

A13

A10

DQ5

DQ0

DQ1

DQ2

DQ3

DQ4

A16

DQ7

A12

A14

A18

VCC

M29F040B

A15

A11

DQ6

VSS

Figu re 3. TSOP C onnec tion s

DQ0

A4 A3

A13

A10

DQ7

A14

A11 G

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A17

A16

A12

A18

VCC

A15

AI02902

M29F040B

16 17

VSS

Figu re 4. PD IP C onnecti on s

DQ0

A13

A10

DQ7

A14

A11

DQ5DQ1

DQ2 DQ3VSS DQ4

DQ6

A17

WA16

A12

A18 VCC

A15

AI02910

M29F040B

Table 1. Sign al Names

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

EChip Enable

GOutput Enable

WWrite Enable

VCC Supply Voltage

VSS Ground

3/21

M29F040B

SUMMARY DESCRIPTION

The M29F040B is a 4 Mbit (512Kb x 8) non-vol atile

memory that can be read, erased and repro-

grammed. These operations can be per formed us -

ing a single 5V supply. On power-up the memory

defaults to its Read mode where it can be read in

the same way as a ROM or EPROM. The

M29F040B is fully backward compatible with the

M29F040.

The memory is divided into blocks that can be

erased independently so it is pos sible to preserv e

va l i d da t a w hi le o l d da t a is eras ed . E ac h bl oc k ca n

be protected independently to prevent accidental

Program or Erase commands from modifying the

memo ry. Program and Erase comm ands are writ-

ten to the Com mand Interface of the mem ory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the speci al operations that are

required to update the mem ory co ntents. The end

of a pro gram or erase operation can be detected

and any error conditions iden tified. Th e comm and

set required to control the memory is consistent

with JEDEC s tandards.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, of ten without additional logic.

The memory is offered in TSOP32 (8 x 20mm),

PLCC32 an d PDIP32 p ackages and it is suppl ied

with all t he bits erased (set to ‘1’).

Table 2. Absol ute Maximum Ratings (1)

Note: 1. Exc ept for th e rati ng "Ope rating T em perature Range" , s tress es above those l i sted in the T able "A bsolu te Maxim um Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indica ted i n t he O perati ng secti ons of this specification is not i m pl i ed. E xposure to Abs ol ut e Max i m um Rat i ng condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity docume nt s.

2. Mini m um Voltage may undershoot to –2 V duri ng transiti on and for less than 20ns during tran sitions.

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C

Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C

TBIAS Temperature Unde r Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage –0.6 to 6 V

VCC Supply Voltage –0.6 to 6 V

VID Identification Voltage –0.6 to 13.5 V

Table 3. Uniform Block Addresse s, M29F04 0B

#Size

(Kbytes) Address Range

7 64 70000h-7FFFFh

6 64 60000h-6FFFFh

5 64 50000h-5FFFFh

4 64 40000h-4FFFFh

3 64 30000h-3FFFFh

2 64 20000h-2FFFFh

1 64 10000h-1FFFFh

0 64 00000h-0FFFFh

M29F040B

4/21

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diag ram, and T able 1, Sign al

Names, for a brief overview of the s ignals connect -

ed to this device.

Address Inputs (A0-A18). The Address Inputs

select the cell s in the memory arra y to access dur-

ing Bus Read operations. During Bus Writ e opera-

tions they control the commands sent to the

Comman d Interface of the internal stat e ma chine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Chip Enable (E). The Chip Enable, E, activates

the memor y, allowing Bus Read and Bus Wr ite op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

ma nd Inte r face.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is dis abled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevent s Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being alt ered will be invalid.

A 0.1µF capacitor should be connected between

the V CC Supply Voltage pin and the VSS Ground

pin to decoupl e the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operat ions, ICC4.

VSS Ground. The VSS Ground is the reference for

all voltage measureme nts.

BUS OPERATIONS

There are five s tandard bus operations that control

the device. These are Bus Read, Bus Wri te, Out-

put Disable, Standby and Automatic Standby. See

Table 4, Bus Operations, for a summary. Ty picall y

glitches of less than 5ns on Chip E nable o r Write

Enable are i gnored by t he mem ory and do not af-

fect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desi red address on the Address

Inputs, appl ying a Low s ig nal, V IL, to C hip E nable

and Output Enable and keeping Write Enable

High, VIH. The Dat a Input s/Ou tputs will outp ut the

value, see Figure 9, Read Mode AC Waveforms,

and Table 11, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desi red address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Int erface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Dat a Input s/Outpu ts a re latched by the Com -

mand Interface on the rising edge of Chip Ena ble

or Write Enable, whichever occurs first. Output En-

able must remai n High, VIH, during the whole Bus

Write operat ion. See Figures 10 and 11, Write AC

Waveforms, and Tables 12 and 13, Write AC

Characteristics, for details of the timing require-

ments.

Outp ut Disable . The Data Inputs/Outputs are in

the high impeda nce state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is re-

duced to the Standby level.

When Chip Enable is at VIH the Supply Current is

reduced to the TTL Standby Supply Current, ICC2.

To further reduce the Supply Current to the CMOS

Standby Supply Current, ICC3, Chip Enable should

be held within VCC ± 0.2V. For Standby current

levels see Table 10, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC4, for Program or Erase operations un-

til t he operat ion com pletes.

5/21

M29F040B

Table 4. Bus Ope rations

Note: X = VIL or VIH.

Operation E G W Address Inputs Data

Inputs/Outputs

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable XV

IH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,

Others VIL or VIH E2h

Aut omatic Standby. If CM OS le v els ( VCC ± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the CMOS Standby Supply Current, ICC3.

The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

Special Bus Operati ons

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require VID to be applied to some pins.

Electronic Sign atur e. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These co des can be re ad by app lying the si gnals

listed in Table 4, Bus Operations.

Block Protection and Blocks Unprotection. Each

block can be separately protected against acci-

dental Program or Erase. Protected blocks can be

unprotected to allow data to be changed. Block

Protection and Blocks Unprotection operations

must only be performed on programming equip-

ment. For further information refer to Application

Note AN1122, Applying P rotection and Unp rotec-

tion to M29 Series Flash.

M29F040B

6/21

COMMAND INTERFACE

All Bus Write operations t o the memory are in ter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a vali d sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The command s are summ arized in Table 5, Com -

mands. Refer to Table 5 in conjunction with the

text descriptions below.

Read/Reset Comm and. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM. It also resets

the errors in the Status Register. Either one or

three Bus Write operations can be used to issue

the Read/ Reset c ommand.

If the Read/Reset command is issued during a

Block Erase operation or following a Programming

or Erase error then the memory will take up to 10µs

to abort. During th e abort period no valid data can

be read from the memory. Issuing a Read/Reset

command during a Block Erase operation will

leave invalid data in the memory.

Auto Select Command. The Auto Select com-

mand i s us ed to read the Man ufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until another com-

mand is issued.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A 0 = VIL and A1 = VIL. The other address bits

may be set to either VIL or VIH. T he Ma nufa cturer

Code for STMicroelectronics is 20h.

The Device Code can b e read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either V IL or VIH. The

Device Code for the M29F 040B is E2h.

The B lock P rot ection S t atus of e ac h bl ock can be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A16, A17 and A18 specifying the ad-

dress of the blo ck. The o ther addres s bits may be

set to either VIL or VIH. If the addressed block is

protected then 01h is output on the Data Inputs/

Outputs, otherwise 00h is output.

Progra m Command . The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the me mory will ig-

nore all co mmands. I t is not poss ible t o issue any

command to abort or pause the operation. Typical

program times are given in Table 6. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set the error condition and return to Read mode.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Comma nd. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program c ommand to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass comm and.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Prog ram Comm an d. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write ope ra tions, the

final write operation latches the address and data

in the internal state machine and starts the Pro-

gram/Erase Controller.

The Program operation using the Unlock Bypass

Program c ommand behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be program m ed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, w hich l eaves the d evice in Unlo ck By-

pass Mode. See the Program command for details

on the behavior.

7/21

M29F040B

Table 5. Command s

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The C om m and Int erface only uses addre ss bi ts A0-A1 0 to veri fy the comm ands, t he upper address bits are Don’ t Care.

Re ad/Reset. After a Read/Reset command, re ad the memory as normal until another command is issued.

Auto Select. After a n A uto Selec t command, read Man ufactu rer ID, Device ID or Block P rot ection Status.

Pro gr am, Unl ock Bypass Progr am, Chi p E r ase, Bl o ck E r ase. Aft er thes e commands read th e Status Register until t he Pro gram/Erase

Co nt rol l er com p l et es a nd the memory returns to Read Mode. Add addi tional B l ocks dur in g Block E rase Com mand wi t h additional Bus Write

Operation s until the Ti meout Bit is set .

Unlock Bypass. After the Unlock Bypass comman d issue Unlock Bypass Pr ogram or Unlock Bypass Reset comman ds.

Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands

on non-era sing bloc ks as nor m al .

Erase Resume. A fte r th e Er as e Res ume com man d th e sus pe nded Eras e o perat ion re sumes , re ad the Stat us R egi ster unt il t he Prog ram/

Eras e Controller completes and the mem ory returns to Read Mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Unlock Bypass Reset Comman d. The Unlock

Bypass Re se t comm and can be used t o return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlo ck Bypa ss Reset command.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks a re p rote cted the Chi p Era se o perat i on ap-

pears to start but will terminate within about 100µs,

leaving the data unchange d. No error condit ion is

given when protected blocks are ignored.

During the erase operation the memory wi ll ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

times are given in Table 6. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operation has com pleted t he

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

M29F040B

8/21

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Wr ite operation using the address of the

additional block. The Bl ock Erase operation st arts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer r estarts when an additional block is select ed.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for

details on how to identify if the Program/Erase

Controller has started the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are pro tected

the Block Erase operation appears to s tart but will

terminate within about 100µs, l eaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Blo ck Erase ope ra tion the me mory will

ignore all commands except the Erase Suspend

and Read/Reset commands. Typical block erase

times are given in Table 6. All Bus Read opera-

tions du ring the Blo ck Er ase operation will ou tput

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selec ted blocks to ’1’. All previous

data in the selected blocks is lost.

Erase Suspend Comm and. The Erase Suspend

Comman d m ay be used to temporari ly sus pend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Prog ram/Eras e Controlle r will sus pend within

15µs of the Erase Suspend Command being is-

sued. Once the Program/Erase Controller has

stopped the memory will be set t o Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is susp ended i mmedi ately and wi ll start im-

mediately when the Erase Resume Command is

issued. It will not be possible to select any further

blocks fo r er asur e aft er the Erase Resume.

During Erase Suspend it is p ossi ble to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these bl ocks. Read ing from b locks that

are being erased will output the Status Register. It

is also possible to enter the Auto Select mode: the

memory will behave as in the Auto Select mode on

all blocks until a Read/Reset command returns the

memory to Erase Suspen d mode.

Erase Resum e Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resumed more than once.

Table 6. Pro gra m , Erase Times and Progra m , Erase Enduran ce Cycle s

(TA = 0 to 70°C, –40 to 85°C or – 40 to 125°C)

Note: 1. TA = 25°C, VCC = 5V .

Parameter Min Typ (1) Typical after

100k W/E Cycles (1) Max Unit

Chip Erase (All bits in the memory set to ‘0’) 1.5 1.5 sec

Chip Erase 5 5 20 sec

Block Erase (64 Kbytes) 0.6 0.6 4 sec

Program 8 8 150 µs

Chip Program 4.5 4.5 18 sec

Program/Erase Cycles (per Block) 100,000 cycles

9/21

M29F040B

STATUS REGIST ER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is acce ssed .

The bits in the Status Register are s um marized in

Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read oper ations from t he ad-

dress just programmed output DQ7, not its com-

plement.

During Erase ope rations the Data Po lling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Aft er s uc cessful completion of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change f rom a ’0’ to a ’1’ when the Program/Erase

Controller has suspe nded the Erase operat ion.

Figure 5, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A V alid Ad-

dress is the address being programmed or an

address wit hin the bl ock being erased.

Toggle Bit (DQ6). The Toggle Bit c an be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 6 , Data Toggle Flowchart, g ives an exam-

ple of how to use the Data Toggle Bit .

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Erro r Bit is set to ’1’ wh en a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Rea d/Re se t comm and must be iss ued

before other command s a re issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’ and attempting to do so may

or may not set DQ5 at ‘1’. In both cases, a s uc ces-

sive Bus Read operation will show the bit is st ill ’0’.

One of the Erase comm ands must be used to set

all the bits in a blo ck or in the whole memory from

’0’ to ’1’.

Table 7. Status Register Bits

No te : Unspecified da ta bits should be i gnore d.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2

Program Any Address DQ7 Toggle 0 ––

Program During Erase

Suspend A ny Address DQ7 Toggle 0 – –

Program Error Any Address DQ7 Toggle 1 – –

Chip Erase Any Address 0 Toggle 0 1 Toggle

Block Erase before

timeout E rasing Block 0 Togg le 0 0 Toggle

Non-Erasing Block 0 Toggle 0 0 No Toggle

Block Erase Erasing Block 0 Togg le 0 1 Toggle

Non-Erasing Block 0 Toggle 0 1 No Toggle

Erase Suspend Erasing Block 1 No To ggle 0 – Toggle

Non-Erasing Block Data read as normal

Erase Error Good Block Address 0 Toggle 1 1 No Toggle

Faulty Block Address 0 Toggle 1 1 Toggle

M29F040B

10/21

Figu re 5. Da ta Po lli ng Fl owch a rt

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

Figu re 6. Da ta To ggl e Fl owchar t

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370B

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Ti mer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional block s to b e erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes fro m ’0’ to ’1’ to ’0’, etc., with

successive Bus Re ad operations from addresses

withi n the blocks being erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will ou tput

the memory cell data as if in Read mode.

After an Erase operation that c auses t he Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or bl ocks have caused t he er-

ror. The Altern ative Toggle Bit changes from ’0’ t o

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

11/21

M29F040B

Figure 7. AC Testing Input Output Waveform

AI01275B

High Speed

1.5V

2.4V

Standard

0.45V

2.0V

0.8V

Fi gure 8. AC Testing Load Circuit

AI03027

1.3V

OUT

CL = 30pF or 100pF

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 9. Capacitance

(TA = 25 °C, f = 1 MHz)

No te : Sam pled o n l y, not 100% test ed.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

OUT Output Capacitance VOUT = 0V 12 pF

Table 8. AC Measu remen t Conditions

Parameter M29F040B

45 / 55 70 / 90

AC Test Conditions High Speed Standard

Load Capacitance (CL)30pF 100pF

Input Rise and Fall Times ≤ 10ns ≤ 10ns

Input Pulse Voltages 0 to 3V 0.45 to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

M29F040B

12/21

Table 10. DC Characteristics

(TA = 0 to 70°C, –40 to 85°C or – 40 to 125°C)

Not e: 1. Sampled only, not 100% tested.

2. TA = 25 ° C, VCC = 5V.

Symbol Parameter Test Condition Min Typ. (2) Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 715mA

CC2 Supply Current (Standby) TTL E = VIH 1mA

CC3 Supply Current (Standby) CMOS E = VCC ±0.2V 30 100 µA

ICC4 (1) Supply Current (Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC +0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

VOH Output High Voltage TTL IOH = –2.5mA 2.4 V

Output High Voltage CMOS IOH = –100µA VCC –0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO (1) Program/Erase Lockout Supply

Voltage 3.2 4.2 V

13/21

M29F040B

Figure 9. Read Mode AC Waveforms

AI02903

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A18

DQ0-DQ7

tELQV tEHQX

tGHQZ

VALID

Table 11. R ead AC Characteri stics

(TA = 0 to 70° C, –40 to 85°C or –40 to 125°C)

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29F040B Unit

45 55 70 / 90

tAVAV tRC Address Valid to Next Address V alid E = VIL,

G = VIL Min 45 55 70 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max455570ns

ELQX (1) tLZ Chip Enable Low to Output

Transition G = VIL Min 0 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max455570ns

GLQX (1) tOLZ Output Enable Low to Output

Transition E = VIL Min 0 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max253030ns

EHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max151820ns

GHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max151820ns

EHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or

Address Transition to Output

Transition Min 0 0 0 ns

M29F040B

14/21

Figure 10. Write AC Waveforms, Wr ite Enable Controlled

AI02908

A0-A18

DQ0-DQ7

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

Table 12. W rite AC Characteristics, Write Enable Con trolled

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)

Symbol Alt Parameter M29F040B Unit

45 55 70 / 90

tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 40 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 25 30 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 40 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 50 µs

15/21

M29F040B

Table 13. Write AC Characteristics, Chip Enable Controlled

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 ° C)

Symbol Alt Parameter M29F040B Unit

45 55 70 / 90

tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 40 40 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 25 30 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 40 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 50 µs

Figure 11. Write AC Wavefo rms, Chip Enable Controlled

AI02909

A0-A18

DQ0-DQ7

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

M29F040B

16/21

Table 14. Ordering Information Scheme

Note: The last two charac ters o f the ordering code m ay be replaced by a letter code for preprogramm ed

parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the ST Sales Office nearest to you.

Example: M29F040B 55 N 1 T

Device Type

M29

Operating Voltage

F = VCC = 5V ± 10%

Device Function

040B = 4 Mbit (512Kb x8), Uniform Block

Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

90 = 90 ns

Package

K = PLCC32

N = TSOP32: 8 x 20 mm

P = PDIP32

Temperature Range

1 = 0 to 70 °C

3 = –40 to 125 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

17/21

M29F040B

Table 15. Revision History

Date Rev. Revision Details

July 1999 -01 First Issue

21-Sep-1999 -02 ICC1 and ICC3 Typ. specification added (Table 10)

28-Jul-2000 -03

New document template

Document type: from Preliminary Data to Data Sheet

Status Register bit DQ5 clarification

Data Polling Flowchart diagram change (Figure 5)

Data Toggle Flowchart diagram change (Figure 6)

22-Apr -2002 -04 PLCC32 package mech anica l data modified

M29F040B

18/21

PLCC32 – 32 lead Plastic Leaded Chip Carri er, Pac kage Ou tline

Not e: Drawing is not to scale.

PLCC32 – 32 lead Plastic Leaded Chip Carrier, Pac kage Mech anical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.18 3.56 0.125 0.140

A1 1.53 2.41 0.060 0.095

A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495

D1 11.35 11.51 0.447 0.453

D2 4.78 5.66 0.188 0.223

D3 7.62 – – 0.300 – –

E 14.86 15.11 0.585 0.595

E1 13.89 14.05 0.547 0.553

E2 6.05 6.93 0.238 0.273

E3 10.16 – – 0.400 – –

e 1.27 – – 0.050 – –

F 0.00 0.13 0.000 0.005

N32 32

R 0.89 – – 0.035 – –

PLCC-A

E3 E1 E

1 N

0.51 (.020)

1.14 (.045)

D2 D2

19/21

M29F040B

TSOP32 – 32 lead Plastic Thin S mall Outline, 8 x 20mm, Package Ou tline

Not e: Drawing is not to scale.

TSOP32 – 32 lead Plastic Thin S mall Outline, 8 x 20mm, Package Me chan ical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.20 0.0472

A1 0.05 0.15 0.0020 0.0059

A2 0.95 1.05 0.0374 0.0413

B 0.15 0.27 0.0059 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 7.90 8.10 0.3110 0.3189

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

α0° 5° 0° 5°

N 32 32

CP 0.10 0.0039

TSOP-a

1 N

N/2

DIE

LA1 α

M29F040B

20/21

PDIP32 - 32 lead Plastic DIP , 600 mils width, Package Ou tline

Note : 1. Dra wing is not to scale.

PDIP32 - 32 lead Plastic DIP , 600 mils width, Package M echanic al Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A– 5.08 – 0.2000

A1 0.38 – 0.0150 –

A2 3.56 4.06 0.1402 0.1598

B 0.38 0.51 0.0150 0.0201

B1 1.52 – – 0.0598 – –

C 0.20 0.30 0.0079 0.0118

D 41.78 42.04 1.6449 1.6551

D2 38.10 – – 1.5000 – –

E 15.24 – – 0.6000 – –

E1 13.59 13.84 0.5350 0.5449

e1 2.54 – – 0.1000 – –

eA 15.24 – – 0.6000 – –

eB 15.24 17.78 0.6000 0.7000

L 3.18 3.43 0.1252 0.1350

S 1.78 2.03 0.0701 0.0799

α0° 10° 0° 10°

N32 32

PDIP

B1 B e1

E1 E

21/21

M29F040B

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