M25PX32 Serial Flash Embedded Memory Features M25PX32 NOR Serial Flash Embedded Memory 32Mb, Dual I/O, 4KB Subsector Erase, 3V Serial Flash Memory with 75 MHz SPI Bus Interface Features * * * * * * * * * Write protections - Software write protection: applicable to every 64KB sector (volatile lock bit) - Hardware write protection: non-volatile bits BP0, BP1, BP2 define protected area size * Deep power down: 5A typical * Electronic signature - JEDEC standard 2-byte signature (7116h) - Unique ID code (UID) with 16-byte read-only space, available upon request * More than 100,000 write cycles per sector * More than 20 years data retention * Packages (RoHS compliant) - VFQFPN8 (MP) 6mm x 5mm (MLP8) - SO8W (MW) 208 mils width - SO16 (MF) 300 mils width - TBGA24 (ZM) 6mm x 8mm * Automotive certified parts available * This latest generation of this product line is available in the N25Q device (see TN 12-13 for migration guide) SPI bus compatible serial interface 75 MHz (maximum) clock frequency 2.7V to 3.6V single supply voltage Dual input/output commands resulting in an equivalent clock frequency of 150 MHz - DUAL OUTPUT FAST READ command - DUAL INPUT FAST PROGRAM command Continuous READ of entire memory using FAST READ or DUAL OUTPUT FAST READ command 32Mb Flash memory - Uniform 4KB subsectors - Uniform 64KB sectors Additional 64-byte user-lockable, one-time programmable (OTP) area Erase capability - Subsector (4KB granularity) - Sector (64KB granularity) - Bulk erase (32Mb) in 34 s typical 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. M25PX32 Serial Flash Embedded Memory Features Contents Important Notes and Warnings ......................................................................................................................... 6 Functional Description ..................................................................................................................................... 7 Signal Descriptions ......................................................................................................................................... 10 Serial Peripheral Interface Modes .................................................................................................................... 11 Operating Features ......................................................................................................................................... 13 Page Programming ..................................................................................................................................... 13 Dual Input Fast Program ............................................................................................................................. 13 Subsector Erase, Sector Erase, Bulk Erase ..................................................................................................... 13 Polling during a Write, Program, or Erase Cycle ............................................................................................ 13 Active Power, Standby Power, and Deep Power-Down .................................................................................. 13 Status Register ............................................................................................................................................ 14 Data Protection by Protocol ........................................................................................................................ 14 Software Data Protection ............................................................................................................................ 14 Hardware Data Protection .......................................................................................................................... 15 Hold Condition .......................................................................................................................................... 19 Memory Configuration and Block Diagram ...................................................................................................... 20 Memory Map - 32Mb Density ......................................................................................................................... 21 Command Set Overview ................................................................................................................................. 22 WRITE ENABLE .............................................................................................................................................. 24 WRITE DISABLE ............................................................................................................................................. 25 READ IDENTIFICATION ................................................................................................................................. 26 READ STATUS REGISTER ................................................................................................................................ 28 WIP Bit ...................................................................................................................................................... 29 WEL Bit ...................................................................................................................................................... 29 Block Protect Bits ....................................................................................................................................... 29 Top/Bottom Bit .......................................................................................................................................... 29 SRWD Bit ................................................................................................................................................... 29 WRITE STATUS REGISTER .............................................................................................................................. 30 READ DATA BYTES ......................................................................................................................................... 32 READ DATA BYTES at HIGHER SPEED ............................................................................................................ 33 DUAL OUTPUT FAST READ ............................................................................................................................ 34 READ LOCK REGISTER ................................................................................................................................... 35 READ OTP ...................................................................................................................................................... 36 PAGE PROGRAM ............................................................................................................................................ 37 DUAL INPUT FAST PROGRAM ........................................................................................................................ 38 PROGRAM OTP .............................................................................................................................................. 39 WRITE to LOCK REGISTER ............................................................................................................................. 41 SUBSECTOR ERASE ....................................................................................................................................... 42 SECTOR ERASE .............................................................................................................................................. 43 BULK ERASE .................................................................................................................................................. 44 DEEP POWER-DOWN ..................................................................................................................................... 45 RELEASE from DEEP POWER-DOWN .............................................................................................................. 46 Power-Up/Down and Supply Line Decoupling ................................................................................................. 47 Maximum Ratings and Operating Conditions .................................................................................................. 49 Electrical Characteristics ................................................................................................................................ 50 AC Characteristics .......................................................................................................................................... 52 Package Information ...................................................................................................................................... 58 Device Ordering Information .......................................................................................................................... 64 Revision History ............................................................................................................................................. 65 Rev. D - 06/18 ............................................................................................................................................. 65 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Features Rev. C - 10/14 ............................................................................................................................................. 65 Rev. B - 03/13 ............................................................................................................................................. 65 Rev. A - 06/12 ............................................................................................................................................. 65 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 7 Figure 2: Pin Connections: VFQFPN and SO8 ................................................................................................... 8 Figure 3: Pin Connections: SO16 ...................................................................................................................... 8 Figure 4: Pinout: 24-Ball BGA, 6x8mm .............................................................................................................. 9 Figure 5: Bus Master and Memory Devices on the SPI Bus ............................................................................... 12 Figure 6: SPI Modes ....................................................................................................................................... 12 Figure 7: Hold Condition Activation ............................................................................................................... 19 Figure 8: Block Diagram ................................................................................................................................ 20 Figure 9: WRITE ENABLE Command Sequence .............................................................................................. 24 Figure 10: WRITE DISABLE Command Sequence ............................................................................................ 25 Figure 11: READ IDENTIFICATION Command Sequence ................................................................................ 27 Figure 12: READ STATUS REGISTER Command Sequence .............................................................................. 28 Figure 13: Status Register Format ................................................................................................................... 28 Figure 14: WRITE STATUS REGISTER Command Sequence ............................................................................. 30 Figure 15: READ DATA BYTES Command Sequence ........................................................................................ 32 Figure 16: READ DATA BYTES at HIGHER SPEED Command Sequence ........................................................... 33 Figure 17: DUAL OUTPUT FAST READ Command Sequence ........................................................................... 34 Figure 18: READ LOCK REGISTER Command Sequence ................................................................................. 35 Figure 19: READ OTP Command Sequence .................................................................................................... 36 Figure 20: PAGE PROGRAM Command Sequence ........................................................................................... 37 Figure 21: DUAL INPUT FAST PROGRAM Command Sequence ....................................................................... 38 Figure 22: PROGRAM OTP Command Sequence ............................................................................................. 39 Figure 23: How to Permanently Lock the OTP Bytes ........................................................................................ 40 Figure 24: WRITE to LOCK REGISTER Instruction Sequence ........................................................................... 41 Figure 25: SUBSECTOR ERASE Command Sequence ...................................................................................... 42 Figure 26: SECTOR ERASE Command Sequence ............................................................................................. 43 Figure 27: BULK ERASE Command Sequence ................................................................................................. 44 Figure 28: DEEP POWER-DOWN Command Sequence ................................................................................... 45 Figure 29: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 46 Figure 30: Power-Up Timing .......................................................................................................................... 48 Figure 31: AC Measurement I/O Waveform ..................................................................................................... 52 Figure 32: Serial Input Timing ........................................................................................................................ 55 Figure 33: Write Protect Setup and Hold During WRSR when SRWD = 1 Timing ............................................... 55 Figure 34: Hold Timing .................................................................................................................................. 56 Figure 35: Output Timing .............................................................................................................................. 56 Figure 36: V PPH Timing .................................................................................................................................. 57 Figure 37: VFQFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 58 Figure 38: SO8W 208 mils Body Width ............................................................................................................ 59 Figure 39: SO16W 300 mils Body Width .......................................................................................................... 60 Figure 40: SO8N 150 mils Body Width ............................................................................................................ 61 Figure 41: QFN8L 6mm x 5mm (MLP8) .......................................................................................................... 62 Figure 42: TBGA 24-Ball, 6mm x 8mm ............................................................................................................ 63 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Features List of Tables Table 1: Signal Names ...................................................................................................................................... 8 Table 2: Signal Descriptions ........................................................................................................................... 10 Table 3: SPI Modes ........................................................................................................................................ 11 Table 4: Software Protection Truth Table ........................................................................................................ 15 Table 5: Sectors 0 to 16, Protected Area Sizes - Upper Area Protection .............................................................. 15 Table 6: Sectors 0 to 16, Protected Area Sizes - Lower Area Protection .............................................................. 15 Table 7: Sectors 0 to 32, Protected Area Sizes - Upper Area Protection .............................................................. 16 Table 8: Sectors 0 to 32, Protected Area Sizes - Lower Area Protection .............................................................. 16 Table 9: Sectors 0 to 63, Protected Area Sizes - Upper Area Protection .............................................................. 16 Table 10: Sectors 0 to 63, Protected Area Sizes - Lower Area Protection ............................................................ 18 Table 11: Sectors 0 to 127, Protected Area Sizes - Upper Area Protection .......................................................... 18 Table 12: Sectors 0 to 127, Protected Area Sizes - Lower Area Protection .......................................................... 18 Table 13: Sectors[127:0] ................................................................................................................................. 21 Table 14: Command Set Codes ....................................................................................................................... 23 Table 15: READ IDENTIFICATION Data Out Sequence .................................................................................... 26 Table 16: Status Register Protection Modes ..................................................................................................... 31 Table 17: Lock Register Out ............................................................................................................................ 35 Table 18: Lock Register In .............................................................................................................................. 41 Table 19: Absolute Maximum Ratings ............................................................................................................. 49 Table 20: Operating Conditions ...................................................................................................................... 49 Table 21: Data Retention and Endurance ........................................................................................................ 49 Table 22: Power Up Timing Specifications ...................................................................................................... 50 Table 23: DC Current Specifications ............................................................................................................... 50 Table 24: DC Voltage Specifications ................................................................................................................ 50 Table 25: AC Measurement Conditions ........................................................................................................... 52 Table 26: Capacitance .................................................................................................................................... 52 Table 27: AC Specifications (75MHz) .............................................................................................................. 53 Table 28: Part Number Information Scheme ................................................................................................... 64 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Functional Description Functional Description The M25PX32 is a 32Mb (4Mb x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The device supports two high-performance dual input/output instructions that double the transfer bandwidth for read and program operations: * DUAL OUTPUT FAST READ instruction reads data at up to 75 MHz by using both pin DQ1 and pin DQ0 as outputs. * DUAL INPUT FAST PROGRAM instruction programs data at up to 75 MHz by using both pin DQ1 and pin DQ0 as inputs. The memory can be programmed 1 to 256 bytes at a time, using the PAGE PROGRAM instruction. It is organized as 64 sectors that are further divided into 16 subsectors each (1024 total subsectors). The memory can be erased a 4KB subsector at a time, a 64KB sector at a time, or as a whole. It can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. Protection granularity is 64KB sectors. The device has 64 one-time-programmable bytes (OTP bytes) that can be read and programmed using two dedicated instructions, READ OTP and PROGRAM OTP, respectively. These 64 bytes can be locked permanently using a PROGRAM OTP command sequence. Further features are available as additional security options. More information on these security features is available, upon completion of an NDA (nondisclosure agreement), and are, therefore, not described in this datasheet. For more details of this option contact your nearest Micron sales office. Figure 1: Logic Diagram VCC DQ0 DQ1 C S# W#/VPP HOLD# VSS 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Functional Description Table 1: Signal Names Signal Name Function Direction C Serial clock Input DQ0 Serial data input (Serves as output during DUAL OUTPUT FAST READ operation) I/O DQ1 Serial data output (Serves as input during DUAL INPUT FAST PROGRAM operation) I/O S# Chip select Input W#/VPP Write protect or enhanced program supply voltage Input HOLD# Hold Input VCC Supply voltage VSS Ground Figure 2: Pin Connections: VFQFPN and SO8 S# 1 8 VCC DQ1 2 7 HOLD# W#/VPP 3 6 C VSS 4 5 DQ0 There is an exposed central pad on the underside of the VFQFPN package. This is pulled internally to V SS, and must not be connected to any other voltage or signal line on the PCB. The Package Mechanical section provides information on package dimensions and how to identify pin 1. Figure 3: Pin Connections: SO16 Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN HOLD# 1 16 C VCC 2 15 DQ0 DNU 3 14 DNU DNU 4 13 DNU DNU 5 12 DNU DNU 6 11 DNU S# 7 10 VSS DQ1 8 9 W#/VPP 1. DNU = do not use. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Functional Description Figure 4: Pinout: 24-Ball BGA, 6x8mm 1 2 3 4 5 A NC NC NC NC NC C VSS VCC NC NC S# NC W#/VPP NC NC DQ1 DQ0 HOLD# NC NC NC NC NC NC B C D E Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. DNU = do not use. NC = no connect. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Signal Descriptions Signal Descriptions Table 2: Signal Descriptions Signal Type DQ1 Output Serial data: The DQ1 output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock (C). During the DUAL INPUT FAST PROGRAM command, pin DQ1 is used as an input. It is latched on the rising edge of C. DQ0 Input Serial data: The DQ0 input signal is used to transfer data serially into the device. It receives commands, addresses, and the data to be programmed. Values are latched on the rising edge of the serial clock (C). During the DUAL OUTPUT FAST READ command, pin DQ0 is used as an output. Data is shifted out on the falling edge of C. C Input Clock: The C input signal provides the timing of the serial interface. Commands, addresses, or data present at serial data input (DQ0) is latched on the rising edge of the serial clock (C). Data on DQ1 changes after the falling edge of C. S# Input Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at high impedance. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device will be in the standby power mode (not the deep powerdown mode). Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. HOLD# Input Hold: The HOLD# signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, DQ1 is High-Z. DQ0 and C are "Don't Care." To start the hold condition, the device must be selected, with S# driven LOW. W#/VPP Input Write protect/enhanced program supply voltage: The W#/VPP signal is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If the W#/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. The W# input signal is used to freeze the size of the area of memory that is protected against program or erase commands as specified by the values in BP2, BP1, and BP0 bits of the Status Register. VPP acts as an additional power supply if it is in the range of VPPH, as defined in the AC Measurement Conditions table. Avoid applying VPPH to the W#/VPP pin during a BULK ERASE operation. VCC Power Device core power supply: Source voltage. VSS Ground DNU - 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN Description Ground: Reference for the VCC supply voltage. Do not use. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Serial Peripheral Interface Modes Serial Peripheral Interface Modes The device can be driven by a microcontroller while its serial peripheral interface (SPI) is in either of the two modes shown here. The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data. Input data is latched in on the rising edge of the clock, and output data is available from the falling edge of the clock. Table 3: SPI Modes SPI Modes Clock Polarity CPOL = 0, CPHA = 0 C remains at 0 for (CPOL = 0, CPHA = 0) CPOL = 1, CPHA = 1 C remains at 1 for (CPOL = 1, CPHA = 1) The following figure is an example of three memory devices in a simple connection to an MCU on an SPI bus. Because only one device is selected at a time, that one device drives DQ1, while the other devices are HIGH-Z. Resistors ensure the device is not selected if the bus master leaves S# HIGH-Z. The bus master might enter a state in which all input/output is HIGH-Z simultaneously, such as when the bus master is reset. Therefore, the serial clock must be connected to an external pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW. This ensures that S# and the serial clock are not HIGH simultaneously and that tSHCH is met. The typical resistor value of 100k, assuming that the time constant R x Cp (Cp = parasitic capacitance of the bus line), is shorter than the time the bus master leaves the SPI bus in HIGH-Z. Example: Cp = 50 pF, that is R x Cp = 5s. The application must ensure that the bus master never leaves the SPI bus HIGH-Z for a time period shorter than 5s. W# and HOLD# should be driven either HIGH or LOW, as appropriate. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Serial Peripheral Interface Modes Figure 5: Bus Master and Memory Devices on the SPI Bus VSS VCC R SDO SPI interface: (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C SPI bus master DQ1 DQ0 R CS3 SPI memory device VCC C VSS R DQ1 DQ0 SPI memory device VCC C VSS R DQ1 DQ0 VSS SPI memory device CS2 CS1 S# W# HOLD# S# W# HOLD# S# W# HOLD# Figure 6: SPI Modes CPOL CPHA 0 0 C 1 1 C DQ0 MSB DQ1 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN MSB 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Operating Features Operating Features Page Programming To program one data byte, two commands are required: WRITE ENABLE, which is one byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by the internal PROGRAM cycle of duration tPP. To spread this overhead, the PAGE PROGRAM command allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To optimize timings, it is recommended to use the PAGE PROGRAM command to program all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM sequences with each containing only a few bytes. Dual Input Fast Program The DUAL INPUT FAST PROGRAM command makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from 1 to 0). For optimized timings, it is recommended to use the DUAL INPUT FAST PROGRAM command to program all consecutive targeted bytes in a single sequence than to use several DUAL INPUT FAST PROGRAM sequences each containing only a few bytes. Subsector Erase, Sector Erase, Bulk Erase The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved a subsector at a time using the SUBSECTOR ERASE command, a sector at a time using the SECTOR ERASE command, or throughout the entire memory using the BULK ERASE command. This starts an internal ERASE cycle of duration t SSE, tSE or tBE. The ERASE command must be preceded by a WRITE ENABLE command. Polling during a Write, Program, or Erase Cycle An improvement in the time to complete the following commands can be achieved by not waiting for the worst case delay (tW, tPP, tSSE, tSE, or tBE). * * * * * WRITE STATUS REGISTER PROGRAM OTP PROGRAM DUAL INPUT FAST PROGRAM ERASE (SUBSECTOR ERASE, SECTOR ERASE, BULK ERASE) The write in progress (WIP) bit is provided in the status register so that the application program can monitor this bit in the status register, polling it to establish when the previous WRITE cycle, PROGRAM cycle, or ERASE cycle is complete. Active Power, Standby Power, and Deep Power-Down When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode. When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS REGISTER). The device then goes in to the STANDBY POWER mode. The device consumption drops to ICC1. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Operating Features The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command is executed. The device consumption drops further to I CC2. The device remains in this mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE commands. This provides an extra software protection mechanism when the device is not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or ERASE operations. For further information, see DEEP POWER-DOWN (page 45). Status Register The status register contains a number of status and control bits that can be read or set (as appropriate) by specific commands. For a detailed description of the status register bits, see READ STATUS REGISTER. Data Protection by Protocol Non-volatile memory is used in environments that can include excessive noise. The following capabilities help protect data in these noisy environments. Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. WRITE, PROGRAM, ERASE, and WRITE STATUS REGISTER commands are checked before they are accepted for execution to ensure they consist of a number of clock pulses that is a multiple of eight. All commands that modify data must be preceded by a WRITE ENABLE command to set the write enable latch (WEL) bit. In addition to the low power consumption feature, the DEEP POWER-DOWN mode offers extra software protection since all WRITE, PROGRAM, and ERASE commands are ignored when the device is in this mode. Software Data Protection Memory can be configured as read-only using the top/bottom bit and the block protect bits (BP2, BP1, BP0) as shown in the Protected Area Sizes table. Memory sectors can be protected by specific lock registers assigned to each 64KB sector. These lock registers can be read and written using the READ LOCK REGISTER and WRITE to LOCK REGISTER commands. In each lock register the following two bits control the protection of each sector: * Write lock bit: This bit determines whether the contents of the sector can be modified using the WRITE, PROGRAM, and ERASE commands. When the bit is set to `1', the sector is write protected, and any operations that attempt to change the data in the sector will fail. When the bit is reset to `0', the sector is not write protected by the lock register, and may be modified. * Lock down bit: This bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the bit is set to '1', further modification to the write lock bit and lock down bit cannot be performed. A power-up, is required before changes to these bits can be made. When the bit is reset to `0', the write lock bit and lock down bit can be changed. The software protection truth table shows the lock down bit and write lock bit settings and the sector protection status. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Operating Features Table 4: Software Protection Truth Table Sector Lock Register Bits Lock Down Write Lock Protection Status 0 0 Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status reversible 0 1 Sector protected from PROGRAM / ERASE / WRITE operations; protection status reversible 1 0 Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status cannot be changed except by a power-up. 1 1 Sector protected from PROGRAM / ERASE / WRITE operations; protection status cannot be changed except by a power-up. Hardware Data Protection Hardware data protection is implemented using the write protect signal applied on the W#/VPP pin. This freezes the status register in a read-only mode, protecting the block protect (BP) bits and the status register write disable bit (SRWD). The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Table 5: Sectors 0 to 16, Protected Area Sizes - Upper Area Protection Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 Protected Area Unprotected Area 0 0 0 0 None All sectors 1 0 0 0 1 Upper 16th (sector 15) Lower 15/16ths (sectors 0 to 14) 0 0 1 0 Upper 8th (sectors 14 to 15) Lower 7/8ths (sectors 0 to 13 ) 0 0 1 1 Upper 4th (sectors 12 to 15) Lower 3/4ths (sectors 0 to 11) 0 1 0 0 Upper half (sectors 8 to 15) Lower half (sectors 0 to 7) 0 1 0 1 All sectors None 0 1 1 0 All sectors None 0 1 1 1 All sectors None Note: 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Table 6: Sectors 0 to 16, Protected Area Sizes - Lower Area Protection Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 Protected Area Unprotected Area 1 0 0 0 None All sectors 1 1 0 0 1 Lower 16th (sector 0) Upper 15/16ths (sectors 1 to 15) 1 1 0 1 0 Lower 8th (sectors 0 to 1) Upper 7/8ths (sectors 2 to 15 ) 0 1 1 Lower 4th (sectors 0 to 3) Upper 3/4ths (sectors 4 to 15) 1 1 0 0 Lower half (sectors 3 to 7) Upper half (sectors 8 to 15) 1 1 0 1 All sectors None 1 1 1 0 All sectors None 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Operating Features Table 6: Sectors 0 to 16, Protected Area Sizes - Lower Area Protection (Continued) Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 1 1 1 1 Note: Protected Area Unprotected Area All sectors None 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Table 7: Sectors 0 to 32, Protected Area Sizes - Upper Area Protection Status Register Content Memory Content Top/Bottom Bit BP 2 BP 1 BP 0 Protected Area Unprotected Area 0 0 0 0 none All sectors 1 0 0 0 1 Upper 32nd (sector 31) Lower 31/32nds (sectors 0 to 30) 0 0 1 0 Upper 16th (sectors 30 to 31) Lower 15/16ths (sectors 0 to 29) 0 0 1 1 Upper 8th (sectors 28 to 31) Lower 7/8ths (sectors 0 to 27) 0 1 0 0 Upper 4th (sectors 24 to 31) Lower 3/4ths (sectors 0 to 23) 0 1 0 1 Upper half (sectors 16 to 31) Lower half (sectors 0 to 15) 0 1 1 0 All sectors none 0 1 1 1 All sectors none Note: 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Table 8: Sectors 0 to 32, Protected Area Sizes - Lower Area Protection Status Register Content Memory Content Top/Bottom Bit BP 2 BP 1 BP 0 Protected Area Unprotected Area 1 0 0 0 none All sectors 1 1 0 1 0 0 1 Lower 32nd (sector 0) Upper 31/32nds (sectors 1 to 31) 1 0 Lower 16th (sectors 0 to 1) Upper 15/16ths (sectors 2 to 31) 1 0 1 1 Lower 8th (sectors 0 to 3) Upper 7/8ths (sectors 4 to 31) 1 1 0 0 Lower 4th (sectors 0 to 7) Upper 3/4ths (sectors 8 to 31) 1 1 0 1 Lower half (sectors 0 to 15) Upper half (sectors 16 to 31) 1 1 1 0 All sectors none 1 1 1 1 All sectors none Note: 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Table 9: Sectors 0 to 63, Protected Area Sizes - Upper Area Protection Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 Protected Area Unprotected Area 0 0 0 0 None All sectors 1 0 0 0 1 Upper 64th (sector 63) Lower 63/64ths (sectors 0 to 62) 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Operating Features Table 9: Sectors 0 to 63, Protected Area Sizes - Upper Area Protection (Continued) Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 Protected Area Unprotected Area 0 0 1 0 Upper 32th (sectors 62 to 63) Lower 31/32nds (sectors 0 to 61) 0 0 1 1 Upper 16th (sectors 60 to 63) Lower 15/16ths (sectors 0 to 59) 0 0 1 0 0 Upper 8th (sectors 56 to 63) Lower 7/8ths (sectors 0 to 55 ) 1 0 1 Upper 4th (sectors 48 to 63) Lower 3/4ths (sectors 0 to 47) 0 1 1 0 Upper half (sectors 32 to 63) Lower half (sectors 0 to 31) 0 1 1 1 All sectors None Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Operating Features Table 10: Sectors 0 to 63, Protected Area Sizes - Lower Area Protection Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 Protected Area Unprotected Area 1 0 0 0 None All sectors 1 1 0 0 1 Lower 64th (sector 0) Upper 63/64ths (sectors 1 to 63) 1 0 1 0 Lower 32th (sectors 0 to 1) Upper 31/32nds (sectors 2 to 63) 1 0 1 1 Lower 16th (sectors 0 to 3) Upper 15/16ths (sectors 4 to 63) 1 1 0 0 Lower 8th (sectors 0 to 7) Upper 7/8ths (sectors 8 to 63) 1 1 0 1 Lower 4th (sectors 0 to 15) Upper 3/4ths (sectors 16 to 63) 1 1 1 0 Lower half (sectors 0 to 31) Upper half (sectors 32 to 63) 1 1 1 1 All sectors None Note: 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Table 11: Sectors 0 to 127, Protected Area Sizes - Upper Area Protection Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 Protected Area Unprotected Area 0 0 0 0 None All sectors 1 0 0 0 1 Upper 64th (sectors 126 to 127) Lower 63/64ths (sectors 0 to 125) 0 0 0 1 0 Upper 32nd (sectors 124 to 127) Lower 31/32nds (sectors 0 to 123) 0 1 1 Upper 16th (sectors 120 to 127) Lower 15/16ths (sectors 0 to119) 0 1 0 0 Upper 8th (sectors 112 to 127) Lower 7/8ths (sectors 0 to 111) 0 1 0 1 Upper 4th (sectors 96 to 127) Lower 3/4ths (sectors 0 to 95) 0 1 1 0 Upper half (sectors 64 to 127) Lower half (sectors 0 to 63) 0 1 1 1 All sectors None Note: 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Table 12: Sectors 0 to 127, Protected Area Sizes - Lower Area Protection Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 Protected Area Unprotected Area 1 0 0 0 None All sectors 1 1 0 0 1 Lower 64th (sectors 0 to 1) Upper (sectors 2 to 127) 1 0 1 0 Lower 32nd (sectors 0 to 3) Upper (sectors 4 to 127) 1 0 1 1 Lower 16th (sectors 0 to 7) Upper (sectors 8 to 127) 1 1 0 0 Lower 8th (sectors 0 to 15) Upper (sectors 16 to 127) 1 1 0 1 Lower 4th (sectors 0 to 31) Upper (sectors 32 to 127) 1 1 1 0 Lower half (sectors 0 to 63) Upper (sectors 64 to 127) 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Operating Features Table 12: Sectors 0 to 127, Protected Area Sizes - Lower Area Protection (Continued) Status Register Content Memory Content Top/Bottom Bit BP2 BP1 BP0 1 1 1 1 Note: Protected Area Unprotected Area None All sectors 1. The device is ready to accept a BULK ERASE command only if all block protect bits are 0. Hold Condition The HOLD# signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal LOW does not terminate any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress. To enter the hold condition, the device must be selected, with S# LOW. The hold condition starts on the falling edge of the HOLD# signal, if this coincides with serial clock (C) being LOW. The hold condition ends on the rising edge of the HOLD# signal, if this coincides with C being LOW. If the falling edge does not coincide with C being LOW, the hold condition starts after C next goes LOW. Similarly, if the rising edge does not coincide with C being LOW, the hold condition ends after C next goes LOW. During the hold condition, DQ1 is HIGH impedance while DQ0 and C are Don't Care. Typically, the device remains selected with S# driven LOW for the duration of the hold condition. This ensures that the state of the internal logic remains unchanged from the moment of entering the hold condition. If S# goes HIGH while the device is in the hold condition, the internal logic of the device is reset. To restart communication with the device, it is necessary to drive HOLD# HIGH, and then to drive S# LOW. This prevents the device from going back to the hold condition. Figure 7: Hold Condition Activation C HOLD# HOLD condition (standard use) 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 19 HOLD condition (nonstandard use) Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Memory Configuration and Block Diagram Memory Configuration and Block Diagram Each page of memory can be individually programmed; bits are programmed from 1 to 0. The device is sector or bulk-erasable, but not page-erasable; bits are erased from 0 to 1. The memory is configured as follows: * * * * * 4,194,304 bytes (8 bits each) 1024 subsectors (4KB each) 64 sectors (64KB each) 16,384 pages (256 bytes each) 64 OTP bytes located outside main memory Figure 8: Block Diagram HOLD# W#/VPP High Voltage Generator Control Logic 64 OTP bytes S# C DQ0 I/O Shift Register DQ1 Address Register and Counter Status Register 256 Byte Data Buffer Y Decoder 3FFFFFh 00000h 000FFh 256 bytes (page size) X Decoder 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Memory Map - 32Mb Density Memory Map - 32Mb Density Table 13: Sectors[127:0] Address Range Sector Subsector Start End 63 1023 003F F000h 003F FFFFh 1008 003F 0000h 003F 0FFFh 0 15 0000 F000h 0000 FFFFh 0 0000 0000h 0000 0FFFh 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Command Set Overview Command Set Overview All commands, addresses, and data are shifted in and out of the device, most significant bit first. Serial data inputs DQ0 and DQ1 are sampled on the first rising edge of serial clock (C) after chip select (S#) is driven LOW. Then, the one-byte command code must be shifted in to the device, most significant bit first, on DQ0 and DQ1, each bit being latched on the rising edges of C. Every command sequence starts with a one-byte command code. Depending on the command, this command code might be followed by address or data bytes, by address and data bytes, or by neither address or data bytes. For the following commands, the shifted-in command sequence is followed by a data-out sequence. S# can be driven HIGH after any bit of the data-out sequence is being shifted out. * * * * * * * * READ DATA BYTES (READ) READ DATA BYTES at HIGHER SPEED DUAL OUTPUT FAST READ READ OTP READ LOCK REGISTERS READ STATUS REGISTER READ IDENTIFICATION RELEASE from DEEP POWER-DOWN For the following commands, S# must be driven HIGH exactly at a byte boundary. That is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must be driven HIGH. Otherwise, the command is rejected and not executed. * * * * * * * * * * * PAGE PROGRAM PROGRAM OTP DUAL INPUT FAST PROGRAM SUBSECTOR ERASE SECTOR ERASE BULK ERASE WRITE STATUS REGISTER WRITE to LOCK REGISTER WRITE ENABLE WRITE DISABLE DEEP POWER-DOWN All attempts to access the memory array are ignored during a WRITE STATUS REGISTER command cycle, a PROGRAM command cycle, or an ERASE command cycle. In addition, the internal cycle for each of these commands continues unaffected. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Command Set Overview Table 14: Command Set Codes Command Name Bytes One-Byte Command Code Address Dummy Data WRITE ENABLE 0000 0110 06h 0 0 0 WRITE DISABLE 0000 0100 04h 0 0 0 READ IDENTIFICATION 1001 1111 9Fh 0 0 1 to 20 1001 1110 9Eh READ STATUS REGISTER 0000 0101 05h 0 0 1 to WRITE STATUS REGISTER 0000 0001 01h 0 0 1 WRITE to LOCK REGISTER 1110 0101 E5h 3 0 1 READ LOCK REGISTER 1110 1000 E8h 3 0 1 READ DATA BYTES 0000 0011 03h 3 0 1 to READ DATA BYTES at HIGHER SPEED 0000 1011 0Bh 3 1 1 to DUAL OUTPUT FAST READ 0011 1011 3Bh 3 1 1 to READ OTP (Read 64 bytes of OTP area) 0100 1011 4Bh 3 1 1 to 65 PROGRAM OTP (Program 64 bytes of OTP area) 0100 0010 42h 3 0 1 to 65 PAGE PROGRAM 0000 0010 02h 3 0 1 to 256 DUAL INPUT FAST PROGRAM 1010 0010 A2h 3 0 1 to 256 SUBSECTOR ERASE 0010 0000 20h 3 0 0 SECTOR ERASE 1101 1000 D8h 3 0 0 BULK ERASE 1100 0111 C7h 0 0 0 DEEP POWER-DOWN 1011 1001 B9h 0 0 0 RELEASE from DEEP POWER-DOWN 1010 1011 ABh 0 0 0 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 23 1 to 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory WRITE ENABLE WRITE ENABLE The WRITE ENABLE command sets the write enable latch (WEL) bit. The WEL bit must be set before execution of every PROGRAM, ERASE, and WRITE command. The WRITE ENABLE command is entered by driving chip select (S#) LOW, sending the command code, and then driving S# HIGH. Figure 9: WRITE ENABLE Command Sequence 0 1 2 3 4 5 6 7 C S# Command bits DQ[0] 0 0 0 0 0 LSB 1 1 0 MSB DQ1 High-Z Don't Care 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory WRITE DISABLE WRITE DISABLE The WRITE DISABLE command resets the write enable latch (WEL) bit. The WRITE DISABLE command is entered by driving chip select (S#) LOW, sending the command code, and then driving S# HIGH. The WEL bit is reset under the following conditions: * * * * * Power-up Completion of any ERASE operation Completion of any PROGRAM operation Completion of any WRITE STATUS REGISTER operation Completion of WRITE DISABLE operation Figure 10: WRITE DISABLE Command Sequence 0 1 2 3 4 5 6 7 C S# Command bits DQ[0] 0 0 0 0 0 LSB 1 0 0 MSB DQ1 High-Z Don't Care 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ IDENTIFICATION READ IDENTIFICATION The READ IDENTIFICATION command reads the following device identification data: * Manufacturer identification (1 byte): This is assigned by JEDEC. * Device identification (2 bytes): This is assigned by device manufacturer; the first byte indicates memory type and the second byte indicates device memory capacity. * A Unique ID code (UID) (17 bytes,16 available upon customer request): The first byte contains length of data to follow; the remaining 16 bytes contain optional Customized Factory Data (CFD) content. Table 15: READ IDENTIFICATION Data Out Sequence Device Identification UID Manufacturer Identification Memory Type Memory Capacity CFD Length CFD Content 20h 20h 11h 10h 16 bytes 71h 12h 13h 14h 15h 16h 17h 18h Note: 1. The CFD bytes are read-only and can be programmed with customer data upon demand. If customers do not make requests, the devices are shipped with all the CFD bytes programmed to zero. A READ IDENTIFICATION command is not decoded while an ERASE or PROGRAM cycle is in progress and has no effect on a cycle in progress. The READ IDENTIFICATION command must not be issued while the device is in DEEP POWER-DOWN mode. The device is first selected by driving S# LOW. Then the 8-bit command code is shifted in and content is shifted out on DQ1 as follows: the 24-bit device identification that is stored in the memory, the 8-bit CFD length, followed by 16 bytes of CFD content. Each bit is shifted out during the falling edge of serial clock (C). The READ IDENTIFICATION command is terminated by driving S# HIGH at any time during data output. When S# is driven HIGH, the device is put in the STANDBY POWER mode and waits to be selected so that it can receive, decode, and execute commands. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ IDENTIFICATION Figure 11: READ IDENTIFICATION Command Sequence 0 7 16 15 8 31 32 C LSB Command DQ0 MSB LSB LSB DQ1 High-Z DOUT DOUT DOUT MSB DOUT MSB Manufacturer identification LSB DOUT DOUT MSB Device identification UID Don't Care 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ STATUS REGISTER READ STATUS REGISTER The READ STATUS REGISTER command allows the status register to be read. The status register may be read at any time, even while a PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new command to the device. It is also possible to read the status register continuously. Figure 12: READ STATUS REGISTER Command Sequence 0 7 8 9 10 11 12 13 14 15 C LSB Command DQ0 MSB LSB DQ1 DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Don't Care Figure 13: Status Register Format b7 SRWD b0 0 BP2 TB BP1 BP0 WEL WIP Status register write protect Top/bottom bit Block protect bits Write enable latch bit Write in progress bit 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ STATUS REGISTER WIP Bit The write in progress (WIP) bit indicates whether the memory is busy with a WRITE STATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress. WEL Bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is set to 0, the internal write enable latch is reset and no WRITE STATUS REGISTER, PROGRAM, or ERASE command is accepted. Block Protect Bits The block protect bits are nonvolatile. They define the size of the area to be software protected against PROGRAM and ERASE commands. The block protect bits are written with the WRITE STATUS REGISTER command. When one or more of the block protect bits is set to 1, the relevant memory area, as defined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM and SECTOR ERASE commands. The block protect bits can be written provided that the HARDWARE PROTECTED mode has not been set. The BULK ERASE command is executed only if all block protect bits are 0. Top/Bottom Bit The top/bottom (TB) bit is nonvolatile. It can be set and reset with the WRITE STATUS REGISTER command provided that the WRITE ENABLE command has been issued. The TB bit is used in conjunction with the block protect bits to determine if the protected area defined by the block protect bits starts from the top or the bottom of the memory array: * When TB is reset to 0 (default value), the area protected by the block protect bits starts from the top of the memory array * When TB is set to 1, the area protected by the block protect bits starts from the bottom of the memory array The TB bit cannot be written when the status register write disable (SRWD) bit is set to 1 and the W# pin is driven LOW. SRWD Bit The status register write disable (SRWD) bit is operated in conjunction with the write protect (W#/VPP) signal. When the SRWD bit is set to 1 and W#/V PP is driven LOW, the device is put in the hardware protected mode. In the hardware protected mode, the nonvolatile bits of the status register (SRWD, and the block protect bits) become readonly bits and the WRITE STATUS REGISTER command is no longer accepted for execution. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory WRITE STATUS REGISTER WRITE STATUS REGISTER The WRITE STATUS REGISTER command allows new values to be written to the status register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded and executed, the device sets the write enable latch (WEL) bit. The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW, followed by the command code and the data byte on serial data input (DQ0). The WRITE STATUS REGISTER command has no effect on b6, b5, b4, b1, and b0 of the status register. The status register b6 is, b5, and b4 are always read as "0". S# must be driven HIGH after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS REGISTER command is not executed. Figure 14: WRITE STATUS REGISTER Command Sequence 0 7 8 9 10 11 12 13 15 14 C LSB Command DQ0 MSB LSB DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initiated; its duration is tW. While the WRITE STATUS REGISTER cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the cycle is completed. Also, when the cycle is completed, the WEL bit is reset. The WRITE STATUS REGISTER command allows the user to change the values of the block protect bits (BP2, BP1, BP0). Setting these bit values defines the size of the area that is to be treated as read-only, as defined in the Protected Area Sizes table. The WRITE STATUS REGISTER command also allows the user to set and reset the status register write disable (SRWD) bit in accordance with the write protect (W#/VPP) signal. The SRWD bit and the W#/V PP signal allow the device to be put in the hardware protected (HPM) mode. The WRITE STATUS REGISTER command is not executed once the HPM is entered. The options for enabling the status register protection modes are summarized here. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory WRITE STATUS REGISTER Table 16: Status Register Protection Modes Memory Content W#/VPP Signal SRWD Bit Protection Mode (PM) Status Register Write Protection Protected Area Unprotected Area 1 0 Commands not accepted Commands accepted 1, 2, 3 0 1 1 Software protected mode (SPM) Software protection 0 0 1 Hardware protected mode (HPM) Hardware protection Commands not accepted Commands accepted 3, 4, 5, Notes: Notes 1. Software protection: status register is writable (SRWD, BP2, BP1, and BP0 bit values can be changed) if the WRITE ENABLE command has set the WEL bit. 2. PAGE PROGRAM, SECTOR ERASE, and BULK ERASE commands are not accepted. 3. PAGE PROGRAM and SECTOR ERASE commands can be accepted. 4. Hardware protection: status register is not writable (SRWD, BP2, BP1, and BP0 bit values cannot be changed). 5. PAGE PROGRAM, SECTOR ERASE, and BULK ERASE commands are not accepted. When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the WEL bit has been set previously by a WRITE ENABLE command, regardless of whether the W#/V PP signal is driven HIGH or LOW. When the status register SRWD bit is set to 1, two cases need to be considered depending on the state of the W#/V PP signal: * If the W#/V PP signal is driven HIGH, it is possible to write to the status register provided that the WEL bit has been set previously by a WRITE ENABLE command. * If the W#/V PP signal is driven LOW, it is not possible to write to the status register even if the WEL bit has been set previously by a WRITE ENABLE command. Therefore, attempts to write to the status register are rejected, and are not accepted for execution. The result is that all the data bytes in the memory area that have been put in SPM by the status register block protect bits (BP2, BP1, BP0) are also hardware protected against data modification. Regardless of the order of the two events, the HPM can be entered in either of the following ways: * Setting the status register SRWD bit after driving the W#/V PP signal LOW * Driving the W#/V PP signal LOW after setting the status register SRWD bit. The only way to exit the HPM is to pull the W#/V PP signal HIGH. If the W#/V PP signal is permanently tied HIGH, the HPM can never be activated. In this case, only the SPM is available, using the status register block protect bits (BP2, BP1, BP0). 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ DATA BYTES READ DATA BYTES The device is first selected by driving chip select (S#) LOW. The command code for READ DATA BYTES is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of serial clock (C). Then the memory contents at that address is shifted out on serial data output (DQ1), each bit being shifted out at a maximum frequency fR during the falling edge of C. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Therefore, the entire memory can be read with a single READ DATA BYTES command. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven HIGH at any time during data output. Any READ DATA BYTES command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 15: READ DATA BYTES Command Sequence 0 7 8 Cx C LSB MSB DQ1 A[MIN] Command DQ[0] A[MAX] DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Don't Care Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. Cx = 7 + (A[MAX] + 1). 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ DATA BYTES at HIGHER SPEED READ DATA BYTES at HIGHER SPEED The device is first selected by driving chip select (S#) LOW. The command code for the READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (C). Then the memory contents at that address are shifted out on serial data output (DQ1) at a maximum frequency fC, during the falling edge of C. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Therefore, the entire memory can be read with a single READ DATA BYTES at HIGHER SPEED command. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH. S# can be driven HIGH at any time during data output. Any READ DATA BYTES at HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 16: READ DATA BYTES at HIGHER SPEED Command Sequence 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB DQ1 A[MAX] DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dummy cycles Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN Don't Care 1. Cx = 7 + (A[MAX] + 1). 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory DUAL OUTPUT FAST READ DUAL OUTPUT FAST READ The DUAL OUTPUT FAST READ command is similar to the READ DATA BYTES at HIGHER SPEED command, except that data is shifted out on two pins (DQ0 and DQ1) instead of one. Outputting the data on two pins doubles the data transfer bandwidth compared to the READ DATA BYTES at HIGHER SPEED command. The device is first selected by driving chip select S# LOW. The command code for the DUAL OUTPUT FAST READ command is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (C). Then the memory contents at that address are shifted out on DQ0 and DQ1 at a maximum frequency fC, during the falling edge of C. Figure 17: DUAL OUTPUT FAST READ Command Sequence 0 7 8 Cx C LSB MSB DQ1 A[MIN] Command DQ0 DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT A[MAX] High-Z DOUT MSB Dummy cycles Note: 1. Cx = 7 + (A[MAX] + 1). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0 and DQ1. Therefore, the entire memory can be read with a single DUAL OUTPUT FAST READ command. When the highest address is reached, the address counter rolls over to 00 0000h so that the read sequence can be continued indefinitely. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ LOCK REGISTER READ LOCK REGISTER The device is first selected by driving chip select (S#) LOW. The command code for the READ LOCK REGISTER command is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector. Each address bit is latched-in during the rising edge of serial clock (C). Then the value of the lock register is shifted out on serial data output (DQ1), each bit being shifted out at a maximum frequency fC during the falling edge of C. The READ LOCK REGISTER command is terminated by driving S# HIGH at any time during data output. Figure 18: READ LOCK REGISTER Command Sequence 0 7 8 Cx C LSB MSB DQ1 A[MIN] Command DQ[0] A[MAX] DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Don't Care Note: 1. Cx = 7 + (A[MAX] + 1). Any READ LOCK REGISTER command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Values of b1 and b0 after power-up are defined in Power-Up/Down and Supply Line Decoupling (page 47). Table 17: Lock Register Out Bit b7-b2 b1 b0 Bit name Value Function 1 The write lock and lock-down bits cannot be changed. Once a value of 1 is written to the lock-down bit, it cannot be cleared to a value of 0 except by a powerup. 0 The write lock and lock-down bits can be changed by writing new values to them. 1 WRITE, PROGRAM, and ERASE operations in this sector will not be executed. The memory contents will not be changed. 0 WRITE, PROGRAM, or ERASE operations in this sector are executed and will modify the sector contents. Reserved Sector lock down Sector write lock 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory READ OTP READ OTP The device is first selected by driving chip select (S#) LOW. The command code for the READ OTP (one-time programmable) command is followed by a 3-byte address (A23A0) and a dummy byte. Each bit is latched in on the rising edge of serial clock (C). Then the memory contents at that address are shifted out on serial data output (DQ1). Each bit is shifted out at the maximum frequency fCmax on the falling edge of C. The address is automatically incremented to the next higher address after each byte of data is shifted out. There is no rollover mechanism with the READ OTP command. This means that the READ OTP command must be sent with a maximum of 65 bytes to read because once the 65th byte has been read, the same 65th byte continues to be read on the DQ1 pin. The READ OTP command is terminated by driving S# HIGH. S# can be driven HIGH at any time during data output. Any READ OTP command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without having any effect on the cycle that is in progress. Figure 19: READ OTP Command Sequence 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB DQ1 A[MAX] DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dummy cycles Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN Don't Care 1. Cx = 7 + (A[MAX] + 1). 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory PAGE PROGRAM PAGE PROGRAM The PAGE PROGRAM command allows bytes in the memory to be programmed, which means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be accepted a WRITE ENABLE command must be executed. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by the command code, three address bytes, and at least one data byte on serial data input (DQ0). If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page; that is, from the address whose eight least significant bits (A7-A0) are all zero. S# must be driven LOW for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effects on the other bytes of the same page. For optimized timings, it is recommended to use the PAGE PROGRAM command to program all consecutive targeted bytes in a single sequence rather than to use several PAGE PROGRAM sequences, each containing only a few bytes. S# must be driven HIGH after the eighth bit of the last data byte has been latched in. Otherwise the PAGE PROGRAM command is not executed. As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cycles's duration is tPP. While the PAGE PROGRAM cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. A PAGE PROGRAM command is not executed if it applies to a page protected by the block protect bits BP2, BP1, and BP0. Figure 20: PAGE PROGRAM Command Sequence 0 7 8 Cx C LSB A[MIN] LSB DIN Command DQ[0] MSB A[MAX] Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN DIN DIN DIN DIN DIN DIN DIN DIN MSB 1. Cx = 7 + (A[MAX] + 1). 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory DUAL INPUT FAST PROGRAM DUAL INPUT FAST PROGRAM The DUAL INPUT FAST PROGRAM command is similar to the PAGE PROGRAM command, except that data is entered on two pins (DQ0 and DQ1) instead of one, doubling the data transfer bandwidth. The DUAL INPUT FAST PROGRAM command is entered by driving Chip Select S# LOW, followed by the command code, three address bytes, and at least one data byte on serial data input (DQ0). If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page is programmed from the start address of the same page; that is, from the address whose eight least significant bits (A7-A0) are all zero. S# must be driven LOW for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data is discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effect on other bytes in the same page. For optimized timings, it is recommended to use the DUAL INPUT FAST PROGRAM command to program all consecutive targeted bytes in a single sequence than to use several DUAL INPUT FAST PROGRAM sequences, each containing only a few bytes. S# must be driven HIGH after the eighth bit of the last data byte has been latched in. Otherwise the DUAL INPUT FAST PROGRAM command is not executed. As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cycle's duration is tPP. While the DUAL INPUT FAST PROGRAM cycle is in progress, the status register may be read to check the value of the write In progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. A DUAL INPUT FAST PROGRAM command is not executed if it applies to a page protected by the block protect bits BP2, BP1, and BP0. Figure 21: DUAL INPUT FAST PROGRAM Command Sequence 0 7 8 Cx C LSB DQ0 MSB DQ1 A[MIN] Command LSB DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN A[MAX] High-Z MSB Notes: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. For the M25PX16, the DUAL INPUT FAST PROGRAM command is available only in VCC range 2.7 V - 3.6 V. 2. Cx = 7 + (A[MAX] + 1). 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory PROGRAM OTP PROGRAM OTP The PROGRAM OTP command allows a maximum of 64 bytes in the OTP memory area to be programmed, which means the bits are changed from 1 to 0. Before a PROGRAM OTP command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The PROGRAM OTP command is entered by driving chip select (S#) LOW, followed by the command opcode, three address bytes, and at least one data byte on serial data input (DQ0). S# must be driven HIGH after the eighth bit of the last data byte has been latched in. Otherwise the PROGRAM OTP command is not executed. There is no rollover mechanism with the PROGRAM OTP command. This means that the PROGRAM OTP command must be sent with a maximum of 65 bytes to program. When all 65 bytes have been latched in, any following byte will be discarded. As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cycle's duration is tPP. While the PROGRAM OTP cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed PROGRAM OTP cycle, and 0 when when the cycle is completed. At some unspecified time before the cycle is complete, the WEL bit is reset. Figure 22: PROGRAM OTP Command Sequence 0 7 8 Cx C LSB A[MIN] LSB DIN Command DQ[0] MSB A[MAX] Note: DIN DIN DIN DIN DIN DIN DIN DIN MSB 1. Cx = 7 + (A[MAX] + 1). The OTP control byte is byte 64. Bit 0 of this OTP control byte is used to permanently lock the OTP memory array. * When bit 0 of the OTP control byte = 1, the 64 bytes of the OTP memory array can be programmed. * When bit 0 of the OTP control byte = 0, the 64 bytes of the OTP memory array are read-only and cannot be programmed anymore. Once a bit of the OTP memory has been programmed to 0, it can no longer be set to 1. Therefore, as soon as bit 0 of the control byte is set to 0, the 64 bytes of the OTP memory array is set permanently as read-only. Any PROGRAM OTP command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory PROGRAM OTP Figure 23: How to Permanently Lock the OTP Bytes 64 data bytes OTP control byte byte byte byte 0 1 2 byte byte 63 64 X X X X X X X bit 0 When bit 0 = 0 the 64 OTP bytes become READ only Bit 1 to bit 7 are NOT programmable 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory WRITE to LOCK REGISTER WRITE to LOCK REGISTER The WRITE to LOCK REGISTER instruction allows the lock register bits to be changed. Before the WRITE to LOCK REGISTER instruction can be accepted, a WRITE ENABLE instruction must have been executed previously. After the WRITE ENABLE instruction has been decoded, the device sets the write enable latch (WEL) bit. The WRITE to LOCK REGISTER instruction is entered by driving chip select (S#) LOW, followed by the instruction code, three address bytes, and one data byte on serial data input (DQ0). The address bytes must point to any address in the targeted sector. S# must be driven HIGH after the eighth bit of the data byte has been latched in. Otherwise the WRITE to LOCK REGISTER instruction is not executed. Lock register bits are volatile, and therefore do not require time to be written. When the WRITE to LOCK REGISTER instruction has been successfully executed, the WEL bit is reset after a delay time of less than tSHSL minimum value. Any WRITE to LOCK REGISTER instruction issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 24: WRITE to LOCK REGISTER Instruction Sequence 0 7 8 Cx C LSB A[MIN] LSB DIN Command DQ[0] MSB A[MAX] Note: DIN DIN DIN DIN DIN DIN DIN DIN MSB 1. Cx = 7 + (A[MAX] + 1). Table 18: Lock Register In Sector Bit Value All sectors b7-b2 0 All sectors b1 Sector lock-down bit value All sectors b0 Sector write lock bit value Note: Values of b1 and b0 after power-up are defined in Power-Up/Down and Supply Line Decoupling (page 47). For the sector lock down and sector write lock values, see the Lock Register Out table. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory SUBSECTOR ERASE SUBSECTOR ERASE The SUBSECTOR ERASE command sets to 1 (FFh) all bits inside the chosen subsector. Before the SUBSECTOR ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The SUBSECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address inside the subsector is a valid address for the SUBSECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the last address byte has been latched in. Otherwise the SUBSECTOR ERASE command is not executed. As soon as S# is driven HIGH, the self-timed SUBSECTOR ERASE cycle is initiated; the cycle's duration is tSSE. While the SUBSECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SUBSECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is complete, the WEL bit is reset. A SUBSECTOR ERASE command issued to a sector that is hardware or software protected is not executed. Any SUBSECTOR ERASE command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 25: SUBSECTOR ERASE Command Sequence 0 7 8 Cx C LSB DQ0 MSB Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN A[MIN] Command A[MAX] 1. Cx = 7 + (A[MAX] + 1). 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory SECTOR ERASE SECTOR ERASE The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address inside the sector is a valid address for the SECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the last address byte has been latched in. Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH, the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is tSE. While the SECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. A SECTOR ERASE command is not executed if it applies to a sector that is hardware or software protected. Figure 26: SECTOR ERASE Command Sequence 0 7 8 Cx C LSB DQ0 MSB Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN A[MIN] Command A[MAX] 1. Cx = 7 + (A[MAX] + 1). 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory BULK ERASE BULK ERASE The BULK ERASE command sets all bits to 1 (FFh). Before the BULK ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The BULK ERASE command is entered by driving chip select (S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the command code has been latched in. Otherwise the BULK ERASE command is not executed. As soon as S# is driven HIGH, the self-timed BULK ERASE cycle is initiated; the cycle's duration is tBE. While the BULK ERASE cycle is in progress, the status register may be read to check the value of the write In progress (WIP) bit. The WIP bit is 1 during the self-timed BULK ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. The BULK ERASE command is executed only if all block protect (BP2, BP1, BP0) bits are 0. The BULK ERASE command is ignored if one or more sectors are protected. Figure 27: BULK ERASE Command Sequence 0 7 C LSB Command DQ0 MSB 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory DEEP POWER-DOWN DEEP POWER-DOWN Executing the DEEP POWER-DOWN command is the only way to put the device in the lowest power consumption mode, the DEEP POWER-DOWN mode. The DEEP POWERDOWN command can also be used as a software protection mechanism while the device is not in active use because in the DEEP POWER-DOWN mode the device ignores all WRITE, PROGRAM, and ERASE commands. Driving chip select (S#) HIGH deselects the device, and puts it in the STANDBY POWER mode if there is no internal cycle currently in progress. Once in STANDBY POWER mode, the DEEP POWER-DOWN mode can be entered by executing the DEEP POWERDOWN command, subsequently reducing the standby current from ICC1 to ICC2. To take the device out of DEEP POWER-DOWN mode, the RELEASE from DEEP POWER-DOWN command must be issued. Other commands must not be issued while the device is in DEEP POWER-DOWN mode. The DEEP POWER-DOWN mode stops automatically at power-down. The device always powers up in STANDBY POWER mode. The DEEP POWER-DOWN command is entered by driving S# LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the command code has been latched in. Otherwise the DEEP POWER-DOWN command is not executed. As soon as S# is driven HIGH, it requires a delay of tDP before the supply current is reduced to ICC2 and the DEEP POWER-DOWN mode is entered. Any DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 28: DEEP POWER-DOWN Command Sequence 0 7 C LSB t DP Command DQ0 MSB Standby Mode Deep Power-Down Mode Don't Care 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory RELEASE from DEEP POWER-DOWN RELEASE from DEEP POWER-DOWN Once the device has entered DEEP POWER-DOWN mode, all commands are ignored except RELEASE from DEEP POWER-DOWN. Executing this command takes the device out of the DEEP POWER-DOWN mode. The RELEASE from DEEP POWER-DOWN command is entered by driving chip select (S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire duration of the sequence. The RELEASE from DEEP POWER-DOWN command is terminated by driving S# high. Sending additional clock cycles on serial clock C while S# is driven LOW causes the command to be rejected and not executed. After S# has been driven high, followed by a delay, tRDP, the device is put in the STANDBY mode. S# must remain HIGH at least until this period is over. The device waits to be selected so that it can receive, decode, and execute commands. Any RELEASE from DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 29: RELEASE from DEEP POWER-DOWN Command Sequence 0 7 C LSB RDP t Command DQ0 MSB DQ1 High-Z Deep Power-Down Mode Standby Mode Don't Care 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Power-Up/Down and Supply Line Decoupling Power-Up/Down and Supply Line Decoupling At power-up and power-down, the device must not be selected; that is, chip select (S#) must follow the voltage applied on V CC until V CC reaches the correct value: * VCC,min at power-up, and then for a further delay of tVSL * VSS at power-down A safe configuration is provided in the SPI Modes section. To avoid data corruption and inadvertent write operations during power-up, a poweron-reset (POR) circuit is included. The logic inside the device is held reset while V CC is less than the POR threshold voltage, V WI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores the following instructions until a time delay of tPUW has elapsed after the moment that V CC rises above the VWI threshold: * * * * * * * * * WRITE ENABLE PAGE PROGRAM DUAL INPUT FAST PROGRAM PROGRAM OTP SUBSECTOR ERASE SECTOR ERASE BULK ERASE WRITE STATUS REGISTER WRITE to LOCK REGISTER However, the correct operation of the device is not guaranteed if, by this time, V CC is still below V CC.min. No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should be sent until: * tPUW after V CC has passed the V WI threshold * tVSL after V CC has passed the V CC,min level If the time, tVSL, has elapsed, after V CC rises above V CC,min, the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed. VPPH must be applied only when V CC is stable and in the V CC,min to V CC,max voltage range. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Power-Up/Down and Supply Line Decoupling Figure 30: Power-Up Timing VCC VCC,max PROGRAM, ERASE, and WRITE commands are rejected by the device Chip selection not allowed VCC,min t RESET state of the device VSL READ access allowed Device fully accessible VWI t PUW Time After power-up, the device is in the following state: * * * * * Standby power mode (not the deep power-down mode) Write enable latch (WEL) bit is reset Write in progress (WIP) bit is reset Write lock bit = 0 Lock down bit = 0 Normal precautions must be taken for supply line decoupling to stabilize the V CC supply. Each device in a system should have the V CC line decoupled by a suitable capacitor close to the package pins; generally, this capacitor is of the order of 100 nF. At power-down, when V CC drops from the operating voltage to below the POR threshold voltage V WI, all operations are disabled and the device does not respond to any instruction. Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress, some data corruption may result. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Maximum Ratings and Operating Conditions Maximum Ratings and Operating Conditions Caution: Stressing the device beyond the absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device beyond any specification or condition in the operating sections of this datasheet is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 19: Absolute Maximum Ratings Symbol Parameter TSTG Storage temperature TLEAD Lead temperature during soldering Min Max Units -65 150 C -- See note C VCC+0.6 V Notes 1 VIO Input and output voltage (with respect to ground) -0.6 VCC Supply voltage -0.6 4.0 V VPP FAST PROGRAM / ERASE voltage -0.2 10.0 V 2 VESD Electrostatic discharge voltage (Human Body model) -2000 2000 V 3 Notes: 1. The TLEAD signal is compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Micron RoHS compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Avoid applying VPPH to the W#/VPP pin during the BULK ERASE operation. 3. The VESD signal: JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 , R2 = 500 ). Table 20: Operating Conditions Symbol Parameter Min Max Unit VCC Supply voltage 2.7 3.6 V VPPH Supply voltage on VPP pin 8.5 9.5 V TA Ambient operating temperature (device grade 6) -40 85 C TA Ambient operating temperature (device grade 3) -40 125 C Table 21: Data Retention and Endurance Parameter Condition Min Max Unit PROGRAM and ERASE cycles Grade 3; Autograde 6; Grade 6 100,000 - Cycles per sector 20 - years Data Retention 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN at 55C 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Electrical Characteristics Electrical Characteristics Table 22: Power Up Timing Specifications Symbol Parameter tVSL VCC[MIN] to S# LOW tPUW Time delay to WRITE command VWI Write Inhibit voltage Min Max Units 30 - s 1 10 ms 1.5 2.5 V Table 23: DC Current Specifications Symbol Parameter Test Condition Min Max Units ILI Input leakage current - - 2 A ILO Output leakage current - - 2 A ICC1 Standby current S# = VCC, VIN = VSS or VCC - 50/100 A ICC2 Deep power-down current S# = VCC, VIN = VSS or VCC - 10/100 A ICC3 Operating current (READ) C = 0.1VCC / 0.9VCC at 75MHz, DQ1 = open - 12 mA C = 0.1VCC / 0.9VCC at 33MHz, DQ1 = open - 4 mA Operating current (DUAL OUTPUT FAST READ) C = 0.1VCC / 0.9VCC at 75MHz, DQ1 = open - 15 mA Operating current (PAGE PROGRAM) S# = VCC - 15 mA Operating current (DUAL INPUT FAST PROGRAM) S# = VCC - 15 mA ICC5 Operating current (WRITE STATUS REGISTER) S# = VCC - 15 mA ICC6 Operating current (SECTOR ERASE) S# = VCC - 15 mA ICC7 Operating current (BULK ERASE) S# = VCC - 15 mA ICC4 Note: Notes 1 1. All specifications apply to both device grade 6 and device grade 3, except for the following standby and deep power-down current differences: device grade 6, ICC1 = 50A and ICC2 = 10A; device grade 3, ICC1 = 100A and ICC2 = 100A. Table 24: DC Voltage Specifications Symbol Parameter Test Condition Min Max Units VIL Input LOW voltage - -0.5 0.3VCC V VIH Input HIGH voltage - 0.7VCC VCC+0.4 V VOL Output LOW voltage IOL = 1.6mA - 0.4 V 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Electrical Characteristics Table 24: DC Voltage Specifications (Continued) Symbol Parameter Test Condition Min Max Units VOH Output HIGH voltage IOL = -100A VCC-0.2 - V Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. All specifications apply to both device grade 6 and device grade 3. 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory AC Characteristics AC Characteristics In the following AC specifications, output High-Z is defined as the point where data out is no longer driven; however, this is not applicable to the M25PX64 device. Table 25: AC Measurement Conditions Symbol CL Parameter Min Max Unit 30 30 pF - 5 ns Input pulse voltages 0.2VCC 0.8VCC V Input timing reference voltages 0.3VCC 0.7VCC V Output timing reference voltages VCC / 2 VCC / 2 V Load capacitance Input rise and fall times Figure 31: AC Measurement I/O Waveform Input levels Input and output timing reference levels 0.8VCC 0.7VCC 0.5VCC 0.2VCC 0.3VCC Table 26: Capacitance Symbol Parameter CIN/OUT CIN Test condition Min Max Unit Notes 1 Input/output capacitance (DQ0/DQ1) VOUT = 0 V - 8 pF Input capacitance (other pins) VIN = 0 V - 6 pF Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. Values are sampled only, not 100% tested, at TA=25C and a frequency of 33MHz. 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory AC Characteristics Table 27: AC Specifications (75MHz) Note 1 applies to the entire table. Symbol Alt. Parameter Min Typ Max Unit Notes fC fC Clock frequency for all commands (except READ) DC - 75 MHz fR - Clock frequency for READ command DC - 33 MHz tCH tCLH Clock HIGH time 6 - - ns 2 tCL tCLL Clock LOW time 6 - - ns 2 tCLCH - Clock rise time (peak to peak) 0.1 - - V/ns 3, 4 tCHCL - Clock fall time (peak to peak) 0.1 - - V/ns 3, 4 tSLCH tCSS S# active setup time (relative to C) 5 - - ns S# not active hold time (relative to C) 5 - - ns tCHSL tDVCH tDSU Data-in setup time 2 - - ns tCHDX tDH Data-in hold time 5 - - ns tCHSH - S# active hold time (relative to C) 5 - - ns tSHCH - S# not active setup time (relative to C) 5 - - ns tSHSL tCSH S# deselect time 80 - - ns tSHQZ tDIS Output disable time - - 8 ns tCLQV tV Clock LOW to output valid under 30pF - - 8 ns Clock LOW to output valid under 10pF - - 6 ns tCLQX tHO Output hold time 0 - - ns tHLCH - HOLD# setup time (relative to C) 5 - - ns tCHHH - HOLD# hold time (relative to C) 5 - - ns tHHCH - HOLD# setup time (relative to C) 5 - - ns 3 tCHHL - HOLD# hold time (relative to C) 5 - - ns tHHQX tLZ HOLD# to output Low-Z - - 8 ns 3 tHLQZ tHZ HOLD# to output High-Z - - 8 ns 3 tWHSL - WRITE PROTECT setup time 20 - - ns 5 tSHWL - WRITE PROTECT hold time 100 - - ns 5 tVPPHSL - Enhanced program supply voltage HIGH (VPPH) to S# LOW 200 - - ns 6 tDP - S# HIGH to deep power-down mode - - 3 s 3 tRDP - S# HIGH to standby mode - - 30 s 3 tW - WRITE STATUS REGISTER cycle time - 1.3 15 ms tPP - PAGE PROGRAM cycle time (256 bytes) - 0.8 5 ms 7 tPP - PAGE PROGRAM cycle time (n bytes) - int(n/8) x 0.025 5 ms 7, 8 tPP - PROGRAM OTP cycle time (64 bytes) - 0.2 5 ms 7 tSSE - SUBSECTOR ERASE cycle time - 70 150 ms tSE - SECTOR ERASE cycle time - 0.7 3 s 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory AC Characteristics Table 27: AC Specifications (75MHz) (Continued) Note 1 applies to the entire table. Symbol Alt. tBE - BULK ERASE cycle time Notes: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN Parameter Min Typ Max Unit - 34 80 s Notes 1. AC specification values for 75MHz operations shown here are allowed only on the VCC range 2.7V - 3.6V. Typical values are given for TA = 25C. 2. The sum of tCH + tCL signal values must be greater than or equal to 1/fC. 3. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, and tRDP signal values are guaranteed by characterization, not 100% tested in production. 4. The tCLCH and tCHCL signals clock rise and fall time values are expressed as a slew-rate. 5. The tWHSL and tSHWL signal values are only applicable as a constraint for a WRITE STATUS REGISTER command when SRWD bit is set at 1. 6. The tVPPHSL signal value for VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. Avoid applying VPPH to the W/VPP pin during the BULK ERASE operation. 7. To obtain optimized timings (tPP) when programming consecutive bytes with the PAGE PROGRAM command, use one sequence including all the bytes versus several sequences of only a few bytes (1 is less than or equal to n is less than or equal to 256). 8. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) = 4 int(15.3) =16. 9. OE# may be delayed by up to tELQV - tGLQV after CE#'s falling edge without impact to tELQV. 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory AC Characteristics Figure 32: Serial Input Timing tSHSL S# tCHSL tCHSH tSLCH tSHCH C tDVCH tCHCL tCHDX DQ0 tCLCH LSB IN MSB IN high impedance DQ1 Figure 33: Write Protect Setup and Hold During WRSR when SRWD = 1 Timing W#/VPP tSHWL tWHSL S# C DQ0 high impedance DQ1 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory AC Characteristics Figure 34: Hold Timing S# tHLCH tHHCH tCHHL C tCHHH tHLQZ tHHQX DQ1 DQ0 HOLD# Figure 35: Output Timing S# tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT DQ1 tQLQH tQHQL DQ0 ADDRESS LSB IN 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory AC Characteristics Figure 36: VPPH Timing end of command (identified by WIP polling) S# C DQ0 VPPH VPP 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN tVPPHSL 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Package Information Package Information Figure 37: VFQFPN8 (MLP8) 6mm x 5mm 0.10 MAX/ 0 MIN 5.75 TYP Pin one indicator 4.75 TYP 5 TYP +0.30 4 -0.20 1.27 TYP 0.10 M C A B B 0.15 C A 6 TYP A 2x 0.15 C B 0.10 C B 0.10 C A +0.15 0.60 -0.10 3.40 0.20 +0.08 0.40 -0.05 12 0.05 +0.15 0.85 -0.05 0.20 TYP 0 MIN/ 0.05 MAX Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 0.65 TYP C 1. Drawing is not to scale. 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Package Information Figure 38: SO8W 208 mils Body Width 1.70 MIN/ 1.91 MAX 0.36 MIN/ 0.48 MAX 1.78 MIN/ 2.16 MAX 0.15 MIN/ 0.25 MAX 0.10 MAX 1.27 TYP 5.08 MIN/ 5.49 MAX 8 7.70 MIN/ 8.10 MAX 5.08 MIN/ 5.49 MAX 1 Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 0.05 MIN/ 0.25 MAX 0 MIN/ 10 MAX 0.50 MIN/ 0.80 MAX 1. Drawing is not to scale. 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Package Information Figure 39: SO16W 300 mils Body Width 10.10 MIN/ 10.50 MAX 16 0.25 MIN/ x 45 0.75 MAX 9 0.23 MIN/ 0.32 MAX 7.40 MIN/ 7.60 MAX 10.00 MIN/ 10.65 MAX o 1 0 MIN/ o 8 MAX 8 2.35 MIN/ 2.65 MAX 0.10 MAX 0.33 MIN/ 0.51 MAX 1.27 TYP Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 0.10 MIN/ 0.30 MAX 0.40 MIN/ 1.27 MAX 1. Drawing is not to scale. 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Package Information Figure 40: SO8N 150 mils Body Width 0.25 MIN/ x 45 0.50 MAX 1.75 MAX/ 1.25 MIN 0.17 MIN/ 0.23 MAX 0.10 MAX 0.28 MIN/ 0.48 MAX 1.27 TYP 0.25mm Gauge plane 4.90 0.10 8 0o MIN/ 8o MAX 6.00 0.20 3.90 0.10 1 0.10 MIN/ 0.25 MAX 0.40 MIN/ 1.27 MAX 1.04 TYP Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. Drawing is not to scale. 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Package Information Figure 41: QFN8L 6mm x 5mm (MLP8) 5.00 TYP 3.00 + 0.20 0PIN 1 ID OPTION +0.15 0.60 -0.10 6.00 TYP 3.00 +0.20 1.27 TYP 0.90 +0.10 +0.08 0.40 -0.05 0.02 TYP/0.05 MAX 0.08 0.20 TYP Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. Drawing is not to scale. 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Package Information Figure 42: TBGA 24-Ball, 6mm x 8mm DETAIL A Top view (balls down) +0.10 6.00 -0.10 MAX 1.50 TYP 0.15 (4x) SOLDER BALL (Typ) A +0.05 0.40 -0.05 2.00 TYP D Ball A1 corner index area +0.10 8.00 -0.10 0.15 S C A S B S 0.08 S C MAX ISO E E B Bottom view seating plane C (balls up) 4.00 TYP Detail A 0.20 MIN 1.00 TYP 0.10 MAX C 0.79 TYP 0.10 MAX C 1.20 MAX E D D 4.00 TYP C B 1.00 TYP A 2.00 TYP 1 1.00 TYP Note: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 2 3 4 5 E 1. Drawing is not to scale. 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Device Ordering Information Device Ordering Information Micron Serial NOR Flash memory is available in different configurations and densities. Verify valid part numbers by using Micron's part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. For more information on how to identify products and top-side marking by the process identification letter, refer to technical note TN-12-24, Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product Families. Table 28: Part Number Information Scheme Part Number Category Category Details Device type M25PX = serial Flash memory, 4KB and 64KB erasable sectors, dual I/O Density 32 = 32Mb (4Mb x 8-bit) Security features - = no extra security Notes 1 SO = OTP configurable ST = OTP configurable plus protection at power-up S = CFD programmed with UID Operating voltage V = VCC = 2.7 to 3.6V Package MP = VFQFPN 6mm x 5mm (MLP8) MW = SO8W (208 mils width) MF = SO16 (300 mils width) ZM = TBGA24 6mm x 8mm Grade 6 = Industrial temperature range: -40C to 85C. Device tested with standard test flow (option A is not selected). Device tested with high reliability certified test flow if automotive grade option A is selected. 3 = Automotive temperature range: -40C to 125C. Device tested with high reliability certified test flow. Packing 2 E = Standard packing F = Tape and reel packing Lithography B = 110nm, Fab 2 diffusion plant Blank = 110nm Automotive grade A = Automotive -40C to 85C (only with device grade 6). Device tested with high reliability certified test flow. 2 Blank = Automotive -40C to 125C Notes: 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 1. Secure options available upon customer request. 2. Micron strongly recommends the use of the Automotive Grade devices (AutoGrade 6 and Grade 3) for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PX32 Serial Flash Embedded Memory Revision History Revision History Rev. D - 06/18 * Added Important Notes and Warnings section for further clarification aligning to industry standards Rev. C - 10/14 * Corrected tape and reel packing information code in the Part Number Information Scheme table. Rev. B - 03/13 * Replaced SO8W package dimension figure * Revised text at the beginning of Ordering Information Rev. A - 06/12 * Initial Micron release with rebrand. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 09005aef845665a9 m25px32.pdf - Rev. D 06/18 EN 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved.