The 1Gb chip is organized as 32Mbit x 4 I/O x 8 bank, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These

synchronous devices achieve high speed double-data-rate transfer rates of up to 800 Mb/sec/pin for general appli-

cations.

The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write

latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance

adjustment and (5) an ODT (On-Die Termination) function.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended

DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x4/x8 organized components

and A 13 bit address bus for x16 component is used to convey row, column, and bank address devices.

not defined, therefore the extended mode register must be written after power-up for proper operation. The extended

mode register is written by asserting low on , , , , BA1 and high on BA0, while controlling the state of the

address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended

mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the

EMRS (1). Mode register contents can be changed using the same command and clock cycle requirements during normal

operation as long as all banks are in precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half

strength output driver. A3-A5 determines the additive latency, A7-A9 are used for OCD control, A10 is used for 

disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning

MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully

(and RDQS) signals are driven high and all  (and ) signals are driven low. In Drive (0) mode, all DQ, DQS (and

RDQS) signals are driven low and all  (and ) signals are driven high. In adjust mode, BL = 4 of operation code

data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18

Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are

specified in the following table. OCD applies only to normal full strength output drive setting defined by EMRS (1) and if half

strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD

default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,

To adjust output driver impedance, controllers must issue the ADJUST EMRS (1) command along with a 4 bit burst code to

DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before

activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at

bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs

simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength

diagram. Input data pattern for adjustment, DT0 ~ DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or

interleave).

Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD

impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers

are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.

ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQ, DQS,

, RDQS, , and DM signal for x8 configurations via the ODT control pin. For x16 configuration ODT is applied to

Termination included on all DQs, DM, DQS, , RDQS, and  pins.

However, to prevent any impedance glitch on the channel, the following conditions must be met.

- tAOFD must be met before issuing the EMRS command.

- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.

Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turn on the ODT.

Following timing diagram shows the proper Rtt update procedure.