UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com Positive Floating Hot-Swap Power Manager FEATURES DESCRIPTION * * * * * * * The UCCx917 family of positive-floating hot-swap managers provides complete power management, hot-swap, and fault handling capability. The voltage limitation of the application is only restricted by the external component voltage limitations. The device provides its own supply voltage via a charge pump referenced to VOUT. The onboard 10-V shunt regulator protects the device from excess voltage. The devices also have catastrophic fault indication to alert the user that the ability to shut off the output N-channel MOSFET has been bypassed. All control and housekeeping functions are integrated and externally programmable. These include the fault current level, maximum output sourcing current, maximum fault time, soft-start time, and average N-channel MOSFET power limiting. 1 * * * * Manages Hot-Swap of 15 V and Above Precision Fault Threshold Programmable Average Power Limiting Programmable Linear Current Control Programmable Overcurrent Limit Programmable Fault Time Internal Charge Pump to Control External N-channel MOSFET Device Fault Output and Catastrophic Fault Indication Fault Mode Programmable to Latch or Retry Shutdown Control Undervoltage Lockout APPLICATIONS * * 390-V DC Distribution General High-Voltage Power Management The fault level across the current-sense amplifier is fixed at 50 mV to minimize total drop out. Once 50 mV is exceeded across the current-sense resistor, the fault timer starts. The maximum allowable sourcing current is programmed with a voltage divider from the VREF/CATFLT pin to generate a fixed voltage on the MAXI pin. The current level at which the output appears as a current source is equal to VMAXI divided by the current-sense resistor. If desired, a controlled current startup can be programmed with a capacitor on MAXI. When the output current is below the fault level, the output device is switched on with full gate drive. When the output current exceeds the fault level, but is less than maximum allowable sourcing level programmed by MAXI, the output remains switched on, and the fault timer starts charging the timing capacitor CT. Once CT charges to 2.5 V, the output device is turned off and attempts either a retry sometime later or waits for the state on the LATCH pin to change if in latch mode. When the output current reaches the maximum sourcing current level, the output device appears as a current source. ORDERING INFORMATION TJ PACKAGED DEVICES DIP (J) DIP (N) SOIC (D) -40C to 85C UCC2917J UCC2917N UCC2917D 0C to 70C UCC3917J UCC3917N UCC3917D 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright (c) 2000-2011, Texas Instruments Incorporated PRODUCT PREVIEW Check for Samples: UCC2917, UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN Output Current Supply (2) SHTDWN, LATCH, VREF (2) UNIT MAX 20 mA -500 A mA Line Current PLIM 10 Input voltage MAXI VDD + 0.3 V Junction temperature, TJ -55 150 C Storage temperature, Tstg -65 150 C 300 C Lead temperature (Soldering, 10 sec.) (1) PRODUCT PREVIEW (2) 2 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.colsep Currents are positive into, negative out of the specified terminal. Consult the Packaging section of the Interface Products Data Book (TI Literature Number SLUD002) for thermal limitations and considerations of package. Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS 0C TA 70C for the UCC3917, -40C to 85C for the UCC2917, CCT = 4.7 nF, TA = TJ, all voltages are with respect to VOUT, current is positive into and negative out of the specified terminal, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY Supply current (1) IDD 4.0 5 11 mA UVLO turn on threshold From VOUT 7.9 8.8 9.7 V UVLO off voltage 5.5 6.5 7.5 V VSS regulator voltage -6 -5 -4 V 47.5 50 53 mV 46 50 54 mV 50 500 -78 -50 -28 A 4.5 V TA = 25C Overcurrent threshold Over operating temperature Overcurrent input bias CT charge current bias VCT = 1 V CT catastrophic fault threshold D 3.4 CT fault threshold 2.25 2.5 2.75 V CT reset threshold 0.32 0.5 0.62 V 1.7% 2.7% 3.7% IOUT = 0 6 8 10 IOUT = -100 A 5 7 9 0.03 0.50 0.6 0.9 Output duty cycle Fault condition PRODUCT PREVIEW FAULT TIMING OUTPUT VOH High-level output voltage VOL Output low voltage IOUT = 500 A IOUT = 1 mA V V LINEAR CURRENT Sense control voltage IBIAS Input bias current VMAXI = 100 mV 85 100 115 mV VMAXI = 400 mV 370 400 430 mV 50 500 nA 2.4 2.8 V VMAXI = 200 mV SHUTDOWN Shutdown threshold 2.0 Input current VSHTDWN = 0 V 40 60 A 100 500 ns 1.7 2 2.3 V 24 40 60 A 24 Shutdown delay LATCH VLATCH Latch threshold Input current VLATCH = 0 V Fault output high VCT = 0 V, ISOURCE = 0 A Fault output low VCT = 5 V, ISINK = 200 A FLTOUT 6 8 10 V 0.01 0.05 V 4.5 5. 5.5 V IPLIM = 64 A 0.6% 1.2% 1.7% IPLIM = 1 mA 0.045% 0.1% 0.2% POWER LIMITING IPLIM = 64 A VSENSE regulator voltage Duty cycle control VREF/CATFLT VREF regulator voltage ISINK (1) 4.5 Fault output low IVREF/CATFLT = 5 mA Output sink current VCT = 5 V, VVREF/CATFLT = 5 V Overload comparator threshold Relative to MAXI 5. 5.5 0.22 0.50 V 15 40 70 mA 110 200 290 mV V Set by user using the RSS resistor. Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 3 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com D PACKAGE 16 PINS (TOP VIEW) J, N PACKAGE 16 PINS (TOP VIEW) PLIM 1 16 LATCH SENSE 2 15 VREF/CATFLT OUTPUT 3 14 MAXI VOUT 4 13 VDD C2N 5 12 SHTDWN C2P 6 11 FLTOUT C1N 7 10 CT C1P 8 9 LATCH PLIM 1 16 SENSE 2 15 VREF/ CATFLT OUTPUT 3 14 MAXI VOUT 4 13 VDD C2N 5 12 SHTDWN C2P 6 11 FLTOUT C1N 7 10 CT C1P 8 9 VSS VSS DEVICE INFORMATION PRODUCT PREVIEW PIN DESCRIPTIONS PIN NAME NO. I/O DESCRIPTION C1N 7 I Negative side of the upper charge-pump capacitor. C1P 8 I Positive side of the upper charge-pump capacitor. C2N 5 I Negative side of the lower charge-pump capacitor. C2P 6 I Positive side of lower charge-pump capacitor. CT 10 I A capacitor is connected to this pin to set the fault time. The fault time must be more than the time to charge the external load capacitance (see application information). FLTOUT 11 O Provides fault output indication. Interface to this pin is usually performed through level-shift transistors. Under a non-fault condition, FLTOUT is pulled to a high state. When a fault is detected by the fault timer or the undervoltage lockout, this pin is driven to a low state, indicating the output N-channel MOSFET is in the off state. LATCH 16 I Pulling this pin low causes a fault to latch until this pin is brought high or a power-on reset is attempted. However, pulling this pin high before the reset time is reached does not clear the fault until the reset time is reached. Keeping LATCH high results in normal operation of the fault timer. Users should note there is an R-C delay dependent upon the external capacitor at this pin. MAXI 14 I Programs the maximum-allowable sourcing current. Since VREF/CATFLT is a regulated voltage, a voltage divider can be derived to generate the program level for MAXI. The current level at which the output appears as a current source is equal to the voltage on MAXI divided by the current-sense resistor. If desired, a controlled current start-up can be programmed with a capacitor on MAXI (to VOUT), and a programmed start delay can be achieved by driving the shutdown with an open collector/drain device into an RC network. OUTPUT 3 O Gate drive to the N-channel MOSFET pass element. PLIM 1 I This feature ensures that the average external N-channel MOSFET power dissipation is controlled. A resistor is connected from this pin to the drain of the external N-channel MOSFET pass element. When the voltage across the N-channel MOSFET exceeds 5 V, current flows into PLIM, which adds to the fault timer charge current, reducing the duty cycle from the 3% level. SENSE 2 I Input voltage from the current-sense resistor. When there is greater than 50 mV across this pin with respect to VOUT, a fault is sensed, and the CCT capacitor starts to charge. SHTDWN 12 I This pin provides shutdown control. Interface to this pin is usually performed through level-shift transistors. When shutdown is driven low, the output disables the N-channel MOSFET pass device. VOUT 4 I Ground reference for the device. 4 Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com PIN DESCRIPTIONS (continued) PIN NAME NO. VDD I/O DESCRIPTION I Power to the device is supplied by an external current-limiting resistor on initial power up or if the load is shorted. As the load voltages rises (VOUT), a small amount of power is drawn from VOUT by an internal charge pump. The charge pump's input voltage is regulated by an on-device 5-V zener. Power to VDD is supplied by the charge pump under normal operation (i.e., external FET is on). 13 VREF/CATFLT 15 O This pin primarily provides an output reference for the programming of MAXI. Secondarily, it provides catastrophic fault indication. In a catastrophic fault, when the device unsuccessfully attempts to shutdown the N-channel MOSFET pass device, this pin pulls to a low state when CT charges above the catastrophic fault threshold. A possible application for this pin is to trigger the shutdown of an auxiliary FET in series with the main FET for redundancy. VSS 9 I Negative reference out of the device. This pin is normally current fed via a resistor to load ground. FUNCTIONAL BLOCK DIAGRAM LATCH 13 16 VDD UVLO >10 V = Enable < 6 V = Disable 40 mA - VDD 5V 40 mA SHTDWN 12 PLIM 3 OUTPUT 2 SENSE 4 VOUT + VDD Disable + VOUT 1 - VOUT VOUT Output Low FLTOUT 11 C1P 5V Reference 8 50 mV 10 V C2P 7 6 10 CT - + 5 + + 5V C2N On-Time Delay Logic Supply + C1N + OC - + - 4V 200 mV 9 15 14 VSS VREF/CATFLT MAXI UDG-99055 Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 5 PRODUCT PREVIEW VDD UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION FAULT TIMING Figure 1 shows the detailed circuitry for the fault timing function of the UCC3917. For simplicity, first consider a typical fault mode where the overload comparator and the current source I3 do not come into play. A typical fault occurs once the voltage across the current-sense resistor, RS, exceeds 50 mV. This causes the overcurrent comparator to trip and the timing capacitor to charge with current source I1 plus the current from the power limiting amplifier, or PLIM amplifier. The PLIM amplifier is designed to only source current into the CT pin once the voltage across the output FET exceeds 5 V. The current IPL is related to the voltage across the FET as shown in Equation 1. IPL = (VIN - VVOUT ) RPL (1) VIN RPLPLIM 1 + 0.2 V Overload PLIM Ampllifier + - + - + SENSE MAXI 5V I3 50 mA IPL VOUT I3 1 mA SENSE 2 + PRODUCT PREVIEW OUTPUT 50 mV + OC - Fault H = Close H = Close 2.5 V - + Fault Latch RSENSE VOUT I2 1.5 mA 4 0.5 V S Q R Q OUTPUT Drive H = Off - + Reset To Load 10 UGD-00073 CT CCT VOUT Figure 1. Fault Timing Circuitry for the UCC3917, Including Power Limit and Overload NOTE Under normal fault conditions where the output current is slightly above the fault level, VVOUT VIN, IPL = 0, and the CCT charging current is I1. During a fault, CCT charges at a rate determined by the internal charging current and the external timing capacitor, CT. Once CCT charges to 2.5 V, the fault comparator switches and sets the fault latch. Setting the fault latch causes both the output to switch off and the charging switch to open. CT must now discharge with current source I2 until 0.5 V is reached. Once the voltage at CCT reaches 0.5 V, the fault latch resets (assuming LATCH is high, otherwise the fault latch does not reset until the LATCH pin is brought high or a power-on reset occurs). This re-enables the output and allows the fault circuitry to regain control of the charging switch. If a fault is still present, the overcurrent comparator closes the charging switch causing the cycle to repeat. 6 Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com Under a constant fault the duty cycle is shown in Equation 2. I2 1.5 mA = D= IPL - I1 IPL + 50 mA where * IPL is 0 A under normal operations (see Figure 2) (2) However, during large transients average power dissipations can be limited using the PLIM pin. The average dissipation in the pass element is shown in Equation 3. 1.5 mA PFET(avg) = (VIN - VVOUT ) IMAXI D = (VIN - VVOUT ) IMAXI IPL + 50 mA where * both Equation 4 and Equation 5 are true (3) VIN - VOUT >> 5 V (VIN - VVOUT ) RPL (5) PRODUCT PREVIEW IPL = (4) Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 7 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com IOUT IMAXI IFAULT IOUT(nom) VCT 2.5 V Timing capacitor (CCT) voltage (w/r/t VOUT) 0.5 V 0V VOUT PRODUCT PREVIEW VIN VOUT (w/r/t GND) 0V t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 UDG-99147 Figure 2. Typical Timing Diagram Table 1. Timing Stages TIME 8 CONDITION DESCRIPTION t0 Safe condition Output current is nominal, output voltage is at the positive rail, VIN t1 Fault control reached Output current rises above the programmed fault value, CT begins to charge with approximately 50 A t2 Maximum current reached Ooutput current reaches the programmed maximum level and becomes a constant current with value IMAX. t3 Fault occurs CCT has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow, VOUT discharges to ground t4 Retry CT has discharged to 0.5 V, but fault current is still exceeded, CT begins charging again, FET is on, VVOUT rises to VIN. t5 t5 = t3 This Illustrates 3% duty cycle. t6 t6 = t4 t7 Output short circuit if VOUT is short circuited to ground, CT charges at a higher rate depending upon the values for VIN and RPL. t8 Fault occurs Output is still short circuited, but the occurrence of a fault turns the FET off so no current is conducted. t9 Fault remains Output short circuit released, still in fault mode. t10 t10 = t0 Fault released, safe condition - return to normal operation of the circuit breaker. Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com Note that t6 - t5 36 x (t5 - t4). and where IPL >> 50 A, the duty cycle can be approximated in Equation 6. 1.5 mA RPL D= (VIN - VVOUT ) (6) Therefore the average power dissipation in the MOSFET can be approximated by Equation 7. 1.5 mA RPL PFET(avg) = (VIN - VVOUT ) IMAXI =I 1.5 mA RPL (VIN - VVOUT ) MAXI (7) 25 RPL = RPL = 10 M RPL = 5 M RPL = 2 M RPL = 1 M RPL = 500 k RPL = 200 k 22.5 Average Power (W) 20 17.5 15 12.5 10 7.5 5 2.5 0 0 30 60 90 120 150 180 MOSFET Voltage (Output Shorted) (V) 210 G000 Figure 3. OVERLOAD COMPARATOR The overload comparator provides protection against a shorted load during normal operation when the external N-channel FET is fully enhanced. Once the FET is fully enhanced the linear current amplifier essentially saturates and the system is in effect operating open loop. Once the FET is fully enhanced the linear current amplifier requires a finite amount of time to respond to a shorted output possibly destroying the external FET. The overload comparator is provided to quickly shutdown the external MOSFET in the case of a shorted output (if the FET is fully enhanced). During an output short, CT is charged by I3 at 1 mA. The current threshold for the overload comparator is a function of IMAX and a fixed offset and is defined as: 200mV IOVERLOAD = IMAX RS (9) WHen the overcurrent comparator trips, the UCC3917 enters a programmed fault mode (hiccup or latched). It should be noted that on subsequent retries during hiccup mode or if a short should occur when the UCC3917 is actively limiting the current, the output current does not exceed IMAX. In the event that the external FET does not respond during a fault the UCC3917 sets the VREF/CATFLT pin low to indicate a catastrophic failure. Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 9 PRODUCT PREVIEW Notice that since (VIN - VVOUT) cancels, average power dissipation is limited in the N-channel MOSFET pass element (see Figure 3). Also, a value for RPL can be approximated by using Equation 8. PFET(avg) RPL = IMAX 1.5 mA (8) UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com SELECTING THE MINIMUM TIMING CAPACITANCE To ensure that the device starts up correctly the designer must ensure that the fault time programmed by CT exceeds the startup time of the load. The startup time (tSTART) is a function of several components; load resistance and load capacitance, soft-start components R1, R2 and CSS, the power limit current contribution determined by RPL, and CIN. Use Equation 10 to calculate the start time using a parallel capacitor-constant current load. C VIN tSTART = LOAD (IMAX - ILOAD ) (10) Use Equation 11 to calculate calculate the start time using a parallel R-C load. ae o VIN tSTART = RLOAD CLOAD ln c 1 / e IMAX RLOAD o (11) If the power limit function is not be used, then CCT(min) can be found using Equation 12. I t CT(min ) = CH START dVCT where PRODUCT PREVIEW * dVCT is the hysteresis on the fault detection circuitry (12) During operation in the latched fault mode configuration dVCT = 2.5 V. When the UCC3917 is configured for the hiccup or retry mode of fault operation dVCT = 2.0 V. If the power limit function is used, the CCT charging current becomes a function of ICH + IPL. CCT(min) is found by integrating Equation 13 with respect to VCT. ae ae ou o e -t c /u / c e R C VIN - (IMAX RLOAD ) e1 - ee LOAD LOAD o u / c c e u/ c e u / dt CT(min ) = c ICH + / dV RPL CT c / c / c / c / e o (13) The minimum timing capacitance is calculated in Equation 14. 1 CT(min ) = e (ICH RPL ) + VIN - (IMAX RLOAD ) tSTART + VIN RLOAD CLOAD u u RPL dVCT e ( 10 Submit Documentation Feedback ) (14) Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com SELECTING OTHER EXTERNAL COMPONENTS Other external components are necessary for correct operation of the device. Referring to Figure 13, resistors RSENSE, RSS, RDD, R17, R18, and R19 and Equation 15 theough Equation 17 apply: 50mV RSENSE = IFAULT (15) ae (VIN - 5 V ) o RSS = c / c / IDD e o (16) ae (VIN - 10 V ) o RDD = c / c / IDD e o (17) (R17 + R18 + R19) > 20 k (current limit out of VREF) Use a value of 0.1 F for the external charge pump capacitors. The soft-start circuits in Figure 4, and Figure 5 gradually ramp up the load current on power-up, retry, or if the SHTDWN pin is pulled high. Control circuitry (not shown) turns on Q1 to discharge C1 when FLTOUT or SHTDWN are low (i.e., external power MOSFET is off) so the load current always ramps from zero. The circuit in Figure 4 uses an inexpensive bipolar transistor for Q1 so the component cost is lower than the circuit in Figure 5. R3 R2 R2 VREF 15 VREF 15 + C1 MAXI 14 Q1 R1 VOUT + C1 MAXI 14 Q1 R1 4 VOUT 4 UDG-00017 Figure 4. Soft-Start Circuit Using A Higher-Cost Bi-Polar Transistor UDG-11278 Figure 5. Soft-Start Circuit Using A Lower-Cost MOSFET Soft-start operation minimizes the voltage disturbance on the power bus when a circuit card is inserted into a live back plane. This disturbance could reset a system, which is not desirable when high availability is required. A server is an example of a high availability system. Soft-start operation is initiated with the SHTDWN pin in as shown in Figure 6. The anode of D2 is grounded when the card is in the back plane. R2 limits the SHTDWN pin current to between 60 A and 500 A (i.e., 60 A < 0.65 V / R2 < 500 A). Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 11 PRODUCT PREVIEW SOFT-START OPERATION UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com VIN RDD U1 UCC3917 D2 R1 Z 13 VDD PLIM 1 8 C1P OUTPUT 3 7 C1N SENSE 2 6 C2P VREF/CATFLT 15 5 C2N MAXI 14 11 FLOUT CT 10 12 SHTDWN VOUT 4 16 LATCH VSS 9 Q1 Short Pin PRODUCT PREVIEW D1 RGR R2 D2 GND Plug-In Card Back Plane UDG-00019 Figure 6. Soft-Start Operation with SHTDWN I/O INTERFACE The SHTDWN and LATCH inputs and FLTOUT output are referenced to VOUT. Level-shifting circuits are needed if the device communicates with logic that is referenced to load/system ground. INTERFACING TO LATCH AND SHTDWN Two level shift circuits for LATCH and SHTDWN are shown in Figure 7. The optocoupler (Figure 7) is simple, but the constant-current sink (Figure 8) is a low-cost solution. 12 SHTDWN 12 SHTDWN 1 kW 1 kW 16 LATCH IN 16 LATCH IN 4N25 4N25 GND 4 VOUT 4 GND UDG-11202 UDG-11202 Figure 7. Optocoupler Interface 12 Submit Documentation Feedback VOUT Figure 8. Constant-Current Sink Interface Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com Design Example 1: Using the TTL Signal to Control the LATCH Pin Input A TTL signal controls the LATCH input of the UCC3917 using the circuit in Figure 8. Determine the component values if the maximum load voltage is 60 V. The assumptions for this analysis are: * VBE 0.65 V * VCE(sat) 0.1 V * R1||R2 << hfe x R3 * Voltage measurements are with respect to load ground Calculation Steps Step 1. Select Q1. The LATCH input is internally pulled up to the charge pump voltage, which is 10 V above the load voltage. Q1 is therefore subjected to 70 V in a 60 V system. A FMMTA06 transistor, with a VCEO(max) of 80 V, is suitable for Q1 in this application. Step 2. Determine R1, R2 and R3. PRODUCT PREVIEW The interface circuit responds to a TTL input as follows. * Logic "0" input: 0 V < VIL < 0.8 V 0 A < IC < 60 A and VC > 1.7 V * Logic "1" input: 2 V < VIH < 5 V 60 mA < IC < 500 A and VC < 1.7 V This response establishes the relationship between R1, R2, and R3. ae R2 o R1 VB - VIL(max ) c > 0.23 / < VBE 3/43/4(R) R2 e R1 + R2 o If VIN = VIL(max) = 0.8 V, then Q1 is off and If VIN = VIH(max) = 5 V, then: ae 1.7 V - VCE(sat ) o ae R2 o R1 c / < 500 mA 3/43/4(R) R3 > 3.2kW = I C VB - VIL(max ) c V 0.23 < 3/43/4 (R) > / BE c / R3 R R R + e o 2o 2 e 1 VC = VCE(sat ) + VE < 1.7 V 3/43/4(R) VE < 1.6 V V = (V - V ) < 1.6 V 3/43/4(R) V < 2.25 V E (V B - VIH(max ) R2 ) R1 + R2 B BE B R < 2.25 V 3/43/4(R) 1 > 1.222 R2 If VIN = VIH(max) = 2 V, then: VB = IC = (V IH(min ) R2 (R1 + R2 ) (VB - VBE ) R3 )3/43/4(R) 2V aeR o 1+ c 1 / e R2 o > 60 mA 3/43/4(R) R3 < (VB - VBE ) 60 mA In summary, R1, R2, and R3 obey the inequalities: R1 > 1.222 R2 and 3.2kW < R3 < (VB - 0.65 ) 60 mA , where VB = 2V aeR o 1+ c 1 / e R2 o If R1 / R2 = 1.3, then 3.2 k < R3 < 3.66 k. R1 = 4.64 k for the case where R2 = R3 = 3 k. The same design can be used to control the UCC3917's SHTDWN input. Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 13 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com Interfacing to FLTOUT The level shift circuit in Figure 9 is a way to interface to FLTOUT. The operation of this circuit and the SHTDWN / LATCH level shift circuit in Figure 8 are similar. Design Example 2: A TTL-Compatible Output Level Shifter Using FLOUT This design example describes a TTL compatible output level shifter for FLTOUT. The maximum system voltage is 60 V. Use a level shift circuit as shown in Figure 9. The FLTOUT output can swing to the charge pump voltage, which is 10 V above the load voltage. In a 60-V application, the collector-emitter of Q1 can be as high as -70 V. A FMMT593 transistor, with a VCEO(max) rating of -100 V, is a suitable choice for Q1. 13 VDD R3 R2 R1 11 FLTOUT Q1 PRODUCT PREVIEW FLTOUT R4 GND UDG-00022 Figure 9. Interfacing to FLTOUT Calculation Steps Step 1. Output saturation voltage constraint. VC(on ) = VE + VCE(sat ) > 2.4 V (TTL output high ) (18) If VC(on ) = 2.6 V, then VE = 2.6 V + (-0.1V ) = 2.5 V (19) ( ) Step 2. Source current constraint. IC = 100 A Step 3. Calculate the value of R3. R3 = (6 V - VE ) (6 V - VE ) (6 V - 2.5V ) IE = IC = 100 mA = 35kW (20) Step 4. Calculate the base voltage. VB = VE + VBE = (2.5 V - 0.65 V ) = 1.85 V (21) Step 5. Calculate the voltage divider. The voltage divider formula for R1 and R2 is shown in Equation 22 R2 R 6V 6 V @ (6 V - VB ) or 1 = R2 (VB - 1) (R1 + R2 ) (22) Equation 23 assumes negligible loading by Q1. R1 = hfe R3 R2 (23) 14 Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com If hfe = 100, then: o R1 ae R 6 =c / = 2.24 and 1 << (100 35kW ) = 3.5M R2 ce (1.85 - 1) /o R2 (24) If R2 = R3 = 34.8 k, then R1 = 15.4 k Step 6. Calculate the output voltage. The output voltage is set by R4. 2.4 V IC R 4 > 2.4 V, R 4 > = 24 kW 100 mA (25) PRODUCT PREVIEW Choose an R4 value of 49.9 k. Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 15 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com PRELOADING THE OUTPUT RDD provides a sneak path for current between 3 mA and 11 mA (e.g., at 0 V output) to trickle into the load when the power FET is off (see Figure 10). VIR VOUT RDD VDD OUTPUT 10 V + - VOUT LOAD 5V VSS Sneak Path UCC3917 PRODUCT PREVIEW RSS GND GND UDG-00021 Figure 10. Simplified Schematic Illustrating IDD Sneak Path This current causes an unacceptably high output voltage at shutdown if the output is not adequately loaded. In this case, it is necessary to preload the HSPM output to keep the shutdown voltage level acceptable. The preload also insures reliable start-up of the UCC3917 by holding the output voltage low when power is first applied to the HSPM. A resistor is usually an unacceptable preload because it creates a power dissipation problem when the FET turns on. For example, a 90.9- preload (used to limit the shutdown voltage of a 48-V HSPM to less than 1 V) adds 25-W of power dissipation to the system. In a 100-V system, this dissipation increases to 110 W. The power dissipation overhead increases with the system voltage squared for a resistive preload. 16 Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com Figure 11 shows how the active load limits the shutdown voltage without creating a power dissipation problem. 4 TAPER - VOUT Q3 VIN R4 R3 Q1 R2 Q2 R1 Figure 11. Active Preload This load is a constant-current sink (i.e., Q3 is off) when the power FET is off. The shutdown voltage is less than 0.85 V if the sink current, set by R1, is greater than 11 mA. V ISNKFET(off ) = BE > 11A R1 (26) The power dissipation of Q1 is kept to a minimum when the power FET turns on by tapering the sink current as the load voltage rises as shown in Equation 27 . o aeae V o o ae R2 ISNKFET(on ) = c c BE / - VOUT / c / c R / c (R R ) / 3 o ee 1 o o e 1 (27) For R1 << R2 << R3 Control circuitry turns on Q3 to activate current tapering. Tapering the current causes the power dissipation of Q1 to peak when the load voltage is calculated in Equation 28. R V VOUT = BE 3 2 R2 (28) The power dissipated by Q1 at this voltage is shown in Equation 29. 2 R3 aeV o PD(max )Q1 = c BE / (R1 R2 ) e 2 o (29) In the case of a brownout or if the input voltage rises slowly (e.g., adjustable lab power supply), it is possible for Q1 to remain in the maximum power dissipation region for a significant time. Limiting the power dissipation of Q1 below its maximum rating insures reliable operation in this case. Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Submit Documentation Feedback 17 PRODUCT PREVIEW UDG-00024 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com Design Example 3: A 14-mA Active Preload for a 60-V Hot Swap Power Manager (HSPM) Calculation Steps Step 1. Set the sink current. R1 = VBE ISNKFET(off ) = 0.65 V = 46.4 W 14mA (30) Use a BC846B transistor for Q1. This device has a collector breakdown voltage of 65 V and power dissipation rating of 225 mW. Step 2. Select R2 and R3. Select R2 and R3 to limit the power dissipation of Q1 to less than 225 mW, in this example 150 mW is chosen. 2 2 R3 ae 2 o ae 2 o =c / R1 PD(max )Q1 = c / 46.4 W 0.15 W = 65.9 R2 e VBE o e 0.65 V o (31) If R2 = 3.01 k, then R3 = 198 k. The power dissipation of Q1 is shown in Figure 12. PRODUCT PREVIEW 0.6 Constant Current Tapered Current Power Dissipation (W) 0.5 0.4 R1 = 46.4 R2 = 3.01 k R2 =198 k 0.3 0.2 0.1 0 0 5 10 15 20 25 Output Voltage (V) 30 35 40 G000 Figure 12. Output Voltage vs. Power Dissipation PROTECTING THE 5-V REGULAOR The UCC3917's 5-V regulator can overvoltage if VOUT is loaded with less than 11 mA (min) on power up. The overvoltage mechanism is best understood by recognizing that the 5-V Zener diode in the UCC3917 block diagram, is actually a feedback shunt regulator. This regulator turns on when the voltage across the UCC3917's 10-V Zener diode is greater than the UVLO threshold. If VOUT is unloaded and power is applied to the UCC3917, the UVLO threshold cannot be reached and the 5-V regulator impedance is infinite. Consequently, the entire input voltage appears across the shunt regulator causing it to break down. Clamping its voltage with Zener diode to 5.6 V can protect the regulator. NOTE The Zener diode is unnecessary if the current drawn from VOUT is greater than 11 mA when power is initially applied to the UCC3917. EVALUATION CIRCUIT EXAMPLE A 28 V to 60 V at 1-A HSPM evaluation circuit is shown in Figure 13. Level translation circuitry allows communications with logic referenced to load ground. This circuit is available as a DV3917 Evaluation Board. Contact your local Texas Instruments sales representative for more information. 18 Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 - Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 Remote + Latch - 1 2 1 P3 2 1 P2 2 1 P1 D2 1N4148 R8 7.32 kW R6 3.57 kW VDD VIN R9 3.57 kW SENSE R10 3.57 kW S3 S2 9 C13 0.01 mF VSS 4 CT 10 VOUT 3 2 1 TP1 GND R11 5.6 kW 1W C9 0.1 mF R17 49.9 kW R23 200 kW S1 Q1 JRF530S R12 200 kW Q7 MMBT 5039 VIN D5 BZX84C5V6 5.6V R18 49.9 kW R14 3.01 kW R13 200 kW Q5 FMMT 593 R19 2 kW S4 R22 0.05 1W 2% C12 10 mF 10 V R15 47 W Q8 BC346 B PRODUCT PREVIEW C14 0.01 mF 16 LATCH 12 SHTDWN 15 2 MAXI 14 C2P VREF /CATFLT C2N 11 FLTOUT 5 6 7 C1N 3 OUTPUT C1P 8 1 PLIM UCC3917 C11 0.1 mF 13 VDD D1 1N4148 R24 4.7 kW 1W Q4 FMMTA 06 R7 3.57 kW Q3 FMMTA 06 D3 1N4148 C8 0.1 mF C7 0.1 mF *D4 BZX04C4V3ZX 4.3 V R3 15.4 kW R5 7.32 kW R4 49.9 kW R1 34.8 kW R2 34.8 kW C1 4.7 mF 100 V S6 TP2 CS Q5 MMBT 5809 R20 150 kW R16 1 MW Q6 FMMT 593 VDD R21 1 MW C2 S7 5 4 C3 6 3 C4 8 SS 1 C6 UDG-00025 7 2 C5 C2-C6 0.22 mF + C10 4.7 mF 100 V 1 2 J2 + - OUT www.ti.com Remote + Shutdown - Fault + - 2 Q2 FMMT 593 IN + J1 - 3 1 2 + UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 Figure 13. A 28 V to 60 V at 1-A Positive Floating HSPM Evaluation Circuit Using the UCC3917 Submit Documentation Feedback 19 UCC2917 UCC3917 SLUS203C - FEBRUARY 2000 - REVISED FEBRUARY 2011 www.ti.com SAFETY RECOMMENDATIONS Although the UCC3917 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UCC3917 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the power device. The UCC3917 prevents the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot-swap benefits of the device. PRODUCT PREVIEW 20 Submit Documentation Feedback Copyright (c) 2000-2011, Texas Instruments Incorporated Product Folder Link(s): UCC2917 UCC3917 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) UCC2917D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2917DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2917DTR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2917DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2917N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UCC2917NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UCC3917D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3917DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3917DTR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3917DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3917N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UCC3917NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2011 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC2917DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC3917DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2917DTR SOIC D 16 2500 367.0 367.0 38.0 UCC3917DTR SOIC D 16 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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