Preliminary Data
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without noti ce.
November 2009 Rev 5 1/65
1
NAND08GW3F2A
NAND16GW3F2A
8-Gbit, 16-Gbit, 4224-byte page,
3 V supply, multiplane architecture, SLC NAND flash memories
Features
■High density SLC NAND flash memory
– 8, 16 Gbits of memory array
– Cost-effective solutions for mass storage
applications
■NAND interface
– x8 bus width
– Multiplexed address/data
■Supply voltage: VDD = 2.7 to 3.6 V
■Page size: (4096 + 128 spare) bytes
■Block size: (256K + 8K spare) bytes
■Multiplane architecture
– Array split int o two independent planes
– All operations can be performed on both
planes simultaneously
■Page read/program
– Random access: 25 µs (max)
– Sequential access: 25 ns (min)
– Page program operation time: 500 µs (typ)
■Multiplane progr am time (2 pages): 500 µs
(typ)
■Copy-back program
– Automatic block download without lat ency
time
■Fast block erase
– Block erase time: 1.5 ms (typ)
– Multiplan e blo ck era se tim e (2 blocks):
1.5 ms (typ)
■Status register
■Electronic signature
■Chip enable ‘don’t care’
■Data protection
– Hardware program/erase locked during
power transitions
■Security features
– OTP area
– Serial number (unique ID)
■Development tools
– Error correction code models
– Bad block man agement and wear leveling
algorithm
– HW simulation models
■Data integrity
– 100,000 program/erase cycles (with ECC)
– 10 years data r etention
■RoHS compliant packages
TSOP48 12 x 20 mm (N)
www.numonyx.com
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Single plane operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1.1 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1.2 Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.4 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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6.1.5 Copy-back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Multiplane operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.1 Multiplane page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.2 Multiplane cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3 Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.4 Multiplane erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.5 Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3 2-Kbyte page backward compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.1 Page program with 2-Kbyte page compatibility . . . . . . . . . . . . . . . . . . . 37
6.3.2 Copy back program with 2-Kbyte page compatibility . . . . . . . . . . . . . . . 37
6.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.5.2 P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.5.3 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.6 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8 Write pr otect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.5 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5.2 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 49
11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 60
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13 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
14 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. Device identifier codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 13. Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 14. Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15. Program and erase times and program erase endurance cycles. . . . . . . . . . . . . . . . . . . . 49
Table 16. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 17. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 18. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20. AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 21. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 22. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 62
Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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List of figures
Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Memory array organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Copy back program operation (without readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Copy back program operation (with readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Copy back program operation with random data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Multiplane page read operation with sequential and random data output . . . . . . . . . . . . . 27
Figure 14. Multiplane page read operation with cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Multiplane page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Multiplane erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Multiplane copy back program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Multiplane copy back program operation with random data input. . . . . . . . . . . . . . . . . . . . 33
Figure 19. Multiplane copy back operation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Multiplane copy back operation flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21. New multiplane copy back operation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. New multiplane copy back operation flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. Page program with 2-Kbyte page compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 24. Copy back program with 2-Kbyte page compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25. Copy back program with 2-Kbyte page compatibility and random data input. . . . . . . . . . . 38
Figure 26. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. Program enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 28. Program disable waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29. Erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 30. Erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 31. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 32. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 33. Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 34. Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 35. Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5
Figure 36. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 37. Read status register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 38. Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 39. Page read operation AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 40. Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 41. Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 42. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 43. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 44. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 45. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 61
Figure 46. TSOP48 - 48 lead plastic thin sm all ou tlin e, 12 x 20 mm, pa ck ag e ou tlin e . . . . . . . . . . . . 62
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1 Description
The NANDxxGW3F2A device belongs to the 4224-byte page family of non-volatile NAND
flash memories. The NANDxxGW3F 2A ha s a density of 8 or 16 Gbits (2 x 8 Gbits ) . Th e
de vice operates from a 3 V power supply.
The address lines are multiplexed with the data input/output signals on a multiplexed x8
input/outp ut bus. This interface reduces the pin count and makes it possible to migrate to
other densitie s with ou t c han gin g th e footprint.
Each b lock can be pr ogrammed an d erased up to 100,0 00 cycles (with error correction code
(ECC) on). A write protect pin is available to provide hardware protection against program
and erase operations.
The devices feature an open-drain, ready/busy output that identifies if the program/erase/
read (P/E/R) controller is currently active. The use of an open-drain output allows the
ready/busy pins of seve ral memories to be connected to a single pull-up resistor.
For each die, the memory array is split into 2 planes of 2048 blocks each. This multiplane
architecture makes it possible to program 2 pages at a time (one in each plane), to erase 2
blocks at a time (one in each plane), or to read 2 pages at a time (one in each plane)
dividing by two the average program, erase, and read times.
The device has the Chip Enable ’don’t care’ feature , which allows the bus to be shared
between more than one memory at the same time, as Chip Enable transition during the
latency time do not stop the read opera tion. Program and erase operations can never be
interrupted by Chip Enable transition.
The device comes with two security features:
●OTP (one time programmable) area, which is a restricted access area where sensitive
data/code can be stored permanently. The access sequence and further details about
this feature are subject to an NDA (non disclosure agreement)
●Serial number (unique identifier), which allows the NANDxxGW3F2A to be uniquely
identified. It is subject to an NDA (non-disclosure agreement) and is, therefore, not
described in the datasheet.
For more details about these security features, contact your nearest Numonyx sales office.
The device is av ailable in TSOP48 (12 × 20 mm) package. an d is shipped from the factory
with block 0 always valid and the memory content bits, in valid blocks, erased to ‘1’.
Refer to the list of available part numbers and to Tabl e 23: Ordering inf ormation scheme for
information on how to order these options.
Description NAND08GW3F2A, NAND16GW3F2A
8/65
Figure 1. Logic block diagram
Tabl e 1. Device summary
Part
number Density Bus
width Page
size Block
size Memory
array
Operating
voltage
(VDD)
Timings
Package
Random
access
time
(max)
Sequential
access
time (min)
Page
program
(typ)
Block
erase
(typ)
NAND0
8GW3F
2A 8 Gbits
x8 4096+
128
bytes
256K
+ 8K
bytes
64 pages
x 4096
blocks 2.7 to
3.6 V 25 µs 25 ns 500 µs 1.5
ms TSOP48
NAND1
6GW3F
2A
16
Gbits
64 pages
x 8192
blocks
Address
register/counter
Command
interface
logic
P/E/R controller
high voltage
generator
Buffers
E
W
AI13296c
RY decoder
Page buffer
NAND flash
memory array
X Decoder
Command register
CL
AL
RB
Data register
I/O
WP
NAND08GW3F2A, NAND16GW3F2A Description
9/65
Figure 2. Logic diagram
Table 2. Signal names
Signal Function Direction
I/O0 - I/O7 Data input/outputs Input/output
CL Command Latch Enable Input
AL Address Latch Enabl e Input
EChip Enable Input
RRead Enable Input
WWrite Enable Input
WP Write Protect Input
RB Ready/Busy (open drain output) Output
VDD Power supply Power supply
VSS Ground Ground
NC No connection –
DU Do not use –
AI13632c
I/O0 - I/O7 x8
VDD
NAND flash
W
VSS
WP
AL
CL
E
R
RB
Description NAND08GW3F2A, NAND16GW3F2A
10/65
Figure 3. TSOP48 connections
I/O3
I/O2
I/O6
R
RB
NC
I/O4
I/O7
AI13633
NAND flash
12
1
13
24 25
36
37
48
E
I/O1
NC
NC
NC
NC
NC
NC
NC
WP
W
NC
NC
NC
VSS
VDD
AL
NC
NC
CL
NC
I/O5
NC
NC
NC
I/O0
NC
NC
NC
NC
VDD
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NAND08GW3F2A, NAND16GW3F2A Memory array organization
11/65
2 Memory array organization
The memory arra y is comp rised of NAND structures where 3 2 cells are con ne cted in series.
It is organized into blocks where ea ch block contains 64 pages. The array is split into two
areas, the main area and the spare area. The main area of the array stores data, whereas
the spare area typic ally stor es so ftware flags or bad block identification.
The pages are split into a 4096-byte main area and a spare area of 128 bytes. Refer to
Figure 4: Memory array organization.
2.1 Bad blocks
The NANDxxGW3F2A devices may contain bad blocks, where the reliability of blocks that
contain one or more in v alid bits is not guar anteed. Additional bad b loc ks may de v elop during
the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 9.1: Bad block
management for more details).
Table 3: Valid blocks shows the mini mu m number of valid bl o cks . Th e values shown include
both the bad blocks that are present when the device is shipped and the bad blocks that
could develop later on.
These blocks need to be managed using bad b locks manage ment and block replacement
(refer to Section 9: Software algorithms).
Table 3. Valid blocks
Density of device Minimum Maximum
8 Gbits 4016 4096
16 Gbits 8032 8192
Memory array organization NAND08GW3F2A, NAND16GW3F2A
12/65
Figure 4. Memory array organization
NI3061
x8 bus width
Plane = 2048 blocks
Block = 64 pages
Page = 4224 bytes (4096+128)
4096 bytes
4096 bytes 128
bytes
Block
128
bytes
page
Page buffer, 4224 bytes
Main area
4096 bytes
4096 bytes
Spare area
128
bytes
8 bits
128
bytes 8 bits
Page buffer, 4224 bytes
Main area
Spare area
2 page buffer, 2x 4224 bytes
First plane Second plane
NAND08GW3F2A, NAND16GW3F2A Signal descriptions
13/65
3 Signal descriptions
See Figure 1: Logic block diagram, and Table 2: Signal names for a brief overview of the
signals connected to this device.
3.1 Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address , output the data during a read
operation, or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2 Address Latc h Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.3 Command Latch Enab le (CL)
The Command Latch Enable acti vates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enab le.
3.4 Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enab le is Lo w, VIL, the device is selected. If Chip Enab le goes
High, VIH, while the device is busy, the device remains selected and does not go into
standby mode.
3.5 Read Enable (R)
The Read Enable pin, R, controls the sequential dat a outpu t during read oper atio ns . Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
3.6 Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address, and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. It is recommend ed to k eep Write Enab le
High during the recovery time.
Signal descriptions NAND08GW3F2A, NAND16GW3F2A
14/65
3.7 Write Protect (WP)
The Write Protect pin is an inpu t that giv es a hardware protecti on against unwanted program
or erase operations. When Write Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to k e ep the Write Prot ect pin L ow, VIL, du ring pow er-up and po w er-do wn.
3.8 Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can identify if the P/E/R controller
is currently active.
When Ready/Busy is Low, VOL, a read , progr am or erase oper ation is in prog ress. Wh en the
operation completes, Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single p ull-up resist or. A Low indicat es t hat one, or more, of the m emories is
busy.
During power-up and power-down a minimum recovery time of 10 µs is required before the
command interf ace is ready to accept a command. During this period the Ready/Busy signal
is Low, VOL.
Refer to Section 12.1: Ready/Busy signal electrical characteristics for details on ho w to
calculate the value of the pull-up resis tor.
3.9 VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operat ions (read, program and erase).
An internal voltage detector disables all functions wh en ever VDD is below VLKO (see
Table 19: DC characteristics) to pr otect the device from any involuntary program/erase
duri n g power transitions.
Each device in a system should ha ve VDD decoupled with a 0.1 µF capacitor . The PCB tr ack
widths should be sufficient to carry the required prog ram and erase currents.
3.10 VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
NAND08GW3F2A, NAND16GW3F2A Bus operations
15/65
4 Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section. See the summary in Table 4: Bus operations.
Typically, glitches of less than 3 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1 Command input
Command input bus operations give commands to the memory. Commands are accepted
when Chip Enable is Lo w, Command Latch Enable is High, Address Latch Enable is Low
and Read Enable is High. They are latched on the rising edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 33 and Table 20 for details of the timings requirements.
4.2 Address input
Address input bus operations input the memory addresses. Five bus cycles are required to
input the addresses (refer to Table 5: Address insertion).
The addresses a re accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are us ed to inp ut addre sse s.
See Figure 34 and Table 20 for details of the timings requirements.
4.3 Data input
Data input bus operations input the data to be programmed. Data is only accepte d when
Chip Enab le is Low , Addre ss Latch Enable is Lo w , Command Latch Enab le is Low and Read
Enab le is High. The data is latched on the rising edge of the Write Enab le signal. The data is
input sequent ially using the Write Enable signal.
See Figure 35 and Table 20 for details of the timing requirements.
4.4 Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the unique identifi er.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low ,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
If the Read Enable pulse frequency is lower then 33 MHz (tRLRL higher than 30 ns), the
output data is latched on the rising edge of Read Enable signal (see Figure 36: Sequentia l
data output after read AC wavefo rms).
Bus operations NAND08GW3F2A, NAND16GW3F2A
16/65
F or higher fr equencies (tRLRL lowe r than 30 ns), the e xtended d ata out (EDO) mode must be
considered. In thi s mode, da ta output is v alid on the input/output b us f or a time of tRLQX after
the f alling edge of Read Enab le signal (see Fi gur e 36: Sequential data ou tp ut af ter re ad AC
waveforms).
See Table 21: AC characteristics for operations, for detai ls on the timings requirement s.
4.5 Write protect
Write protect bus ope rations protect the memory against prog ram or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operat ions, theref ore , the contents of the mem ory arra y cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection, even during power-up.
4.6 Standby
The memory enters standby mode by holding Chip Enable, E, High for at least 10 µs. In
standby mode, the de vice is deselected, outputs are disabled and power consumption is
reduced.
Table 4. Bus operations
Bus opera t io n E AL CL R WWP I/O0 - I/O7
Command input VIL VIL VIH VIH Rising X(1)
1. WP must be VIH when issuing a program or erase command.
Command
Address input VIL VIH VIL VIH Rising X Address
Data input VIL VIL VIL VIH Rising VIH Data input
Data output VIL VIL VIL Falling VIH X Data outpu t
Write protect X X X X X VIL X
Standby VIH XXXXV
IL/VDD X
Table 5. Address insertion(1)
1. Any additional address input cycles are ignored.
Bus cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st A7 A6 A5 A4 A3 A2 A1 A0
2nd VIL VIL VIL A12 A11 A10 A9 A8
3rd A20 A19 A18 A17 A16 A15 A14 A13
4th A28 A27 A26 A25 A24 A23 A22 A21
5th VIL VIL VIL VIL VIL A31(2)
2. A31 is required only for 16-Gbit devices.
A30 A29
NAND08GW3F2A, NAND16GW3F2A Bus operations
17/65
Table 6. Address definitions
Address Definition
A0 - A12 Column address
A13 - A18 Page address
A19 - A31 Block address
Command set NAND08GW3F2A, NAND16GW3F2A
18/65
5 Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on th e rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are se lected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in Table 7: Command set.
Table 7. Command set
Function 1st cycle 2nd cycle 3rd cycle 4th cycle Acceptable during
comman d busy
Page Read 00h 30h
Read for Copy Back 00h 35h
Read ID 90h
Reset FFh Yes
Page Program 80h 10h
Multiplane Page Program 80h 11h 81h 10h
Multiplane Read 60h 60h 30h
Copy Back Program 85h 10h
Multiplane Copy Back
Program 85h 11h 81h 10h
Multiplane Copy Back
Read 60h 60h 35h
Block Erase 60h D0h
Multiplane Block Erase 60h 60h D0h
Read Status Register 70h Yes
Random Data Input 85h
Random Data Output 05h E0h
Multiplane Random Data
Output 00h 05h E0h
Cache Read 31h
End Cache Read 3Fh
Page Program with
2-Kbyte compatibility 80h 11h 80h 10h
Copy Bac k Program with
2-Kbyte compatibility 85h 11h 85h 10h
NAND08GW3F2A, NAND16GW3F2A Device operations
19/65
6 Device operations
6.1 Single plane operations
This section gives the details of the single plane device operations.
6.1.1 Page read
At power-up the device defaults to read mode. To enter read mode from another mode the
Read command must be issu ed, see Table 7: Command set. Once a Read command is
issued, subsequent consecutive read commands only require the confirm command code
(30h).
After a first pag e read operation, the de vice sta ys in read mode and a second page r ead can
be started b y inputting 5 address cycles and a read confirm command.
Once a read command is issued, two types of operations are available: random read and
sequential page read. The random read mode is enabled when the page address is
changed.
After the first random read access, the page data (4224 bytes) is transferred to the page
buf f er in a time of tWHBH (r efer to Table 21: AC char acteristics f or operati ons for value). Once
the transfer is comple te, the Ready/Busy signal goes High. The data can then be read out
sequentially (from the selected column add ress to last column addr ess) by p ulsing the Read
Enable signal (see Figure 39: Page read operation AC waveforms).
The de vice can output random dat a in a page, instead of the co nsecutive sequentia l data, by
issuing a Random Data Outpu t command. The Random Data Outpu t command can be used
to skip some data during a sequential data output.
The sequential ope r at ion ca n be resum ed by chang ing the co lumn add ress of th e next data
to be output, t o the address which f ollows th e Random Data Output command. The Ran dom
Data Output comma nd can be issued as many times as required within a page.
Device operations NAND08GW3F2A, NAND16GW3F2A
20/65
Figure 5. Random data output
6.1.2 Cache read
The cache read operation improves the read throughput by reading data using the cache
register. As soon as the user starts to read one page, the device automatically loads the
next page into the cache register.
A Read P age command is issued prior to the first Cache Read command in a cache read
sequence. Once the Read Page command execution is terminated, the Cach e Read
command can be issued as follows:
1. Issue a Seque nt ial Cache Read com man d to copy the next pa ge in sequ ent ial ord er to
the cache register
2. Issue a Random Cache Read command to copy the page addressed in this command
to the cache register.
The two commands can be used interchangeably, in any order. When there are no more
pages to be read, the final page is copied into the cache register by issuing the Exit Cache
Read command. A Cache Read command must not be issued after the last page of the
de vice is read. Dat a output only starts after issuing the 31st com mand for the first time. See
Figure 6: Cache read (sequential) operation and Figure 6.1.3: Page program for examples
of the two sequences.
I/O
RB
Address
inputs
ai08658b
Data output
Busy
tBLBH1
(Read Busy time)
00h
Cmd
code
30h
Address
inputs Data output
05h E0h
5 Add cycles
Main area Spare
area
Col Add 1,2
Row Add 1,2,3
Cmd
code
Cmd
code
Cmd
code
2 Add cycles
Main area Spare
area
Col Add 1,2
R
NAND08GW3F2A, NAND16GW3F2A Device operations
21/65
After the Sequential Cache Read or Random Cache Read command has been issued, the
Ready/Busy signal goes Low and the statu s regi st er bits are se t to SR5=’0’ a nd SR6=’0’ for
a period of cache read busy time, tRCBSY, while the device copies the ne xt page into the
cache register.
After the ca che read busy time has passed, the Read y/Busy signal goes High and the status
register bits are set to SR5=’0’ and SR6=’1’, signifying that the cache register is ready to
download new data. dat a o f the pr eviously r ead page ca n be ou tput fr om the p age buffer by
toggling the Read En ab le sign al. Data out put alw ays begins at column address 00h, b ut the
Random Data Output command is also supported.
Figure 6. Cache read (sequential) operation
6.1.3 Page program
The page prog ram o peration is t he standard op eration to p rogram data to the memo ry arra y.
Generally, data is prog rammed sequentially, however, the de vice does support random input
within a page.
The memory array is programmed by page, however, partial page progra mming is allowed
where any number of bytes (1 to 4224) can be programmed.
The maximum n um ber of consecutive partial page progr am oper a tions on the same pag e i s
8 (see Table 15: Program and erase times and program erase endurance cycles). After
exceeding this a Block Erase command must be issued before any further program
operations can take place in that page (see Figure 7: Page program operation).
Within a given block, the pages must be programmed sequentially and random page
address programming is not allowed.
I/O0-7
RB
Address
inputs
ai13176b
00h
Read
Setup
code
30h Busy
tBLBH1
(Read Busy time)
Exit
Cache
Read
code
tRCBSY
R
31h Data outputs
(Read Cache Busy time)
tRCBSY
(Read Cache Busy time)
3Fh Data outputs
Read
code Cache
Read
Sequential
code
Repeat as many times as necessary
Device operations NAND08GW3F2A, NAND16GW3F2A
22/65
Figure 7. Page program operation
Once the prog ram oper ation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to ‘1’ that have not been successfully programmed to ‘0’.
During the program operation, only the Read Status Register and Reset commands are
accepted; all oth er commands ar e ignored. Once the progr am o perat ion has complet ed, the
P/E/R controller bit SR6 is set to ‘1’ and the Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Sequential input
To input data sequentially the addresses must be sequential and remain in one block.
For sequential input, each page program operation comprises five steps:
1. One b us cycle is required to set up the P age Program (sequen tial input) command (se e
Table 7: Command set)
2. Five bus cycles are then required to input the program address (refer to Table 5:
Address insertion)
3. The data is loaded into the data registers
4. One bus cycle is required to issue the Page Pro gram Confirm command to start the
P/E/R controller. The P/E/R controller only starts if the data has been loaded in step 3
5. The P/E/R contr oller then prog rams the data into the array.
Random data input
During a sequential input operation, the next sequential address to be programmed can be
replaced by a random address issuing a Random Data Input command. The following two
steps are required to issue the command:
1. One bus cycle is required to setup the Random Data Input command (see Table 7).
2. Two bus cycles are then requir ed to input the new column address (refer to Table 5).
Random data input operations can be repeated as often as required in any given page.
I/O
RB
Address inputs SR0
ai08659
Data input 10h 70h
80h
Page program
setup code Confirm
code Read status register
Busy
tBLBH2
(Program Busy time)
NAND08GW3F2A, NAND16GW3F2A Device operations
23/65
Figure 8. Random data input during sequential data input
6.1.4 Block erase
Erase operations are done one block at a time. An erase operation sets all the bits in the
addressed block to ‘1’. All prev ious data in the block is lost.
An erase operation consists of three steps (refer to Figure 9: Block erase operation):
1. One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A30 are valid while the ad dresses A13 to A18 are igno red
2. Three bus cycles are th en required to load the address of the b lo c k to be erase d. Refer
to Table 6: Address definitions for the block addresses of each device
3. One bus cycl e is required to issue the Block Era se Confirm command to start the P/E/R
controller.
The erase operation is initiated on the rising edge of Write Enable, W, after the Confirm
command is issued. The P/E/R controller handles block erase and implements th e verify
process.
During the block erase operation, only the Read Status Regi ster and Reset commands are
accepted; all other commands are ignored.
Once the progr am opera tion has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completes successfully, th e write status bit
SR0 is ‘0’, otherwise it is set to ‘1’ (refer to Section 6.5: Read status register).
I/O Address
inputs
ai08664
Data input
80h
Cmd
code
Address
inputs Data input
85h
5 Add cycles
Main area Spare
area
Col Add 1,2Row Add 1,2,3
Cmd
code
2 Add cycles
Main area Spare
area
Col Add 1,2
RB
Busy
tBLBH2
(Program Busy time)
SR0
10h 70h
Confirm
code Read status register
Device operations NAND08GW3F2A, NAND16GW3F2A
24/65
Figure 9. Block erase operation
6.1.5 Copy-back program
The copy-back program with read for copy-back operation is configured to quickly and
efficiently rewrite data stored in one page without data reloading when the bit error is not in
data stored.
Since the time-consuming re-loading cycles are rem oved, the system performance is
improv ed. The benefit is especially obvious when a portion of a b lock is updated an d the rest
of the block also needs to be copied to the newly-assigned free block. The copy-back
operation is a sequential execution of read for copy-back and copy back program with the
destination page address. A read operation with a 35h command in the address of the
source page moves the entire 4224 bytes into the internal data buffer. When the device
returns to the read y sta te (RB High), optional readout of data is allowed by pulsing R to
check ECC (see Figure 11: Copy back program operation (with readout of data)). The next
bus write cycle of the command is given to input the target page address.
The actual prog ramming operation begins after the Program Confirm command (10h) is
issued. Once the program process starts, the Read Status Register command (70h) may be
entered to read the status register. The system controller can detect the completion of a
program cycle by monit oring the RB output, or th e sta tu s bit (I/O6) of the status regist er.
When the copy back program is complete, the write status bit (I/O0) can be checked. The
command register remains in read status command mode until another valid command is
written to the command register. During the copy back program, data modification is
possible using Random Data Input command (85h) as shown in Figure 12: Copy back
program operatio n with random data input.
The copy back program operation is only allowed within the same memory plane (A19 and
A31 fixed for sour ce and target address).
I/O
RB
Block Address
Inputs SR0
ai07593
D0h 70h
60h
Block Erase
Setup Code Confirm
Code Read Status Register
Busy
tBLBH3
(Erase Busy time)
NAND08GW3F2A, NAND16GW3F2A Device operations
25/65
Figure 10. Copy back program operation (without readout of data)
Figure 11. Copy back program operation (with readout of data)
Figure 12. Copy back program operation with random data input
I/O
RB
Source
Add inputs
ai09858b
85h
Copy back
code
Read
code Read status register
Target
Add inputs
tBLBH1
(Read Busy time)
Busy
tBLBH2
(Program Busy time)
00h 10h 70h SR0
Busy
35h
I/O
RB
Source
Add Inputs
ai09858c
85h
Copy Back
Code
Read
Code
Read Status
Register
Target
Add Inputs
tBLBH1
(Read Busy time)
Busy
tBLBH2
(Program Busy time)
00h 10h 70h SR0
Busy
35h Data Outputs
I/O
RB
Source
Add inputs
ai11001
85h
Read
code
Target
Add inputs
tBLBH1
(Read Busy time)
00h
Busy
35h 85h Data
2 cycle
Add inputs
Data
Copy back
code
10h 70h
Unlimited number of repetitions
Busy
tBLBH2
(Program Busy time)
SR0
Device operations NAND08GW3F2A, NAND16GW3F2A
26/65
6.2 Multiplane operations
6.2.1 Multiplane page read
The multipla ne page read operation is an extension of a page read operation for a single
plane . Since the device is equipped with two memory planes, a read of two pages (one for
each plane) is enabled by activating two sets of 4224-byte page registers (one for each
plane). The m ultiplane page read operatio n is initiated b y repeating twice the command 60h,
f ollow ed by 3-address cycles , and then b y one 30h Read Confirm command (only 3-address
cycles are needed because the multiplane page read operation addresses the whole pa ge
starting form the first byte). In this case only the same page of the same block can be
selected from each plane.
After the Read Confirm command (30h) the 8448 bytes of dat a within the selected two
pages are transferred into the data registers in less than 25 µs (tWHBH). The system
controller can detect the completion of data transfer (tWHBH) by monitoring the output of the
RB pin.
Once the data is loaded into the data registers, the data of first plane must be read by
issuing the command 00 h with 5 address cycles (all 00h), the command 05h with a 2-
column address, the command E0h, and then b y toggling Read Enable, R. If the 2-column
address is 00h, then the read output starts from the beginning of the page, otherwise the
data output starts from selected column for random data output (see Figure 13: Multiplane
page read operation with sequential and rand om data output).
The data of the second pla ne must be read using the following command sequence:
command 00h with 5 add ress cycles (all 00h e xcept A19 = 1 and A31= fix ed) , command 05h
with a 2-column address , E0h, and then toggling Re ad Enable , R. If the 2-column address is
00h, then the read output starts from the beginning of the page, otherwise the data output
starts from selected column for random data output.
To execute multiple random data outputs with in the same 2 selected pages, the command
sequence is: comma nd 00h with 5 add ress cycle s, command 05h with a 2- co lumn ad dr ess,
and finally E0h. I n 5 address cycles A1 9=0 allo ws r andom read in the first plane page , while
A19=1 allows random read in the second plane page (Figure 13: Multiplane page read
operation with sequential and random data outp ut).
Restrict ion s an d de ta ils ab ou t th e multipla ne page rea d op e ration are shown in Figure 13:
Multiplane page r ead operation with sequential and ra ndom data output. The multiplane
page read operation must be used in the block that has been programmed with multiplane
page program.
NAND08GW3F2A, NAND16GW3F2A Device operations
27/65
Figure 13. Multiplane page read operat ion with sequential and random data output
RB ai14435b
I/O Add. 5
cycles 05h
Read
code
Read
code
00h E0h Dou;
MDou
M+1
Col. Add. 1, 2
Row Add. 1, 2, 3
E0h 00h
Col. Add. 1, 2 Col. Add. 1, 2
Row Add. 1, 2, 3 Col. Add. 1, 2
A0-A12 = fixed 'Low'
Add. 2
cycles Add. 5
cycles
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
A20-A30 = fixed 'Low'
A0-A12 = Valid
D
ND
N+1 05h Add. 2
cycles
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'High'
A20-A30 = fixed 'Low'
A0-A12 = Valid
R
tRLRL
AL tRLQV
tWHRL
W
tWLWL
E
CL
tCLLRL
RB
I/O Add. 3
cycles 60h
60h
Row Add. 1, 2, 3
30h
Add. 3
cycles
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
A20-A30 = fixed 'Low'
R
AL
tWHBL
W
E
CL
Row Add. 1, 2, 3
A13-A18 = fixed 'Low'
A19 = fixed 'High'
A20-A30 = Valid
Busy
tWHBH
A31 = fixed A31 = fixed
A31 = fixed A31 = fixed
Device operations NAND08GW3F2A, NAND16GW3F2A
28/65
6.2.2 Multiplane cache read
NANDxxGW3F2A devices have a multiplane page read with cache oper ation, which
enables much higher speed read operation compared to page read operation. The
restrictions for this operation are shown in Figure 14: Multiplane page read operation with
cache read.
Figure 14. Multiplane page read operation with cache read
I/O
RB
ai14298b
60h Busy
tWHBH
60h Address
input
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
A20-A30 = fixed 'Low'
30h
Address
input
A13-A18 = Valid
A19 = fixed 'High'
A20-A30 = Valid
I/O
RB
05h
00h Address
input
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
E0h
Address
input
A0-A12 = Valid
Data
output
A20-A30 = fixed 'Low'
I/O
RB
05h
00h Address
input
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'High'
E0h
Address
input
A0-A12 = Valid
Data
output
A20-A30 = fixed 'Low'
I/O
RB
05h
00h Address
input
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'High'
E0h
Address
input
A20-A30 = fixed 'Low'
tBLBH5
A0-A12 = Valid
31h
1
Return to 1
Repeat 63 times maximum
3Fh Data
output
I/O
RB
05h
00h Address
input
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'High'
E0h
Address
input
A0-A12 = Valid
Data
output
A20-A30 = fixed 'Low'
tBLBH1
A31 = fixed A31 = fixed
A31 = fixed
A31 = fixed
A31 = fixed
A31 = fixed
NAND08GW3F2A, NAND16GW3F2A Device operations
29/65
6.2.3 Multiplane page program
The de vice s support multiplan e page prog ram, t hat allo ws the prog r amming of two pages in
parallel, one in each plane.
A multiplane page program operation requires two steps:
1. The first step loads serially up to two pages of data (8448 bytes) into the data buffer. It
requires:
– One cloc k cycle to set up the Page Program command (see Section : Sequential
input)
– Five bus write cycles to input the first page address and data. The address of the
first page must be within the first plane (A19 = 0)
– One bus write cycle to issue the page program confirm code. After this the device
is busy for a time of tBLBH5
– When the device returns to the ready state (ready/busy high), a multiplane page
progr am setup code mu st be issued, f ollow ed by th e second page address (5 write
cycles) and data. The address of the second pag e must be within the second
plane (A19=1), and A18 to A13 must be the address bits loaded during the first
address insertion
2. The second step prog rams , in parallel, the two pages of d ata loaded into the data buff er
into the appropriate memory pages. It is started by issuing a Program Confirm
command.
As for standard page program operations, the device supports random data input during
both data loading phases.
Once the mult iplane pa ge pr og ra m oper at ion ha s st arted, maintaining a delay of tBLBH5, the
status register can be read using the Read Status Register command.
If the first or second page program fails, the fail bit of the status register is set: the device
supports a pass/fail status of each plane (I/O0: total; I/O1: plane0; I/O2: plane1).
Device operations NAND08GW3F2A, NAND16GW3F2A
30/65
Figure 15. Multiplane page program operation
1. No command between 11h and 81h is permitted except 70h and FFh.
6.2.4 Multiplane erase
The multiplane erase opera tion allows the erasure of two blocks in parallel, one in each
plane (refer to Figure 16: Multiplane erase operation for details of the sequ en ce ).
The Bloc k Erase Setup command (60 h) must be issued tw o times, each time f ollo wed b y the
1st and 2nd block address cycles, respectively (3 cycles for each time). As for block erase
operation, the Erase Confirm command (D0h) makes this operation start. No dummy busy
time is required between the first and second block address cycles insertion.
Address limitation required for a multiplane program applies also to multiplane erase. The
operat ion progress can also be checked as for multiplane program operation.
If the first or second block erase fails, the fail bit of the st atus register is set: the device
supports a pass/fail status of each plane (I/O0: total; I/O1: plane0; I/O2: plane1).
I/O
RB
Address inputs
NI3062
Data input 11h 81h
80h
Page program
setup code Confirm
code Multiplane page
program setup
code
Busy
tBLBH5
A0-A12 = Valid
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
A20-A30 = fixed 'Low'
A31 = fixed
Address inputs SR0
Data input 10h 70h
Confirm
code Read Status Register
A0-A12 = Valid
A13-A18 = Valid
A19 = fixed 'High'
A20-A30 = Valid
A31 = fixed
Busy
tBLBH2
(Program Busy time)
.
.
Block 4094
Block 4092
Block 0
Block 2
Plane 0
(2048 blocks)
80h 11h
Data
input
.
.
Block 4095
Block 4093
Block 1
Block 3
Plane 1
(2048 blocks)
81h 10h
NAND08GW3F2A, NAND16GW3F2A Device operations
31/65
Figure 16. Multiplane erase operation
6.2.5 Multiplane copy back program
The two-plane copy back program operation is an extension of the copy back program
operat ion for a single plane with 4224-byte page registers. As f or the single plane cop y bac k,
a multiplane read operation with ‘35h’ command (multiplane read for cop y back) and the
address of th e source pages mo ves the whole 4224-b yte of each page into the int ernal data
buffer of each plane. Since the device is equipped with two memory planes, activating the
two sets of 4224-byte page registers enables a simultaneo us programming of two pages.
Figure 17: Multiplane copy bac k program operation and Figure 18: Multiplane copy back
program operatio n with random data input show the details of the command sequence for
the multiplane copy back operation in standard operation mode. Figure 19 to 22 show the
new multiplane copy back program flows introduced to reduce the buffer size (8 Kbytes)
required b y the host to p erfo rm the multiplane cop y back pr ogram op eration. The sequen ces
of data out followed by data input for each plane can be performed an indefinite n umber of
times, depending on the buffer size used by the host. Figure 19 shows the sequence when
the host is equipped with a 4-Kbyte buffer size, while Figure 22 shows the sequence when
the host is equipped with a 2-Kbyte b uff er siz e. The multiplane cop y bac k prog ram operat ion
is allowed in the same die in stacked devices (A31 is fixed between source and target
addresses).
RB
I/O
ai14275
D0h 70h
60h
Block Erase
Setup command 1 Erase Confirm
command Read Status
Register command
Busy
tBLBH3
(Erase Busy time)
60h
Row addresses 1, 2, 3
Block Erase
Setup command 2
Row addresses 1, 2, 3
I/O1=0 successful erase in plane 0
I/O1=1 error in plane 0
I/O2=0 successful erase in plane 1
I/O2=1 error in plane 1
I/Ox
R
AL
W
tWLWL tWHBL tWHRL
E
CL
Device operations NAND08GW3F2A, NAND16GW3F2A
32/65
Figure 17. Multiplane copy back program operation
I/O
RB
ai14298c
60h Busy
tWHBH
60h Address
(3 cycles)
Row add: 1,2,3
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
A20-A30 = fixed 'Low'
35h
Address
(3 cycles)
Row add: 1,2,3
A13-A18 = Valid
A19 = fixed 'High'
A20-A30 = Valid
I/O
RB
05h
00h Address
(5 cycles)
Col add: 1,2 & Row add: 1,2,3
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
E0h
Address
(2 cycles)
Col add: 1,2
A0-A12: Valid
Data
output
A20-A30 = fixed 'Low'
I/O
RB
05h
00h Address
(5 cycles)
Col add: 1,2 & Row add: 1,2,3
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'High'
E0h
Address
(2 cycles)
Col add: 1,2
A0-A12: Valid
Data
output
A20-A30 = fixed 'Low'
I/O
RB
11h
85h Address
(5 cycles)
Col add: 1,2 & Row add: 1,2,3
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
10h
Address
(5 cycles)
A20-A30 = fixed 'Low'
tBLBH5
81h
tBLBH2
70h I/O
Destination address Col add: 1,2 & Row add: 1,2,3
A0-A12 = fixed 'Low'
A13-A18 = Valid
A19 = fixed 'High'
A20-A30 = Valid
Destination address I/O1 = 0 Successful program in plane 0
I/O1 = 1 Error in plane 0
I/O2 = 0 Successful program in plane 1
I/O2 = 1 Error in plane 1
A31 = fixed A31 = fixed
A31 = fixed
A31 = fixed
A31 = fixed A31 = fixed
NAND08GW3F2A, NAND16GW3F2A Device operations
33/65
Figure 18. Multiplane copy back program operation with random data input
I/O
RB
ai14299b
60h Busy
tWHBH
60h Address
(3 cycles)
Row add: 1,2,3
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
A20-A30 = fixed 'Low'
35h
Address
(3 cycles)
Row add: 1,2,3
A13-A18 = Valid
A19 = fixed 'High'
A20-A30 = Valid
I/O
RB
05h
00h Address
(5 cycles)
Col add: 1,2 & Row add: 1,2,3
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
E0h
Address
(2 cycles)
Col add: 1,2
A0-A12 = Valid
Data
output
A20-A30 = fixed 'Low'
I/O
RB
05h
00h Address
(5 cycles)
Col add: 1,2 & Row add: 1,2,3
A0-A12 = fixed 'Low'
A13-A18 = fixed 'Low'
A19 = fixed 'High'
E0h
Address
(2 cycles)
Col add: 1,2
A0-A12 = Valid
Data
output
A20-A30 = fixed 'Low'
I/O
RB
Data
85h Address
(5 cycles)
Col add: 1,2 & Row add: 1,2,3
A0-A12 = Valid
A13-A18 = fixed 'Low'
A19 = fixed 'Low'
Address
(2 cycles)
A20-A30 = fixed 'Low'
tBLBH5
85h
tBLBH2
Destination address Col add: 1,2
Data 11h
I/O Data
81h Address
(5 cycles)
Col add: 1,2 & Row add: 1,2,3
A0-A12 = Valid
A13-A18 = Valid
A19 = fixed 'High'
Address
(2 cycles)
A20-A30 = Valid
85h
Destination address Col add: 1,2
Data 10h
RB
A31 = fixed A31 = fixed
A31 = fixed
A31 = fixed
A31 = fixed
A31 = fixed
Device operations NAND08GW3F2A, NAND16GW3F2A
34/65
Figure 19. Multiplane copy back operation sequence
Figure 20. Multiplane copy back operation flow
I/O
RB
NI3052
60h Busy
tWHBH
60h Row addr.
(3 cycles) 35h
Row addr.
(3 cycles)
05h
00h Address
(5 cycles) E0h
Col. addr.
(2 cycles) Data out
4 Kbytes
I/O
RB
Data in
x bytes
85h Address
(5 cycles) Col. addr.
(2 cycles)
tBLBH5
85h
tBLBH2
Data in
x bytes 11h
I/O Data in
x bytes
81h Address
(5 cycles) Col. addr.
(2 cycles)
85h Data in
x bytes 10h
RB
I/O
05h
00h Address
(5 cycles) E0h
Col. addr.
(2 cycles) Data out
4 Kbytes
I/O
NAND08GW3F2A, NAND16GW3F2A Device operations
35/65
Figure 21. New multiplane copy back operation sequence
I/O
RB
NI3053
60h Busy
tWHBH
60h Row addr.
(3 cycles) 35h
Row addr.
(3 cycles)
05h
00h Address
(5 cycles) E0h
Col. addr.
(2 cycles) Data out
2 Kbytes
I/O
RB
Data in
x bytes
85h Address
(5 cycles) Col. addr.
(2 cycles)
tBLBH5
85h
tBLBH2
Data in
x bytes 11h
I/O Data in
x bytes
81h Address
(5 cycles) Col. addr.
(2 cycles)
85h Data in
x bytes 10h
RB
I/O
05h
00h Address
(5 cycles) E0h
Col. addr.
(2 cycles) Data out
2 Kbytes
I/O
I/O Data in
x bytes
85h Address
(5 cycles) Col. addr.
(2 cycles)
85h Data in
x bytes
05h
00h Address
(5 cycles) E0h
Col. addr.
(2 cycles) Data out
2 Kbytes
I/O
I/O Data in
x bytes
81h Address
(5 cycles) Col. addr.
(2 cycles)
85h Data in
x bytes
05h
00h Address
(5 cycles) E0h
Col. addr.
(2 cycles) Data out
2 Kbytes
I/O
Device operations NAND08GW3F2A, NAND16GW3F2A
36/65
Figure 22. New multiplane copy back oper ation flow
NAND08GW3F2A, NAND16GW3F2A Device operations
37/65
6.3 2-Kbyte page backward compatibility
6.3.1 Page program with 2-Kbyte page compatibility
A special page program operation is provided for 2-Kbyte compatibility, as shown in
Figure 23: Page program with 2-Kbyte page compatibility.
Figure 23. Page program with 2-Kbyte page compatibility
1. Any command between 11h and 80h is not allowed, except 70h/F1h and FFh.
6.3.2 Copy bac k program with 2-Kbyte page compatibility
A special copy back program oper ation is pro vided for 2-Kbyte page compatibility as shown
in Figure 24: Copy back progra m with 2-Kbyte page compatibility and Fig ur e 25: Cop y back
program with 2-Kbyte page compatibility and random data input.
ai14280c
R
AL
tWHRL
W
tWLWL
E
CL
tWHBL
I/O
RB
Address inputs Data input 11h 80h
80h
A0-A12 = Valid
A13-A18 = fixed 'Low'
A19 = Valid'
A20-A30 = fixed 'Low'
A31 = fixed
Address inputs Data input 10h 70h
A0-A12 = Valid
A13-A18 = Valid
A19 = must be same with the previous
A20-A32 = Valid
A31 = fixed
tBLBH2
tBLBH1
Col add 1,2 & Row add 1,2,3
2112-byte data
(1)
Col add 1,2 & Row add 1,2,3
2112-byte data
Device operations NAND08GW3F2A, NAND16GW3F2A
38/65
Figure 24. Copy back program with 2-Kbyte page compatibility
1. Copy back program operation is allowed only within the same memory plane.
2. On the same plane, it is not allowed to operate a copy-back program from an odd address page (source page) to an even
address page (target page) or from an even address page (source page) to an odd address page (target page). Therefore,
the copy-back program is permitted only between odd address pages or even address pages.
3. Any command between 11h and 85h is not allowed, except 70h/F1h and FFh.
Figure 25. Copy back program with 2-Kbyte page compatibility and random data input
1. Copy back program operation is allowed only within the same memory plane.
2. On the same plane, it is not allowed to operate a copy-back program from an odd address page (source page) to an even
address page (target page) or from an even address page (source page) to an odd address page (target page). Therefore,
the copy-back program is permitted only between odd address pages or even address pages.
3. Any command between 11h and 85h is not allowed, except 70h/F1h and FFh.
I/O
RB
Source
Add inputs
ai14281b
Read
code
tBLBH1
(Read Busy time)
00h
Busy
35h 85h Data
Target
Add inputs
Data output 11h
Busy
tBLBH2
(Program Busy time)
Col add 1,2 &
Row add 1,2,3 Col add 1,2 &
Row add 1,2,3
A0-A12 = Valid
A13-A18 = fixed 'Low'
A19 = Valid'
A20-A30 = fixed 'Low'
A31 = fixed
85h Data
Target
Add inputs
10h
Col add 1,2 &
Row add 1,2,3
A0-A12 = Valid
A13-A18 = fixed 'Low'
A19 = must be same with the previous
A20-A30 = Valid
A31 = fixed
I/O
RB
Source
Add inputs
ai14282b
Read
code
tWHBH
(Read Busy time)
00h
Busy
35h 85h Data
Target
Add inputs
Data output
Busy
tBLBH1
Col add 1,2 &
Row add 1,2,3 Col add 1,2 &
Row add 1,2,3
A0-A12 = Valid
A13-A18 = fixed 'Low'
A19 = Valid
A20-A30 = fixed 'Low'
A31 = fixed
85h Data
Add inputs
11h
Col add 1,2
RB
85h Data
Target
Add inputs
Busy
tBLBH2
Col add 1,2 &
Row add 1,2,3
A0-A12 = Valid
A13-A18 = Valid
A19 = must be same with the previous
A20-A30 = Valid
A31 = fixed
85h Data
Add inputs
10h
Col add 1,2
I/O
NAND08GW3F2A, NAND16GW3F2A Device operations
39/65
6.4 Reset
The Reset command reset the command interface and stat us register. If the Reset
command is issued during an y operation , the operatio n is aborted. If it is a prog ram or er ase
operat ion th at is bei ng aborted, the contents of t he memory locations being mod ified a re no
longer valid as the data is partia lly pr ogrammed or erased .
If the device has already been reset, th en the new Reset command is not accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the oper ation that the de vice w as p erf o rming when the command was
issued. Refer to Table 21: AC characteristics for opera tions for the values.
6.5 Read status register
The device contains a status register that provides information on the current or previous
program or erase operation. The various bits in the status register convey information and
errors on the operation.
The status register is read by issuing the Read Status Register command. The status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enab le, or Read Enab le , whichever occurs last. Wh en se ver al memories are connected in a
system, the use of Chip Enable and Read Enable signals allo ws the system to poll each
de vice separately, e ven when th e Ready/Busy pins are common-wired. It is not ne cessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a random read cycle a new read command must be issued to
continue with a page read operation.
Refer to Table 8 which summarizes status register bits and should be read in conjunction
with the following text descriptions.
Table 8. Status registe r bits
I/O Page program
(SP/DP) Block erase
(SD/DP) Page read Definition
0 Pass/fail Pass/fail NA Pass: ‘0’, Fail: ‘1’
1 Plane 0: pass/fail Plane 0 Pass/fail NA Plane 0: Pass: ‘0’, Fail: ‘1’
2 Plane 1: pass/fail Plane 1 Pass/fail NA Plane 1: Pass: ‘0’, Fail: ‘1’
3NA NA NA–
4NA NA NA–
5Ready/busy Ready/busy Ready/busy Busy: ‘0’; Ready:’1’
6Ready/busy Ready/busy Ready/busy Busy: ‘0’, Ready: ‘1’
7Write protect Write protect Write protect Protected: ‘0’, Not protected: ‘1’
Device operations NAND08GW3F2A, NAND16GW3F2A
40/65
6.5.1 Write protection bit (SR7)
The write protection bit can identif y if the d e vice is prot ected or no t. If the write protection b it
is set to ‘1’ the device is not protected and program or erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and progr am or erase operations are
not allowed.
6.5.2 P/E/R controller bit (SR6)
Status register bit SR6 acts as a P/E/R c ontroller bit, which indicates whether the P/E/R
controller is active or inactive . When the P/E/R controller bit is set to ‘0’, the P/E/R controller
is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is
ready).
6.5.3 Error bit (SR0)
T he error bit identifies if any errors hav e bee n detect ed by the P/E/R controller. The error bit
is set to ‘1’ when a program or erase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’, the operation has co mp let ed suc ces sfu lly.
6.6 Read electronic signature
The device contains a manufacturer code and device code. The following three steps are
required to read these codes:
1. One bus write cycle to issue the Read Electronic Signature command (90h)
2. One bus write cycle to input the address (00h)
3. Four bus read cycles to sequentially output the data ( as shown in Table 10: Electronic
signature).
Table 9. Device identifier codes
Device identifier cycle Description
1st Manufacturer code
2nd Device identifier
3rd Internal chip number, cell type, etc.
4th Page size, block size, spare size organization
5th Multiplane inf ormation
Table 10. Electronic signature
Root part number
Byte/word 1 Byte/word 2 Byte 3
(see Table 11)Byte 4
(see Table 12)Byte 5
(see Table 13)
Manufacturer
code Device code
NAND08GW3F2A 20h D3h 10h A6h 34h
NAND16GW3F2A 20h D5h 51h A6h 38h
NAND08GW3F2A, NAND16GW3F2A Device operations
41/65
Table 11. Electr onic signature byte 3
I/O Definition Value Description
I/O1-I/O0 Die/package
0 0
0 1
1 0
1 1
1
2
4
8
I/O3-I/O2 Cell type
0 0
0 1
1 0
1 1
2-level cell
4-level cell
8-level cell
16-level cell
I/O5-I/O4 Number of simultaneously
programmed pages
0 0
0 1
1 0
1 1
1
2
4
8
I/O6 Interleaved programming
between multiple devices 0
1Not supported
Supported
I/O7 Write cache 0
1Not supported
Supported
Table 12. Electr onic signature byte 4
I/O Definition Value Description
I/O1-I/O0 Page size
(without spare area)
0 0
0 1
1 0
1 1
1 Kbyte
2 Kbytes
4 Kbytes
8 Kbytes
I/O2 Spare area size
(byte/512 byte) 0
1 8
16
I/O7, I/O3 Serial access time
0 0
0 1
1 0
1 1
50 ns
30 ns
25 ns
Reserved
I/O5-I/O4 Block size
(without spare area)
0 0
0 1
1 0
1 1
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
I/O6 Organization 0
1x8
x16
Data protection NAND08GW3F2A, NAND16GW3F2A
42/65
7 Data protection
The device has hardware features to protect again st spurious program and erase
operations. An internal voltage detector disables all functi ons whenever VDD is below the
VLKO threshold. It is recommended to keep WP at VIL during power-up and power-down.
In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept
Low (VIL) to guarant ee hardw a re prot ection du ring pow er transitions , as sho wn in Figure 26.
Figure 26. Data protection
Table 13. Electr onic signature byte 5
I/O Definition Value Description
I/O1 - I/O0 Reserved 0 0
I/O3 - I/O2 Plane number
0 0
0 1
1 0
1 1
1 plane
2 planes
4 planes
8 planes
I/O6 - I/O4 Plane size
(without redundant area)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
512 Mbits
1 Gbit
2 Gbits
4 Gbits
8 Gbits
Reserved
Reserved
Reserved
I/O7 Reserved 0
Ai11086b
VLKO
VDD
W
Nominal range
Locked
Locked
NAND08GW3F2A, NAND16GW3F2A Write protect operation
43/65
8 Write protect operation
Erase and pr ogr am operations ar e automatically r eset when WP goes Lo w (tVLWH= 100 ns).
Erase and pro gram operations are enabled and disabled as shown in Figure 27, Figure 28,
Figure 29, and Figure 30.
If WP goes Low after the device has gone busy, the internal reset is executed and
program/erase op eration exits. The device becomes ready again after the internal reset
sequence is e x ecuted. To av oid any corruption of stored data, WP must not go Lo w aft er the
Confirm command.
Figure 27. Program enable waveform
Figure 28. Program disable waveform
AI14276
WP
R/B
I/Ox 80h 10h
W
tVHWH
AI14277
WP
R/B
I/Ox 80h 10h
W
tVLWH
Software algorithms NAND08GW3F2A, NAND16GW3F2A
44/65
Figure 29. Erase enable waveform
Figure 30. Erase disable waveform
9 Software algorithms
This section provides information on the software algorithms that Numonyx recommends
implementing to manage the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are prog rammed and erased by Fowler-Nordheim tunneling using
high voltage. Exposing the device to high voltage for extended periods can cause the oxide
layer to be damaged. For this reason, the number of program and erase cycles is limited
(see Tabl e 1 5: Prog ra m and er ase ti mes and prog r am er ase end ura nce cycles for value). To
extend the n umber of program and erase cycles and to increase data r etention, it is
recommended to implement garbage collection and wear-leveling while the implementation
of error correction code algorithms is mandatory.
To help integrate a NAND memory into an application, Numonyx can provide a full range of
software solutions: file system, sector manager, drivers, and code management.
Contact the near est Numonyx sales office or visit www.numonyx.com for more details.
9.1 Bad block management
Devices with bad b locks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
AI14278
WP
R/B
I/Ox 60h D0h
W
tVHWH
AI14279
WP
R/B
I/Ox 60h D0h
W
tVLWH
NAND08GW3F2A, NAND16GW3 F 2A Soft war e al go rit hms
45/65
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 1st and 6th bytes, in the
spare area of the first page, does not contain FFh is a bad block.
The bad block information must be read before any erase is attempted as the bad block
Inf ormation ma y be erased . F or th e system to be ab le to recogniz e the bad b loc ks base d on
the original inf ormation it is recommended to create a bad b loc k tab le f ollowing the f lowchart
shown in Fig ure 31: Bad block management flowchart.
9.2 NAND flash memory failure modes
The NANDxxGW3F2A may contain bad blocks, where the reliability of blocks that contain
one or more inv alid bits is not guara nteed. Additional bad blocks may develop during the
lifetime of the devices.
To implement a highly reliable system, all the possible failure modes must be considered:
●Program/erase failure
in this case, the block has to be replaced by copying the data to a valid block. These
additional bad blocks can be identif ied as attempts to program or erase them and give
errors in the status register.
Because the failure of a page program operation does not affect the data in other
pages in the same b lock, the b loc k can be replaced b y re-programmin g the current data
and copying the rest of the replaced block to an available valid block. The Copy Back
Program command can be used to copy the data to a valid block. See Figure 8:
Random data input during sequential data input for more details.
●Read failure
in this case, ECC correction must be implemented. To efficiently use the memory
space, it is recommended t o recover single- bit errors in re ad b y ECC , with out replacing
the whole block.
Refer to Table 14 for the procedure to follow if an error occurs during an operation.
Tabl e 14. Block failure
Operation Procedure
Erase Block replacement
Program Bloc k replacement or ECC (with 1 bit/528 bytes)
Read ECC (with 1 bit/528 bytes)
Software algorithms NAND08GW3F2A, NAND16GW3F2A
46/65
Figure 31. Bad block management flowchart
9.3 Garbage collection
When a data page needs to be modified, it is faster to write to the first available page and
mark the previous page as invalid. After several updates it is necessary to remove invalid
pages to free some memory space.
To free this memory space and allow further program operations, it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 32).
Figure 32. Garbage collection
AI07588C
START
END
NO
YES
YES
NO
Block Address =
Block 0
Data
= FFh?
Last
block?
Increment
Block Address
Update
Bad Block table
Valid
page
Invalid
page Free
page
(erased)
Old area
AI07599B
New area (after GC)
NAND08GW3F2A, NAND16GW3 F 2A Soft war e al go rit hms
47/65
9.4 Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-lev eling algorithm
to monitor and sprea d the number of write cycles per block.
In memories that do not use a wear-leveling algorithm, not all blocks get used at the same
rate. The wear-leveling algorithm ensures that equal use is made of all the available write
cycles for each block.
There are two wear-leveling levels:
1. First level wear-leveling, where new data is programmed to the free bloc ks that have
had the fewest write cycles
2. Second le v el we ar-le v eling, where long-liv ed data is copi ed to another b loc k so that the
original block can be use d for more frequently changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
Software algorithms NAND08GW3F2A, NAND16GW3F2A
48/65
9.5 Hardware simulation models
9.5.1 Behavioral simulation models
Denali softw are corporation models are pl atform-independent funct ional models designed to
assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic beha vior and timings of NAND flash de vices, and, there fo re, allo w
software to be developed before hardware.
9.5.2 IBIS simulations models
I/O buffer information specification (IBIS) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
These models provide information such as AC charact eristics, rise/fa ll times, and package
mechanical data, all of which are measured or simula ted at v oltage and te mperatur e ranges
wider than those allowed by target specifica tions.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
NAND08GW3F2A, NAND16GW3F2A Program and erase times and endurance cycles
49/65
10 Program and erase times and endurance cycles
Table 15 shows the program and erase times and the number of program/erase cycles per
block.
Table 15. Program and erase times and program erase endurance cycles
Parameters Min Typ Max Unit
Page program time 500 700 µs
Block erase time 1.5 2ms
Cache read busy time (tRCBSY)–3t
WHBH (tR)µs
Program/er ase cycles (per bloc k (with ECC) 100,000 cycles
Data retention 10 years
Number of partial program cycles (NOP) within the
same page (main array or spare array) 8 cycles
Maximum ratings NAND08GW3F2A, NAND16GW3F2A
50/65
11 Maximum ratings
Stressing the device above the ratings listed in Table 16: Absolute maximum ratings may
cause permanent damage to the device. These are stre ss r a t ings o nly, and operat ion of t he
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exp osur e to abso lute maximum rating conditions for
extended periods may affect device reliability.
Table 16. Absolute maximum ratings
Symbol Parameter Value Unit
Min Max
TBIAS Temperature under bias – 50 125 °C
TSTG Storage temperature – 65 150 °C
VIO(1)
1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
Input or output voltage – 0.6 4.6 V
VDD Supply voltage – 0.6 4.6 V
NAND08GW3F2A, NAND16GW3F2A DC and AC parameters
51/65
12 DC and AC parameters
This section summarizes the oper a ting an d mea suremen t con ditions as w ell as th e DC and
A C charact eristics of the de vice . The paramet ers in the f ollo wing DC and A C ch aracteristics
tables are derived from tests performed under the measurement conditions summarized in
Table 17: Operating and AC measurement conditions. Design er s sho u ld che ck that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 17. Operating and AC measurement conditions
Parameter Min Max Units
Supply voltage (VDD)2.7 3.6V
Ambient temperature (TA) –40 85 °C
Load capacitance (CL) (1 TTL GATE and CL)50pF
Input pulses voltages 0 VDD V
Input and output timing ref. voltages 1.5 V
Output circuit resistor Rref 8.35 kΩ
Input rise and fall times 5 ns
Tabl e 18. Capacit ance(1)
1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
Symbol Parameter Test condition Typ Max U nit
CIN Input capacitance VIN = 0 V 10 pF
CI/O Input/output
capacitance VIL = 0 V 10 pF
DC and AC parameters NAND08GW3F2A, NAND16GW3F2A
52/65
Table 19. DC characteristics(1)
Symbol Parameter Test conditi on s Min Typ Max Unit
IDD1 Operating
current
Sequential read tRLRL minimum
E=V
IL, IOUT =0mA –1530mA
IDD2 Program – – 15 30 mA
IDD3 Erase – – 15 30 mA
IDD4 Standby current (TTL) E=V
IH, WP =0/V
DD 1mA
IDD5 Standby current (CMOS) E=V
DD-0.2,
WP =0/V
DD –10 50 µA
ILI Input leakage current VIN = 0 to 3.6 V – – ±10 µA
ILO Output leakage current VOUT = 0 to 3.6 V – – ±10 µA
VIH Input high voltage –0.8 x VDD – VDD +0.3 V
VIL Input low voltage –-0.3 –0.2 x VDD V
VOH Output high voltage level IOH = -400 µA 2.4 – – V
VOL Output low voltage lev el IOL = 2.1 mA – – 0.4 V
IOL (RB)Output low current (RB) VOL = 0.4V 810 mA
VLKO VDD supply voltage (erase and
program lockout) – – – 2 V
1. Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the
number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently
executing different operations.
Tabl e 20. AC charac teristics for command, address, data inpu t
Symbol Alt. symbol Parameter Value Unit
tALLWH tALS Address Latch Low to Write Enable High AL setup time Min 12 ns
tALHWH Address Latch High to Write Enable High
tCLHWH tCLS Command Latch High to Write Enable High CL setup time Min 12 ns
tCLLWH Command Latch Low to Write Enable High
tDVWH tDS Data Valid to Write Enable High Data setup time Min 12 ns
tELWH tCS Chip Enable Low to Write Enable High E setup time Min 20 ns
tWHALH tALH Write Enable High to Address Latch High AL hold time Min 5ns
tWHALL Write Enable High to Address Latch Low
tWHCLH tCLH Write Enable High to Command Latch High CL hold time Min 5ns
tWHCLL Write Enable High to Command Latch Low
tWHDX tDH Write Enable High to Data Transition Data hold time Min 5ns
tWHEH tCH Write Enable High to Chip Enable High E hold time Min 5ns
tWHWL tWH Write Enable High to Write Enable Low W High hold time Min 10 ns
tWLWH tWP W rite En able Low to Write Enable High W pulse width Min 12 ns
tWLWL tWC Write En able Low to Write Enable Low Wr ite cycle time Min 25 ns
NAND08GW3F2A, NAND16GW3F2A DC and AC parameters
53/65
Table 21. AC characteristics for operations
Symbol Alt.
symbol Parameter Value Unit
Min Typ Max
tALLRL1 tAR Address Latch Low to Read Enable Low Read electronic signature 10 ns
tALLRL2 Read cycle 10 ns
tBHRL tRR Ready/Busy High to Read Enable Low 20 ns
tBLBH1 tRBSY Ready/Busy Low to Ready/Busy High
Read busy time 25 µs
tBLBH2 tPROG Program busy time 500 700 µs
tBLBH3 tBERS Erase busy time 1.5 2ms
tBLBH4 tRST
Reset Busy time, during ready 5µs
Reset Busy time, during read 20 µs
Reset Busy time, during program 20 µs
Reset Busy time, during erase 50 µs
tBLBH5 tCBSY Dummy Busy time for multiplane operations 1 2 µs
tCLLRL tCLR Command Latch Low to Read Enable Low 10 ns
tDZRL tIR Data Hi-Z to Read Enable Low 0ns
tEHQZ tCHZ Chip Enable High to Output Hi-Z 50 ns
tELQV tCEA Chip Enable Low to Output Valid 25 ns
tRHRL tREH Read Enable High to Read Enable Low Read Enable High hold
time 10 ns
tEHQX tCOH Chip Enable High to Output Hold 15 ns
tRHQX tRHOH Read Enable High to Output Hold 15 ns
tRLQX tRLOH Read Enable Low to Output Hold (EDO mode) 5ns
tRHQZ tRHZ Read Enable High to Output Hi-Z 100 ns
tRLRH tRP Read Enable Low to Read Enable High Read Enable pulse width 12 ns
tRLRL tRC Read Enable Low to Read Enable Low Read cycle time 25 ns
tRLQV tREA Read Enable Low to Output Valid Read Enable access time 20 ns
Read ES access time(1)
tWHBH tRWrite Enable High to Ready/Busy High Read busy time 25 µs
tWHBL tWB Write Enable High to Ready/Busy Low 100 ns
tWHRL tWHR Write Enable High to Read Enable Low 80 ns
tWHWH(2) tADL Last Address latched on Data Loading time during program operations 70 ns
tVHWH(3) tWW Write protection time 100 ns
tVLWH(3) 100 ns
1. ES = electronic signature.
2. tWHWH is the delay from Write Enable rising edge during the final address cycle to Write Enable rising edge during the first
data cycle.
3. WP High to W High during program/erase enable operations or WP Low to W High during program/erase disable
operations.
DC and AC parameters NAND08GW3F2A, NAND16GW3F2A
54/65
Figure 33. Command latch AC wa veforms
Figure 34. Address latch AC waveforms
ai12470b
CL
E
W
AL
I/O
tCLHWH
tELWH
tWHCLL
tWHEH
tWLWH
tALLWH tWHALH
Command
tDVWH tWHDX
(CL Setup time) (CL Hold time)
(Data Setup time) (Data Hold time)
(ALSetup time) (AL Hold time)
H(E Setup time) (E Hold time)
ai12471
CL
E
W
AL
I/O
tWLWH
tELWH tWLWL
tCLLWH
tWHWL
tALHWH
tDVWH
tWLWL tWLWL
tWLWHtWLWH tWLWH
tWHWL tWHWL
tWHDX
tWHALL
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
tWHALL
Adrress
cycle 1
tWHALL
(AL Setup time)
(AL Hold time)
Adrress
cycle 4
Adrress
cycle 3
Adrress
cycle 2
(CL Setup time)
(Data Setup time)
(Data Hold time)
(E Setup time)
Adrress
cycle 5
tWLWL
tWLWH
tDVWH
tWHDX
tWHWL
tWHALL
NAND08GW3F2A, NAND16GW3F2A DC and AC parameters
55/65
Figure 35. Data input latch AC waveforms
Figure 36. Sequential data output after read AC waveforms
1. CL and AL are Low, VIL, and W is High, VIH.
2. tRHQX is applicable for frequencies lower than 33 MHz (for instance, tRLRL lower than 30 ns).
3. tRLQX is applicable for frequencies higher than 33 MHz (for instance, tRLRL lower than 30 ns).
tWHCLH
CL
E
AL
W
I/O
tALLWH
tWLWL
tWLWH
tWHEH
tWLWH
tWLWH
Data In 0 Data In 1 Data In
Last
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
ai12472
(Data Setup time)
(Data Hold time)
(ALSetup time)
(CL Hold time)
(E Hold time)
E
ai13175
R
I/O
RB
tRLRL
tRLQV
tRHRL
tRLQV
Data Out Data Out Data Out
tBHRL
tRHQZ
tEHQZ
(R Accesstime)
tEHQX
tRHQX(2)
tRLRH
tELQV tRLQX(3)
DC and AC parameters NAND08GW3F2A, NAND16GW3F2A
56/65
Figure 37. Read status register AC waveforms
Figure 38. Read electronic signature AC waveforms
1. Refer to Table 10 for the values of the manufacturer and device codes, and to Table 11, Table 12, and Table 13 for the
information contained in byte 3, byte 4, and byte 5.
tELWH
tDVWH
Status Register
Output
70h or 7Bh
CL
E
W
R
I/O
tCLHWH
tWHDX
tWLWH
tWHCLL
tCLLRL
tDZRL
tRLQV
tEHQX
tRHQX
tWHRL
tELQV
tWHEH
ai13177
(Data Setup time) (Data Hold time)
tEHQZ
tRHQZ
90h 00h
Man.
code Device
code
CL
E
W
AL
R
I/O
tRLQV
Read Electronic
Signature
command
1st Cycle
address
ai13178
(Read ES Access time)
tALLRL1
Byte4
Byte3Byte1 Byte2
see Note.1
Byte5
NAND08GW3F2A, NAND16GW3F2A DC and AC parameters
57/65
Figure 39. Page read operation AC waveforms
CL
E
W
AL
R
I/O
RB
tWLWL
tWHBL
tALLRL2
00h
Data
NData
N+1 Data
N+2 Data
Last
tWHBH tRLRL
tEHQZ
tRHQZ
ai13638
Busy
Command
code Address N input Data Output
from address N to last byte in page
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Read Cycle time)
tRLRH
tBLBH1
30h
Add.N
cycle 5
Command
code
DC and AC parameters NAND08GW3F2A, NAND16GW3F2A
58/65
Figure 40. Page program AC waveforms
CL
E
W
AL
R
I/O
RB
SR0
ai13639
N
Last 10h
70h
80h
Page Program
setup code Confirm
code Read Status Register
tWLWL tWLWL tWLWL
tWHBL
tBLBH2
Page
Program
Address Input Data Input
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Write Cycle time)
(Program Busy time)
Add.N
cycle 5
tWHWH
NAND08GW3F2A, NAND16GW3F2A DC and AC parameters
59/65
Figure 41. Block erase AC wavef orms
Figure 42. Reset AC waveforms
D0h60h SR0
70h
ai08038c
tWHBL
tWLWL
tBLBH3
Block Erase
setup command Block Erase
CL
E
W
AL
R
I/O
RB
Confirm
code Read Status Register
Block Address Input
(Erase Busy time)
(Write Cycle time)
Add.
cycle 1 Add.
cycle 3
Add.
cycle 2
W
R
I/O
RB
tBLBH4
AL
CL
FFh
ai08043
(Reset Busy time)
DC and AC parameters NAND08GW3F2A, NAND16GW3F2A
60/65
12.1 Ready/Busy signal electrical characteristics
Figure 44, Figure 43 and Figure 45 show the electrical characteristics for the Ready/Busy
signal. The v alue required for th e resistor R P can be calculated using the following equation:
So,
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP
max is determined by the maximum value of tr.
Figure 43. Ready/Busy AC waveform
Figure 44. Ready/Busy load circuit
RPmin VDDmax VOLmax
–()
IOL IL
+
-------------------------------------------------------------=
RPmin 3.2V
8mA IL
+
---------------------------=
NI3087B
busy
VOH
ready VDD
VOL
tftr
AI07563B
RP
VDD
VSS
RB
DEVICE
Open drain output
ibusy
NAND08GW3F2A, NAND16GW3F2A DC and AC parameters
61/65
Figure 45. Resistor value versus waveform timings for Ready/Busy signal
1. T = 25 °C.
Package mechanical NAND08GW3F2A, NAND16GW3F2A
62/65
13 Package mechanical
To meet environmental requirements, Numonyx off ers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 46. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1. Drawing is not to scale.
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
Tabl e 22. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
Symbol Millimeters Inches
Typ Min Max Typ Min Max
A1.200.047
A1 0.10 0.05 0.15 0.004 0.002 0.006
A2 1.00 0.95 1.05 0.039 0.037 0.041
B 0.22 0.17 0.27 0.009 0.007 0.011
C 0.10 0.21 0.004 0.008
CP 0.08 0.003
D1 12.00 11.90 12.10 0.472 0.468 0.476
E 20.00 19.80 20.20 0.787 0.779 0.795
E1 18.40 18.30 18.50 0.724 0.720 0.728
e 0.50 – – 0.020 –
L 0.60 0.50 0.70 0.024 0.020 0.028
L1 0.80 0.031
a3°0°5°3°0°5°
NAND08GW3F2A, NAND16GW3F2A Ordering information
63/65
14 Ordering information
Note: Not all combinations are necessarily available. For a list of available devices or for further
information on any aspect of these products, please contact y our nearest Numonyx sales
office.
Table 23. Ordering information scheme
Example: NAND08G W 3 F 2 A N 6 E
Device type
NAND flash memory
Density
08G = 8 Gbits
16G = 16 Gbits
Operatin g voltage
W = VDD = 2.7 to 3.6 V
Bus width
3 = x8
Family identifier
F = 4 Kbyte-page SLC
Device options
2 = Chip Enable ‘don't care’ enabled
Pro duct version
A = first version
Package
N = TSOP48 12 x 20 mm
Temperature range
6 = −40 to 85 °C
Option
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape and reel packing
Revision history NAND08GW3F2A, NAND16GW3F2A
64/65
15 Revision history
Table 24. Document revision history
Date Revision Changes
06-Aug-2008 1 Initial release.
30-Oct-2008 2 Document status promoted from target specification to preliminary
data. Added information about the OTP area security feature.
24-Sep-2009 3
Added note 1 below Table 19: DC character istics. References to
ECOPACK removed and replaced by RoHS compliance. Modified:
random access value on the cover page and in Table 1: Device
summary, Figure 43: Ready/Busy AC waveform and Figure 45:
Resistor value versus waveform timings for Ready/Busy signal.
Minor text changes.
07-Oct-2009 4 Modified Section 9.1: Bad block management.
19-Nov-2009 5 Further modifications to Section 9.1: Bad block management.
Modified the value of the single and multiplane page program
operation time throughout the document.
NAND08GW3F2A, NAND16GW3F2A
65/65
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Contact your local Numonyx sales office or your dist ributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a tra demark or regi stered trademark of Numonyx or its subsidiar ies in the United States and ot her countries.
*Other names and brands may be claimed as the property of others.
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