Intel(R) XeonTM Processor MP with up to 2-MB L3 Cache (on the 0.13 Micron Process) Datasheet Product Features Available at 1.50, 1.90, and 2 GHz Multi-processing server support Binary compatible with applications running on previous members of the Intel(R) IA32 microprocessor line Intel(R) NetBurstTM microarchitecture Hyper-Threading Technology -- Hardware support for multi-threaded applications 400 MHz System bus -- Bandwidth up to 3.2 GB/second Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency Hyper-Pipelined Technology Advance Dynamic Execution -- Very deep out-of-order execution -- Enhanced branch prediction Level 1 Execution Trace Cache stores 12 K micro-ops and removes decoder latency from main execution loops -- Includes 8- KB Level 1 data cache 512-KB Advanced Transfer L2 Cache (ondie, full speed Level 2 cache) with 8-way associativity and Error Correcting Code (ECC) 1-MB or 2-MB L3 Cache (on-die, full speed Level 3 cache) with 8-way associativity and Error Correcting Code (ECC) Enables system support of up to 64 GB of physical memory Streaming SIMD Extensions 2 (SSE2) -- 144 new instructions for double-precision floating point operations, media/video streaming, and secure transactions Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities -- System Management mode -- Multiple low-power states Advanced System Management Features -- System Management Bus -- Processor Information ROM (PIROM) -- OEM Scratch EEPROM -- Thermal Monitor -- Machine Check Architecture (MCA) The Intel(R) XeonTM processor MP with up to 2-MB L3 cache on the 0.13 micron process is designed for high-performance multi-processor server applications. Based on the Intel(R) NetBurstTM microarchitecture and the new Hyper-Threading Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The Intel Xeon processor MP with up to 2MB L3 cache is scalable to four processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Microsoft Windows* XP and Windows* 2000 operating systems, Linux*, and UNIX*. The Intel Xeon processor MP with up to 2 MB L3 cache delivers compute power at unparalleled value and flexibility for internet infrastructure and departmental server applications. The Intel NetBurst microarchitecture and Hyper-Threading Technology deliver outstanding performance and headroom for peak internet server workloads, resulting in faster response times, support for more users, and improved scalability. Document Number: 251931-001 November 2002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) XeonTM processor MP with up to 2-MB L3 Cache may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. * Other names and brands may be claimed as the property of others. Copyright (c) 2002 Intel Corporation Datasheet Contents Contents 1 Introduction ................................................................................................................11 1.1 1.2 2 Electrical Specifications ........................................................................................15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3 3.2 3.3 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines ...........................................................................................................47 System Bus Signal Quality Specifications and Measurement Guidelines...........48 System Bus Signal Quality Specifications and Measurement Guidelines...........51 3.3.1 Overshoot/Undershoot Guidelines .........................................................51 3.3.2 Overshoot/Undershoot Magnitude .........................................................52 3.3.3 Overshoot/Undershoot Pulse Duration...................................................52 3.3.4 Activity Factor .........................................................................................52 3.3.5 Reading Overshoot/Undershoot Specification Tables............................53 3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifications .........................................................................................53 Mechanical Specifications....................................................................................57 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Datasheet System Bus and GTLREF ...................................................................................15 Power and Ground Pins ......................................................................................15 Decoupling Guidelines ........................................................................................16 2.3.1 VCC Decoupling .....................................................................................16 2.3.2 System Bus AGTL+ Decoupling.............................................................16 System Bus Clock (BCLK[1:0]) and Processor Clocking ....................................16 2.4.1 Bus Clock ..............................................................................................17 PLL Filter .............................................................................................................18 2.5.1 Mixing Processors ..................................................................................19 Voltage Identification ..........................................................................................20 2.6.1 Mixing Processors of Different Voltages ................................................21 Reserved or Unused Pins ...................................................................................22 System Bus Signal Groups .................................................................................22 Asynchronous GTL+ Signals...............................................................................24 Maximum Ratings................................................................................................24 Processor DC Specifications...............................................................................25 AGTL+ System Bus Specifications .....................................................................30 System Bus AC Specifications ............................................................................31 Processor AC Timing Waveforms .......................................................................36 System Bus Signal Quality Specifications ....................................................47 3.1 4 Terminology.........................................................................................................13 1.1.1 Processor Packaging Terminology.........................................................13 References ..........................................................................................................14 Mechanical Specifications ...................................................................................59 Package Load Specifications ..............................................................................64 Insertion Specifications .......................................................................................64 Mass Specifications.............................................................................................64 Materials..............................................................................................................65 Markings..............................................................................................................65 Pinout Diagram....................................................................................................66 3 Contents 5 Thermal Specifications .......................................................................................... 69 5.1 5.2 6 Features ....................................................................................................................... 75 6.1 6.2 6.3 6.4 7 7.3 7.4 Logic Analyzer Interface (LAI)............................................................................. 97 8.1.1 Mechanical Considerations .................................................................... 97 8.1.2 Electrical Considerations........................................................................ 97 Pin Listing and Signal Definitions..................................................................... 99 9.1 4 Introduction ......................................................................................................... 91 Mechanical Specifications................................................................................... 92 7.2.1 Boxed Processor Heatsink Dimensions ................................................. 92 7.2.2 Boxed Processor Heatsink Weight......................................................... 92 7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports........... 92 Boxed Processor Requirements ......................................................................... 95 7.3.1 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor ............................................................................................... 95 Thermal Specifications........................................................................................ 95 7.4.1 Boxed Processor Cooling Requirements ............................................... 95 Debug Tools Specifications................................................................................. 97 8.1 9 Power-On Configuration Options ........................................................................ 75 Clock Control and Low Power States.................................................................. 75 6.2.1 Normal State--State 1 ........................................................................... 75 6.2.2 AutoHALT Powerdown State--State 2 .................................................. 76 6.2.3 Stop-Grant State--State 3 ..................................................................... 77 6.2.4 HALT/Grant Snoop State--State 4 ........................................................ 77 6.2.5 Sleep State--State 5.............................................................................. 77 6.2.6 Bus Response during Low Power States ............................................... 78 Thermal Monitor .................................................................................................. 78 6.3.1 Thermal Diode........................................................................................ 79 System Management Bus (SMBus) Interface ..................................................... 79 6.4.1 Processor Information ROM (PIROM).................................................... 80 6.4.2 Scratch EEPROM .................................................................................. 83 6.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions ........... 83 6.4.4 SMBus Thermal Sensor ......................................................................... 83 6.4.5 Thermal Sensor Supported SMBus Transactions .................................. 84 6.4.6 SMBus Thermal Sensor Registers ......................................................... 86 6.4.6.1 Thermal Reference Registers ................................................... 86 6.4.6.2 Thermal Limit Registers ............................................................ 87 6.4.6.3 Status Register.......................................................................... 87 6.4.6.4 Configuration Register............................................................... 87 6.4.6.5 Conversion Rate Registers ....................................................... 88 6.4.7 SMBus Thermal Sensor Alert Interrupt .................................................. 88 6.4.8 SMBus Device Addressing..................................................................... 89 Boxed Processor Specifications ....................................................................... 91 7.1 7.2 8 Thermal Specifications........................................................................................ 71 Measurements for Thermal Specifications.......................................................... 73 5.2.1 Processor Case Temperature Measurement ......................................... 73 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Pin Assignments........................................................................................................ 99 Datasheet Contents 9.2 9.1.1 Pin Listing by Pin Number ....................................................................108 Signal Definitions...............................................................................................117 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Datasheet Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................18 Phase Lock Loop (PLL) Filter Requirements ......................................................19 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Voltage-Current Projections ................................................................................26 Electrical Test Circuit...........................................................................................36 TCK Clock Waveform..........................................................................................37 Differential Clock Waveform................................................................................37 Differential Clock Crosspoint Specification..........................................................38 System Bus Common Clock Valid Delay Timing Waveform ...............................38 System Bus Source Synchronous 2X (Address) Timing Waveform....................39 System Bus Source Synchronous 4X (Data) Timing Waveform .........................40 System Bus Reset and Configuration Timing Waveform ....................................41 Power-On Reset and Configuration Timing Waveform .......................................41 TAP Valid Delay Timing Waveform .....................................................................42 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform ............................................................................................................42 THERMTRIP# to Vcc Timing...............................................................................42 SMBus Timing Waveform....................................................................................43 SMBus Valid Delay Timing Waveform ................................................................43 Example 3.3 Volt/SM_VCC Sequencing .............................................................44 FERR#/PBE# Valid Delay Timing .......................................................................45 BCLK[1:0] Signal Integrity Waveform..................................................................48 Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers ...............................................................................49 High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers ...............................................................................49 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers .........................................................................................................50 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers .........................................................................................................51 Maximum Acceptable Overshoot/Undershoot Waveform ...................................56 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package Assembly Drawing (Including Socket).................................................................58 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package Top View Component Placement Detail...............................................59 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package Drawing ................................................................................................59 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Top View - Component Keep-In ..........................................................................61 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package Cross Section View - Pin Side Component Keep-In ...........................................61 5 Contents 44 45 46 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package Processor Pin Details.......................................................................................... 62 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package IHS Flatness and Tilt Drawing.............................................................. 63 Intel(R) XeonTM Processor MP on the 0.13 Micron Process INT-mPGA Package IHS Flatness and Tilt Drawing.............................................................. 63 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Top-Side Markings (Package Example).............................................................. 65 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Bottom-Side Markings (Package Example) ........................................................ 66 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package Pinout Diagram - Top View ................................................................................. 67 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package Pinout Diagram - Bottom View ............................................................................ 68 Thermal and Mechanical Components - Exploded View .................................... 70 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Thermal Design Power vs. Electrical Projections................................................ 72 Thermal Measurement Point for Processor TCASE ........................................... 73 Stop Clock State Machine................................................................................... 76 Logical Schematic of SMBus Circuitry ................................................................ 80 Mechanical Representation of the Boxed Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Passive Heatsink................................... 91 Boxed Processor Clip.......................................................................................... 93 Boxed Processor Retention Mechanism ............................................................. 93 Multiple View Space Requirements for Boxed Processors ................................. 94 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Feature Table for Intel(R) XeonTM Processor MP on the 0.13 Micron Process ..... 12 Core Frequency to System Bus Multiplier Configuration .................................... 17 System Bus Clock Frequency Select Truth Table for BSEL[1:0] ........................ 18 Voltage Identification Definition........................................................................... 21 System Bus Signal Groups ................................................................................. 23 Processor Absolute Maximum Ratings ............................................................... 24 Voltage and Current Specifications..................................................................... 25 System Bus Differential BCLK DC Specifications ............................................... 27 AGTL+ Signal Group DC Specifications ............................................................. 28 PWRGOOD and TAP Signal Group DC Specifications ...................................... 28 Asynchronous GTL+ Signal Group DC Specifications ........................................ 29 SMBus Signal Group DC Specifications ............................................................. 29 BSEL[1:0] and VID[4:0] DC Specifications.......................................................... 30 AGTL+ Bus Voltage Definitions........................................................................... 31 System Bus Differential Clock AC Specifications............................................... 32 System Bus Common Clock AC Specifications .................................................. 32 System Bus Source Synchronous AC Specifications ......................................... 33 Miscellaneous Signals AC Specifications ........................................................... 34 31 32 33 34 35 36 37 38 39 40 41 42 43 Tables 6 Datasheet Contents 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Datasheet System Bus AC Specifications (Reset Conditions) .............................................34 TAP Signal Group AC Specifications ..................................................................35 SMBus Signal Group AC Specifications..............................................................35 BCLK Signal Quality Specifications.....................................................................47 Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers ...............48 Ringback Specifications for PWRGOOD Input and TAP Buffers ........................49 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Tolerance ............................................................................................................54 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Common Clock AGTL+ Signal Group Overshoot/Undershoot Tolerance ...........54 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Common Clock AGTL+ Signal Group Overshoot/Undershoot Tolerance ...........55 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance ............................................................................................................55 Dimensions for the Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package ...............................................................................60 Package Dynamic and Static Load Specifications ..............................................64 Processor Mass...................................................................................................64 Processor Material Properties .............................................................................65 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Thermal Design Power........................................................................................71 Power-On Configuration Option Pins ..................................................................75 Processor Information ROM Format ...................................................................80 Read Byte SMBus Packet ...................................................................................83 Write Byte SMBus Packet ...................................................................................83 Write Byte SMBus Packet ...................................................................................84 Read Byte SMBus Packet ...................................................................................85 Send Byte SMBus Packet ...................................................................................85 Receive Byte SMBus Packet...............................................................................85 ARA SMBus Packet ............................................................................................85 SMBus Thermal Sensor Command Byte Bit Assignments..................................85 Thermal Reference Register Values ...................................................................86 SMBus Thermal Sensor Status Register.............................................................87 SMBus Thermal Sensor Configuration Register .................................................88 SMBus Thermal Sensor Conversion Rate Registers ..........................................88 Thermal Sensor SMBus Addressing on the Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor ...............................................................90 Memory Device SMBus Addressing on the Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor ...............................................................90 Pin Listing by Pin Name for the INT-mPGA Package .........................................99 Pin Listing by Pin Number for the INT-mPGA Package ....................................108 Signal Definitions...............................................................................................117 7 Contents This page is intentionally left blank. 8 Datasheet Contents Revision History Revision -001 Datasheet Description Initial public release Date November 2002 9 Contents This page is intentionally left blank. 10 Datasheet Introduction Introduction 1 The Intel(R) XeonTM processor MP with up to 2-MB L3 cache on the 0.13 micron process is based on the Intel(R) NetBurstTM microarchitecture, which operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA-32 processors. While based on the Intel NetBurst microarchitecture, it maintains the tradition of compatibility with IA-32 software. The Intel NetBurst microarchitecture features include Hyper Pipelined Technology, a Rapid Execution Engine, a 400 MHz system bus, and an Execution Trace Cache. The Hyper Pipelined Technology doubles the pipeline depth in the processor, allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in one half of the internal core clock period. The 400 MHz system bus is a quad-pumped bus running off a 100 MHz system bus clock making 3.2 GB/sec data transfer rates possible. The Execution Trace Cache is a L1 cache that stores approximately twelve thousand decoded micro-operations, which removes the decoder from the main execution path and increases performance. Improved features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution, Advanced Transfer Cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The Advanced Transfer Cache is a 512-KB, on-die L2 cache with increased bandwidth over previous microarchitectures. The floating point and multi-media units have been improved by making the registers 128 bits wide and adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for doubleprecision floating point, SIMD integer, and memory management. In addition, the Intel Xeon processor MP with up to 2-MB L3 cache includes Hyper-Threading Technology. This new technology delivers two logical processors that can execute different tasks simultaneously using shared hardware resources. As a result, multi-threaded applications will execute on more than one thread per physical processor. This will increasing the performance of system applications. The Intel Xeon processors MP with up to 2-MB L3 Cache are intended for high performance server systems with up to four processors on one bus. The processor is designed for 1-4 way (and beyond) designs. The Intel Xeon processor MP with up to 2-MB L3 cache is available with 1 MB or 2 MB of integrated level 3 (L3) cache. All versions of this processor will include manageability features and are based upon the Intel NetBurst microarchitecture. Components of the manageability features include an OEM EEPROM and Processor Information ROM which are accessed through a SMBus interface and contain information relevant to the particular processor and system in which it is installed. In addition, enhancements have been made to the Machine Check Architecture. The Intel Xeon processor MP with 400 MHz system bus support will be offered only in the Interposer Micro-Pin Grid Array (INT-mPGA) package. These output pins can interface with a thermal sensor device that is placed on the baseboard. The 603-pin socket will accommodate the Intel Xeon processor in the INT-mPGA package. The different processor features are summarized in Table 1. Datasheet 11 Introduction The Intel Xeon processor MP on the 0.13 micron process processor in INT-mPGA package utilize a surface mount ZIF socket with 603 pins. This INT-mPGA package will include the processor die, and a pinned FR4 interposer. This package includes an integrated heat spreader (IHS). As a note of reference, the Intel(R) XeonTM processor with 512-KB L2 cache on the 0.13 micron process in the FC-mPGA2 package contains an extra pin (located at location AE30) compared to the INT-mPGA package. This additional pin serves as a keying mechanism to prevent the FCmPGA2 package from being installed in the 603-pin socket since processors in the FC-mPGA2 package are only supported in the 604-pin socket. Since the additional contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this location. Mechanical components used for attaching thermal solutions to the baseboard should have a high degree of commonality with the thermal solution components enabled for the Intel Xeon processor. Enabled heatsinks and retention mechanisms have been designed with manufacturability as a high priority. Hence, mechanical assembly can be completed from the top of the baseboard. System Bus Frequency SMBus Features Intel(R) NetBurstTM Microarchitecture Intel(R) Hyper-Threading Technology 512 KB 1MB, 2 MB 400 MHz Yes Yes Yes Socket Integrated L3 Cache 1-4 Package L2 Advanced Transfer Cache Intel(R) XeonTM processor MP with up to 2MB L3 cache Feature Table for Intel(R) XeonTM Processor MP on the 0.13 Micron Process # of Supported Symmetric Agents Table 1. INTmPGA 603-pin (603 pins) The Intel Xeon processor MP on the 0.13 micron process uses a scalable system bus protocol referred to as the "system bus" in this document. This processor system bus utilizes a splittransaction, deferred reply protocol similar to that of the P6 processor family system bus, but is not compatible with the P6 processor family system bus. This processor system bus is compatible with the Intel Xeon processor system bus. The system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance. Whereas the P6 processor family transfers data once per bus clock, the Intel Xeon processor MP on the 0.13 micron process processor transfers data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a `double-clocked' or 2X address bus. In addition, the Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 GB/second (3200 MB/sec) with a 400 MHz system bus. Finally, the system bus also introduces transactions that are used to deliver interrupts. Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in the appropriate platform design guide (refer to Section 1.2). 12 Datasheet Introduction 1.1 Terminology A `#' symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the `#' symbol implies that the signal is inverted. For example, D[3:0] = `HLHL' refers to a hex `A', and D[3:0]# = `LHLH' also refers to a hex `A' (H= High logic level, L= Low logic level). "System bus" refers to the interface between the processor, system core logic (the chipset components), and other bus agents. The system bus is a multiprocessing interface to processors, memory, and I/O. For this document, "system bus" is used as the generic term for the "Intel(R) XeonTM processor MP with up to 2-MB L3 cache processor system bus". 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: * 603-Pin Socket - The connector which mates the Intel Xeon processor MP with up to 2-MB L3 Cache in INT-mPGA package to the baseboard. The 603-pin socket is a surface mount technology (SMT), zero insertion force (ZIF) socket utilizing solder ball attachment to the platform. See the 603-Pin Socket Design Guidelines for details regarding this socket. * 604-Pin Socket - The 604-pin socket contains an additional contact to accept the additional keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The 604-pin socket will also accept processors with the INT-mPGA package. Since the additional contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this location. Therefore, the additional keying pin will not require a baseboard via nor a surfacemount pad. * Flip Chip Ball Grid Array (FCBGA) - Microprocessor packaging using "flip chip" design, where the processor is attached to the substrate face-down for better signal integrity, more efficient heat removal and lower inductance. * FC-mPGA2 - Packaging technology with the processor die mounted directly to a micro-Pin Grid Array substrate with an integrated heat spreader (IHS). * Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal solution to the Intel Xeon processor MP with up to 2-MB L3 cache processor. The IHS will come in two sizes for the Intel Xeon processor MP with up to 2-MB L3 cache processor, see Section 4 for specific details. * Interposer - The structure on which the processor core package and I/O pins are mounted. * INT-mPGA - Packaging technology with the processor die on a Flip Chip Ball Grid Array (FC-BGA) core mounted to a pinned interposer with an integrated heat spreader (IHS). * OEM - Original Equipment Manufacturer. * Processor core - The processor's execution engine. All AC timing and signal integrity specifications are to the pads of the processor core. * Processor Information ROM (PIROM) - A memory device located on the Intel Xeon processor MP with up to 2-MB L3 cache processor and the Intel Xeon processor in INTmPGA package, accessible via the SMBus which contains information regarding the processor's features. This device is shared with a scratch EEPROM. The PIROM is Datasheet 13 Introduction programmed during the manufacturing and is write-protected. See Section 6.4 for details on the PIROM. * Retention mechanism - The support components that are mounted through the baseboard to the chassis to provide mechanical retention for the processor and heatsink assembly. * Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) - A memory device located on the Intel Xeon processor MP with up to 2-MB L3 cache processor and the Intel Xeon processor in INT-mPGA package, addressable via the SMBus which can be used by the OEM to store information (e.g., information for system management, etc). See Section 6.4 for details on the Scratch EEPROM. * SMBus - System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system. It is based on the principals of the operation of the I2C two-wire serial bus from Philips Semiconductor. 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Document AP-485, IA-32 Intel(R) Intel(R) Number/Location Processor Identification and the CPUID Instruction 241618 Architecture Software Developer's Manual 1. Volume I: Basic Architecture 245470 2. Volume II: Instruction Set Reference 245471 3. Volume III: System Programming Guide 245472 CK00 Clock Synthesizer/Driver Design Guidelines 249206 VRM 9.1 DC-DC Converter Design Guidelines 298646 Intel(R) XeonTM Processor Multiprocessor Platform Design Guide 250397 Intel(R) XeonTM Processor (MP) Thermal Design Guidelines 298650 603 -Pin Socket Design Guidelines 249672 Intel(R) XeonTM Processor MP Family Enabled Components ProE* Files http://developer.intel.com Intel(R) XeonTM Processor MP Family Enabled Components IGES Files http://developer.intel.com Intel(R) XeonTM Processor MP with 512-KB L2 Cache Core Boundary Scan Descriptor Language (BSDL) Model (V1.1) and Cell Descriptor File (V1.0) http://developer.intel.com ITP 700 Debug Port Design Guide System Management Bus Specification, rev 1.1 Wired for Management 2.0 Design Guide 249679 www.sbs-forum.org/smbus http://developer.intel.com NOTES:. 1. Available electronically on the Intel Developer public website http://developer.intel.com 2. Available electronically on the www.sbs-forum.org/smbus. 14 Datasheet Electrical Specifications Electrical Specifications 2.1 2 System Bus and GTLREF Most Xeon processor family system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. The termination voltage level for the Xeon processor family AGTL+ signals is VCC, the operating voltage of the processor core. This is the same as the previous Intel Xeon processor MP processor. VTT (termination voltage level for the I/O buffers) is identical to VCC on the Intel Xeon processor family. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for the Intel Xeon processor MP on the 0.13 micron process. Because of the speed improvements to data and address busses, signal integrity and platform design methods become more critical than with previous processor families. Design guidelines for the Intel Xeon processor MP on the 0.13 micron process system bus are detailed in the appropriate platform design guide (refer to Section 1.2). The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See Table 14 for GTLREF specifications). Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination can be enabled to control reflections on the transmission line. For middle bus agents, on-die termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for details on ODTEN resistor termination requirements. Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard. See Table 5 for details regarding these signals. The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. The Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Signal Integrity and Package Models are available through your Intel representative. 2.2 Power and Ground Pins For clean on-chip power distribution, Intel Xeon processor MP on the 0.13 micron process processor has 190 VCC (power) and 189 VSS (ground) inputs. All power pins must be connected to the system power plane, while all VSS pins must be connected to the system ground plane. The processor VCC pins must be supplied the voltage determined by the processor VID (Voltage ID) pins. Datasheet 15 Electrical Specifications 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the Intel Xeon processor MP on the 0.13 micron process processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines. 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and the baseboard designer must assure a low interconnect resistance from the regulator (or VRM pins) to the 603-pin socket. Bulk decoupling may be provided on the voltage regulation module (VRM) to meet, in part, the need to handle large current swings. The remaining decoupling is provided on the baseboard. The power delivery path must be capable of delivering enough current while maintaining the required tolerances (defined in Table 7). For further information regarding power delivery, decoupling, and layout guidelines, refer to the appropriate platform design guidelines. 2.3.2 System Bus AGTL+ Decoupling The Intel Xeon processor MP on the 0.13 micron process integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the system bus. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines. 2.4 System Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Intel Xeon processor MP on the 0.13 micron process processor core frequency is a multiple of the BCLK[1:0] frequency. The Intel Xeon processor MP on the 0.13 micron process processor bus ratio multiplier will be set during manufacturing. The default setting will equal the maximum speed for the processor. It will be possible to override this setting using software. This will permit operation at speeds lower than the processor's tested frequency. The BCLK[1:0] inputs directly control the operating speed of the system bus interface. The processor core frequency is configured during Reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can 16 Datasheet Electrical Specifications operate. If lower speeds are desired, the appropriate ratio can be set with software using MSR_EBC_FREQ_GOAL to produce a lower operating speed. For details of operation at core frequencies lower than the maximum rated processor speed. Clock multiplying within the processor is provided by the internal PLL, which requires a constant frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are provided in Table 8 and Table 13, respectively. These specifications must be met while also meeting signal integrity requirements as outlined in Section 3. The Intel Xeon processor MP on the 0.13 micron process processor utilizes a differential clock. Details regarding BCLK[1:0] driver specifications are provided in the CK00 Clock Synthesizer/Driver Design Guidelines. Table 2 contains Intel Xeon processor MP on the 0.13 micron process processor bus fraction ratios and their corresponding core frequencies. Table 2. Core Frequency to System Bus Multiplier Configuration Core Frequency to System Bus Multiplier Configuration Core Frequency 100 MHz BCLK 1/12 1.20 GHz 1/13 1.30 GHz 1/14 1.40 GHz 1/15 1.50 GHz 1/16 1.60 GHz 1/17 1.70 GHz 1/18 1.80 GHz 1/19 1.90 GHz 1/20 2 GHz Notes1,2,3 NOTES: 1. Individual processors operate only at or below the frequency marked on the package. 2. Listed frequencies are not necessarily committed production frequencies. 3. Platforms should support a 400 MHz system bus. 2.4.1 Bus Clock The system bus frequency is set to the maximum supported by the individual processor. BSEL[1:0] are outputs used to select the system bus frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. All system bus agents must operate at the same frequency. Individual processors will only operate at their specified system bus clock frequency. The Intel Xeon processor with a 400 MHz system bus is designed to run on a baseboard with a 100 MHz bus clock. On these baseboards, BSEL[1:0] are both considered `reserved' at the processor socket. No change is required for operation with Intel Xeon processor MP on the 0.13 micron process processors. Operation will default to 100 MHz. See the appropriate platform design guide for further details. Datasheet 17 Electrical Specifications Table 3. 2.5 System Bus Clock Frequency Select Truth Table for BSEL[1:0] BSEL1 BSEL0 Bus Clock Frequency 0 0 100 MHz 0 1 Reserved 1 0 Reserved 1 1 Reserved PLL Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Intel Xeon processor MP on the 0.13 micron process processor. This requirement is identical to that used on the Intel Xeon processors. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system; it degrades external I/O timings as well as internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown in Figure 1. The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 1), is as follows: * * * * < 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements) > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter refer to the appropriate platform design guidelines. Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution Trace < 0.02 VCC Processor interposer "pin" L1/L2 R-Socket R-Trace C Baseboard via that connects filter to VCC plane Socket pin VCCA PLL R-Socket Processor VSSA C R-Socket R-Trace VCCIOPLL L1/L2 18 Datasheet Electrical Specifications Figure 2. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB -0.5 dB forbidden zone -28 dB forbidden zone -34 dB DC 1 Hz fpeak 1 MHz passband 66 MHz fcore high frequency band NOTES: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 2.5.1 Mixing Processors Intel only supports multi-processor combinations that operate with the same system bus frequency, core frequency, VID settings, and cache sizes. Mixing processors operating at different internal clock frequencies is not supported and will not be validated by Intel. Not all operating systems can support multiple processors with mixed frequencies. Intel does not support or validate operation of processors with different cache sizes. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported. Details on CPUID are provided in the Intel Processor Identification and the CPUID Instruction application note. Unlike previous Intel Xeon processors, the Intel Xeon processor with 512-KB L2 cache and the Low Voltage Intel Xeon processor do not sample the pins IGNNE, LINT0, LINT1, and A20M# to establish the core to system bus ratio. Rather, the processor runs at its tested frequency at initial power-on. If the processor needs to run at a lower core frequency, as must be done when a higher speed processor is added to a system that contains a lower frequency processor, the system BIOS writes a value in the MSR_EBC_FREQ_GOAL (Ratio Configuration Register), and asserts a system reset to effect the change in the core to system bus ratio. On previous platforms, the second reset has not been required, so the impact of this second reset needs to be comprehended by the system designer. Datasheet 19 Electrical Specifications 2.6 Voltage Identification The VID specification for the Intel Xeon processor MP on the 0.13 micron process processor is supported by the VRM 9.1 DC-DC Converter Design Guidelines. The minimum voltage is provided in Table 7, and changes with processor frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator design can work with all supported processor frequencies. Note that the VID pins will drive valid and correct logic levels when the Intel Xeon processor MP on the 0.13 micron process processor is provided with a valid voltage applied to the SM_VCC pins. SM_VCC must be correct and stable prior to enabling the output of the VRM that supplies VCC. Similarly, the output of the VRM must be disabled before SM_VCC becomes invalid. Refer to Figure 18 for details. The Intel Xeon processor MP on the 0.13 micron process processor uses five voltage identification pins, VID[4:0], to support automatic selection of processor voltages. Table 4 specifies the voltage level corresponding to the state of VID[4:0]. A `1' in this table refers to a high voltage and a `0' refers to low voltage level. If the processor socket is empty (VID[4:0] = 11111), or the VRM cannot supply the voltage that is requested, this VRM must disable itself. See the VRM 9.1 DC-DC Converter Design Guidelines. 20 Datasheet Electrical Specifications Table 4. Voltage Identification Definition Processor Pins 2.6.1 VID4 VID3 VID2 VID1 VID0 VCC_VID (V) 1 1 1 1 1 VRM output off 1 1 1 1 0 1.100 1 1 1 0 1 1.125 1 1 1 0 0 1.150 1 1 0 1 1 1.175 1 1 0 1 0 1.200 1 1 0 0 1 1.225 1 1 0 0 0 1.250 1 0 1 1 1 1.275 1 0 1 1 0 1.300 1 0 1 0 1 1.325 1 0 1 0 0 1.350 1 0 0 1 1 1.375 1 0 0 1 0 1.400 1 0 0 0 1 1.425 1 0 0 0 0 1.450 0 1 1 1 1 1.475 0 1 1 1 0 1.500 0 1 1 0 1 1.525 0 1 1 0 0 1.550 0 1 0 1 1 1.575 0 1 0 1 0 1.600 0 1 0 0 1 1.625 0 1 0 0 0 1.650 0 0 1 1 1 1.675 0 0 1 1 0 1.700 0 0 1 0 1 1.725 0 0 1 0 0 1.750 0 0 0 1 1 1.775 0 0 0 1 0 1.800 0 0 0 0 1 1.825 0 0 0 0 0 1.850 Mixing Processors of Different Voltages Mixing processors operating with different VID settings (voltages) is not supported and will not be validated by Intel. Datasheet 21 Electrical Specifications 2.7 Reserved or Unused Pins All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 9 for a pin listing of the processor and for the location of all Reserved pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. In a system level design, on-die termination has been included on the Intel Xeon processor MP on the 0.13 micron process processor to allow signals to be terminated within the processor silicon. Most unused AGTL+ inputs should be left as no connects, as AGTL+ termination is provided on the processor silicon. However, see Table 4 for details on AGTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value for the on-die termination resistors (RTT). See Table 14. TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and all used outputs must be terminated on the baseboard. Unused outputs may be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which matches the trace impedance within a range of 10 . TESTHI[3:0] and TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if desired. However, utilization of boundary scan test will not be functional if these pins are connected together. TESTHI4 must always be pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for TESTHI[6:0] pins should have a resistance value within 20% of the impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 , then a value between 40 and 60 should be used. The TESTHI[6:0] termination recommendations provided in the Intel(R) XeonTM Processor MP Datasheet are still suitable for the Intel Xeon processor MP on the 0.13 micron process processor. However, Intel recommends new designs or designs undergoing design updates follow the trace impedance matching termination guidelines given in this section. 2.8 System Bus Signal Groups In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as 22 Datasheet Electrical Specifications the rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 5 identifies which signals are common clock, source synchronous and asynchronous. Table 5. System Bus Signal Groups Signal Group Signals 1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, BR[3:1]#3, DEFER#, RESET#3, RS[2:0]#, RSP#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#6, BNR#6, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#6, HITM#6, LOCK#, MCERR#6 Signals Associated Strobe 5 AGTL+ Source Synchronous I/O AGTL+ Strobes Synchronous to assoc. strobe REQ[4:0]#,A[16:3]# ADSTB0# A[35:17]#4 ADSTB1# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3# Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# Asynchronous GTL+ Input 3 Asynchronous A20M#4, IGNNE#4, INIT#5, LINT0/INTR4, LINT1/NMI4, SMI#5, SLP#, STPCLK# Asynchronous GTL+ Output 3 Asynchronous FERR#, IERR#, THERMTRIP#, PROCHOT# System Bus Clock Clock BCLK1, BCLK0 Synchronous to TCK TCK, TDI, TMS, TRST# TAP Input 2 TAP Output 2 SMBus Interface 7 Power/Other Synchronous to TCK TDO Synchronous to SM_CLK SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT, SM_CLK, SM_ALERT#, SM_WP Power/Other BSEL[1:0], COMP[1:0], GTLREF, ODTEN, PWRGOOD, Reserved, SKTOCC#, TESTHI[6:0],VID[4:0], VCC, SM_VCC8, VCCA , VCCIOPLL, VSSA, , VSS, VCCSENSE, VSSSENSE NOTES: 1. Refer to Section 9.2 for signal descriptions. 2. These signal groups are not terminated by the processor. 3. These signals do not have on-die termination. Refer to corresponding platform design guidelines for termination requirements. 4. Note that Reset initialization function of these pins is now a software function on the Intel Xeon processor MP on the 0.13 micron process processor. 5. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration options. See Section 6.1 for details. 6. These signals may be driven simultaneously by multiple agents (wired-or). 7. These signals are not terminated by the processor's on-die termination. However, some signals in this group include termination on the processor interposer. See Section 6.4 for details. 8. SM_Vcc is required for correct operation of the Intel Xeon processor MP on the 0.13 micron process processors VID logic. Refer to Figure 18 for details. Datasheet 23 Electrical Specifications 2.9 Asynchronous GTL+ Signals The Intel Xeon processor MP on the 0.13 micron process processor does not utilize CMOS voltage levels on any signals that connect to the processor silicon. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the same DC requirements as AGTL+ signals, however the outputs are not driven high (during the logical 0-to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous GTL+ signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them. See Table 11 and Table 18 for the DC and AC specifications for the asynchronous GTL+ signal groups. SMBus signals are derived from components mounted on the processor interposer along with the processor silicon. The required SM_VCC for these signals is 3.3 V. See Section 6.4 for further details. 2.10 Maximum Ratings Table 6 lists the processor's maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. Table 6. Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes TSTORAGE Processor storage temperature -40 85 C 2 VCC Any processor supply voltage with respect to VSS -0.3 1.75 V 1 VinAGTL+ AGTL+ buffer DC input voltage with respect to VSS -0.1 1.75 V VinGTL+ Async GTL+ buffer DC input voltage with respect to Vss -0.1 1.75 V VinSMBus SMBus buffer DC input voltage with respect to Vss -0.3 6.0 V IVID Max VID pin current 5 mA NOTES: 1. This rating applies to any pin of the processor. 2. Contact Intel for storage requirements in excess of one year. 24 Datasheet Electrical Specifications 2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See for the Intel Xeon processor MP on the 0.13 micron process processor pin listings and Section 9.2 for the signal definitions. The voltage and current specifications for all versions of the processor are detailed in Table 6. For platform planning refer to Figure 3. Notice that the graphs include Thermal Design Power (TDP) associated with the maximum current levels. The DC specifications for the AGTL+ signals are listed in Table 9. The system bus clock signal group and the SMBus interface signal group are detailed in Table 8 and Table 12, respectively. The DC specifications for these signal groups are listed in Table 12. Table 7 through Table 11 list the DC specifications for the Intel Xeon processor MP on the 0.13 micron process processor and are valid only while meeting specifications for case temperature (TCASE as specified inSection 5), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. ) Table 7. Symbol Voltage and Current Specifications Notes 1 Parameter Core Freq Min Typ Max VID Unit VCC VCC for processor core with 2-MB L3 cache 2 GHz 1.333 Refer to Figure 3 1.449 1.475 V VCC VCC for processor core with 1-MB L3 cache 1.50 GHz 1.345 1.336 Refer to Figure 3 1.453 1.90 GHz 1.475 V SMBus supply voltage All frequencies 3.135 3.30 3.465 V 8 ICC ICC for processor core with 2-MB L3 cache 2 GHz 44.8 A 4, 5 ICC ICC for processor core with 1-MB L3 Cache 1.50 GHz 37.2 1.90 GHz 43.1 ICC_PLL ICC for PLL power pins All frequencies 60 mA 9 ICC_SMBus Icc for SMBus power supply All frequencies 122.5 mA 8 ICC_GTLREF ICC for GTLREF pins All frequencies 15 uA 10 ICC Stop-Grant All frequencies 25 A 6 Low Voltage Intel Xeon processor All frequencies 10.1 A 6 ICC TCC active All frequencies 18.6 A 7 SM_VCC ISGnt/ISLP 100.0 1.450 A 2, 3, 4,11,12 2, 3, 4,11,12 2, 3, 4,11,12 4, 5 4, 5 ICC Stop-Grant for ISGnt/ISLP ITCC NOTES: 1. Unless otherwise noted, all specifications in this table are based on the latest silicon measurements available at the time of publication. 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.6 and Table 4 for more information. 3. The voltage specification requirements are measured across vias on the platform for the VCC_SENSE and VSS_SENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 mohm minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. Datasheet 25 Electrical Specifications 4. Refer to Figure 3 as appropriate for the particular Intel Xeon processor MP on the 0.13 micron process processor of interest. The processor should not be subjected to any static VCC level that exceeds the VCC_MAX associated with any particular current. Moreover, Vcc should never exceed VCC_VID. Failure to adhere to this specification can shorten the processor lifetime. 5. Maximum current is defined at VCC_max. 6. The current specified is also for AutoHALT State. 7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT#. 8. SM_Vcc/VID_Vcc is required for correct operation of the Intel Xeon processor MP on the 0.13 micron process processor VID and BSEL logic. Refer to Figure 18 for details. 9. This specification applies to the PLL power pins VCCA and VCCIOPLL. See Section 2.4.1 for details. This parameter is based on design characterization and is not tested 10.This specification applies to each GTLREF pin. 11. The loadlines specify voltage limits at the die measured at VCC_sense and Vss_sense pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. 12.Adherence to this loadline specification as shown in Figure 3 is required to ensure reliable processor operations. Figure 3. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Voltage-Current Projections Maximum Processor Voltage (VDC) 1.480 1.475 1.470 1.465 1.460 1.455 1.450 1.445 1.440 1.435 1.430 0 10 20 30 40 50 60 70 Processor Current (A) 26 Datasheet Electrical Specifications Table 8. System Bus Differential BCLK DC Specifications Notes Symbol Parameter Min Typ Max Unit Figure VL Input Low Voltage -0.150 0.000 N/A V 6 VH Input High Voltage 0.660 0.710 0.850 V 6 VCROSS( Absolute Crossing Point 0.250 N/A 0.550 V 6, 7 2,8 V 6, 7 2,3,8,9 abs) 0.250 + 0.550 + 1 rel) Relative Crossing Point VCROS Range of Crossing Points N/A N/A 0.140 V 6, 7 2,10 Overshoot N/A N/A VH + 0.3 V 6 4 VCROSS( S VOV 0.5(VHavg - 0.710) N/A 0.5(VHavg - 0.710) VUS Undershoot -0.300 N/A N/A V 6 5 VRBM Ringback Margin 0.200 N/A N/A V 6 6 VTM Threshold Margin VCROSS - 0.100 N/A VCROSS + 0.100 V 6 7 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using "Vtop" on Agilent scopes and "High" on Tektronix scopes. 10.VCROSS is defined as the total variation of all crossing voltages as defined in note 2. Datasheet 27 Electrical Specifications Table 9. AGTL+ Signal Group DC Specifications Symbol VIH Notes Parameter Min Max Unit Input High Voltage 1.10 * GTLREF VCC V 2, 4, 5 1,8 VIL Input Low Voltage 0.0 0.90 * GTLREF V 3, 5 VOH Output High Voltage N/A VCC V 4, 5 IOL Output Low Current N/A 50 mA 5 IHI Pin Leakage High N/A 100 A 8 ILO Pin Leakage Low N/A 500 A 7 RON Buffer On Resistance 7 11 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 3. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3. 5. The VCC referred to in these specifications refers to instantaneous VCC. 6. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 4, with Rtt enabled. 7. Leakage to Vcc with Pin held at 300 mV. 8. Leakage to Vss with pin held at Vcc. Table 10. PWRGOOD and TAP Signal Group DC Specifications Parameter Min Max Unit Notes 1,2 VHYS Input Hysteresis 200 300 mV 7 VT+ Input Low to High Threshold Voltage 1/2*(Vcc + VHYS_MIN) 1/2*(Vcc + VHYS_MAX) V 4 VT- Input High to Low Threshold Voltage 1/2*(Vcc - VHYS_MAX) 1/2*(Vcc - VHYS_MIN) V 4 VOH Output High Voltage N/A VCC V 3,4 IOL Output Low Current 40 mA 5,6 Symbol IHI Pin Leakage High N/A 100 A 9 ILO Pin Leakage Low N/A 500 A 8 RON Buffer On Resistance 8.75 13.75 NOTES:. 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. All outputs are open drain 3. TAP signal group must meet the system signal quality specification in Section 3. 4. The Vcc referred to in these specifications refers to instantaneous Vcc. 5. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 6. VOL_MAX of 0.300 V is guaranteed when driving a test load. 7. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc, for all TAP inputs. 8. Leakage to Vcc with Pin held at 300 mV. 9. Leakage to Vss with pin held at Vcc. 28 Datasheet Electrical Specifications Table 11. Asynchronous GTL+ Signal Group DC Specifications Symbol VIH Parameter Min Max Unit Input High Voltage 1.10 * GTLREF VCC V Notes 1, 6 3, 5, 6 VIL Input Low Voltage 0.0 0.90 * GTLREF V 4 VOH Output High Voltage N/A VCC V 2, 5, 6 IOL Output Low Current 50 mA 7, 8 IHI Pin Leakage High N/A 100 A 10 ILO Pin Leakage Low N/A 500 A 9 RON Buffer On Resistance 7 11 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. All outputs are open drain 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 5. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3. 6. The VCC referred to in these specifications refers to instantaneous VCC. 7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 8. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 4, with Rtt enabled. 9. Leakage to Vcc with Pin held at 300 mV. 10. Leakage to Vss with pin held at Vcc. Table 12. SMBus Signal Group DC Specifications Symbol Parameter Min Max Unit VIL Input Low Voltage -0.30 0.30 * SM_VCC V VIH Input High Voltage 0.70 * SM_VCC 3.465 V VOL Output Low Voltage 0 0.400 V IOL Output Low Current N/A 3.0 mA ILI Input Leakage Current N/A 10 A ILO Output Leakage Current N/A 10 A CSMB SMBus Pin Capacitance 15.0 pF Notes 1, 2, 3 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. These parameters are based on design characterization and are not tested. 3. All DC specifications for the SMBus signal group are measured at the processor pins. 4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals. Datasheet 29 Electrical Specifications Table 13. BSEL[1:0] and VID[4:0] DC Specifications Symbol Parameter Min Max Unit Notes1 Ron (BSEL) Buffer On Resistance 9.2 14.3 2 Ron (VID) Buffer On Resistance 7.8 12.8 2 IHI Pin Leakage Hi N/A 100 A 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to Vss with pin held at 2.50 V. 2.12 AGTL+ System Bus Specifications Routing topologies are dependent on the number of processors supported and the chipset used in the design. Please refer to the appropriate platform design guidelines. In most cases, termination resistors are not required as these are integrated into the processor. See Table 5 for details on which AGTL+ signals do not include on-die termination. The termination resistors are enabled or disabled through the ODTEN pin. To enable termination, this pin should be pulled up to VCC through a resistor and to disable termination, this pin should be pulled down to VSS through a resistor. For optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should have a resistance value within 20% of the impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 , then a value between 40 and 60 should be used. The processor's on-die termination must be enabled for the end agent only. Please refer to Table 12 for termination resistor values. For more details on platform design see the appropriate platform design guidelines. Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF. Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be generated on the baseboard using high precision voltage divider circuits. It is important that the baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on platform design see the appropriate platform design guidelines. 30 Datasheet Electrical Specifications Table 14. AGTL+ Bus Voltage Definitions Min Typ Max Units Notes 1 Bus Reference Voltage 2/3 VCC - 2% 2/3 VCC 2/3 VCC + 2% V 2, 3, 6 Bus Reference Voltage 0.63*VCC - 2% 0.63*VCC 0.63*VCC + 2% V 2, 3, 6 RTT Termination Resistance 36 41 46 4 RTT Termination Resistance 45 50 55 4, 8 COMP Resistance 42.77 43.2 43.63 5, 7 COMP Resistance 49.55 50 50.45 5, 7, 8 Symbol GTLREF GTLREF New Design New Design COMP[1:0] COMP[1:0] New Design Parameter NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of VCC. 3. GTLREF is generated from VCC on the baseboard by a voltage divider of 1% resistors. Refer to the appropriate platform design guidelines for implementation details. 4. RTT is the on-die termination resistance measured from VCC to 1/3 VCC at the AGTL+ output driver. 5. COMP resistors are pull downs to VSS provided on the baseboard with 1% tolerance. See the appropriate platform design guidelines for implementation details. 6. The VCC referred to in these specifications refers to instantaneous VCC. 7. COMP value may vary with chipset. 8. The values for RTT and COMP noted as `New Designs' apply to designs that will not support Intel Xeon processor MP (previously code named Foster MP). These designs are optimized for the Intel Xeon processor MP on the 0.13 micron process processor. 2.13 System Bus AC Specifications The processor system bus timings specified in this section are defined at the processor core (pads). See Section 9 for the Intel Xeon processor MP on the 0.13 micron process processor pin listing and signal definitions. Table 15 through Table 20 list the AC specifications associated with the processor system bus. Specific parameters for a 400 MHz system bus are listed in these tables. All AGTL+ timings are referenced to GTLREF for both `0' and `1' logic levels unless otherwise specified. AGTL+ layout guidelines are also available in the appropriate platform design guidelines. Note: Datasheet Care should be taken to read all notes associated with a particular timing parameter 31 Electrical Specifications Table 15. System Bus Differential Clock AC Specifications T# Parameter Min Nom System Bus Clock Frequency (400 MHz) Unit Figure 100.0 MHz 10.00 10.20 ns T2: BCLK[1:0] Period Stability N/A 150 ps T3: TPH BCLK[1:0] Pulse High Time (400 MHz) 3.94 5 6.12 ns 6 5 T1: BCLK[1:0] Period (400 MHz) . Max Notes1 2 6 3 4, 5 T4: TPL BCLK[1:0] Pulse Low Time (400 MHz) 3.94 6.12 ns 6 T5: BCLK[1:0] Rise Time 175 700 ps 6 6 T6: BCLK[1:0] Fall Time 175 700 ps 6 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. The Intel Xeon processor MP on the 0.13 micron process processor core clock frequency is derived from BCLK. The bus clock to processor core clock ratio is determined during initialization as described in Section 2.4. Table 2 shows the supported ratios for the Intel Xeon processor MP on the 0.13 micron process processor. 3. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). 4. For the clock jitter specification, refer to either the CK00 Clock Synthesizer/Driver Design Guidelines or the CK408 Clock Synthesizer/Driver Design Guidelines or the CK408B Clock Synthesizer/Driver Design Guidelines. 5. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 6. Slew rate is measured between the 35% and 65% points of the clock swing (VL and VH). Table 16. System Bus Common Clock AC Specifications Min Max Unit Figure Notes 1,2,3 T10: Common Clock Output Valid Delay 0.12 1.27 ns 8 4 T11: Common Clock Input Setup Time 0.65 N/A ns 8 5 T12: Common Clock Input Hold Time 0.40 N/A ns 8 5 T13: RESET# Pulse Width 1.00 10.00 ms 11 6, 7, 8 T# Parameter NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. Not 100% tested. Specified by design characterization. 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core. 4. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF at 2/3 VCC 2%. 5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ ns to 4.0V/ns. 6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. 7. This should be measured after VCC and BCLK[1:0] become stable. 8. Maximum specification applies only while PWRGOOD is asserted. 32 Datasheet Electrical Specifications . Table 17. System Bus Source Synchronous AC Specifications Min Max Unit Figure Notes1,2,3,4 T20: Source Sync. Output Valid Delay (first data/ address only) 0.20 1.30 ns 9, 10 5 T21: TVBD Source Sync. Data Output Valid Before Data Strobe (400 MHz) 0.85 ns 10 5, 8 T22: TVAD Source Sync. Data Output Valid After Data Strobe (400 MHz) 0.85 ns 10 5, 8 T23: TVBA Source Sync. Address Output Valid Before Address Strobe (400 MHz) 1.88 ns 9 5, 8 T24: TVAA Source Sync. Address Output Valid After Address Strobe (400 MHz) 1.88 ns 9 5, 9 T# Parameter T25: TSUSS Source Sync. Input Setup Time 0.21 ns 9, 10 6 T26: THSS Source Sync. Input Hold Time 0.21 ns 9, 10 6 T27: TSUCC Source Sync. Input Setup Time to BCLK 0.65 ns 9, 10 7 T28: TFASS First Address Strobe to Second Address Strobe 1/2 BCLKs 9 10, 14 T29: TFDSS: First Data Strobe to Subsequent Strobes n/4 BCLKs 10 11, 12, 14 13 T30: Data Strobe `n' (DSTBN#) Output Valid Delay (400 MHz) 8.80 10.20 ns 10 T31: Address Strobe Output Valid Delay (400 MHz) 2.27 4.23 ns 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. Not 100% tested. Specified by design characterization. 3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core. 4. Unless otherwise noted, these specifications apply to both data and address timings. 5. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF at 2/3 VCC 2%. 6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ns to 4.0 V/ns. 7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe. 8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications. 9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications. 10.The rising edge of ADSTB# must come approximately 1/2 BCLK period after the falling edge of ADSTB#. 11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively. 12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period after the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must come approximately 3/4 BCLK period after the first falling edge of DSTBp#. 13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe. 14.This specification reflects a typical value, not a minimum or maximum. Datasheet 33 Electrical Specifications . Table 18. Miscellaneous Signals AC Specifications T# Parameter Min Max Unit T35: Async GTL+ input pulse width 2 N/A BCLKs T36: PWRGOOD to RESET# de-assertion time 1 10 T37: PWRGOOD inactive pulse width 10 N/A T38: PROCHOT# pulse width 500 T39: THERMTRIP# to Vcc Removal T40: FERR# Valid Delay from STPCLK# deassertion 0 Figure Notes ms 12 1, 2, 3, 4 BCLKs 12 1, 2, 3, 4, 5 s 14 1, 2, 3, 4, 6 0.5 s 18 5 BCLKs 19 1, 2, 3, 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage (VCROSS). All Asynchronous GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge at 0.5*VCC. 3. These signals may be driven asynchronously. 4. Refer to Section 6.2 for additional timing requirements for entering and leaving low power states. 5. Refer to the PWRGOOD signal definition in Section 9.2 for more detail information on behavior of the signal. 6. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion of PROCHOT# for the processor to complete current instruction execution. Table 19. System Bus AC Specifications (Reset Conditions) T# Parameter Min T45: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#) Setup Time 4 T46: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#) Hold Time 2 Max 20 Unit Figure Notes BCLKs 11 1 BCLKs 11 2 NOTES: 1. Before the de-assertion of RESET# 2. After the clock that de-asserts RESET# . 34 Datasheet Electrical Specifications Table 20. TAP Signal Group AC Specifications T# Parameter T55: TCK Period Min Max 60.0 Unit Figure ns 5 Notes 1,2,3,9 T56: TCK Rise Time 9.5 ns 5 4 T57: TCK Fall Time 9.5 ns 5 4 T58: TMS, TDI Rise Time 8.5 ns 5 4 T59: TMS, TDI Fall Time 8.5 ns 5 4 T61: TDI, TMS Setup Time 0 ns 13 5, 7 T62: TDI, TMS Hold Time 3.0 ns 13 5,7 T63: TDO Clock to Output Delay 0.5 ns 13 6 T64: TRST# Assert Time 2.0 TTCK 14 8 3.5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. Not 100% tested. Specified by design characterization. 3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 * Vcc at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at the 0.5 * Vcc processor pins. 4. Rise and fall times are measured from the 20% to 80% points of the signal swing. 5. Referenced to the rising edge of TCK. 6. Referenced to the falling edge of TCK. 7. Specification for a minimum swing defined between TAP 20% to 80%. This assumes a minimum edge rate of 0.5 V/ns 8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor. 9. It is recommended that TMS be asserted while TRST# is being deasserted. . Table 21. SMBus Signal Group AC Specifications T# Parameter T70: SM_CLK Frequency Min Max Unit 10 100 KHz Figure Notes1,2,3 T71: SM_CLK Period 10 100 s T72: SM_CLK High Time 4.0 N/A s 16 T73: SM_CLK Low Time 4.7 N/A s 16 T74: SMBus Rise Time 0.02 1.0 s 16 5 T75: SMBus Fall Time 0.02 0.3 s 16 5 T76: SMBus Output Valid Delay 0.1 4.5 s 17 T77: SMBus Input Setup Time 250 N/A ns 16 T78: SMBus Input Hold Time 300 N/A ns 16 T79: Bus Free Time 4.7 N/A s 16 T80: Hold Time after Repeated Start Condition 4.0 N/A s 16 T81: Repeated Start Condition Setup Time 4.7 N/A s 16 T82: Stop Condition Setup Time 4.0 N/A s 16 4, 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. These parameters are based on design characterization and are not tested. 3. All AC timings for the SMBus signals are referenced at VIL_MAX or VIH_MIN and measured at the processor pins. Refer to Figure 16. 4. Minimum time allowed between request cycles. Datasheet 35 Electrical Specifications 5. Rise time is measured from (VIL_MAX - 0.15 V) to (VIH_MIN + 0.15 V). Fall time is measured from (0.9 * SM_VCC) to (VIL_MAX - 0.15V). DC parameters are specified in Table 12. 6. Following a write transaction, an internal device write cycle time of 10ms must be allowed before starting the next transaction. 2.14 Processor AC Timing Waveforms The following figures are used in conjunction with the AC timing tables, Table 14 through Table 21. Note: For Figure 4 through Figure 19, the following apply: 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core (pads). 2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core (pads). 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads). 4. All AC Timing for the TAP signals are referenced to the TCK signal at 0.5 * Vcc at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at the 0.5 * Vcc at the processor core (pads). 5. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_VCC at the processor pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc) are referenced at VIL_MAX or VIL_MIN at the processor pins. Figure 4. Electrical Test Circuit Vtt Vtt Rload = 50 ohms Zo = 50 ohms, d=420mils, So=169ps/in L = 2.4nH C = 1.2pF AC Timings specified at pad. 36 Datasheet Electrical Specifications Figure 5. TCK Clock Waveform tr *V2 CLK *V3 *V1 tf tp Tr = T56, T58 (Rise Time) Tf = T57, T59 (Fall Time) T p = T55 (Period) V1, V2: For rise and fall times, TCK is measured between 20% to 80%points on the waveform V3: TCK is referenced to 0.5 * Vcc Figure 6. Differential Clock Waveform Tph Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tpl Tp Tp = T1 (BCLK[1:0] period) T2 = BCLK[1:0] Period stability (not shown) Tph =T3 (BCLK[1:0] pulse high time) Tpl = T4 (BCLK[1:0] pulse low time) T5 = BCLK[1:0] rise time through the threshold region T6 = BCLK[1:0] fall time through the threshold region Datasheet 37 Electrical Specifications Figure 7. Differential Clock Crosspoint Specification Crosspoint Specification 650 600 Crossing CrossingPoint Point(mV) (V) 550 550 mV 500 450 550 + 0.5 (VHavg - 710) 400 250 + 0.5 (VHavg - 710) 350 300 250 250 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg Vhavg(V) (mV) Figure 8. System Bus Common Clock Valid Delay Timing Waveform T0 T1 T2 BCLK1 BCLK0 Common Clock Signal (@ driver) TP valid valid TQ Common Clock Signal (@ receiver) TR valid TP = T10: Common Clock Output Valid Delay TQ = T11: Common Clock Input Setup TR = T12: Common Clock Input Hold Time 38 Datasheet Electrical Specifications Figure 9. System Bus Source Synchronous 2X (Address) Timing Waveform 1/4 BCLK 1/2 BCLK T1 3/4 BCLK T2 BCLK1 BCLK0 TP ADSTB# (@ driver) TR TH A# (@ driver) valid TJ TH TJ valid TS ADSTB# (@ receiver) TK A# (@ receiver) valid valid TN TM TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Input Setup to BCLK TM = T26: Source Sync. Input Hold Time TN = T25: Source Sync. Input Setup Time TP = T28: First Address Strobe to Second Address Strobe TS = T20: Source Sync. Output Valid Delay TR = T31: Address Strobe Output Valid Delay Datasheet 39 Electrical Specifications Figure 10. System Bus Source Synchronous 4X (Data) Timing Waveform T0 1/4 BCLK BCLK1 1/2 BCLK T1 3/4 BCLK T2 BCLK0 DSTBp# (@ driver) TH DSTBn# (@ driver) TA TB TA TD D# (@ driver) DSTBp# (@ receiver) TJ DSTBn# (@ receiver) TC D# (@ receiver) TE TG TE TG TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync. Setup Time to BCLK TD = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay TE = T25: Source Sync. Input Setup Time TG = T26: Source Sync. Input Hold Time TH = T29: First Data Strobe to Subsequent Strobes TJ = T20: Source Sync. Data Output Valid Delay 40 Datasheet Electrical Specifications Figure 11. System Bus Reset and Configuration Timing Waveform Tu Tt RESET# Tv Tx Configuration (A[31:3]#, BR0#, SMI#, INIT#) Safe Valid Tw Configuration (A[31:3]#, BR0#, SMI#, INIT#) Valid Tv = T13 (RESET# Pluse Width) Tw = T45 (Reset Configuration Signals (A[14:5]#, BR0#, SMI#, INIT#) Setup Time) Tx = T46 (Reset Configuration signals (A[14:5]#, BR0#, SMI#, INIT#) Hold Time) Figure 12. Power-On Reset and Configuration Timing Waveform BLCK VCC PWRGOOD T a T b RESET# Ta = T37 (PWRGOOD Inactive Pluse Width) Tb = T36 (PWRGOOD to RESET# de-assertion time) NOTES: 1. The function of configuration signals (A20M#, IGNNE#, LINT[1:0]) are illustrated for legacy designs only. Setting the bus ratio for Intel Xeon processor MP on the 0.13 micron process processor is software controlled. Datasheet 41 Electrical Specifications Figure 13. TAP Valid Delay Timing Waveform V TCK Ts Tx Th Signal V Valid Tx = T63 (TDO Clock to Output Delay) Ts = T61 (TDI, TMS Setup Time) Th = T62 (TDI, TMS Hold Time) V = 0.5 *Vcc Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T = T64 (TRST# Pulse Width), V = 0.5 * Vcc q T38 (PROCHOT# Pulse Width), V=GTLREF Figure 15. THERMTRIP# to Vcc Timing T39 THERMTRIP# Vcc T39 < 0.5 seconds NOTE: THERMTRIP# is undefined when RESET is active. 42 Datasheet Electrical Specifications Figure 16. SMBus Timing Waveform t LOW t t R F t HD;STA Clk t HD;STA t t HD;DAT t SU;DAT HIGH t SU;STA t SU;STO Data t BUF P STOP S S START START t LOW = T73 t HD;STA = T80 t SU;STA = T81 t HIGH = T72 t HD;DAT = T78 t SU;STD = T82 tR = T74 t BUF = T75 t SU;DAT = T77 tF P STOP = T79 Figure 17. SMBus Valid Delay Timing Waveform SM_CLK TAA DATA VALID SM_DAT DATA OUTPUT TAA = T76 Datasheet 43 Electrical Specifications Figure 18. Example 3.3 Volt/SM_VCC Sequencing T0=95% 3.3 volt level Power UP 3.3 VDC/SM_VCC > T0 + 100 ms PWR_OK / OUTEN VID[4:0] T0 + 1 mS BSEL[1:0] T0 + 1 mS VRM PWRGD > 10 ms Processor PWRGOOD Processor RESET# 1 ms<T 36<10 ms VID[4:0] PWRGD VRM PWRGOOD OUTEN CPU PWR_OK SM_VCC Power Supply 3.3 VDC 95% 3.3 volt level 3.3 VDC/SM_VCC Power Down PWROK Power Down Warning > 1 ms 44 Datasheet Electrical Specifications Figure 19. FERR#/PBE# Valid Delay Timing BCLK system bus SG Ack STPCLK# FERR#/ PBE# Ta FERR# undefined PBE# undefined FERR# Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion) Note: FERR#/PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE# signal is driven. FERR# is driven at all other times. Datasheet 45 Electrical Specifications This page is intentionally left blank. 46 Datasheet System Bus Signal Quality Specifications System Bus Signal Quality Specifications 3 Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines. Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and undershoot can degrade timing due to the build up of inter-symbol interference (ISI) effects. For these reasons, it is crucial that the designer assure acceptable signal quality across all systematic variations encountered in volume manufacturing. This section documents signal quality metrics used to derive topology and routing guidelines through simulation and all specifications are specified at the processor core (pad measurements). Specifications for signal quality are for measurements at the processor core only and are only observable through simulation. The same is true for all system bus AC timing specifications in Section 2.13. 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines Table 22 describes the signal quality specifications at the processor pads for the processor system bus clock (BCLK) signals. Figure 20 describes the signal quality waveform for the system bus clock at the processor pads. Table 22. BCLK Signal Quality Specifications Parameter Min Max Unit Figure BCLK[1:0] Overshoot N/A 0.30 V 20 BCLK[1:0] Undershoot N/A 0.30 V 20 BCLK[1:0] Ringback Margin 0.20 N/A V 20 BCLK[1:0] Threshold Region N/A 0.10 V 20 Notes1 2 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value. Datasheet 47 System Bus Signal Quality Specifications Figure 20. BCLK[1:0] Signal Integrity Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot 3.2 System Bus Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in the appropriate platform design guidelines. Table 23 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor pads. Intel Xeon processor MP on the 0.13 micron process processor maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 25 through Table 28. Figure 21 shows the system bus ringback tolerance for low-to-high transitions and Figure 22 shows ringback tolerance for high-to-low transitions. Table 23. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers Signal Group Transition Maximum Ringback (with Input Diodes Present) AGTL+, Asynch GTL+ LH GTLREF + 0.100*GTLREF V 21 1, 2, 3, 4, 5, 6 AGTL+, Asynch GTL+ HL GTLREF - 0.100*GTLREF V 22 1, 2, 3, 4, 5, 6 Unit Figure Notes NOTES: 1. All signal integrity specifications are measured at the processor core (pads). 2. Unless otherwise noted, all specifications in this table apply to all Intel Xeon processor MP on the 0.13 micron process processor frequencies and cache sizes. 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns at the receiver. 4. All values specified by design characterization. 5. Please see Section 3.1 for maximum allowable overshoot. 6. Intel recommends simulations not exceed a ringback value of GTLREF 0.100*GTLREF to allow margin for other sources of system noise. 48 Datasheet System Bus Signal Quality Specifications Table 24. Ringback Specifications for PWRGOOD Input and TAP Buffers Signal Group Transition Maximum Ringback (with Input Diodes Present) Threshold Unit Figure Notes TAP and PWRGOOD LH VT+(max) TO VT-(max) VT+(max) V 23 1, 2, 3, 4, 5 TAP and PWRGOOD HL VT-(min) TO VT+(min) VT-(min) V 24 1, 2, 3, 4, 5 NOTES: 1. All signal integrity specifications are measured at the processor core (pads). 2. Unless otherwise noted, all specifications in this table apply to all Intel Xeon processor MP on the 0.13 micron process processor frequencies and cache sizes 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns. 4. All values specified by design characterization. 5. Please see Section 3.1 for maximum allowable overshoot. Figure 21. Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers VCC +10% GTLREF -10% Noise Margin VSS Figure 22. High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers V CC +10% GTLREF -10% Noise Margin V SS Datasheet 49 System Bus Signal Quality Specifications Figure 23. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.5 * Vcc Vt- (max) Allowable Ringback Vss 50 Datasheet System Bus Signal Quality Specifications Figure 24. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0. Vss 3.3 System Bus Signal Quality Specifications and Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The overshoot/undershoot specifications limit transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by single and/or repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modelled within Intel I/O buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being used to characterize the Intel Xeon processor MP on the 0.13 micron process processor Datasheet 51 System Bus Signal Quality Specifications system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot. 3.3.2 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Intel Xeon processor MP on the 0.13 micron process processor both are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in Table 25 through Table 28. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse duration. Provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications, the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications. 3.3.3 Overshoot/Undershoot Pulse Duration Pulse duration describes the total time an overshoot/undershoot event exceeds VID. The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. Note: 3.3.4 Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration. Activity Factor Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any common clock signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge. The highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. So, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every strobe cycle. The specifications provided in Table 25 through Table 28 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). 52 Datasheet System Bus Signal Quality Specifications NOTES: 1. Activity factor for common clock AGTL+ signals is referenced to BCLK[1:0] frequency. 2. Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#. 3. Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]#and DSTBN[3:0]#. 3.3.5 Reading Overshoot/Undershoot Specification Tables The overshoot/undershoot specification for the Intel Xeon processor MP on the 0.13 micron process processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification. In addition to the magnitude of the overshoot, the following parameters must be considered: the width of the overshoot and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group that particular signal falls into. For AGTL+ signals operating in the 4X source synchronous domain, use Table 25. For AGTL+ signals operating in the 2X source synchronous domain, use Table 26. If the signal is an AGTL+ signal operating in the common clock domain, use Table 27. Finally, all other signals reside in the 33 MHz domain (asynchronous GTL+, TAP, etc.) and are referenced in Table 28. 2. Determine the magnitude of the overshoot or the undershoot (relative to VSS). 3. Determine the activity factor (how often does this overshoot occur). 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive. 3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events for a given transition, with each having their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail (see Figure 25). A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. 1. Ensure no signal ever exceeds VCC or -0.25V or 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables or 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where AF=1), then the system passes. Datasheet 53 System Bus Signal Quality Specifications The following notes apply to Table 25 through Table 28. NOTES: 1. Absolute Maximum Overshoot magnitude of 1.8V must never be exceeded. 2. Absolute Maximum Overshoot is measured referenced to VSS, Pulse Duration of overshoot is measured relative to VCC. 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS. 4. Ringback below VCC cannot be subtracted from overshoots/undershoots. 5. Lesser undershoot does not allocate longer or larger overshoot. 6. OEMs are strongly encouraged to follow Intel layout guidelines. 7. All values specified by design characterization. 8. Refer to Table 5 for signal group definitions. Table 25. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Source Synchronous AGTL+ Signal Group (Data) Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.80 - 0.347 0.04 0.46 4.70 1.75 - 0.297 0.12 1.37 5.00 1.70 - 0.247 0.36 5.00 5.00 1.65 - 0.197 1.05 5.00 5.00 1.60 - 0.147 3.09 5.00 5.00 1.55 - 0.097 5.00 5.00 5.00 1.50 - 0.047 5.00 5.00 5.00 NOTES: 1. These specifications are measured at the processor pad. 2. Assumes a BCLK period of 10 ns. 3. AF is referenced to associated source synchronous strobes Table 26. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Common Clock AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.80 - 0.347 0.08 0.86 8.67 1.75 - 0.297 0.25 2.53 10.00 1.70 - 0.247 0.73 7.34 10.00 1.65 - 0.197 2.11 10.00 10.00 1.60 - 0.147 6.19 10.00 10.00 1.55 - 0.097 10.00 10.00 10.00 1.50 - 0.047 10.00 10.00 10.00 NOTES: 1. These specifications are measured at the processor pad. 2. Assumes a BCLK period of 10 ns. 3. AF is referenced to associated source synchronous strobes. . 54 Datasheet System Bus Signal Quality Specifications Table 27. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Common Clock AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.80 - 0.347 0.17 1.73 17.34 1.75 - 0.297 0.50 5.06 20.00 1.70 - 0.247 1.46 14.69 20.00 1.65 - 0.197 4.23 20.00 20.00 1.60 - 0.147 12.39 20.00 20.00 1.55 - 0.097 20.00 20.00 20.00 1.50 - 0.047 20.00 20.00 20.00 NOTES: 1. These specifications are measured at the processor pad. 2. BCLK period is 10 ns. 3. WIRED OR signals on Intel Xeon processor MP on the 0.13 micron process processor can tolerate up to 1 V of overshoot/undershoot. 4. AF is referenced to BCLK[1:0]. Table 28. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.80 - 0.347 0.52 5.20 52.03 1.75 - 0.297 1.51 15.19 60.00 1.70 - 0.247 4.40 44.90 60.00 1.65 - 0.197 12.71 60.00 60.00 1.60 - 0.147 37.19 60.00 60.00 1.55 - 0.097 60.00 60.00 60.00 1.50 - 0.047 60.00 60.00 60.00 NOTES: 1. These specifications are measured at the processor pad. 2. These signals are assumed in a 33 MHz time domain. Datasheet 55 System Bus Signal Quality Specifications Figure 25. Maximum Acceptable Overshoot/Undershoot Waveform VMAX Maximum Absolute Overshoot Time-dependent Overshoot VCC GTLREF VOL VSS VMIN Maximum Absolute Undershoot 56 Time-dependent Undershoot Datasheet Mechanical Specifications Mechanical Specifications 4 The Intel Xeon processor MP on the 0.13 micron process processor uses a Micro-Pin Grid Array (INT-mPGA) packaging technology. The Intel Xeon processor with 512-KB of L2 cache uses the INT-mPGA package for 400 MHz system bus processors and the Flip Chip Micro-Pin Grid Array (FC-mPGA2) package for 533 MHz system bus processors. In addition, the Low Voltage Intel Xeon processor uses the Flip Chip Micro-Pin Grid Array (FC-mPGA2) package for 400 MHz system bus processors. Both packages include an integrated heat spreader (IHS). The Intel Xeon processor MP on the 0.13 micron process and the Intel Xeon processor in INT-mPGA package include the processor die, and a pinned FR4 interposer. The Intel Xeon processor in the FCmPGA2 package contains the processor die but no interposer, PIROM or scratch EEPROM. Mechanical specifications for the processor are given in this section. See Section 1.1 for terminology definitions. Figure 26 and Figure 27 provide a basic processor assembly drawing and includes the components which make up the entire processor. The Intel Xeon processor MP on the 0.13 micron process processor and the Intel Xeon processor in INT-mPGA package also includes several SMBus components on the package interposer, an EEPROM, and a thermal sensor. Table 29 provides dimensions for the package shown in Figure 28. These dimensions describe a high thermal performance package for use on the Intel Xeon processor MP on the 0.13 micron process processor. A thermal performance benefit is expected from the use of an IHS with an increase in thickness from 1.5 mm to 3.0 mm. This results in a change from the Intel Xeon processor package configuration. The Intel Xeon processor MP on the 0.13 micron process processor and the Intel Xeon processor in INT-mPGA utilize a surface mount 603-pin zero-insertion force (ZIF) socket for installation into the baseboard. Please refer to the 603- Pin Socket Design Guidelines for further details on the processor socket. The Intel Xeon processor in the FC-mPGA2 package utilizes a surface mount 604-pin zero-insertion force (ZIF) socket for installation into the baseboard. The 604-pin socket is required to accommodate the solder fillet on the FC-mPGA2 package pins. Please refer to the 604Pin Socket Design Guidelines for further details on the processor socket. Note that Intel Xeon processor in INT-mPGA package can utilize the 604-pin socket. Note: For Figure 26 through Figure 37, the following notes apply: 1. Unless otherwise specified, the following drawing dimensions are expressed in millimeters. 2. Currently, all mechanical specifications are preliminary and subject to change. 3. Figures and drawings labelled as "Reference Dimensions" are provided for informational purposes only. Reference Dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. Reference Dimensions are NOT checked as part of the processor manufacturing process. Unless noted as such, dimensions in parentheses without tolerances are Reference Dimensions. 4. The Intel Xeon processor MP on the 0.13 micron process processor will utilize a 42.5 mm INT-mPGA package and for the purpose of this section will be referred to as the "Xeon MP package." The Intel Xeon processor will use a 35 mm INT-mPGA or 31 mm for the FCmPGA2 package. The differences between these packages include the package dimensions and the IHS dimensions. Thermal solutions should be designed to support both packages and their associated IHS sizes. See the Intel(R) XeonTM Processor (MP) Thermal Design Guidelines for additional details on thermal solution design. Datasheet 57 Mechanical Specifications Figure 26. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package - Assembly Drawing (Including Socket) 1 2 5 6 3 7 4 8 9 Note: This drawing is not to scale and is for reference only. The assembly applies to both Intel Xeon processor MP on the 0.13 micron process processor and Intel Xeon processor in the INT-mPGA package. The 603-pin socket is supplied as a reference only. 1. 2. 3. 4. 5. 6. 7. 8. 9. 58 Integrated Heat Spreader (IHS) Thermal Interface Material (TIM) between processor die and IHS Processor die Flip Chip interconnect FCBGA (Flip Chip Ball Grid Array) package FCBGA solder joints Processor interposer 603-pin socket 603-pin socket solder joints Datasheet Mechanical Specifications 4.1 Mechanical Specifications Figure 27. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package Top View Component Placement Detail P in A 1 C PU Figure 28. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package Drawing Datasheet 59 Mechanical Specifications Table 29. Dimensions for the Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package Millimeters Symbol Notes Min Nominal Max A 53.19 53.34 53.49 B 42.45 42.50 42.64 Includes placement tolerance C 38.40 38.50 38.95 Includes placement tolerance D 3.47 3.81 4.15 E 6.05 6.50 6.95 F 1.95 2.03 2.11 G 19.05 Nominal H 38.10 Nominal J 7.19 7.32 7.44 K 14.38 14.63 14.88 L 13.97 Nominal M 30.48 Nominal N 5.92 6.05 6.17 P 0.28 0.31 0.36 14.38 14.63 R T Pin Tp 1.27 Pin Diameter Nominal 14.88 0.26 Figure 29 details the keep-in zone for components mounted to the top side of the processor interposer for the Intel Xeon processor MP on the 0.13 micron process processor and Intel Xeon processor in INT-mPGA package. The components include the EEPROM, thermal sensor, resistors and capacitors. 60 Datasheet Mechanical Specifications Figure 29. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Top View Component Keep-In Figure 30 details the keep in specification for pin-side components. The Intel Xeon processor MP on the 0.13 micron process processor may contain pin side capacitors mounted to the processor INT-mPGA package. The capacitors will be exposed within the opening of the interposer cavity. This keep-out specification applies to the Intel Xeon processor MP on the 0.13 micron process processor and the Intel Xeon processor in INT-mPGA package. Figure 30. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package - Cross Section View - Pin Side Component Keep-In IHS FCBGA Interposer 1.270mm 13.411mm Socket must allow clearance for pin shoulders and mate flush with this surface Datasheet Component Keepin Component Keepin 61 Mechanical Specifications Figure 31. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package - Processor Pin Details NOTES: 1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni. 2. 0.254 Diametric true position, pin to pin. Figure 32 and Figure 33 detail the flatness and tilt specifications for the IHS of the Intel Xeon processor MP on the 0.13 micron process processor and Intel Xeon processor. Tilt is measured with the reference datum set to the bottom of the processor interposer. 62 Datasheet Mechanical Specifications Figure 32. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Package IHS Flatness and Tilt Drawing Figure 33. Intel(R) XeonTM Processor MP on the 0.13 Micron Process INT-mPGA Package IHS Flatness and Tilt Drawing Datasheet 63 Mechanical Specifications 4.2 Package Load Specifications Table 30 provides dynamic and static load specifications for the Intel Xeon processor MP on the 0.13 micron process processor IHS. These mechanical load limits should not be exceeded during heat sink assembly, mechanical stress testing, or standard drop and shipping conditions. The heat sink attach solutions must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heat sink-to-processor thermal interface. It is not recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions. Table 30. Package Dynamic and Static Load Specifications Parameter Max Static Dynamic Unit Notes 50 lbf 1, 2, 3 50 + 1 lb * 50G input * 1.8 (AF) lbf 1, 2, 4,5 NOTES: 1. This specification applies to a uniform compressed load. 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. 3. These parameters are based on design characterization and not tested. 4. Dynamic loading specifications are defined assuming a maximum duration of 11 ms. 5. 1 lb is Heatsink weight. 50 G is shock input to the system during shock testing. AF is the amplification factor. This is equivalent to 140 lbs. 4.3 Insertion Specifications The Intel Xeon processor MP on the 0.13 micron process processor can be inserted and removed 15 times from a 603/604-pin socket meeting the 603-Pin Socket Design Guidelines document. 4.4 Mass Specifications Table 31 specifies the processors mass. This includes all components which make up the entire processor product. Table 31. Processor Mass Processor 64 Mass (grams) Intel(R) XeonTM processor MP on the 0.13 micron process processor with 1-MB L3 cache 57 Intel(R) XeonTM processor MP on the 0.13 micron process processor with 2-MB L3 cache 57 Datasheet Mechanical Specifications 4.5 Materials The Intel Xeon processor MP on the 0.13 micron process processor is assembled from several components. The basic material properties are described in Table 32. Table 32. Processor Material Properties Component Integrated Heat Spreader INT-mPGA & FC-mPGA2 package Interposer Notes Nickel plated copper BT Resin FR4 Interposer pins (INT-mPGA2) FC-mPGA2 package pins 4.6 Material Kovar with Gold over nickel Cu Alloy 194 Markings Figure 34 shows the topside markings while Figure 35 shows the bottom side markings on the processor. These diagrams are to aid in the identification of the Intel Xeon processor MP on the 0.13 micron process processor. Figure 34. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Top-Side Markings (Package Example) Dynamic Laser Mark Area with 2D Matrix Group A Line1 Group A Line2 Group B Line1 Group B Line2 2D Matrix encodes ATPO number and Serial number Pin A1 NOTES: 1. Character size for laser marking is: height 0.050 inch (1.27mm), width 0.032 inch (0.81mm) 2. All characters will be in upper case. Datasheet 65 Mechanical Specifications Figure 35. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Bottom-Side Markings (Package Example) Gallatin Processor & Intel Xeon Processor w/ 512 KB L2 cache Engr (QDF) Sample Mark Prod(SSPEC) Sample Mark Description Group A Line 1 Intel Confidential Group A Line 2 i(m)'02 {Intel Brand} i(m)'02 Legal mark Group B Line 1 XXXXXXXX Croup B Line 2 YYYY XXXXXXXX YYYY ATPO mark Serial number mark Group C Line 1 80532KC2.0G2M 2000/2M/400/1/475V Product code Group C Line 2 QXXX Costa Rica S XXX Costa Rica QDF/Sspec, Assy site Group C Line 3 XXXXXXXX-YYYY XXXXXXXX-YYYY FPO-SN mark Group C Line 1 Group C Line 2 Group C Line 3 *Example shown is a 2.0GHz Intel(R) Xeon(TM) Processor Pin A1 4.7 Pinout Diagram This section provides two views of the processor pin grid. Figure 36 and Figure 37 detail the coordinates of the Intel Xeon processor MP on the 0.13 micron process processor and Intel Xeon processor in INT-mPGA 603-pins package. 66 Datasheet Mechanical Specifications Figure 36. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram Top View COMMON CLOCK 3 5 7 9 11 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 13 15 19 21 23 25 27 29 31 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Top View 2 4 6 8 10 12 14 16 18 20 22 DATA CLOCKS = Signal = Power = Ground Datasheet 17 Async / JTAG 24 26 Vcc/Vss Vcc/Vss 1 COMMON CLOCK ADDRESS 28 SMBus = SM_VCC = GTLREF = Reserved 67 Mechanical Specifications Figure 37. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor and Intel(R) XeonTM Processor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram Bottom View 31 29 27 COMMON CLOCK 25 Vcc/Vss A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 23 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Family Bottom View AD AE 28 SMBus 26 24 22 20 18 16 14 12 10 DATA = Signal = Power = Ground 68 COMMON CLOCK ADDRESS Vcc/Vss Async / JTAG 8 6 4 2 CLOCKS = SM_VCC = GTLREF = Reserved Datasheet Thermal Specifications Thermal Specifications 5 This chapter provides the thermal specifications necessary for designing a thermal solution for the Intel Xeon processor MP on the 0.13 micron process processor. The IHS provides a common interface intended to be compatible with many heatsink designs. Thermal specifications are based on the temperature of the IHS top, referred to as "TCASE". Thermal solutions should be designed to maintain the processor within its TCASE specifications. For information on performing Tcase measurements for thermal solution design and validation, refer to the Intel(R) XeonTM Processor (MP) Thermal Design Guidelines. See Figure 38 for an exploded view of the processor package and thermal solution assembly. For boxed processor specifications, refer to Section 7. Datasheet 69 Thermal Specifications Note: The processor is either shipped alone or with a heatsink (boxed processor only). All other components shown in Figure 38 must be purchased separately. Figure 38. Thermal and Mechanical Components - Exploded View Heat sink clip Heat sink EMI ground frame Retention mechanism 603-pin socket NOTE: This is a graphical representation. It is applicable for the 604-pin socket also which is required for the Intel Xeon processor with 512-KB L2 cache in the FC-mPGA2 package. For specifications, see each component's respective documentation listed in Section 1.2. 70 Datasheet Thermal Specifications 5.1 Thermal Specifications Table 33 specifies the thermal design power for Intel Xeon processor MP on the 0.13 micron process processor. The processor power listed in Table 33 is described in two ways; maximum power and thermal design power. Analysis indicates that real applications are unlikely to cause the processor to consume the maximum possible power. Intel recommends that system thermal be designed to meet the Thermal Design Power (TDP) indicated in Table 33 instead of "Maximum Processor Power." Thermal Design Power recommendations are chosen through characterization of server applications on the Intel Xeon processor MP on the 0.13 micron process processor. The Thermal Monitor feature is intended to protect the processor from exceeding its thermal limit on any high power application that exceeds the recommendations in this table. For more details on the Thermal Monitor feature, refer to Section 6.3. For maximum upgrade flexibility, systems should be designed to future processor power increases, even if a processor with a lower power dissipation is planned. In all cases, the Thermal Monitor feature must be enabled for the processor to be operating within specification. Table 33 also lists the minimum and maximum processor TCASE temperature specifications. A thermal solution should be designed to ensure the temperature of the processor never exceeds these specifications. Table 33. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Thermal Design Power Maximum Processor Power 1 (W) Thermal Design Power 2 (W) Minimum TCASE (C) Maximum TCASE 7 (C) 65 57 5 69 1.50 GHz 54 48 5 67 1.90 GHz 63 55 5 68 Core Frequency Note3, 4 Processor with 2-MB L3 Cache 2 GHz Processor 1-MB L3 Cache NOTES: 1. Maximum Processor Power is the maximum thermal power that can be dissipated by the processor through the integrated heat spreader. 2. Intel recommends that thermal solutions be designed to meet the Thermal Design Power guidelines. Refer to the Intel(R) XeonTM Processor (MP) Thermal Design Guidelines. 3. TDP values are specified at the point on Vcc_max loadline corresponding to Icc_TDP. 4. Systems must be designed to ensure that the processor is not subjected to any static Vcc and Icc combination wherein Vcc exceeds Vcc_max at specified Icc. Please refer to the loadline specifications in Section 2. 5. Values are based on the latest silicon available at the time of publication. Any updates will be provided in a future revision of this document. 6. Actual specifications for future processor frequencies may be different. 7. TCASE values are based on Intel reference heatsink with psi_ca of 0.33 C/W. Refer to the Intel(R) XeonTM Processor (MP) Thermal Design Guidelines for details. Datasheet 71 Thermal Specifications Figure 39. Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Thermal Design Power vs. Electrical Projections 80 TDP 1.450 70 1.445 60 1.440 50 VMAX 1.435 Thermal Design Power (W) Processor Maximum Voltage (VDC) 1.455 40 35 40 45 50 55 60 65 70 Processor Maximum Current (A) 72 Datasheet Thermal Specifications 5.2 Measurements for Thermal Specifications 5.2.1 Processor Case Temperature Measurement The minimum and maximum case temperatures (TCASE) for processors are specified in Table 33 of the previous section. These temperature specifications are meant to ensure correct and reliable operation of the processor. Figure 40 illustrates the thermal measurement point for TCASE. The 42.5 mm package measurement location applies to the Intel Xeon processor MP on the 0.13 micron process processor, the 35 mm package measurement location applies to the Intel Xeon processor in INT-mPGA package, and the 31 mm measurement location applies to the Intel Xeon processor in the FC-mPGA2 package. For information on performing Tcase measurements for thermal solution design and validation, refer to the Intel(R) XeonTM Processor (MP) Thermal Design Guidelines. Figure 40. Thermal Measurement Point for Processor TCASE Measure from edge of processor interposer Measure TCASE at this point (geometric center of IHS) 26.67 mm [1.05 in] 22.86 mm [0.90 in] Thermal grease should cover entire area of IHS Intel(R) XeonTM MP Processor with up to 2-MB L3 Cache (53.34 mm x 53.34 mm interposer) NOTE: Figure is not to scale, and is for reference only Datasheet 73 Thermal Specifications This page is intentionally left blank. 74 Datasheet Features 6 Features 6.1 Power-On Configuration Options Intel Xeon processor MP on the 0.13 micron process processor members have several configuration options that are determined by the state of specific processor pins at the active-toinactive transition of the processor RESET# signal. These configuration options cannot be changed except by another reset. Both power on and software induced resets reconfigure the processor(s). Table 34. Power-On Configuration Option Pins Configuration Option Pin Output tri state SMI# Execute BIST (Built-In Self Test) INIT# In Order Queue de-pipelining (set IOQ depth to 1) A7# Disable MCERR# observation A9# Disable BINIT# observation A10# APIC cluster ID (0-3) A[12:11]# Disable bus parking A15# Disable Hyper-Threading Technology Symmetric agent arbitration ID Notes1 2 A31# BR[3:0]# 3 NOTES: 1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option. 6.2 Clock Control and Low Power States The Intel Xeon processor MP on the 0.13 micron process processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 41 for a visual representation of the processor low power states. Due to the inability of processors to recognize bus transactions during the Sleep state, multiprocessor Intel Xeon processor MP on the 0.13 micron process processor based systems are not allowed to simultaneously have one processor in Sleep state and the other processors in Normal or Stop-Grant state. 6.2.1 Normal State--State 1 This is the normal operating state for the processor. Datasheet 75 Features 6.2.2 AutoHALT Powerdown State--State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the system bus. RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. Figure 41. Stop Clock State Machine HALT Instruction and HALT Bus Cycle Generated 2. Auto HALT Power Down State BCLK running Snoops and interrupts allowed INIT#, BINIT#, INTR, NMI, SMI#, RESET# ST PC LK #A ss ert ed Snoop Event Occurs Snoop Event Serviced 4. HALT/Grant Snoop State BCLK running Service snoops to caches 1. Normal State Normal execution STPCLK# Asserted . STPCLK# De-asserted ST PC LK #D e-a ss ert ed Snoop Event Occurs Snoop Event Serviced 3. Stop Grant State BCLK running Snoops and interrupts allowed SLP# Asserted SLP# De-asserted 5. Sleep State BCLK running No snoops or interrupts allowed 76 Datasheet Features 6.2.3 Stop-Grant State--State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. For the Intel Xeon processor MP on the 0.13 micron process processor, both logical processors must be in the Stop Grant state before the deassertion of STPCLK#. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will be recognized while the processor is in Stop-Grant state. If STPCLK# is still asserted at the completion of the BINIT# bus initialization, the processor will remain in Stop-Grant mode. If the STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor will return to Normal state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should only be deasserted one or more bus clocks after the deassertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the system bus (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with the assertion of the SLP# signal. While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. 6.2.4 HALT/Grant Snoop State--State 4 The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate. 6.2.5 Sleep State--State 5 The Sleep state is a very low power state in which each processor maintains its context, maintains the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT states. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. Datasheet 77 Features If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence. Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. For Intel Xeon processor MP on the 0.13 micron process processors, the SLP# pin may only be asserted when all logical processors are in the Stop-Grant state. SLP# assertions while the processors are not in the Stop-Grant state is out of specification and may result in illegal operation. 6.2.6 Bus Response during Low Power States While in AutoHALT Power Down and Stop-Grant states, the processor will process a system bus snoop. When the processor is in Sleep state, the processor will not process interrupts or snoop transactions. 6.3 Thermal Monitor Thermal Monitor is a feature of the Intel Xeon processor MP on the 0.13 micron process processor which allows system designers to lower the cost of thermal solutions, without compromising system integrity or reliability. By using a factory-tuned, precision on-die temperature sensor, and a fast acting thermal control circuit (TCC), the processor, without the aid of any additional software or hardware, can control the processors' die temperature within factory specifications under typical real-world operating conditions. Thermal Monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications, instead of being designed to the much higher maximum processor power envelopes. Thermal Monitor controls the processor temperature by modulating (starting and stopping) the internal processor core clocks. The processor clocks are modulated when the thermal control circuit (TCC) is activated. Thermal Monitor uses two modes to activate the TCC: automatic mode and on-Demand mode. Automatic mode must be enabled via BIOS, which is required for the processor to operate within specifications. Once automatic mode is enabled, the TCC will activate only when the internal die temperature is very near the temperature limits of the processor. When the TCC is enabled, and a high temperature situation exists (i.e., TCC is active), the clocks will be modulated by maintaining a duty cycle within a range of 30% - 50%. Clocks will not be off or on more than 3.0 s when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. Once the temperature has returned to a non-critical level, and the hysteresis timer has expired, modulation ceases and the TCC goes inactive. Processor performance will be decreased by ~50% when the TCC is active (assuming a duty cycle that varies from 30%-50%), however, with a properly designed and characterized thermal solution the TCC most likely will only be activated briefly during the most power intensive applications. For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers or interrupt handling routines. 78 Datasheet Features The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Thermal Monitor Control Register is written to a "1" the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed anywhere within a range of 30% to 50%; however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if you try to enable the TCC via On-Demand mode at the same time automatic mode is enabled AND a high temperature condition exists, the fixed duty cycle of the automatic mode will override the duty cycle selected by the on-demand mode. An external signal, PROCHOT# (processor hot), is always asserted when the processor die temperature has reached its thermal limit. If the TCC is enabled (note that the TCC must be enabled for the processor to be operating within spec), TCC will be active when PROCHOT# signal is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Thermal Monitor feature also includes one ACPI register, one performance counter register, three model specific registers (MSR), and one output pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT# (i.e. upon the activation/deactivation of TCC). If automatic mode is disabled the processor will be operating out of specification and cannot be guaranteed to provide reliable results. Regardless of enabling of the automatic or OnDemand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 C. At this point the system bus signal THERMTRIP# will go active and stay active until the processor has cooled down and RESET# has been initiated. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.If THERMTRIP# is asserted, processor core voltage (Vcc) must be removed within the time frame defined in Table 18 and Figure 15. 6.3.1 Thermal Diode The Intel Xeon processor MP on the 0.13 micron process processor incorporates an on-die thermal diode. This thermal diode is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. See Section 6.4.4 for details. 6.4 System Management Bus (SMBus) Interface The Intel Xeon processor MP on the 0.13 micron process processor in the INT-mPGA package includes an SMBus interface which allows access to a memory component with two sections (referred to as the Processor Information ROM and the Scratch EPROM) and a thermal sensor on the substrate. The SMBus thermal sensor may be used to read the thermal diode mentioned in Section 6.3.1. These devices and their features are described below. See Section 4 for the physical location of these devices. The SMBus thermal sensor and its associated thermal diode are not related to, and are completely independent of, the precision on-die temperature sensor and thermal control circuit (TCC) of the Thermal Monitor feature discussed in Section 6.3. Datasheet 79 Features The processor SMBus implementation uses the clock and data signals of the V1.1 System Management Bus Specification. It does not implement the SMBSUS# signal. Layout and routing guidelines are available in the appropriate platform design guidelines document and the SMBus and I2C Bus Design Guide application note. For platforms which do not implement any of the SMBus features found on the processor, all of the SMBus connections, except SM_VCC, to the socket pins may be left unconnected (SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP). SM_VCC provides power to the VID generation logic in addition to supplying the SMBus and must be supplied with 3.3 volt power to assure correct setting of the processor core voltage (VCC). Figure 42. Logical Schematic of SMBus Circuitry SM_VCC SM_TS_A0 SM_TS_A1 VCC SM_EP_A0 A0 SM_EP_A1 A1 SM_EP_A2 A2 SM_WP WP Processor Information ROM and Scratch EEPROM (1 Kbit each) VCC CLK A0 CLK DATA A1 DATA Thermal Sensor STDBY# ALERT# VSS VSS SM_CLK SM_DAT SM_ALERT# NOTE: Actual implementation may vary. For use in general understanding of the architecture. All SMBus pull-up and pull-down resistors are 10K and located on the processor. 6.4.1 Processor Information ROM (PIROM) The lower half (128 bytes) of the SMBus memory component is an electrically programmed readonly memory with information about the processor. This information is permanently writeprotected. Table 35 shows the data fields and formats provided in the Processor Information ROM (PIROM). Table 35. Processor Information ROM Format (Sheet 1 of 3) # of Bits Offset/Section Function Notes Header: 80 00h 8 Data Format Revision Two 4-bit hex digits 01 - 02h 16 EEPROM Size Size in bytes (MSB first) Datasheet Features Table 35. Processor Information ROM Format (Sheet 2 of 3) # of Bits Offset/Section Function Notes 03h 8 Processor Data Address Byte pointer, 00h if not present 04h 8 Processor Core Data Address Byte pointer, 00h if not present 05h 8 L3 Cache Data Address Byte pointer, 00h if not present 06h 8 Package Data Address Byte pointer, 00h if not present 07h 8 Part Number Data Address Byte pointer, 00h if not present 08h 8 Thermal Reference Data Address Byte pointer, 00h if not present 09h 8 Feature Data Address Byte pointer, 00h if not present 0Ah 8 Other Data Address Byte pointer, 00h if not present 0Bh 16 Reserved Reserved 0Dh 8 Checksum 1 byte checksum 48 S-spec/QDF Number Six 8-bit ASCII characters 6 Reserved Reserved (most significant bits) 2 Sample/Production 00b=Sample only, 01-11b=Production 8 Checksum 1 byte checksum 2 Processor Core Type From CPUID 4 Processor Core Family From CPUID 4 Processor Core Model From CPUID 4 Processor Core Stepping From CPUID Processor Data: 0E - 13h 14h 15h Processor Core Data: 16 - 17h 2 Reserved Reserved 18 - 19h 16 Reserved Reserved 1A - 1Bh 16 System Bus Speed 16-bit binary number (in MHz) 2 Multiprocessor Support 00b=UP, 01b=DP, 10b=RSVD, 11b=MP 6 Reserved Reserved 1Ch 1D - 1Eh 16 Maximum Core Frequency 16-bit binary number (in MHz) 1F - 20h 16 Processor VID (Voltage ID) Voltage requested by VID outputs in mV 21 - 22h 16 Core Voltage, Minimum Minimum processor DC Vcc spec in mV 23h 8 TCASE Maximum Maximum case temperature spec in C 24h 8 Checksum 1 byte checksum 25 - 26h 16 Reserved Reserved 27-28h 16 L2 Cache Size 16-bit binary number (in KB) Cache Data: Datasheet 29 - 2Ah 16 L3 Cache Size 16-bit binary number (in KB) 2B - 30h 48 Reserved Reserved 31h 8 Checksum 1 byte checksum 81 Features Table 35. Processor Information ROM Format (Sheet 3 of 3) # of Bits Offset/Section Function Notes Package Data: 32 - 35h 32 Package Revision Four 8-bit ASCII characters 36h 8 Reserved Reserved 37h 8 Checksum 1 byte checksum Part Number Data: 38 - 3Eh 56 Processor Part Number Seven 8-bit ASCII characters 3F - 4Ch 112 Reserved Reserved 4D - 54h 64 Processor Electronic Signature 64-bit identification number 55 - 6Eh 208 Reserved Reserved 8 Checksum 1 byte checksum 70h 8 Thermal Reference Byte See Section 6.4.4 for details 71 - 72h 16 Reserved Reserved 73h 8 Checksum 1 byte checksum 32 Processor Core Feature Flags From CPUID function 1, EDX contents 6Fh Thermal Ref. Data: Feature Data: 74 - 77h 78h 8 Processor Feature Flags [7] = Reserved [6] = Serial Signature [5] = Electronic Signature Present [4] = Thermal Sense Device Present [3] = Thermal Reference Byte Present [2] = OEM EEPROM Present [1] = Core VID Present [0] = L3 Cache Present 79-7Bh 24 Additional Processor Feature Flags Reserved 7Ch 8 Reserved Reserved 7Dh 8 Checksum 1 byte checksum 16 Reserved Reserved Other Data: 7E - 7Fh 82 Datasheet Features 6.4.2 Scratch EEPROM Also available in the memory component on the Intel Xeon processor MP on the 0.13 micron process processor in INT-mPGA package, is an EEPROM which may be used for other data at the system or processor vendor's discretion. The data in this EEPROM, once programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a weak pull-down (10 k) to allow the EEPROM to be programmed in systems with no implementation of this signal. The Scratch EEPROM resides in the upper half of the memory component (addresses 80 FFh). The lower half comprises the Processor Information ROM (address 00 - 7Fh), which is permanently write protected by Intel. 6.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM (PIR) responds to two SMBus packet types: Read Byte and Write Byte. However, since the PIR is write-protected, it will acknowledge a Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte commands. Table 36 diagrams the Read Byte command. Table 37 diagrams the Write Byte command. Following a write cycle to the scratch ROM, software must allow a minimum of 10 ms before accessing either ROM of the processor. In the tables, `S' represents the SMBus start bit, `P' represents a stop bit, `R' represents a read bit, `W' represents a write bit, `A' represents an acknowledge (ACK), and `///' represents a negative acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM, and the bits that aren't shaded are transmitted by the SMBus host controller. In the tables the data addresses indicate 8 bits.The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed: the Processor Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1). Table 36. Read Byte SMBus Packet S Slave Address Write A Command Code A S Slave Address Rea d A Data /// P 1 7-bits 1 1 8-bits 1 1 7-bits 1 1 8-bits 1 1 Table 37. Write Byte SMBus Packet 6.4.4 S Slave Address Write A Command Code A Data A P 1 7-bits 1 1 8-bits 1 8-bits 1 1 SMBus Thermal Sensor The Intel Xeon processor MP on the 0.13 micron process processor in INT-mPGA package provide a SMBus thermal sensor as a means of acquiring thermal data from the processor. The thermal sensor is composed of control logic, SMBus interface logic, a precision analog-to-digital converter, and a precision current source. The sensor drives a small current through the p-n junction of a thermal diode located on the processor core. The forward bias voltage generated across the thermal diode is sensed and the precision A/D converter derives a single byte of thermal reference data, or a "thermal byte reading." The nominal precision of the least significant bit of a thermal byte is 1C. Datasheet 83 Features The processor incorporates the SMBus thermal sensor and thermal reference byte onto the processor package for the Intel Xeon processor MP on the 0.13 micron process processor and Intel Xeon processor in the INT-mPGA package. Upper and lower thermal reference thresholds can be individually programmed for the SMBus thermal sensor. Comparator circuits sample the register where the single byte of thermal data (thermal byte reading) is stored. These circuits compare the single byte result against programmable threshold bytes. If enabled, the alert signal on the processor SMBus (SM_ALERT#) will be asserted when the sensor detects that either threshold is reached or crossed. Analysis of SMBus thermal sensor data may be useful in detecting changes in the system environment that may require attention. During manufacturing, the thermal reference byte (TRB) is programmed into the Processor Information ROM. The thermal reference byte represents the approximate temperature reading from the thermal diode when the processor is operating at its maximum specified TCASE under steady state temperature and application conditions. The TRB is derived for the processor through device characterization and the value varies with processor core frequency, similar to the TCASE specifications. The processor SMBus thermal sensor and thermal reference byte may be used to monitor long term temperature trends, but can not be used to manage the short term temperature of the processor or predict the activation of the thermal control circuit. As mentioned earlier, the processors high thermal ramp rates make this infeasible. Refer to the Intel(R) XeonTM Processor (MP) Thermal Design Guidelines for more details. The SMBus thermal sensor feature in the processor cannot be used to measure TCASE. The TCASE specification in Section 5 must be met regardless of the reading of the processor's thermal sensor in order to ensure adequate cooling for the entire Intel Xeon processor MP on the 0.13 micron process processor. The SMBus thermal sensor feature is only available while VCC and SM_VCC are at valid levels and the processor is not in a low-power state. 6.4.5 Thermal Sensor Supported SMBus Transactions The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte, Send Byte, Receive Byte, and Alert Response Address (ARA). The Send Byte packet is used for sending oneshot commands only. The Receive Byte packet accesses the register commanded by the last Read Byte packet and can be used to continuously read from a register. If a Receive Byte packet was preceded by a Write Byte or send Byte packet more recently than a Read Byte packet, then the behavior is undefined. Table 38 through Table 42 diagram the five packet types. In these figures, `S' represents the SMBus start bit, `P' represents a stop bit, `Ack' represents an acknowledge, and `///' represents a negative acknowledge (NACK). The shaded bits are transmitted by the thermal sensor, and the bits that aren't shaded are transmitted by the SMBus host controller. Table 43 shows the encoding of the command byte. Table 38. Write Byte SMBus Packet 84 S Slave Address Write Ack Command Code Ack Data Ack P 1 7-bits 1 1 8-bits 1 8-bits 1 1 Datasheet Features Table 39. Read Byte SMBus Packet S Slave Address Write Ack Command Code Ack S Slave Address Read Ack Data /// P 1 7-bits 1 1 8-bits 1 1 7-bits 1 1 8-bits 1 1 Table 40. Send Byte SMBus Packet S Slave Address Read Ack Command Code Ack P 1 7-bits 1 1 8-bits 1 1 Table 41. Receive Byte SMBus Packet S Slave Address Read Ack Data /// P 1 7-bits 1 1 8-bits 1 1 Table 42. ARA SMBus Packet S ARA Read Ack Address 1 0001 100 1 1 Device Address 1 /// P 1 1 NOTE: This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the seven most significant bits. The least significant bit is undefined and may return as a `1' or `0'. See Section 6.4.8 for details on the Thermal Sensor Device addressing. Table 43. SMBus Thermal Sensor Command Byte Bit Assignments (Sheet 1 of 2) Datasheet Register Command Reset State Function RESERVED 00h RESERVED TRR 01h 0000 0000 Read processor core thermal diode RS 02h N/A Read status byte (flags, busy signal) Reserved for future use RC 03h 00XX XXXX RCR 04h 0000 0010 Read configuration byte RESERVED 05h RESERVED Reserved for future use RESERVED 06h RESERVED Reserved for future use Read conversion rate byte RRHL 07h 0111 1111 Read processor core thermal diode THIGH limit RRLL 08h 1100 1001 Read processor core thermal diode TLOW limit WC 09h N/A Write configuration byte WCR 0Ah N/A Write conversion rate byte RESERVED 0Bh RESERVED Reserved for future use RESERVED 0Ch RESERVED Reserved for future use WRHL 0Dh N/A Write processor core thermal diode THIGH limit 85 Features Table 43. SMBus Thermal Sensor Command Byte Bit Assignments (Sheet 2 of 2) WRLL 0Eh N/A Write processor core thermal diode TLOW limit OSHT 0Fh N/A One shot command (use send byte packet) RESERVED 10h - FFh N/A Reserved for future use All of the commands in Table 48 are for reading or writing registers in the SMBus thermal sensor, except the one-shot command (OSHT) register. The one-shot command forces the immediate start of a new conversion cycle. If a conversion is in progress when the one-shot command is received, then the command is ignored. If the thermal sensor is in stand-by mode when the one-shot command is received, a conversion is performed and the sensor returns to stand-by mode. The oneshot command is not supported when the thermal sensor is in auto-convert mode. Note: Writing to a read-command register or reading from a write-command register will produce invalid results. The default command after reset is to a reserved value (00h). After reset, "Receive Byte" SMBus packets will return invalid data until another command is sent to the thermal sensor. 6.4.6 SMBus Thermal Sensor Registers 6.4.6.1 Thermal Reference Registers Once the SMBus thermal sensor reads the processor thermal diode, it performs an analog to digital conversion and stores the result in the Thermal Reference Register (TRR). The supported range is +127 to 0 decimal and is expressed as an eight-bit number representing temperature in degrees Celsius. This eight-bit value consists of seven data bits and a sign bit (MSB) as shown in Table 44. The values shown are also used to program the Thermal Limit Registers. The values of these registers should be treated as saturating values. Values above 127 are represented as 127 decimal, while values of zero and below may be represented as 0 to -127 decimal. If the thermal sensor returns a value with the sign bit set (1) and the data is 000_0000 through 111_1110, the temperature should be interpreted as 0 C. Table 44. Thermal Reference Register Values Temperature (C) 86 Register Value (binary) +127 0 111 1111 +126 0 111 1110 +100 0 110 0100 +50 0 011 0010 +25 0 001 1001 +1 0 000 0001 0 0 000 0000 Datasheet Features 6.4.6.2 Thermal Limit Registers The SMBus thermal sensor has four Thermal Limit Registers: RRHL is used to read the high limit; RRLL is read for the low limit; WRHL is used to write the high limit; and the WRLL to write the low limit. These registers allow the user to define high and low limits for the processor core thermal diode reading. The encoding for these registers is the same as for the Thermal Reference Register shown in Table 44. If the processor thermal diode reading equals or exceeds one of these limits, then the alarm bit (RHIGH or RLOW) in the Thermal Sensor Status Register is triggered. 6.4.6.3 Status Register The Status Register shown in Table 45 indicates which (if any) thermal value thresholds for the processor core thermal diode have been exceeded. It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection. Once set, alarm bits stay set until they are cleared by a Status Register read. A successful read to the Status Register will clear any alarm bits that may have been set, unless the alarm condition persists. If the SM_ALERT# signal is enabled via the Thermal Sensor Configuration Register and a thermal diode threshold is exceeded, an alert will be sent to the platform via the SM_ALERT# signal. This register is read by accessing the RS Command Register. Table 45. SMBus Thermal Sensor Status Register 6.4.6.4 Bit Name Reset State Function 7 (MSB) BUSY N/A If set, indicates that the device's analog to digital converter is busy. 6 RESERVED RESERVED 5 RESERVED RESERVED Reserved for future use Reserved for future use 4 RHIGH 0 If set, indicates the processor core thermal diode high temperature alarm has activated. 3 RLOW 0 If set, indicates the processor core thermal diode low temperature alarm has activated. 2 OPEN 0 If set, indicates an open fault in the connection to the processor core diode. 1 RESERVED RESERVED Reserved for future use. 0 (LSB) RESERVED RESERVED Reserved for future use. Configuration Register The Configuration Register controls the operating mode (stand-by vs. auto-convert) of the SMBus thermal sensor. Table 46 shows the format of the Configuration Register. If the RUN/STOP bit is set (high) then the thermal sensor immediately stops converting and enters stand-by mode. The thermal sensor will still perform analog to digital conversions in stand-by mode when it receives a one-shot command. If the RUN/STOP bit is clear (low) then the thermal sensor enters autoconversion mode. This register is accessed by using the thermal sensor Command Register: The RC command register is used for read commands and the WC command register is used for write commands. See Table 43. Datasheet 87 Features Table 46. SMBus Thermal Sensor Configuration Register Bit 6.4.6.5 Name Reset State Function 7 (MSB) MASK 0 Mask SM_ALERT# bit. Clear bit to allow interrupts via SM_ALERT# and allow the thermal sensor to respond to the ARA command when an alarm is active. Set the bit to disable interrupt mode. The bit is not used to clear the state of the SM_ALERT# output. An ARA command may not be recognized if the mask is enabled. 6 RUN/STOP 0 Stand-by mode control bit. If set, the device immediately stops converting, and enters stand-by mode. If cleared, the device converts in either one-shot mode or automatically updates on a timed basis. 5:0 RESERVED RESERVED Reserved for future use. Conversion Rate Registers The contents of the Conversion Rate Registers determine the nominal rate at which analog to digital conversions happen when the SMBus thermal sensor is in auto-convert mode. There are two Conversion Rate Registers, RCR for reading the conversion rate value and WCR for writing the value. Table 47 shows the mapping between Conversion Rate Register values and the conversion rate. As indicated in Table 43, the Conversion Rate Register is set to its default state of 02h (0.25 Hz nominally) when the thermal sensor is powered up. There is a 30% error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate. Table 47. SMBus Thermal Sensor Conversion Rate Registers 6.4.7 Register Value Conversion Rate (Hz) 00h 0.0625 01h 0.125 02h 0.25 03h 0.5 04h 1.0 05h 2.0 06h 4.0 07h 8.0 08h to FFh Reserved for future use SMBus Thermal Sensor Alert Interrupt The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus when a fault condition exists. The fault conditions consist of: 1) a processor thermal diode value measurement that exceeds a user-defined high or low threshold programmed into the Command Register or 2) disconnection of the processor thermal diode from the thermal sensor. The interrupt can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the baseboard via the SM_ALERT# open drain output. Once latched, the SM_ALERT# should only be cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor. The Alert Response Address is a special slave address shown in Table 42. The SM_ALERT# will 88 Datasheet Features be cleared once the SMBus master device first reads the status register then reads the slave ARA unless the fault condition persists. Reading the Status Register alone or setting the mask bit within the Configuration Register does not clear the interrupt. 6.4.8 SMBus Device Addressing Of the addresses broadcast across the SMBus, the memory component claims those of the form "1010XXXZb". The "XXX" bits are defined by pullups and pulldowns on the system baseboard. These address pins are pulled down weakly (10 k) on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus, or only support a partial implementation. The "Z" bit is the read/write bit for the serial bus transaction. The thermal sensor internally decodes one of three upper address patterns from the bus of the form "0011XXXZb", "1001XXXZb", or "0101XXXZb". The device's addressing, as implemented, uses the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state. Therefore, the thermal sensor supports nine unique addresses. To set either pin for the Hi-Z state, the pin must be left floating. As before, the "Z" bit is the read/write bit for the serial transaction. Note that addresses of the form "0000XXXXb" are Reserved and should not be generated by an SMBus master. The thermal sensor samples and latches the SM_TS_A[1:0] signals at power-up and at the starting point of every conversion. System designers should ensure that these signals are at valid VIH, VIL, or floating input levels prior to or while the thermal sensor's SM_VCC supply powers up. This should be done by pulling the pins to SM_VCC or VSS via a 1 k or smaller resistor, or leaving the pins floating to achieve the Hi-Z state. If the designer desires to drive the SM_TS_A[1:0] pins with logic, the designer must still ensure that the pins are at valid input levels prior to or while the SM_VCC supply ramps up. The system designer must also ensure that their particular implementation does not add excessive capacitance to the address inputs. Excess capacitance at the address inputs may cause address recognition problems. Refer to the appropriate platform design guidelines document and the SMBus and I2C Bus Design Guide application note. Figure 42 on page 80 shows a logical diagram of the pin connections. Table 48 and Table 49 describe the address pin connections and how they affect the addressing of the devices. Datasheet 89 Features Table 48. Thermal Sensor SMBus Addressing on the Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Device Select Address (Hex) 8-bit Address Word on Serial Bus Upper Address1 3Xh SM_TS_A1 SM_TS_A0 b[7:0] 0 0 0011000Xb Z2 0 0011001Xb 1 0 0011010Xb 0011 5Xh 0101 9Xh 1001 0 Z 2 0101001Xb Z2 Z2 0101010Xb 1 Z2 0101011Xb 0 1 1001100Xb Z2 1 1001101Xb 1 1 1001110Xb NOTES: 1. Upper address bits are decoded in conjunction with the select pins. 2. A tri-state or "Z" state on this pin is achieved by leaving this pin unconnected. Note: System management software must be aware of the processor dependent addresses for the thermal sensor. Table 49. Memory Device SMBus Addressing on the Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Address (Hex) Upper Address1 Device Select R/W bits 7-4 SM_EP_A2 bit 3 SM_EP_A1 bit 2 SM_EP_A0 bit 1 bit 0 A0h/A1h 1010 0 0 0 X A2h/A3h 1010 0 0 1 X A4h/A5h 1010 0 1 0 X A6h/A7h 1010 0 1 1 X A8h/A9h 1010 1 0 0 X AAh/ABh 1010 1 0 1 X ACh/ADh 1010 1 1 0 X AEh/AFh 1010 1 1 1 X NOTES: 1. . This addressing scheme will support up to 8 processors on a single SMBus. 90 Datasheet Boxed Processor Specifications Boxed Processor Specifications 7.1 7 Introduction The Intel Xeon processor MP on the 0.13 micron process processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The current plan for the Intel Xeon processor MP on the 0.13 micron process boxed processor is to include an unattached passive heatsink. Intel boxed processors do not include voltage regulation modules (VRMs). Integrators should contact their baseboard supplier to receive a list of supported module vendors and models. This chapter documents baseboard and platform requirements for the cooling solution that is supplied with the boxed processor. This chapter is particularly important for OEM's that manufacture baseboards and chassis for integrators. Figure 43 shows the a mechanical representation of the boxed processor heatsink for the Intel Xeon processor MP on the 0.13 micron process processor. Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designer's responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platform and chassis. Figure 43. Mechanical Representation of the Boxed Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Passive Heatsink Datasheet 91 Boxed Processor Specifications 7.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive heatsink. Proper clearance is required around the heatsink to ensure proper installation of the processor and unimpeded airflow for proper cooling. 7.2.1 Boxed Processor Heatsink Dimensions The boxed processor is shipped with an unattached passive heatsink. Clearance is required around the heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed Intel Xeon processor with 512KB L2 cache and assembled heatsink are shown in Figure 44 and Figure 45. The airflow requirements for the boxed processor heatsink must also be taken into consideration when designing new baseboards and chassis. The airflow requirements are detailed in the Thermal Specifications, Section 7.4. Please refer to the Intel(R) XeonTM Processor Multiprocessor (MP) Thermal Design Guidelines for details on the processor clearance requirements. 7.2.2 Boxed Processor Heatsink Weight The boxed processor heatsink weighs no more than 450 grams. See Section 4 and Section 5 of this document along with the Intel(R) XeonTM Processor Multiprocessor (MP) Thermal Design Guidelines for details on the processor weight and heatsink requirements. 7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports The boxed processor requires a processor retention solution to secure the processor, the baseboard, and the chassis. The retention solution contains two retention mechanisms and two retention clips per processor. For the boxed processor, the current plan is to ship with retention mechanisms, cooling solution retention clips, and direct chassis attach screws. Baseboards and chassis designed for use by system integrators should include holes that are in proper alignment with each other to support the boxed processor. Refer to the Server System Infrastructure Specification (SSI-EEB) at http://www.ssiforum.org for details on the hole locations. Please see the <Boxed integration notes> at http://support.intel.com/support/processors/xeon/ for retention mechanism installation instructions. Retention mechanism clips must interface with the boxed processor heatsink area shown in Detail A in Figure 46. The retention mechanism that ships with the boxed Intel Xeon processor is different than the reference solution from Intel. It adds tabs that allow the PWT (processor wind tunnel) to be attached directly to it. Please reference Figure 45 below, which contains the dimensions for the tabs that are different. For dimensions of the reference solution, please see the appropriate platform design guidelines. 92 Datasheet Boxed Processor Specifications Figure 44. Boxed Processor Clip Figure 45. Boxed Processor Retention Mechanism Datasheet 93 Boxed Processor Specifications Figure 46. Multiple View Space Requirements for Boxed Processors 94 Datasheet Boxed Processor Specifications 7.3 Boxed Processor Requirements 7.3.1 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Systems do not need to account for the processor wind tunnel or heat sink fan header in order to support the Intel boxed processor based on the Intel Xeon processor MP on the 0.13 micron process processor. If the system has no intention of supporting the boxed Intel Xeon processor with 512-KB L2 cache, these features may be removed. It has not yet been determined if the retention mechanism for the Intel Xeon processor MP on the 0.13 micron process processor will ship with the boxed processor or with the baseboards. If the retention mechanism is not included with the boxed processor, the system integrator or baseboard supplier will have to account for these pieces. No other special platform or system design considerations are required for integrated boxed Intel Xeon processor MP on the 0.13 micron process processor. 7.4 Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor will be directly cooled with a passive heatsink. For the passive heatsink to effectively cool the boxed processor, it is critical that sufficient, unimpeded, cool air flow over the heatsink of every processor in the system. Meeting the processor's temperature specification is a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is found in Section 5. It is important that system integrators perform thermal tests to verify that the boxed processor is kept below its maximum temperature specification in a specific baseboard and chassis. At an absolute minimum, the boxed processor heatsink will require 500 Linear Feet per Minute (LFM) of cool air flowing over the heatsink. The airflow must be directed from the outside of the chassis directly over the processor heatsinks in a direction passing from one retention mechanism to the other. It also should flow from the front to the back of the chassis. Directing air over the passive heatsink of the boxed Intel Xeon processor MP on the 0.13 micron process processor can be done with auxiliary chassis fans, fan ducts, or other techniques. It is also recommended that the ambient air temperature outside of the chassis be kept at or below 35 C. The air passing directly over the processor heatsink should not be preheated by other system components (such as another processor), and should be kept at or below 45 C. Again, meeting the processor's temperature specification is the responsibility of the system integrator. The processor temperature specification is found in Section 5. Datasheet 95 Boxed Processor Specifications This page is intentionally left blank. 96 Datasheet Debug Tools Specifications Debug Tools Specifications 8 The Debug Port design information has been moved. This includes all information necessary to develop a Debug Port on this platform, including electrical specifications, mechanical requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700 Debug Port Design Guide for the design of your platform. Note: 8.1 This change is effective for all future processors. Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing a system that can make use of an LAI: mechanical and electrical. 8.1.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI. 8.1.2 Electrical Considerations The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide. Datasheet 97 Debug Tools Specifications This page is intentionally left blank. 98 Datasheet Pin Listing and Signal Definitions 9 Pin Listing and Signal Definitions 9.1 Intel(R) XeonTM Processor MP on the 0.13 Micron Process Processor Pin Assignments Section 2.8 contains the system bus signal groups in Table 5 for the Intel Xeon processor MP on the 0.13 micron process processor. This section provides a sorted pin list in Table 50 and Table 51 for INT-mPGA package. Table 50 is a listing of all processor pins ordered alphabetically by pin name. Table 51 is a listing of all processor pins ordered by pin number. Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Direction A3# A22 Source Sync Input/Output A4# A20 Source Sync Input/Output A5# B18 Source Sync Input/Output A6# C18 Source Sync Input/Output A7# A19 Source Sync Input/Output A8# C17 Source Sync Input/Output A9# D17 Source Sync Input/Output A10# A13 Source Sync Input/Output A11# B16 Source Sync Input/Output A12# B14 Source Sync Input/Output A13# B13 Source Sync Input/Output A14# A12 Source Sync Input/Output A15# C15 Source Sync Input/Output A16# C14 Source Sync Input/Output A17# D16 Source Sync Input/Output A18# D15 Source Sync Input/Output A19# F15 Source Sync Input/Output A20# A10 Source Sync Input/Output A21# B10 Source Sync Input/Output A22# B11 Source Sync Input/Output A23# C12 Source Sync Input/Output A24# E14 Source Sync Input/Output A25# D13 Source Sync Input/Output A26# Datasheet A9 Source Sync Input/Output Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Direction A27# B8 Source Sync Input/Output A28# E13 Source Sync Input/Output A29# D12 Source Sync Input/Output A30# C11 Source Sync Input/Output A31# B7 Source Sync Input/Output A32# A6 Source Sync Input/Output A33# A7 Source Sync Input/Output A34# C9 Source Sync Input/Output A35# C8 Source Sync Input/Output A20M# F27 Async GTL+ Input ADS# D19 Common Clk Input/Output ADSTB0# F17 Source Sync Input/Output ADSTB1# F14 Source Sync Input/Output AP0# E10 Common Clk Input/Output AP1# D9 Common Clk Input/Output BCLK0 Y4 Sys Bus Clk Input BCLK1 W5 Sys Bus Clk Input BINIT# F11 Common Clk Input/Output BNR# F20 Common Clk Input/Output BPM0# F6 Common Clk Input/Output BPM1# F8 Common Clk Input/Output BPM2# E7 Common Clk Input/Output BPM3# F5 Common Clk Input/Output BPM4# E8 Common Clk Input/Output BPM5# E4 Common Clk Input/Output 99 Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name for the INT-mPGA Package Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No. Signal Buffer Type Direction BPRI# D23 Common Clk Input D30# AD19 Source Sync Input/Output BR0# D20 Common Clk Input/Output D31# AB17 Source Sync Input/Output BR1# AB16 Source Sync Input/Output F12 Common Clk Input D32# 1 E11 Common Clk Input D33# AA16 Source Sync Input/Output BR3# 1 D10 Common Clk Input D34# AC17 Source Sync Input/Output BSEL0 2 AA3 Power/Other Output D35# AE13 Source Sync Input/Output BSEL1 2 AB3 Power/Other Output D36# AD18 Source Sync Input/Output BR2# COMP0 AD16 Power/Other Input D37# AB15 Source Sync Input/Output COMP1 E16 Power/Other Input D38# AD13 Source Sync Input/Output D0# Y26 Source Sync Input/Output D39# AD14 Source Sync Input/Output D1# AA27 Source Sync Input/Output D40# AD11 Source Sync Input/Output D2# Y24 Source Sync Input/Output D41# AC12 Source Sync Input/Output D3# AA25 Source Sync Input/Output D42# AE10 Source Sync Input/Output D4# AD27 Source Sync Input/Output D43# AC11 Source Sync Input/Output D5# Y23 Source Sync Input/Output D44# AE9 Source Sync Input/Output D6# AA24 Source Sync Input/Output D45# AD10 Source Sync Input/Output D7# AB26 Source Sync Input/Output D46# AD8 Source Sync Input/Output D8# AB25 Source Sync Input/Output D47# AC9 Source Sync Input/Output D9# AB23 Source Sync Input/Output D48# AA13 Source Sync Input/Output D10# AA22 Source Sync Input/Output D49# AA14 Source Sync Input/Output D11# AA21 Source Sync Input/Output D50# AC14 Source Sync Input/Output D12# AB20 Source Sync Input/Output D51# AB12 Source Sync Input/Output D13# AB22 Source Sync Input/Output D52# AB13 Source Sync Input/Output D14# AB19 Source Sync Input/Output D53# AA11 Source Sync Input/Output D15# AA19 Source Sync Input/Output D54# AA10 Source Sync Input/Output D16# AE26 Source Sync Input/Output D55# AB10 Source Sync Input/Output D17# AC26 Source Sync Input/Output D56# AC8 Source Sync Input/Output D18# AD25 Source Sync Input/Output D57# AD7 Source Sync Input/Output D19# AE25 Source Sync Input/Output D58# AE7 Source Sync Input/Output D20# AC24 Source Sync Input/Output D59# AC6 Source Sync Input/Output D21# AD24 Source Sync Input/Output D60# AC5 Source Sync Input/Output D22# AE23 Source Sync Input/Output D61# AA8 Source Sync Input/Output D23# AC23 Source Sync Input/Output D62# Y9 Source Sync Input/Output D24# AA18 Source Sync Input/Output D63# AB6 Source Sync Input/Output D25# AC20 Source Sync Input/Output DBSY# F18 Common Clk Input/Output D26# AC21 Source Sync Input/Output DEFER# C23 Common Clk Input D27# AE22 Source Sync Input/Output DBI0# AC27 Source Sync Input/Output D28# AE20 Source Sync Input/Output DBI1# AD22 Source Sync Input/Output D29# AD21 Source Sync Input/Output DBI2# AE12 Source Sync Input/Output 100 Datasheet Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name 14 for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Direction Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Direction DBI3# AB9 Source Sync Input/Output Reserved A15 Reserved Reserved DP0# AC18 Common Clk Input/Output Reserved A16 Reserved Reserved DP1# AE19 Common Clk Input/Output Reserved A26 Reserved Reserved DP2# AC15 Common Clk Input/Output Reserved B1 Reserved Reserved DP3# AE17 Common Clk Input/Output Reserved C5 Reserved Reserved DRDY# E18 Common Clk Input/Output Reserved D25 Reserved Reserved DSTBN0# Y21 Source Sync Input/Output Reserved W3 Reserved Reserved DSTBN1# Y18 Source Sync Input/Output Reserved Y3 Reserved Reserved DSTBN2# Y15 Source Sync Input/Output Reserved Y27 Reserved Reserved DSTBN3# Y12 Source Sync Input/Output Reserved Y28 Reserved Reserved DSTBP0# Y20 Source Sync Input/Output Reserved AC1 Reserved Reserved DSTBP1# Y17 Source Sync Input/Output Reserved AD1 Reserved Reserved DSTBP2# Y14 Source Sync Input/Output Reserved AE4 Reserved Reserved DSTBP3# Y11 Source Sync Input/Output Reserved AE15 Reserved Reserved FERR# E27 Async GTL+ Output Reserved AE16 Reserved Reserved GTLREF W23 Power/Other Input RESET# Y8 Common Clk Input GTLREF W9 Power/Other Input RS0# E21 Common Clk Input GTLREF F23 Power/Other Input RS1# D22 Common Clk Input GTLREF F9 Power/Other Input RS2# F21 Common Clk Input HIT# E22 Common Clk Input/Output RSP# C6 Common Clk Input HITM# A23 Common Clk Input/Output SKTOCC# A3 Power/Other Output IERR# E5 Async GTL+ Output SLP# AE6 Async GTL+ Input IGNNE# C26 Async GTL+ Input SM_ALERT# AD28 SMBus Output INIT# D6 Async GTL+ Input SM_CLK AC28 SMBus Input LINT0 B24 Async GTL+ Input SM_DAT AC29 SMBus Input/Output LINT1 G23 Async GTL+ Input SM_EP_A0 AA29 SMBus Input LOCK# A17 Common Clk Input/Output SM_EP_A1 AB29 SMBus Input MCERR# D7 Common Clk Input/Output SM_EP_A2 AB28 SMBus Input ODTEN B5 Power/Other Input SM_TS1_A0 AA28 SMBus Input PROCHOT# B25 Async GTL+ Output SM_TS1_A1 Y29 SMBus Input PWRGOOD AB7 Power/Other Input SM_VCC AE28 Power/Other REQ0# B19 Source Sync Input/Output SM_VCC AE29 Power/Other REQ1# B21 Source Sync Input/Output SM_WP AD29 SMBus Input REQ2# C21 Source Sync Input/Output SMI# C27 Async GTL+ Input REQ3# C20 Source Sync Input/Output STPCLK# D4 Async GTL+ Input REQ4# B22 Source Sync Input/Output TCK E24 TAP Input Reserved A1 Reserved Reserved TDI C24 TAP Input Reserved A4 Reserved Reserved TDO E25 TAP Output Datasheet 101 Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name for the INT-mPGA Package Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No. Signal Buffer Type TESTHI0 W6 Power/Other Input VCC E2 Power/Other TESTHI1 W7 Power/Other Input VCC E6 Power/Other TESTHI2 W8 Power/Other Input VCC E12 Power/Other TESTHI3 Y6 Power/Other Input VCC E20 Power/Other TESTHI4 AA7 Power/Other Input VCC E26 Power/Other TESTHI5 AD5 Power/Other Input VCC E28 Power/Other TESTHI6 AE5 Power/Other Input VCC E30 Power/Other THERMTRIP# F26 Async GTL+ Output VCC F1 Power/Other TMS A25 TAP Input VCC F4 Power/Other TRDY# E19 Common Clk Input VCC F10 Power/Other TRST# F24 TAP Input VCC F16 Power/Other VCC A2 Power/Other VCC F22 Power/Other VCC A8 Power/Other VCC F29 Power/Other VCC A14 Power/Other VCC F31 Power/Other VCC A18 Power/Other VCC G2 Power/Other VCC A24 Power/Other VCC G4 Power/Other VCC A28 Power/Other VCC G6 Power/Other VCC A30 Power/Other VCC G8 Power/Other VCC B4 Power/Other VCC G24 Power/Other VCC B6 Power/Other VCC G26 Power/Other VCC B12 Power/Other VCC G28 Power/Other VCC B20 Power/Other VCC G30 Power/Other VCC B26 Power/Other VCC H1 Power/Other VCC B29 Power/Other VCC H3 Power/Other VCC B31 Power/Other VCC H5 Power/Other VCC C2 Power/Other VCC H7 Power/Other VCC C4 Power/Other VCC H9 Power/Other VCC C10 Power/Other VCC H23 Power/Other VCC C16 Power/Other VCC H25 Power/Other VCC C22 Power/Other VCC H27 Power/Other VCC C28 Power/Other VCC H29 Power/Other VCC C30 Power/Other VCC H31 Power/Other VCC D1 Power/Other VCC J2 Power/Other VCC D8 Power/Other VCC J4 Power/Other VCC D14 Power/Other VCC J6 Power/Other VCC D18 Power/Other VCC J8 Power/Other VCC D24 Power/Other VCC J24 Power/Other VCC D29 Power/Other VCC J26 Power/Other VCC D31 Power/Other VCC J28 Power/Other 102 Direction Datasheet Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type VCC J30 VCC K1 VCC Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Power/Other VCC N31 Power/Other Power/Other VCC P2 Power/Other K3 Power/Other VCC P4 Power/Other VCC K5 Power/Other VCC P6 Power/Other VCC K7 Power/Other VCC P8 Power/Other VCC K9 Power/Other VCC P24 Power/Other VCC K23 Power/Other VCC P26 Power/Other VCC K25 Power/Other VCC P28 Power/Other VCC K27 Power/Other VCC P30 Power/Other VCC K29 Power/Other VCC R1 Power/Other VCC K31 Power/Other VCC R3 Power/Other VCC L2 Power/Other VCC R5 Power/Other VCC L4 Power/Other VCC R7 Power/Other VCC L6 Power/Other VCC R9 Power/Other VCC L8 Power/Other VCC R23 Power/Other VCC L24 Power/Other VCC R25 Power/Other VCC L26 Power/Other VCC R27 Power/Other VCC L28 Power/Other VCC R29 Power/Other VCC L30 Power/Other VCC R31 Power/Other VCC M1 Power/Other VCC T2 Power/Other VCC M3 Power/Other VCC T4 Power/Other VCC M5 Power/Other VCC T6 Power/Other VCC M7 Power/Other VCC T8 Power/Other VCC M9 Power/Other VCC T24 Power/Other VCC M23 Power/Other VCC T26 Power/Other VCC M25 Power/Other VCC T28 Power/Other VCC M27 Power/Other VCC T30 Power/Other VCC M29 Power/Other VCC U1 Power/Other VCC M31 Power/Other VCC U3 Power/Other VCC N1 Power/Other VCC U5 Power/Other VCC N3 Power/Other VCC U7 Power/Other VCC N5 Power/Other VCC U9 Power/Other VCC N7 Power/Other VCC U23 Power/Other VCC N9 Power/Other VCC U25 Power/Other VCC N23 Power/Other VCC U27 Power/Other VCC N25 Power/Other VCC U29 Power/Other VCC N27 Power/Other VCC U31 Power/Other VCC N29 Power/Other VCC V2 Power/Other Datasheet Direction Direction 103 Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type VCC V4 VCC 104 Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Power/Other VCC AD20 Power/Other V6 Power/Other VCC AD26 Power/Other VCC V8 Power/Other VCC AD30 Power/Other VCC V24 Power/Other VCC AE3 Power/Other VCC V26 Power/Other VCC AE8 Power/Other VCC V28 Power/Other VCC AE14 Power/Other VCC V30 Power/Other VCC AE18 Power/Other VCC W1 Power/Other VCC AE24 Power/Other VCC W25 Power/Other VCCA AB4 Power/Other Input VCC W27 Power/Other VCCIOPLL AD4 Power/Other Input VCC W29 Power/Other VCCSENSE B27 Power/Other Output VCC W31 Power/Other VID0 F3 Power/Other Output VCC Y10 Power/Other VID1 E3 Power/Other Output VCC Y16 Power/Other VID2 D3 Power/Other Output VCC Y2 Power/Other VID3 C3 Power/Other Output VCC Y22 Power/Other VID4 B3 Power/Other Output VCC Y30 Power/Other VSS A5 Power/Other VCC AA1 Power/Other VSS A11 Power/Other VCC AA4 Power/Other VSS A21 Power/Other VCC AA6 Power/Other VSS A27 Power/Other VCC AA12 Power/Other VSS A29 Power/Other VCC AA20 Power/Other VSS A31 Power/Other VCC AA26 Power/Other VSS B2 Power/Other VCC AA31 Power/Other VSS B9 Power/Other VCC AB2 Power/Other VSS B15 Power/Other VCC AB8 Power/Other VSS B17 Power/Other VCC AB14 Power/Other VSS B23 Power/Other VCC AB18 Power/Other VSS B28 Power/Other VCC AB24 Power/Other VSS B30 Power/Other VCC AB30 Power/Other VSS C1 Power/Other VCC AC3 Power/Other VSS C7 Power/Other Direction VCC AC4 Power/Other VSS C13 Power/Other VCC AC10 Power/Other VSS C19 Power/Other VCC AC16 Power/Other VSS C25 Power/Other VCC AC22 Power/Other VSS C29 Power/Other VCC AC31 Power/Other VSS C31 Power/Other VCC AD2 Power/Other VSS D2 Power/Other VCC AD6 Power/Other VSS D5 Power/Other VCC AD12 Power/Other VSS D11 Power/Other Direction Datasheet Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type VSS D21 VSS D27 VSS Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Power/Other VSS J7 Power/Other Power/Other VSS J9 Power/Other D28 Power/Other VSS J23 Power/Other VSS D30 Power/Other VSS J25 Power/Other VSS E1 Power/Other VSS J27 Power/Other VSS E9 Power/Other VSS J29 Power/Other VSS E15 Power/Other VSS J31 Power/Other VSS E17 Power/Other VSS K2 Power/Other VSS E23 Power/Other VSS K4 Power/Other VSS E29 Power/Other VSS K6 Power/Other VSS E31 Power/Other VSS K8 Power/Other VSS F2 Power/Other VSS K24 Power/Other Direction VSS F7 Power/Other VSS K26 Power/Other VSS F13 Power/Other VSS K28 Power/Other VSS F19 Power/Other VSS K30 Power/Other VSS F25 Power/Other VSS L1 Power/Other VSS F28 Power/Other VSS L3 Power/Other VSS F30 Power/Other VSS L5 Power/Other VSS G1 Power/Other VSS L7 Power/Other VSS G3 Power/Other VSS L9 Power/Other VSS G5 Power/Other VSS L23 Power/Other VSS G7 Power/Other VSS L25 Power/Other VSS G9 Power/Other VSS L27 Power/Other VSS G25 Power/Other VSS L29 Power/Other VSS G27 Power/Other VSS L31 Power/Other VSS G29 Power/Other VSS M2 Power/Other VSS G31 Power/Other VSS M4 Power/Other VSS H2 Power/Other VSS M6 Power/Other VSS H4 Power/Other VSS M8 Power/Other VSS H6 Power/Other VSS M24 Power/Other VSS H8 Power/Other VSS M26 Power/Other VSS H24 Power/Other VSS M28 Power/Other VSS H26 Power/Other VSS M30 Power/Other VSS H28 Power/Other VSS N2 Power/Other VSS H30 Power/Other VSS N4 Power/Other VSS J1 Power/Other VSS N6 Power/Other VSS J3 Power/Other VSS N8 Power/Other VSS J5 Power/Other VSS N24 Power/Other Datasheet Direction 105 Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type VSS N26 VSS 106 Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type Power/Other VSS V1 Power/Other N28 Power/Other VSS V3 Power/Other VSS N30 Power/Other VSS V5 Power/Other VSS P1 Power/Other VSS V7 Power/Other VSS P3 Power/Other VSS V9 Power/Other VSS P5 Power/Other VSS V23 Power/Other VSS P7 Power/Other VSS V25 Power/Other Direction VSS P9 Power/Other VSS V27 Power/Other VSS P23 Power/Other VSS V29 Power/Other VSS P25 Power/Other VSS V31 Power/Other VSS P27 Power/Other VSS W2 Power/Other VSS P29 Power/Other VSS W4 Power/Other VSS P31 Power/Other VSS W24 Power/Other VSS R2 Power/Other VSS W26 Power/Other VSS R4 Power/Other VSS W28 Power/Other VSS R6 Power/Other VSS W30 Power/Other VSS R8 Power/Other VSS Y1 Power/Other VSS R24 Power/Other VSS Y5 Power/Other VSS R26 Power/Other VSS Y7 Power/Other VSS R28 Power/Other VSS Y13 Power/Other VSS R30 Power/Other VSS Y19 Power/Other VSS T1 Power/Other VSS Y25 Power/Other VSS T3 Power/Other VSS Y31 Power/Other VSS T5 Power/Other VSS AA2 Power/Other VSS T7 Power/Other VSS AA9 Power/Other VSS T9 Power/Other VSS AA15 Power/Other VSS T23 Power/Other VSS AA17 Power/Other VSS T25 Power/Other VSS AA23 Power/Other VSS T27 Power/Other VSS AA30 Power/Other VSS T29 Power/Other VSS AB1 Power/Other VSS T31 Power/Other VSS AB5 Power/Other VSS U2 Power/Other VSS AB11 Power/Other VSS U4 Power/Other VSS AB21 Power/Other VSS U6 Power/Other VSS AB27 Power/Other VSS U8 Power/Other VSS AB31 Power/Other VSS U24 Power/Other VSS AC2 Power/Other VSS U26 Power/Other VSS AC7 Power/Other VSS U28 Power/Other VSS AC13 Power/Other VSS U30 Power/Other VSS AC19 Power/Other Direction Datasheet Pin Listing and Signal Definitions Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin Name Pin No. Signal Buffer Type VSS AC25 Power/Other VSS AC30 Power/Other VSS AD3 VSS Table 50. Pin Listing by Pin Name for the INT-mPGA Package Pin No. Signal Buffer Type VSS AE11 Power/Other VSS AE21 Power/Other Power/Other VSS AE27 Power/Other AD9 Power/Other VSSA AA5 Power/Other Input VSS AD15 Power/Other VSSSENSE D26 Power/Other Output VSS AD17 Power/Other VSS AD23 Power/Other VSS AD31 Power/Other VSS AE2 Power/Other Datasheet Direction Pin Name Direction NOTES: 1. In systems utilizing the Intel Xeon processor, the system designer must pull-up these signals to the processor VCC. 2. Baseboard treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 100 MHz. 107 Pin Listing and Signal Definitions 9.1.1 Pin Listing by Pin Number Table 51. Pin Listing by Pin Number for the INT-mPGA Package Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Direction B1 Reserved Reserved Reserved B2 VSS Power/Other Pin No. Pin Name Signal Buffer Type A1 Reserved Reserved A2 VCC Power/Other B3 VID4 Power/Other VCC Power/Other OTDEN Power/Other 108 Direction Reserved Output A3 SKTOCC# Power/Other Output B4 A4 Reserved Reserved Reserved B5 A5 VSS Power/Other B6 VCC Power/Other A31# Source Sync Input/Output A27# Source Sync Input/Output Input A6 A32# Source Sync Input/Output B7 A7 A33# Source Sync Input/Output B8 A8 VCC Power/Other B9 VSS Power/Other A21# Source Sync Input/Output A22# Source Sync Input/Output A9 A26# Source Sync Input/Output B10 A10 A20# Source Sync Input/Output B11 A11 VSS Power/Other B12 VCC Power/Other A13# Source Sync Input/Output Input/Output A12 A14# Source Sync Input/Output B13 A13 A10# Source Sync Input/Output B14 A12# Source Sync A14 VCC Power/Other B15 VSS Power/Other A15 Reserved Reserved Reserved B16 A11# Source Sync VSS Power/Other Source Sync Input/Output Input/Output Input/Output A16 Reserved Reserved Reserved B17 A17 LOCK# Common Clk Input/Output B18 A5# A18 VCC Power/Other B19 REQ0# Common Clk VCC Power/Other Common Clk Input/Output Input/Output A19 A7# Source Sync Input/Output B20 A20 A4# Source Sync Input/Output B21 REQ1# A21 VSS Power/Other B22 REQ4# Common Clk VSS Power/Other A22 A3# Source Sync Input/Output B23 A23 HITM# Common Clk Input/Output B24 LINT0 Async GTL+ Input A24 VCC Power/Other B25 PROCHOT# Power/Other Output VCC Power/Other VCCSENSE Power/Other A25 TMS TAP Input B26 A26 Reserved Reserved Reserved B27 A27 VSS Power/Other B28 VSS Power/Other VCC Power/Other A28 VCC Power/Other B29 A29 VSS Power/Other B30 VSS Power/Other A30 VCC Power/Other B31 VCC Power/Other A31 VSS Power/Other C1 VSS Power/Other Output Datasheet Pin Listing and Signal Definitions Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type C2 VCC Power/Other C3 VID3 Power/Other C4 VCC Power/Other C5 Reserved Reserved C6 RSP# Common Clk C7 VSS Power/Other C8 A35# Source Sync C9 A34# Source Sync C10 VCC Power/Other Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Direction D10 BR3# 1 Common Clk Input D11 VSS Power/Other D12 A29# Source Sync Input/Output Reserved D13 A25# Source Sync Input/Output Input D14 VCC Power/Other D15 A18# Source Sync Input/Output Input/Output D16 A17# Source Sync Input/Output Input/Output D17 A9# Source Sync Input/Output D18 VCC Power/Other D19 ADS# Common Clk Input/Output D20 BR0# Common Clk Input/Output Direction Output C11 A30# Source Sync Input/Output C12 A23# Source Sync Input/Output C13 VSS Power/Other C14 A16# Source Sync Input/Output D21 VSS Power/Other C15 A15# Source Sync Input/Output D22 RS1# Common Clk Input C16 VCC Power/Other D23 BPRI# Common Clk Input C17 A8# Source Sync Input/Output D24 VCC Power/Other C18 A6# Source Sync Input/Output D25 Reserved Reserved Reserved C19 VSS Power/Other D26 VSSSENSE Power/Other Output C20 REQ3# Common Clk Input/Output D27 VSS Power/Other C21 REQ2# Common Clk Input/Output D28 VSS Power/Other C22 VCC Power/Other D29 VCC Power/Other C23 DEFER# Common Clk Input D30 VSS Power/Other C24 TDI TAP Input D31 VCC Power/Other C25 VSS Power/Other Input E1 VSS Power/Other C26 IGNNE# Async GTL+ Input E2 VCC Power/Other C27 SMI# Async GTL+ Input E3 VID1 Power/Other Output C28 VCC Power/Other E4 BPM5# Common Clk Input/Output C29 VSS Power/Other E5 IERR# Common Clk Output C30 VCC Power/Other E6 VCC Power/Other C31 VSS Power/Other E7 BPM2# Common Clk Input/Output D1 VCC Power/Other E8 BPM4# Common Clk Input/Output D2 VSS Power/Other E9 VSS Power/Other D3 VID2 Power/Other Output E10 AP0# D4 STPCLK# Async GTL+ Input D5 VSS Power/Other E12 VCC Power/Other D6 INIT# Async GTL+ Input E13 A28# Source Sync Input/Output D7 MCERR# Common Clk Input/Output E14 A24# Source Sync Input/Output D8 VCC Power/Other E15 VSS Power/Other D9 AP1# Common Clk Datasheet E11 BR2# 1 Common Clk Input/Output Common Clk Input Input/Output 109 Pin Listing and Signal Definitions Table 51. Pin Listing by Pin Number for the INT-mPGA Package Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Direction Pin No. Pin Name Signal Buffer Type Direction E16 COMP1 Power/Other Input F24 TRST# TAP Input E17 VSS Power/Other F25 VSS Power/Other E18 DRDY# Common Clk Input/Output F26 Output TRDY# Input THERMTRIP # Async GTL+ E19 Common Clk E20 VCC Power/Other F27 A20M# Async GTL+ Input F28 VSS Power/Other F29 VCC Power/Other F30 VSS Power/Other F31 VCC Power/Other G1 VSS Power/Other G2 VCC Power/Other 110 E21 RS0# Common Clk Input E22 HIT# Common Clk Input/Output E23 VSS Power/Other E24 TCK TAP E25 TDO TAP E26 VCC Power/Other E27 FERR# Async GTL+ E28 VCC Power/Other E29 VSS Power/Other E30 VCC Power/Other E31 VSS Power/Other F1 VCC Power/Other F2 VSS Power/Other F3 VID0 Power/Other F4 VCC Power/Other F5 BPM3# Common Clk Input Output Output Output Input/Output Input/Output F6 BPM0# Common Clk F7 VSS Power/Other F8 BPM1# Common Clk Input/Output F9 GTLREF Power/Other Input F10 VCC Power/Other F11 BINIT# Common Clk Input/Output F12 BR1# Common Clk Input F13 VSS Power/Other F14 ADSTB1# Source Sync Input/Output F15 A19# Source Sync Input/Output F16 VCC Power/Other F17 ADSTB0# Source Sync Input/Output F18 DBSY# Common Clk Input/Output F19 VSS Power/Other F20 BNR# Common Clk Input/Output F21 RS2# Common Clk Input F22 VCC Power/Other F23 GTLREF Power/Other Input G3 VSS Power/Other G4 VCC Power/Other G5 VSS Power/Other G6 VCC Power/Other G7 VSS Power/Other G8 VCC Power/Other G9 VSS Power/Other G23 LINT1 Async GTL+ G24 VCC Power/Other G25 VSS Power/Other G26 VCC Power/Other G27 VSS Power/Other G28 VCC Power/Other G29 VSS Power/Other G30 VCC Power/Other G31 VSS Power/Other H1 VCC Power/Other H2 VSS Power/Other H3 VCC Power/Other H4 VSS Power/Other H5 VCC Power/Other H6 VSS Power/Other H7 VCC Power/Other H8 VSS Power/Other H9 VCC Power/Other H23 VCC Power/Other H24 VSS Power/Other H25 VCC Power/Other Input Datasheet Pin Listing and Signal Definitions Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type H26 VSS H27 Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Power/Other K29 VCC Power/Other VCC Power/Other K30 VSS Power/Other H28 VSS Power/Other K31 VCC Power/Other H29 VCC Power/Other L1 VSS Power/Other H30 VSS Power/Other L2 VCC Power/Other H31 VCC Power/Other L3 VSS Power/Other Direction J1 VSS Power/Other L4 VCC Power/Other J2 VCC Power/Other L5 VSS Power/Other J3 VSS Power/Other L6 VCC Power/Other J4 VCC Power/Other L7 VSS Power/Other J5 VSS Power/Other L8 VCC Power/Other J6 VCC Power/Other L9 VSS Power/Other J7 VSS Power/Other L23 VSS Power/Other J8 VCC Power/Other L24 VCC Power/Other J9 VSS Power/Other L25 VSS Power/Other J23 VSS Power/Other L26 VCC Power/Other J24 VCC Power/Other L27 VSS Power/Other J25 VSS Power/Other L28 VCC Power/Other J26 VCC Power/Other L29 VSS Power/Other J27 VSS Power/Other L30 VCC Power/Other J28 VCC Power/Other L31 VSS Power/Other J29 VSS Power/Other M1 VCC Power/Other J30 VCC Power/Other M2 VSS Power/Other J31 VSS Power/Other M3 VCC Power/Other K1 VCC Power/Other M4 VSS Power/Other K2 VSS Power/Other M5 VCC Power/Other K3 VCC Power/Other M6 VSS Power/Other K4 VSS Power/Other M7 VCC Power/Other K5 VCC Power/Other M8 VSS Power/Other K6 VSS Power/Other M9 VCC Power/Other K7 VCC Power/Other M23 VCC Power/Other K8 VSS Power/Other M24 VSS Power/Other K9 VCC Power/Other M25 VCC Power/Other K23 VCC Power/Other M26 VSS Power/Other K24 VSS Power/Other M27 VCC Power/Other K25 VCC Power/Other M28 VSS Power/Other K26 VSS Power/Other M29 VCC Power/Other K27 VCC Power/Other M30 VSS Power/Other K28 VSS Power/Other M31 VCC Power/Other Datasheet Direction 111 Pin Listing and Signal Definitions Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type N1 VCC N2 N3 112 Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Power/Other R4 VSS Power/Other VSS Power/Other R5 VCC Power/Other VCC Power/Other R6 VSS Power/Other Direction N4 VSS Power/Other R7 VCC Power/Other N5 VCC Power/Other R8 VSS Power/Other N6 VSS Power/Other R9 VCC Power/Other N7 VCC Power/Other R23 VCC Power/Other N8 VSS Power/Other R24 VSS Power/Other N9 VCC Power/Other R25 VCC Power/Other N23 VCC Power/Other R26 VSS Power/Other N24 VSS Power/Other R27 VCC Power/Other N25 VCC Power/Other R28 VSS Power/Other N26 VSS Power/Other R29 VCC Power/Other N27 VCC Power/Other R30 VSS Power/Other N28 VSS Power/Other R31 VCC Power/Other N29 VCC Power/Other T1 VSS Power/Other N30 VSS Power/Other T2 VCC Power/Other N31 VCC Power/Other T3 VSS Power/Other P1 VSS Power/Other T4 VCC Power/Other P2 VCC Power/Other T5 VSS Power/Other P3 VSS Power/Other T6 VCC Power/Other P4 VCC Power/Other T7 VSS Power/Other P5 VSS Power/Other T8 VCC Power/Other P6 VCC Power/Other T9 VSS Power/Other P7 VSS Power/Other T23 VSS Power/Other P8 VCC Power/Other T24 VCC Power/Other P9 VSS Power/Other T25 VSS Power/Other P23 VSS Power/Other T26 VCC Power/Other P24 VCC Power/Other T27 VSS Power/Other P25 VSS Power/Other T28 VCC Power/Other P26 VCC Power/Other T29 VSS Power/Other P27 VSS Power/Other T30 VCC Power/Other P28 VCC Power/Other T31 VSS Power/Other P29 VSS Power/Other U1 VCC Power/Other P30 VCC Power/Other U2 VSS Power/Other P31 VSS Power/Other U3 VCC Power/Other R1 VCC Power/Other U4 VSS Power/Other R2 VSS Power/Other U5 VCC Power/Other R3 VCC Power/Other U6 VSS Power/Other Direction Datasheet Pin Listing and Signal Definitions Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type U7 VCC U8 Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Direction Power/Other W23 GTLREF Power/Other Input VSS Power/Other W24 VSS Power/Other U9 VCC Power/Other W25 VCC Power/Other U23 VCC Power/Other W26 VSS Power/Other U24 VSS Power/Other W27 VCC Power/Other U25 VCC Power/Other W28 VSS Power/Other U26 VSS Power/Other W29 VCC Power/Other U27 VCC Power/Other W30 VSS Power/Other U28 VSS Power/Other W31 VCC Power/Other U29 VCC Power/Other Y1 VSS Power/Other U30 VSS Power/Other Y2 VCC Power/Other U31 VCC Power/Other Y3 Reserved Reserved Reserved Input Direction V1 VSS Power/Other Y4 BCLK0 Sys Bus Clk V2 VCC Power/Other Y5 VSS Power/Other V3 VSS Power/Other Y6 TESTHI3 Power/Other V4 VCC Power/Other Y7 VSS Power/Other V5 VSS Power/Other Y8 RESET# Common Clk Input V6 VCC Power/Other Y9 D62# Source Sync Input/Output V7 VSS Power/Other Y10 VCC Power/Other V8 VCC Power/Other Y11 DSTBP3# Source Sync Input/Output V9 VSS Power/Other Y12 DSTBN3# Source Sync Input/Output V23 VSS Power/Other Y13 VSS Power/Other V24 VCC Power/Other Y14 DSTBP2# Source Sync Input/Output V25 VSS Power/Other Y15 DSTBN2# Source Sync Input/Output V26 VCC Power/Other Y16 VCC Power/Other Input V27 VSS Power/Other Y17 DSTBP1# Source Sync Input/Output V28 VCC Power/Other Y18 DSTBN1# Source Sync Input/Output V29 VSS Power/Other Y19 VSS Power/Other V30 VCC Power/Other Y20 DSTBP0# Source Sync Input/Output V31 VSS Power/Other Y21 DSTBN0# Source Sync Input/Output W1 VCC Power/Other Y22 VCC Power/Other W2 VSS Power/Other Y23 D5# Source Sync Input/Output W3 Reserved Reserved Y24 D2# Source Sync Input/Output W4 VSS Power/Other Y25 VSS Power/Other W5 BCLK1 Sys Bus Clk Input Y26 D0# Source Sync Input/Output W6 TESTHI0 Power/Other Input Y27 Reserved Reserved Reserved W7 TESTHI1 Power/Other Input Y28 Reserved Reserved Reserved W8 TESTHI2 Power/Other Input Y29 SM_TS1_A1 SMBus Input W9 GTLREF Power/Other Input Y30 VCC Power/Other Datasheet Reserved 113 Pin Listing and Signal Definitions Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Y31 VSS AA1 AA2 Pin No. Pin Name Signal Buffer Type Power/Other AB8 VCC Power/Other VCC Power/Other AB9 DBI3# Source Sync Input/Output VSS Power/Other AB10 D55# Source Sync Input/Output Direction Output Direction BSEL0 Power/Other AA4 VCC Power/Other AA5 VSSA Power/Other AA6 VCC Power/Other AB14 VCC Power/Other AA7 TESTHI4 Power/Other Input AB15 D37# Source Sync Input/Output AA8 D61# Source Sync Input/Output AB16 D32# Source Sync Input/Output Input/Output AA3 Input AB11 VSS Power/Other AB12 D51# Source Sync Input/Output AB13 D52# Source Sync Input/Output AA9 VSS Power/Other AB17 D31# Source Sync AA10 D54# Source Sync Input/Output AB18 VCC Power/Other AA11 D53# Source Sync Input/Output AB19 D14# Source Sync Input/Output Input/Output AA12 VCC Power/Other AB20 D12# Source Sync AA13 D48# Source Sync Input/Output AB21 VSS Power/Other AA14 D49# Source Sync Input/Output AB22 D13# Source Sync Input/Output AB23 D9# Source Sync Input/Output AB24 VCC Power/Other AB25 D8# Source Sync Input/Output D7# Source Sync Input/Output AA15 VSS Power/Other AA16 D33# Source Sync AA17 VSS Power/Other AA18 D24# Source Sync Input/Output AB26 AA19 D15# Source Sync Input/Output AB27 VSS Power/Other AA20 VCC Power/Other AB28 SM_EP_A2 SMBus Input AA21 D11# Source Sync Input/Output AB29 SM_EP_A1 SMBus Input AA22 D10# Source Sync Input/Output AB30 VCC Power/Other AA23 VSS Power/Other AB31 VSS Power/Other AA24 D6# Source Sync Input/Output AC1 Reserved Reserved AA25 D3# Source Sync Input/Output AC2 VSS Power/Other AA26 VCC Power/Other AC3 VCC Power/Other AA27 D1# Source Sync Input/Output AC4 VCC Power/Other AA28 SM_TS1_A0 SMBus Input AC5 D60# Source Sync Input/Output AA29 SM_EP_A0 SMBus Input AC6 D59# Source Sync Input/Output AA30 VSS Power/Other AC7 VSS Power/Other AA31 VCC Power/Other AC8 D56# Source Sync Input/Output AB1 VSS Power/Other AC9 D47# Source Sync Input/Output AB2 VCC Power/Other AC10 VCC Power/Other BSEL1 Power/Other Output AC11 D43# Source Sync Input/Output Input Input/Output AB3 114 2 Table 51. Pin Listing by Pin Number for the INT-mPGA Package 2 Input/Output Reserved AB4 VCCA Power/Other AC12 D41# Source Sync AB5 VSS Power/Other AC13 VSS Power/Other AB6 D63# Source Sync AC14 D50# Source Sync Input/Output AB7 PWRGOOD Power/Other AC15 DP2# Common Clk Input/Output Input Datasheet Pin Listing and Signal Definitions Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type AC16 VCC Power/Other AC17 D34# Source Sync AC18 DP0# Common Clk Table 51. Pin Listing by Pin Number for the INT-mPGA Package Pin No. Pin Name Signal Buffer Type Direction AD24 D21# Source Sync Input/Output Input/Output AD25 D18# Source Sync Input/Output Input/Output AD26 VCC Power/Other Direction AC19 VSS Power/Other AD27 D4# Source Sync Input/Output AC20 D25# Source Sync Input/Output AD28 SM_ALERT# SMBus Output AC21 D26# Source Sync Input/Output AD29 SM_WP SMBus Input AC22 VCC Power/Other AD30 VCC Power/Other AC23 D23# Source Sync Input/Output AD31 VSS Power/Other AC24 D20# Source Sync Input/Output AE2 VSS Power/Other AC25 VSS Power/Other AE3 VCC Power/Other AC26 D17# Source Sync Input/Output AE4 Reserved Reserved Reserved AC27 DBI0# Source Sync Input/Output AE5 TESTHI6 Power/Other Input AC28 SM_CLK SMBus Input AE6 SLP# Async GTL+ Input AC29 SM_DAT SMBus Output AE7 D58# Source Sync Input/Output AC30 VSS Power/Other AE8 VCC Power/Other AC31 VCC Power/Other AD1 Reserved Reserved AD2 VCC AD3 AE9 D44# Source Sync Input/Output AE10 D42# Source Sync Input/Output Power/Other AE11 VSS Power/Other VSS Power/Other AE12 DBI2# Source Sync Input/Output AD4 VCCIOPLL Power/Other Input AE13 D35# Source Sync Input/Output AD5 TESTHI5 Power/Other Input AE14 VCC Power/Other AD6 VCC Power/Other AE15 Reserved Reserved AD7 D57# Source Sync Input/Output AE16 Reserved Reserved Reserved AD8 D46# Source Sync Input/Output AE17 DP3# Common Clk Input/Output AD9 VSS Power/Other AE18 VCC Power/Other Reserved Reserved AD10 D45# Source Sync Input/Output AE19 DP1# Common Clk Input/Output AD11 D40# Source Sync Input/Output AE20 D28# Source Sync Input/Output AD12 VCC Power/Other AE21 VSS Power/Other AD13 D38# Source Sync Input/Output AE22 D27# Source Sync Input/Output AD14 D39# Source Sync Input/Output AE23 D22# Source Sync Input/Output AD15 VSS Power/Other AE24 VCC Power/Other AD16 COMP0 Power/Other AE25 D19# Source Sync Input/Output AD17 VSS Power/Other AE26 D16# Source Sync Input/Output AD18 D36# Source Sync Input/Output AE27 VSS Power/Other AD19 D30# Source Sync Input/Output AE28 SM_VCC Power/Other AE29 SM_VCC Power/Other Input AD20 VCC Power/Other AD21 D29# Source Sync Input/Output AD22 DBI1# Source Sync Input/Output AD23 VSS Power/Other Datasheet 1. In systems utilizing the Intel Xeon processor, the system designer must pull-up these signals to the processor VCC. 2. Baseboards treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 100 MHz. 115 Pin Listing and Signal Definitions This page is intentionally left blank. 116 Datasheet 9.2 Signal Definitions Table 52. Signal Definitions (Sheet 1 of 10) Name A[35:3]# Type I/O Description A[35:3]# (Address) define a 236 byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In subphase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Intel(R) XeonTM processor MP on the 0.13 micron process processor system bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processors sample a subset of the A[35:3]# pins to determine their power-on configuration. See Section 6.1. A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on all Intel Xeon processor MP on the 0.13 micron process processor System Bus agents. ADSTB[1:0]# I/O Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edge. AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Intel Xeon processor MP on the 0.13 micron process processor system bus agents. The following table defines the coverage model of these signals. AP[1:0]# BCLK[1:0] I/O I Request Signals Subphase 1 Subphase 2 A[35:24]# AP0# AP1# A[23:3]# AP1# AP0# REQ[4:0]# AP1# AP0# The differential pair BCLK (Bus Clock) determines the bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing the falling edge of BCLK1. Datasheet 117 Table 52. Signal Definitions (Sheet 2 of 10) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information. BINIT# I/O If BINIT# observation is enabled during power-on configuration (see Section 6.1) and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# assertion. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BNR# I/O Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must connect the appropriate pins of all processor system bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Intel Xeon processor MP on the 0.13 micron process processor system bus agents. BPM[5:0]# I/O BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processors. BPM[5:4]# must be bussed to all bus agents. These signals do not have on-die termination and must be terminated at the end agent. See the ITP Debug Port Design Guide for more information. BPRI# 118 I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. Datasheet Table 52. Signal Definitions (Sheet 3 of 10) Name Type Description BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. The tables below give the rotating interconnect between the processor and bus signals for 2-way and 4-way systems. BR[3:0]# Signals Rotating Interconnect, 4-way system (MP processors only) BR0# BR[1:3]#1 I/O I Bus Signal Agent 0 Pins Agent 1 Pins Agent 2 pins Agent 3 pins BREQ0# BR0# BR3# BR2# BR1# BREQ1# BR1# BR0# BR3# BR2# BREQ2# BR2# BR1# BR0# BR3# BREQ3# BR3# BR2# BR1# BR0# BR[1:0]# Signals Rotating Interconnect, 2-way system Bus Signal Agent 0 Pins Agent 1 Pins BREQ0# BR0# BR1# BREQ1# BR1# BR0# BR2# and BR3# must not be utilized in 2-way platform designs. During power-on configuration, the central agent must assert the BR0# bus signal. All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition of RESET#. The pin which the agent samples asserted determines it's agent ID. These signals do not have on-die termination and must be terminated at the end agent. See the appropriate platform design guideline for additional information. BSEL[1:0] O BSEL[1:0] (Bus Select) output signals are used to select the system bus frequency. A BSEL[1:0] = "00" will select a 100 MHz bus clock frequency. The frequency is determined by the processor(s), chipset, and frequency synthesizer capabilities. All system bus agents must operate at the same frequency. The Intel Xeon processor MP on the 0.13 micron process processor currently operates at 100 MHz system bus frequencies. Individual processors will only operate at their specified front side bus (FSB) frequency. On baseboards which support operation only at 100 MHz bus clocks these signals can be ignored. See the appropriate platform design guide for implementation examples. See Table 3, "System Bus Clock Frequency Select Truth Table for BSEL[1:0]" on page 18 for output values. COMP[1:0] Datasheet I COMP[1:0] must be terminated to VSS on the baseboard using precision resistors. These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate platform design guidelines and Table 14 for implementation details. 119 Table 52. Signal Definitions (Sheet 4 of 10) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to strobes and DBI#. D[63:0]# I/O Data Group DSTBN/ DSTBP DBI# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within a 16-bit group, change logic level in the next cycle. DBI[3:0] Assignment To Data Bus DBI[3:0]# Bus Signal Data Bus Signals DBI0# D[15:0]# DBI1# D[31:16]# DBI2# D[47:32]# DBI3# D[63:48]# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. DEFER# I DEFER# (Defer) is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the appropriate pins of all processor system bus agents. DP[3:0]# I/O DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all processor system bus agents. DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents. DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#. DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. DBSY# 120 I/O Datasheet Table 52. Signal Definitions (Sheet 5 of 10) Name FERR#/PBE# Type O Description FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/ PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/ PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. This signal does not have on-die termination and must be terminated at the end agent. See the appropriate platform design guideline for additional information. GTLREF I HIT# I/O HITM# I/O IERR# O GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set to either 2/3Vcc or 0.63*Vcc (future processors). GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. Since multiple agents may deliver snoop results at the same time, HIT# and HITM# are wire-OR signals which must connect the appropriate pins of all processor system bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, HIT# and HITM# are activated on specific clock edges and sampled on specific clock edges. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination and must be terminated at the end agent. See the appropriate platform design guideline for additional information. IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. INIT# I INIT# (Initialization), when asserted, resets integer registers inside all processors without affecting their internal caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). Datasheet 121 Table 52. Signal Definitions (Sheet 6 of 10) Name LINT[1:0] Type Description I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all system bus agents. When the APIC functionality is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# I/O LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: * Enabled or disabled. * Asserted, if configured, for internal errors along with IERR#. MCERR# I/O * Asserted, if configured, by the request initiator of a bus transaction after it observes an error. * Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the IA-32 Software Developer's Manual, Volume 3: System Programming Guide. Since multiple agents may drive this signal at the same time, MCERR# is a wire-OR signal which must connect the appropriate pins of all processor system bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, MCERR# is activated on specific clock edges and sampled on specific clock edges. 122 ODTEN I PROCHOT# O ODTEN (On-die termination enable) should be connected to VCC to enable on-die termination for end bus agents. For middle bus agents, pull this signal down via a resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die termination will be active, regardless of other states of the bus. The assertion of PROCHOT# (processor hot) indicates that the processor die temperature has reached its thermal limit. See Section 6.3 for more details. These signals do not have on-die termination and must be terminated at the end agent. See the appropriate platform design guideline for additional information. Datasheet Table 52. Signal Definitions (Sheet 7 of 10) Name PWRGOOD Type I Description PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all Intel Xeon processor MP on the 0.13 micron process processor clocks and power supplies are stable and within their specifications. "Clean" implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. Figure 12 illustrates the relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 18, and be followed by a 1 ms RESET# pulse. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# RESET# I/O I REQ[4:0]# (Request Command) must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking of these signals. Asserting the RESET# signal resets all processors to known states and invalidates their internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10ms. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1. This signal does not have on-die termination and must be terminated at the end agent. See the appropriate platform design guideline for additional information. RS[2:0]# Datasheet I RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents. RSP# I SKTOCC# O SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that the processor is present. SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. SMB_PRT O SMB_PRT (SMBus Present) pin is grounded on processor packages (FC-mPGA2) that do not contain SMBus components (PIROM, Scratch EEPROM, and thermal sensor). It is floating on processor packages (INT-mPGA) that do contain the SMBus components. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. 123 Table 52. Signal Definitions (Sheet 8 of 10) Name SM_ALERT# SM_CLK SM_DAT SM_EP_A[2:0] Type Description O SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with the SMBus Thermal Sensor device. It is an open-drain output and the processor includes a 10k pull-up resistor to SM_VCC for this signal. It is only available on the Intel Xeon processor in INT-mPGA package. For more information on the usage of the SM_ALERT# pin, see Section 6.4.5. I/O The SM_CLK (SMBus Clock) signal is an input clock to the system management logic which is required for operation of the system management features of the Intel Xeon processor MP on the 0.13 micron process processor. This clock is driven by the SMBus controller and is asynchronous to other clocks in the processor.The processor includes a 10 k pull-up resistor to SM_VCC for this signal. It is only available on the Intel Xeon processor in INT-mPGA package. I/O The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal provides the single-bit mechanism for transferring data between SMBus devices.The processor includes a 10 k pull-up resistor to SM_VCC for this signal. It is only available on the Intel Xeon processor in INT-mPGA package. I The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors. To set an SM_EP_A line high, a pull-up resistor should be used that is no larger than 1k. The processor includes a 10k pull-down resistor to VSS for each of these signals. It is only available on the Intel Xeon processor in INT-mPGA package. For more information on the usage of these pins, see Section 6.4.8. The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors. SM_TS_A[1:0] I The device's addressing, as implemented, includes a Hi-Z state for both address pins. The use of the Hi-Z state is achieved by leaving the input floating (unconnected). It is only available on the Intel Xeon processor in INT-mPGA package. For more information on the usage of these pins, see Section 6.4.8. SM_VCC SM_WP SMI# I Provides power to the SMBus components which are only available on the Intel Xeon processor in INT-mPGA package. Additionally provides power for the VID and BSEL logic. Intel Xeon processor MP on the 0.13 micron processprocessor baseboards MUST provide SM_Vcc. See Figure for further details. I WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch EEPROM is write-protected when this input is pulled high to SM_VCC.The processor includes a 10k pull-down resistor to VSS for this signal. It is only available on the Intel Xeon processor in INT-mPGA package. I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tri-state its outputs. It is only available on the Intel Xeon processor in INT-mPGA package. 124 STPCLK# I STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). Datasheet Table 52. Signal Definitions (Sheet 9 of 10) Name Type Description TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. I All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which matches the trace impedance within a range of 10 . TESTHI[3:0] and TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if desired. However, utilization of boundary scan test will not be functional if these pins are connected together. TESTHI4 must always be pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for TESTHI[6:0] pins should have a resistance value within 20% of the impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 , then a value between 40 and 60 should be used. TESTHI[6:0] THERMTRIP# O Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135C. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (Vcc) must be removed following the assertion of THERMTRIP#. See Figure 15 and Table 18 for the appropriate power down sequence and timing requirements. Once activated, THERMTRIP# remains latched until RESET# is asserted. While the assertion of the RESET# signal will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted. This signal does not have on-die termination and must be terminated at the end agent. See the appropriate platform design guideline for additional information. Datasheet TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TMS I TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. See the appropriate platform design guideline for additional information. VCCA I VCCA provides isolated power for the analog portion of the internal PLL's. Use a discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to provide clean power to the PLL. The tolerance and total ESR for the filter is important. Refer to the appropriate platform design guidelines for complete implementation details. VCCIOPLL I VCCIOPLL provides isolated power for digital portion of the internal PLL's. Follow the guidelines for VCCA (Section 2.5). Refer to the appropriate platform design guidelines for complete implementation details. This signal does not have on-die termination and must be terminated at the end agent. See the appropriate platform design guideline for additional information. 125 Table 52. Signal Definitions (Sheet 10 of 10) Name Type Description O The Vccsense and Vsssense pins are the points for which processor minimum and maximum voltage requirements are specified. Uniprocessor designs may utilize these pins for voltage sensing for the processor's voltage regulator. However, multiprocessor designs must not connect these pins to sense logic, but rather utilize them for power delivery validation. VID[4:0] O VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages (VCC). Unlike previous generations of processors, these are logic signals and are driven by the Intel Xeon processor MP on the 0.13 micron process processor. Hence the voltage supply for these pins (SM_Vcc) must be valid before the VRM supplying Vcc to the processor is enabled (see Figure ). Conversely, the VRM output must be disabled prior to the voltage supply for these pins becomes invalid. The VID pins are needed to support processor voltage specification variations. See Table 4 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. VSSA I VSSA provides an isolated, internal ground for internal PLL's. Do not connect directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a discrete filter circuit. Follow the guidelines for VSSA (Section 2.5). Refer to the appropriate platform design guidelines for complete implementation details. VCCSENSE VSSSENSE NOTES: 1. Intel Xeon processors only support BR0# and BR1#. However, the Intel Xeon processors must terminate BR2# and BR3# to the processor VCC.. 126 Datasheet Intel(R) Xeon(TM) Processors - Product Order Codes United States Home | Select a Location Home Computing Business Computing Site Map Developer Reseller / Solutions | Contact Us | About Intel Advanced Search Intel(R) XeonTM Processors Home Technical Specs Software & Drivers Troubleshooting Intel(R) XeonTM Processors Product Order Codes Warranty Information Email Support Intel(R) Processor Frequency ID Utility Application Notes Datasheets Manuals Specification Updates Intel(R) XeonTM processors Intel(R) XeonTM Processor for 1U Rack Mount Servers Intel(R) XeonTM processors MP Intel(R) XeonTM processors Speed/Features Box Product Order Code OEM Product Order Code 2.80 GHz (PGA package/604 BX80532KE2800D pins/.13/512 KB L2 Advanced Transfer Cache/533 MHz Bus/supports dual processing) RK80532KE072512 BX80532KC2800D 2.80 GHz (PGA package/603 pins/.13/512 KB L2 Advanced Transfer Cache/400 MHz Bus/supports dual processing) RN80532KC072512 2.66 GHz (PGA package/604 BX80532KE2667D pins/.13/512 KB L2 Advanced Transfer Cache/533 MHz Bus/supports dual processing) RK80532KE067512 BX80532KC2600D 2.60 GHz (PGA package/603 pins/.13/512 KB L2 Advanced Transfer Cache/400 MHz Bus/supports dual processing) RN80532KC064512 2.40 GHz (PGA package/604 BX80532KE2400D pins/.13/512 KB L2 Advanced Transfer Cache/533 MHz Bus/supports dual processing) RK80532KE056512 2.40 GHz (PGA package/603 BX80532KC2400D pins/.13/512 KB L2 Advanced Transfer Cache/400 MHz Bus/supports dual processing) RN80532KC056512 2.20 GHz (PGA package/603 pins/.13/512 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80532KC2200D RN80532KC049512 2 GHz (PGA package/604 pins/.13/512 KB Advanced Transfer Cache/533 MHz Bus/supports dual processing) BX80532KE2000D RK80532KE041512 2 GHz (PGA package/603 pins/.13/512 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80532KC2000D RN80532KC041512 http://www.intel.com/support/processors/xeon/poc.htm (1 of 3) [2/28/03 2:43:11 PM] Intel(R) Xeon(TM) Processors - Product Order Codes 2 GHz (PGA package/603 pins/.18/256 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80528KL200GA RN80528KC041G0K 1.80 GHz (PGA package/603 pins/.13/512 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80532KC1800D RN80532KC033512 1.70 GHz (PGA package/603 pins/.18/256 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80528KL170GA RN80528KC029G0K 1.50 GHz (PGA package/603 pins/.18/256 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80528KL150GA RN80528KC021G0K 1.40 GHz (PGA package/603 pins/.18 BX80528KL140GA /256 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) 80528KC017G0K Intel(R) XeonTM Processor for 1U Rack Mount Servers Speed/Features Box Product Order Code OEM Product Order Code 2.80 GHz (PGA package/604 BX80532KE2800DU pins/.13/512 KB L2 Advanced Transfer Cache/533 MHz Bus/supports dual processing) RN80532KE072512 2.80 GHz (PGA package/603 BX80532KC2800DU pins/.13/512 KB L2 Advanced Transfer Cache/400 MHz Bus/supports dual processing) RN80532KC072512 2.66 GHz (PGA package/604 BX80532KE2667DU pins/.13/512 KB L2 Advanced Transfer Cache/533 MHz Bus/supports dual processing) RK80532KE067512 2.60 GHz (PGA package/603 BX80532KC2600DU pins/.13/512 KB L2 Advanced Transfer Cache/400 MHz Bus/supports dual processing) RN80532KC064512 2.40 GHz (PGA package/604 BX80532KE2400DU pins/.13/512 KB L2 Advanced Transfer Cache/533 MHz Bus/supports dual processing) RK80532KE056512 2.40 GHz (PGA package/603 BX80532KC2400DU pins/.13/512 KB L2 Advanced Transfer Cache/400 MHz Bus/supports dual processing) RN80532KC056512 2.20 GHz (PGA package/603 pins/.13/512 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80532KC2200DU RN80532KC049512 2 GHz (PGA package/604 pins/.13/512 KB Advanced Transfer Cache/533 MHz Bus/supports dual processing) BX80532KE2000DU RK80532KE041512 http://www.intel.com/support/processors/xeon/poc.htm (2 of 3) [2/28/03 2:43:11 PM] Intel(R) Xeon(TM) Processors - Product Order Codes 1.80 GHz (PGA package/603 pins/.13/512 KB Advanced Transfer Cache/400 MHz Bus/supports dual processing) BX80532KC1800DU RN80532KC033512 Box Product Order Code OEM Product Order Code Intel(R) XeonTM Processor MP Speed/Features 2.00 GHz (PGA package/603 BX80532KC2000E pins/.13/512K L2 Cache/2MB L3 cache/400 MHz Bus/supports dual and 4-way processing) YF80532KC0412M BX80532KC1900E 1.90 GHz (PGA package/603 pins/.13/512K L2 Cache/1MB L3 cache/400 MHz Bus/supports dual and 4-way processing) YF80532KC0371M 1.60 GHz (PGA package/603 BX80528KL160GE pins/.18/256K L2 Cache/1MB L3 cache/400 MHz Bus/supports dual and 4-way processing) YF80528KC025011 BX80532KC1500E 1.50 GHz (PGA package/603 pins/.13/512K L2 Cache/1MB L3 cache/400 MHz Bus/supports dual and 4-way processing) YF80532KC0211M 1.50 GHz (PGA package/603 BX80528KL150GD pins/.18/256K L2 Cache/512K L3 cache/400 MHz Bus/supports dual and 4-way processing) YF80528KC021512 1.40 GHz (PGA package/603 BX80528KL140GD pins/.18/256K L2 Cache/512K L3 cache/400 MHz Bus/supports dual and 4-way processing) YF80528KC017512 *Legal Information | Privacy Policy http://www.intel.com/support/processors/xeon/poc.htm (3 of 3) [2/28/03 2:43:11 PM] (c)2003 Intel Corporation